QVL Monitors Ref PDF

Questa Verification Library
Monitors Data Book

Software Version 2010.2
1991-2010 Mentor Graphics Corporation

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Table of Contents
Chapter 1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mentor Graphics Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
24
Chapter 2
QVL Monitors Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QVL Use Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Global Defines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiate QVL Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instance Templates Directory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compile QVL Monitor Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compile and Simulate the DUT with the QVL Monitor . . . . . . . . . . . . . . . . . . . . . . . . . .
Verify and Troubleshoot the QVL Monitor Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Review and Debug Simulation QVL Monitor Results . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QVL Monitor Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Run Formal Verification with QVL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity on the Bi-Directional/Tri-State Buffer Signals . . . . . . . . . . . . . . . . . . . . . . . .
25
25
26
28
28
32
33
34
35
36
39
39
Chapter 3
Advanced Microcontroller Bus Architecture (AMBA) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APB Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Master Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Master Monitor Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Master Monitor FAQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Target Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Target Monitor Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
41
41
41
42
42
43
43
44
45
46
50
51
51
52
52
52
53
54
55
60
61
Questa Verification Library Monitors Data Book, v2010.2
Table of Contents
AHB Target Monitor FAQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

APB Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APB Monitor Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
62
62
62
63
63
64
65
65
Chapter 4
AMBA 3 Advanced Peripheral Bus (APB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AMBA 3 APB Monitor Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
67
67
67
67
68
69
69
71
71
Chapter 5
AMBA AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Supported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Monitor Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
AMBA AXI Monitor Instantiation Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Chapter 6
Double Data Rate SDRAM (DDR SDRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V1.0 Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization Sequence Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR SDRAMs Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
103
103
103
103
103
104
104
105
105
107
108
Table of Contents
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V2.0 Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data interface and Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization Sequence Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
113
119
132
133
134
134
134
134
135
135
135
136
139
145
154
165
167
Chapter 7
Double Data Rate-II SDRAM (DDR-II SDRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V1.0 Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR-II SDRAMs Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V2.0 Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization Sequence Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
169
169
169
169
169
170
170
171
173
174
176
178
187
189
190
190
190
190
191
191
192
196
201
204
221
222
Table of Contents
Chapter 8
Gigabit Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gigabit Media Independent Interface (GMII). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reduced Gigabit Media Independent Interface (RGMII). . . . . . . . . . . . . . . . . . . . . . . . . .
Media Independent Interface (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reduced Media Independent Interface (RMII). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 Gigabit Media Independent Interface (XGMII). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40/100 Gigabit Media Independent Interface (XLGMII/CGMII) . . . . . . . . . . . . . . . . . . .
1000BASE-X Ten bit Interface (TBI) between PCS and PMA . . . . . . . . . . . . . . . . . . . . .
Reduced Ten bit Interface (RTBI) between PCS and PMA . . . . . . . . . . . . . . . . . . . . . . . .
10 Gigabit Attachment Unit Interface (XAUI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XAUI Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 Gigabit Sixteen Bit Interface (XSBI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40G/100G Attachment Unit Interface (XLAUI, CAUI). . . . . . . . . . . . . . . . . . . . . . . . . . .
40G or 100G Auto Negotiation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Control Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
223
223
224
224
224
224
225
225
225
226
226
226
227
227
227
228
228
229
229
229
230
238
249
249
250
251
251
252
252
253
253
254
255
255
256
256
285
287
Chapter 9
High-Definition Multimedia Interface (HDMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
289
289
289
289
290
291
292
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HDMI Monitor Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Coverage Count Totals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
295
296
297
303
307
Chapter 10
I2C (Inter-IC) Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Monitor Instantiation Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Master Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Slave Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Master/Slave Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assertion Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
309
309
310
310
311
313
313
313
314
314
315
318
319
320
320
321
321
Chapter 11
Low Pin Count (LPC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
323
323
323
323
323
324
325
326
329
329
Chapter 12
Open Core Protocol (OCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Response Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Threads and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
331
331
331
331
331
331
331
332
332
332
Table of Contents
Data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sideband Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCP Disconnect Proposal Revision 0.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Modification is Required for OCP 2.1 Users. . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Modification is Required for OCP 2.1 and 2.2 Users . . . . . . . . . . . . . . . . . .
Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
332
332
332
333
333
333
334
338
340
350
352
352
354
356
395
397
Chapter 13
Peripheral Component Interconnect (PCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initiator (Master) Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Target Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Top-level Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
399
399
399
399
400
402
402
403
404
407
412
414
414
Chapter 14
PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIPE Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity (PIPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity Notes (PIPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters (PIPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
415
415
415
415
418
418
418
421
423
424
427
429
431
433
435
Table of Contents
Instantiation Examples (PIPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Link Layer Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transaction Layer Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIPE Interface Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compliance Rules Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Checks Not Performed by the Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Gen2 Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Gen2 Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor FAQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
438
442
442
458
466
487
493
504
505
613
615
616
617
619
Chapter 15
Serial Attached SCSI (SAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connecting Clocks in Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Recovery Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMP, SSP and STP Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor FAQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
623
623
623
623
624
624
626
630
630
635
635
637
638
639
640
640
642
642
647
659
662
663
664
Chapter 16
SERIAL ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
671
671
671
671
672
673
676
Table of Contents
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power on Sequence Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phy Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAPIS Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Layer Normal and Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transport Layer Normal and Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor FAQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
680
683
683
686
688
700
707
708
711
714
Chapter 17
Serial Parallel Interface (SPI) Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Monitor Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
719
719
719
719
719
720
721
721
722
Chapter 18
System Packet Interface Level 4 Phase 2 (SPI4-2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
723
723
723
724
724
724
728
730
734
741
741
743
743
743
747
749
749
750
751
753
759
760
10
Table of Contents
Chapter 19
Universal Serial Bus 2.0 (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 Monitor Instantiated on the Host or Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 (Standard) Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 UTMI Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 ULPI Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 Standard Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 UTMI Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 ULPI Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
761
761
761
762
763
763
764
764
765
767
768
768
769
770
770
772
774
779
781
781
782
783
788
790
790
804
824
846
849
Appendix 20
QVL Defines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Defines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Global Defines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Defines Common to All Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
851
851
851
852
End-User License Agreement
11
List of Examples
Example 2-1. Verilog AHB Master Monitor Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Example 2-2. VHDL AHB Master Monitor Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Example 2-3. Binding an Assertion Module to the DUT in SVA . . . . . . . . . . . . . . . . . . . . . 31
Example 2-4. Verilog Simulator Argument Sample File. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Example 3-1. AHB Master Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Example 3-2. AHB Target Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Example 3-3. APB Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Example 4-1. AMBA 3 APB Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Example 5-1. AMBA AXI Monitor Instantiation for Example 1 . . . . . . . . . . . . . . . . . . . . . 79
Example 5-2. AMBA AXI Monitor Instantiation for Example 2 . . . . . . . . . . . . . . . . . . . . . 81
Example 6-1. DDR SDRAM Monitor Instantiated in the Controller . . . . . . . . . . . . . . . . . . 113
Example 6-2. Two DDR SDRAM Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Example 6-3. DDR SDRAM Monitor Instantiated in the Controller . . . . . . . . . . . . . . . . . . 116
Example 6-4. DDR SDRAM Monitor Instantiated with NON JEDEC Timing Parameter Values
117
Example 6-5. DDR SDRAM 2.0 Monitor Instantiated in the Controller . . . . . . . . . . . . . . . 145
Example 6-6. Two DDR SDRAM 2.0 Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Example 6-7. DDR SDRAM 2.0 Monitor Instantiated in the Controller . . . . . . . . . . . . . . . 149
Example 6-8. DDR SDRAM 2.0 Monitor Instantiated with NON JEDEC Timing Values
Configured Through Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Example 6-9. DDR SDRAM 2.0 Monitor Instantiated with NON JEDEC Timing Values
Configured Through Input Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Example 7-1. DDR-II SDRAM 1.0 Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Example 8-1. 1 Gigabit Ethernet GMII Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . 249
Example 8-2. Reduced Gigabit Ethernet RGMII Monitor Instantiation . . . . . . . . . . . . . . . . 250
Example 8-3. 10/100M Gigabit Ethernet MII Monitor Instantiation . . . . . . . . . . . . . . . . . . 251
Example 8-4. 10/100M Gigabit Ethernet RMII Monitor Instantiation . . . . . . . . . . . . . . . . . 251
Example 8-5. 10 Gigabit Ethernet XGMII Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . 252
Example 8-6. 40/100 Gigabit Ethernet XLGMII/CGMII Monitor Instantiation. . . . . . . . . . 252
Example 8-7. 1000BASE-X TBI Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Example 8-8. Reduced Ten bit Interface Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Example 8-9. 10 Gigabit Ethernet XAUI Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . 254
Example 8-10. 10 Gigabit Ethernet XSBI Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . 255
Example 8-11. 100 Gigabit Ethernet CAUI Monitor Instantiation . . . . . . . . . . . . . . . . . . . . 255
Example 8-12. 100 Gigabit Ethernet Auto-Negotiation Monitor Instantiation . . . . . . . . . . . 256
Example 9-1. HDMI Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Example 10-1. I2C Master Monitor Instantiation for a Master Only Design . . . . . . . . . . . . 314
12
List of Examples
Example 10-2. I2C Slave Monitor Instantiation for a Slave Only Design . . . . . . . . . . . . . .
Example 10-3. I2C Master/Slave Monitor Instantiation for a Master/Slave Design. . . . . . .
Example 11-1. LPC Monitor Instantiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 12-1. OCP Monitor Instantiation for Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 12-2. OCP Monitor Instantiation for Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 13-1. PCI Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 14-1. PCI Express Monitor Instantiation Example 1 . . . . . . . . . . . . . . . . . . . . . . .
Example 14-2. PCI Express Monitor Instantiation Example 2 . . . . . . . . . . . . . . . . . . . . . . .
Example 14-3. PCI Express Gen2 Monitor Instantiation Example 3 . . . . . . . . . . . . . . . . . .
Example 14-4. PIPE Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 14-6. PIPE Monitor Instantiation Example 3 (9Bit Mode). . . . . . . . . . . . . . . . . . .
Example 15-1. SAS Monitor Within an SAS Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 15-2. SAS Monitor Within an Expander Device . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 15-3. SAS Monitor Within a SAS Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 15-4. SAS Monitor Within an Expander Device . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 15-5. Clock Recovery Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 16-1. SATA Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 16-3. SATA Monitor Instantiation for Example 3 . . . . . . . . . . . . . . . . . . . . . . . . .
Example 17-1. SPI Monitor Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 18-1. SPI4-2 Receive Monitor Instantiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 18-4. SPI4-2 Transmit Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 19-1. USB Monitor on the Downstream Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 19-2. USB Monitor on the Upstream Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 19-3. USB Monitor to Track an 8-bit UTM Interface . . . . . . . . . . . . . . . . . . . . . .
Example 19-5. USB Monitor to Track an 4-bit ULP Interface . . . . . . . . . . . . . . . . . . . . . . .
314
314
325
352
354
403
427
428
429
438
439
440
441
636
637
638
639
642
680
681
682
682
721
731
732
733
749
751
752
768
769
779
780
788
789
13
List of Figures
Figure 2-1. RTL Signals and Tri-State Buffer (I/O Structure) . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-1. AHB-Based System Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-2. APB-Based System Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-3. AHB Master Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-4. AHB Target Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-5. APB Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-1. AMBA 3 APB Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5-1. AMBA AXI Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5-2. AMBA AXI Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-1. DDR SDRAM System Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-2. DDR SDRAM Monitor Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-3. Stacking DDR SDRAMs by Data Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-4. Stacking DDR SDRAMs by Address Width . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-5. DDR SDRAM System Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-6. DDR SDRAM 2.0 Monitor Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-1. DDR-II SDRAM 1.0 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-2. DDR-II SDRAM 1.0 Monitor Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-3. Stacking DDR-II SDRAMs by Data Width . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-4. Stacking DDR-II SDRAMs by Address Width . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-5. DDR-II SDRAM 2.0 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-6. DDR-II SDRAM 2.0 Monitor Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8-1. Gigabit Ethernet Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8-2. Gigabit Ethernet Monitor Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 9-1. HDMI Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 9-2. HDMI Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-1. I2C System Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-2. I2C Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-3. I2C Master Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-4. I2C Slave Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-5. I2C Master/Slave Monitor Pins Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-1. LPC Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-2. LPC Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-1. OCP Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-2. OCP Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-3. OCP Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-1. PCI Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-2. PCI Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-1. PCI Express Gen1 Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-2. PCI Express Gen2 Monitor Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-3. PCI Express Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
40
42
42
43
52
62
67
74
75
105
106
108
108
136
137
171
171
173
173
192
193
230
231
290
291
309
310
311
311
311
323
324
338
340
341
399
400
419
420
421
List of Figures
Figure 14-4. Gen1 PIPE Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 14-5. Gen2 PIPE Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-6. PIPE Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15-1. SAS Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15-2. SAS Monitor (dynamic timer values) Implementation . . . . . . . . . . . . . . . . . .
Figure 15-3. SAS Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15-4. Connecting Clocks in Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15-5. Connecting Clock Recovery Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15-6. Examples of Single- and Multi-PHY Devices . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 16-1. SATA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 16-2. SATA Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17-1. SPI Monitor Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17-2. SPI Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18-1. SPI4-2 Receive Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18-2. SPI4-2 Receive Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18-3. SPI4-2 Transmit Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18-4. SPI4-2 Transmit Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-1. USB 2.0 Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-2. USB 2.0 (standard) Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-3. USB 2.0 UTMI Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-4. USB 2.0 ULPI Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
430
430
431
625
626
627
640
641
664
673
674
720
720
724
725
743
744
764
765
770
781
15
List of Tables
Table 1-1. Conventions for Command Line Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-1. AHB Master Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-2. AMBA AHB Master Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-3. AMBA AHB Master Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-4. AMBA AHB Master Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-5. AMBA AHB Master Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-6. AHB Target Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-7. AMBA AHB Target Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-8. AMBA AHB Target Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-9. AMBA AHB Target Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-10. AMBA AHB Target Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-11. APB Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-12. AMBA APB Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-13. AMBA APB Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-14. AMBA APB Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-15. AMBA APB Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4-1. AMBA 3 APB Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4-2. AMBA 3 APB Monitor Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4-3. AMBA 3 APB Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4-4. AMBA 3 APB Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4-5. AMBA 3 APB Protocol Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-1. AMBA AXI Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-2. AMBA AXI Monitor Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-3. AMBA AXI Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-4. AMBA AXI Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-5. AMBA AXI Protocol Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-1. DDR SDRAM Monitor Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-2. DDR SDRAM Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-3. JEDEC Mode Burst Length Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-4. JEDEC Mode CAS Latency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-5. JEDEC Standard Compliant Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-6. DDR SDRAM Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-7. DDR SDRAM Monitor Checks for Each Bank . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-8. Calculate Minimum Delay From a Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-9. DDR SDRAM Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-10. DDR SDRAM Monitor Corner Cases Maintained for Each Bank . . . . . . . . . .
Table 6-11. DDR SDRAM Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-12. DDR SDRAM Monitor Statistics Maintained for Each Bank . . . . . . . . . . . . . .
Table 6-13. DDR SDRAM 2.0 Monitor Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-14. DDR SDRAM 2.0 Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
43
44
46
50
51
52
53
55
60
61
62
63
64
65
65
68
68
69
71
71
75
77
82
99
102
106
108
112
112
113
119
123
131
132
132
133
133
137
140
16
List of Tables
Table 6-15. JEDEC Mode Burst Length Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6-16. JEDEC Mode CAS Latency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-17. JEDEC Compliant Min. Timing for DDR SDRAM Speed Grade 266 . . . . . . .
Table 6-18. DDR SDRAM 2.0 Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank . . . . . . . . . . . . . . . . . . . . .
Table 6-20. Calculate Minimum Delay From a read/Write . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-21. DDR SDRAM 2.0 Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-22. DDR SDRAM 2.0 Monitor Corner Cases Maintained for Each Bank . . . . . . .
Table 6-23. DDR SDRAM 2.0 Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-24. DDR SDRAM 2.0 Monitor Statistics Maintained for Each Bank . . . . . . . . . . .
Table 7-1. DDR-II SDRAM 1.0 Monitor Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-2. DDR-II SDRAM 1.0 Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-3. JEDEC Standard Compliant Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-4. Checks Performed by a DDR-II SDRAM 1.0 Monitor . . . . . . . . . . . . . . . . . . . .
Table 7-5. DDR-II SDRAM 1.0 Monitor Bank Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-6. DDR-II SDRAM 1.0 Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-7. DDR-II SDRAM 1.0 Bank Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-8. DDR-II SDRAM 1.0 Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-9. DDR-II SDRAM 1.0 Bank Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-10. DDR-II SDRAM 2.0 Monitor Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-11. DDR-II SDRAM 2.0 Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-12. JEDEC Standard Compliant Timing for DDR2 400 Speed Grade . . . . . . . . . .
Table 7-13. DDR-II SDRAM 2.0 Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-14. DDR-II SDRAM 2.0 Monitor Bank Checks . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-15. DDR-II SDRAM 2.0 Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-16. DDR-II SDRAM 2.0 Bank Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-17. DDR-II SDRAM 2.0 Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-18. DDR-II SDRAM 2.0 Bank Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-1. GMII Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-2. RGMII Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-3. MII Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-4. RMII Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-5. XGMII Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-6. XLGMII/CGMII Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-7. 1000BASE-X Ten bit Interface Monitor Pin Descriptions . . . . . . . . . . . . . . . . .
Table 8-8. Reduced Ten bit Interface Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . .
Table 8-9. XAUI Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-10. XSBI Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-11. XLAUI/CAUI Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-12. 40/100G Auto-Negotiation Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . .
Table 8-13. GMII Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-14. RGMII Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-15. MII Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-16. RMII Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-17. XGMII Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
144
144
145
154
158
165
165
166
167
167
172
174
176
178
181
187
188
189
189
194
196
201
204
212
221
221
222
222
232
232
233
233
234
234
234
235
235
236
236
237
238
238
239
240
241
17
List of Tables
Table 8-18. XLGMII/CGMII Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 8-19. TBI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-20. RTBI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-21. XAUI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-22. XSBI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-23. XLAUI/CAUI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-24. 40/100G Auto-Negotiation Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-25. MAC Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-26. GMII Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-27. RGMII Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-28. MII Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-29. RMII Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-30. XGMII Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-31. XLGMII/CGMII Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-32. TBI Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-33. XAUI Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-34. BASER Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-35. XLAUI/CAUI Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-36. 40/100G Auto-Negotiation Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-37. Gigabit Ethernet Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-38. Gigabit Ethernet Protocol Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-1. HDMI Monitor Pins Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-2. HDMII Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-3. Verilog and SystemVerilog Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-4. HDMI Data Channel Unknown Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-5. HDMI Data Integrity Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-6. HDMI Protocol Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-7. HDMI Programming Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-8. HDMI Cover Basic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-9. HDMI Cover Corner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-10. HDMI Packet Cover Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-11. HDMI Programming Cover Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-12. Coverage Count Totals for HDMI 1.3a Monitor . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-13. Statistics Count Totals for HDMI 1.3a Monitor . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-1. I2C Monitor PINs Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-2. I2C Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-3. I2C Master Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-4. I2C Slave Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-5. I2C Assertion Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-6. I2C Master Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-7. I2C Master Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-8. I2C Slave Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-9. I2C Slave Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-1. LPC Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-2. LPC Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
242
242
243
244
245
246
247
258
261
263
265
268
269
272
273
275
280
282
283
285
287
291
292
296
297
297
298
300
303
303
304
305
307
308
312
313
315
318
319
320
320
321
321
324
324
List of Tables
Table 11-3. LPC Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 11-4. LPC Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-5. LPC Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12-1. OCP Monitor Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12-2. OCP Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12-3. OCP Monitor Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12-4. OCP Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12-5. OCP Protocol Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13-1. PCI Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13-2. PCI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13-3. PCI Initiator Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13-4. PCI Target Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13-5. PCI Top-Level Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13-6. PCI Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13-7. PCI Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-1. PCI Express Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-2. PCI Express Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-3. PIPE Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-4. PIPE Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-5. PCI Express Monitor Physical Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-6. Link Training and Width Negotiation Checks . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-7. PCI Express Monitor Data Link Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks . . . . . . . . . . . . . . . .
Table 14-9. PCI Express Monitor Power Management Checks . . . . . . . . . . . . . . . . . . . . . .
Table 14-10. Receive Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-11. PIPE Interface Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-12. PCI Express Gen2 Physical Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-13. PCI Express Gen2 Link Training and Width Negotiation Checks . . . . . . . . .
Table 14-14. PCI Express Gen2 Transaction Layer Transmit Checks . . . . . . . . . . . . . . . .
Table 14-15. PCI Express Gen2 Power Management Checks . . . . . . . . . . . . . . . . . . . . . . .
Table 14-16. PCI Express Gen2 PIPE Interface Checks . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-17. PCI Express Compliance Checklist: Topology . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-18. PCI Express Compliance Checklist: Transaction Protocol . . . . . . . . . . . . . . .
Table 14-19. PCI Express Compliance Checklist: Link Protocol . . . . . . . . . . . . . . . . . . . . .
Table 14-20. PCI Express Compliance Checklist: Link-Physical Layer Interface . . . . . . . .
Table 14-21. PCI Express Compliance Checklist: Electrical . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-22. PCI Express Compliance Checklist: Power Management . . . . . . . . . . . . . . . .
Table 14-23. PCI Express Compliance Checklist: System Architecture . . . . . . . . . . . . . . .
Table 14-24. PCI Express Compliance Checklist: Configuration . . . . . . . . . . . . . . . . . . . .
Table 14-25. PCI Express Compliance Checklist: Isochronous Applications . . . . . . . . . . .
Table 14-26. PCI Express Compliance Checklist: Electromechanical . . . . . . . . . . . . . . . . .
Table 14-27. Checklist Applicable for End Point Only . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-28. Checklist Applicable for Root Complex Only . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-29. Checklist Applicable for Switch Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-30. Physical Layer Corner Cases Maintained by the PCI Express Monitor . . . . .
326
329
329
341
350
356
395
397
400
402
404
407
412
414
414
421
424
431
435
442
449
458
466
487
491
493
497
498
501
503
504
506
506
530
538
567
567
572
573
573
574
574
589
601
613
19
List of Tables
Table 14-31. Data Link Layer Corner Cases Maintained by the PCI Express Monitor . . . .
Table 14-32. Transaction Layer Corner Cases Maintained by the PCI Express Monitor . .
Table 14-33. Physical Layer Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-34. Data Link Layer Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-35. Transaction Layer Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-36. Physical Layer Corner Cases PCI Express Monitor Gen2 . . . . . . . . . . . . . . .
Table 14-37. Data Link Layer Corner Cases PCI Express Monitor Gen2 . . . . . . . . . . . . . .
Table 14-38. Transaction Layer Corner Cases PCI Express Monitor Gen2 . . . . . . . . . . . . .
Table 14-39. Physical Layer Statistics PCI Express Monitor Gen2 . . . . . . . . . . . . . . . . . . .
Table 14-40. Data Link Layer Statistics PCI Express Monitor Gen2 . . . . . . . . . . . . . . . . . .
Table 14-41. Transaction Layer Statistics PCI Express Monitor Gen2 . . . . . . . . . . . . . . . .
Table 15-1. SAS Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-2. SAS Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-3. SAS Monitor (dynamic timer values) Parameters . . . . . . . . . . . . . . . . . . . . . . .
Table 15-4. Clock Recovery Module Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-5. SAS Monitor Physical Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-6. SAS Monitor Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-7. SMP Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-8. SSP Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-9. STP Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-10. SAS Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-11. SAS Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-12. Bit Order for TX and RX Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-1. SATA - Serial and parallel 10B Interface Monitor Pins . . . . . . . . . . . . . . . . . .
Table 16-2. SAPIS Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-3. SATA Monitor Parameters - Serial / Parallel10B Interfaces . . . . . . . . . . . . . .
Table 16-4. SATA Monitor Parameters - SAPIS Interface . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-5. Power on Sequence Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-6. Phy Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-7. Link Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-8. Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-9. SAPIS Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-10. Link Layer Normal Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-11. Link Layer Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-12. Transport Layer Normal Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-13. Transport Layer Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 17-1. SPI Monitor Pins Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 17-2. SPI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 17-3. SPI Master Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-1. SPI4-2 Receive Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-2. SPI4-2 Receive Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-3. SPI4-2 Receive Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-4. SPI4-2 Receive Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-5. SPI4-2 Receive Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-6. SPI4-2 Transmit Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
613
614
615
615
615
616
617
617
617
618
618
628
630
633
641
642
647
659
660
661
662
663
665
674
675
676
678
683
686
688
700
707
708
709
711
711
720
721
722
725
728
734
741
741
744
List of Tables
Table 18-7. SPI4-2 Transmit Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 18-8. SPI4-2 Transmit Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-9. SPI4-2 Transmit Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-10. SPI4-2 Transmit Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-1. USB 2.0 (standard) Monitor Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-2. USB 2.0 Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-3. USB 2.0 UTMI Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-4. USB 2.0 UTMI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-5. USB 2.0 ULPI Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-6. USB2.0 ULPI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-7. USB 2.0 Standard Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-8. USB 2.0 UTMI Monitor UTMI Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-9. USB 2.0 UTMI Monitor USB 2.0 Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-10. USB 2.0 ULPI Monitor ULPI Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-11. USB 2.0 ULPI Monitor USB 2.0 Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-12. USB 2.0 Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-13. USB 2.0 Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
747
753
759
760
765
767
770
774
781
783
790
804
812
824
835
846
849
21
List of Tables
22
Chapter 1
Introduction
Syntax Conventions
This manual uses the following command usage line syntax conventions.
Table 1-1. Conventions for Command Line Syntax
Convention
Example
Usage
Boldface
SET COMmand Editing

A boldface font indicates a required argument.
-Off | -Vi | -Emacs | -Gmacs
[ ]
EXIt [-Discard]
Square brackets enclose optional arguments. Do

not enter the brackets.
Italic
DOFile filename
An italic font indicates a user-supplied

argument.
{ }
ADD LFsrs lfsr_name

{Prpg | Misr} length seed
[-Out | -In]
Braces enclose arguments to show grouping. Do

not enter the braces.
ADD LFsrs lfsr_name

{Prpg | Misr} length seed
[-Out | -In]
The vertical bar indicates an either/or choice

between items. Do not include the bar in the
command.
ADD LFsr Connections

primary_pin lfsr_name
position
An ellipsis follows an argument that may appear

more than once. Do not include the ellipsis when
entering commands.
The following examples demonstrate these syntax conventions.

signal
One or more occurrences of signal.
[-var req_signal]
Zero or one occurrences of -var

req_signal.
-var {req_signal}
-var followed by one or more occurrences

of req_signal.
[std_option]
Zero or more occurrences of std_option.
23
Introduction
Mentor Graphics Support
{arg1 arg2}
One or more occurrences of arg1 arg2.
var1 | var2 | var3
One occurrence of var1or var2 or var3.
constant | val1 val2
One occurrence of constant or val1 val2.
{[var1][var2][var3]}
Zero or more occurrences of any of var1,

var2, and var3.
Mentor Graphics Support

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24
Chapter 2
QVL Monitors Basics
The Questa Verification Library Monitors (QVL monitors) is a set of monitors that validate
specific industry-standard interface protocols and verify specific interface behaviors.
The QVL monitors are supported by the 0-In Formal Verification tool suite. In addition, the
QVL monitors are licensed for the Questa product.
Interface protocol monitors are modules that include QVL assertion checkers. A monitor
performs its verification functions using checkers embedded in the monitor itself. The monitor
is, in essence, a compound checker. QVL monitors are instantiated directly by identifying the
connections to the monitor inputs.
QVL monitors are SystemVerilog components that are wired to probe your design during
simulation and do the following as simulation progresses:
They warn of violations of the interface protocol through SystemVerilog assertion

failures.
They accumulate and maintain cover point data relevant to the protocol.
A QVL monitor can be configured to act as a formal constraint. Here, specific protocol rules are
turned into constraints (with the SystemVerilog assume construct) that constrain the formal
engines to restrict analysis to states that do not violate the monitors interface protocol.
QVL Use Model

The appropriate placement of the QVL monitor in the simulation environment depends on the
standard protocol being verified. Refer to the specific monitor in this manual for the
recommended monitor placement in your design.
Following are the steps to use QVL monitors:
1. Specifying Global Defines on page 26
2. Instantiate QVL Monitors on page 28
3. Compile QVL Monitor Libraries on page 32
4. Compile and Simulate the DUT with the QVL Monitor on page 33
5. Verify and Troubleshoot the QVL Monitor Setup on page 34
6. Review and Debug Simulation QVL Monitor Results on page 35
25
QVL Monitors Basics

QVL Use Model
7. QVL Monitor Coverage on page 36

8. Run Formal Verification with QVL on page 39
Specifying Global Defines

You specify preferred control settings with standard global defines in either of the following
ways:
Specify settings using the standard +define options in the simulation argument file or at
the command line.
Specify settings in a Verilog file loaded before the libraries.

Note
If you reference QVL_ defines in a Verilog file, you should have a `include
"<qvl_install_dir>/qvl_src/qvl_checkers/std_qvl_defines.h" statement in the file.
Otherwise, you must specify the -mfcu option to vlog.
Enabling Assertion and Coverage Logic

The QVL consists of two types of logic: assertion logic and coverage logic. These capabilities
are enabled by defining the following standard global defines:
QVL_ASSERT_ON
Activates QVL assertion logic. Default: not defined.
QVL_COVER_ON
Activates QVL coverage logic. Default: not defined.
If neither of these constants is defined, then the QVL checkers are not activated. The
instantiations of these checkers has no influence on the verification performed.
Following is an example of using global defines:
vlog +define+QVL_ASSERT_ON+QVL_COVER_ON ...
Creating Cover Groups

By default, when QVL coverage logic is enabled (by specifying QVL_COVER_ON),
SystemVerilog cover groups are created. To disable cover groups, specify the following global
macro:
QVL_SV_COVERGROUP_OFF
26
Disables creation of SystemVerilog covergroup logic. Default:

not defined.
QVL Monitors Basics

QVL Use Model
Displaying Final Coverage Information

When QVL coverage logic is enabled (by specifying QVL_COVER_ON), accumulated cover point
data can be displayed for each QVL checker and monitor at the end of simulation. For example,
the following output shows a sample AMBA AHB Master Monitor final coverage information:
----------------- Coverage for AMBA AHB Master Monitor ---------------Monitor instance
: ahb_master_tb.DUT.mas_mon
----------------- Statistics for AMBA AHB Master Monitor -------------Total Transfers
: 3324
----------------- Cornercases for AMBA AHB Master Monitor ------------Read Transfers
: 1274
Write Transfers
: 1517
IDLE Transfers
: 222
BUSY Transfers
: 311
OKAY Responses
: 3210
ERROR Responses
: 19
RETRY Responses
: 45
SPLIT Responses
: 50
SINGLE Burst Type
: 47
INCR Burst Type
: 112
WRAP4 Burst Type
: 51
INCR4 Burst Type
: 85
WRAP8 Burst Type
: 67
INCR8 Burst Type
: 115
WRAP16 Burst Type
: 960
INCR16 Burst Type
: 1354
Byte (8 bits) Transfer Size
: 100
Half Word (16 bits) Transfer Size
: 84
Word (32 bits) Transfer Size
: 2607
Double Word (64 bits) Transfer Size : 0
4 Word (128 bits) Transfer Size
: 0
8 Word (256 bits) Transfer Size
: 0
512 Bits Transfer Size
: 0
: 0
By default, final coverage information is displayed for monitors, but not for checkers. To
change this behavior, specify one or both of the following global defines:
QVL_CW_FINAL_COVER
Turns on the display of final coverage information for QVL

checkers. Default: final coverage not displayed.
QVL_MW_FINAL_COVER_OFF
Turns off the display of final coverage information for QVL

monitors. Default: final coverage is displayed.
X/Z Checks
Assertion checkers can produce indeterminate results if a checker port value contains an X or Z
bit when the checker samples the port. (Note that a checker does not necessarily sample every
port at every active clock edge.) To assure determinate results, QVL monitors have special
assertions for X/Z checks (see Global Defines on page 851).
27
QVL Monitors Basics

QVL Use Model
By default, QVL assertion checker logic includes logic implementing assertion checks for X
and Z bits in the values of checker ports when they are sampled. To exclude all X/Z checking
logic, specify the following global variable:
QVL_XCHECK_OFF
Turns off all X/Z checks.
Instantiation in an SVA Interface Construct

If QVL checkers are instantiated in a SystemVerilog interface construct, then define the
following global variable:
QVL_SVA_INTERFACE
Instantiates QVL assertion checkers in a SystemVerilog interface

construct. Default: not defined.
Resolving Race Conditions at QVL Inputs

By default, the input signals of QVL monitors are sampled directly. In some cases, this results
in race conditions on the sampled data. To resolve this problem, define the following global
variable:
QVL_RACE_AVOID
Adds one resolution unit of delay (that is, Verilog #1) to all QVL
input signals. Default: zero delay.
Instantiate QVL Monitors

To instantiate a QVL monitor into a design, it is easiest to cut and paste the monitor
instantiation from the associated template. The template lists the instances available ports on
the monitor and the available Verilog parameters or VHDL generics.
Starting from the QVL template, the user can modify the parameters or generic mapping as
appropriate, and also modify the port mapping to point to the relevant local signals.
Instance Templates Directory

Verilog and VHDL templates for the QVL monitors are located in the following directories,
respectively:
questasim_install_dir/qvl_src/templates/verilog/qvl_monitors/<monitor>
questasim_install_dir/qvl_src/templates/vhdl/qvl_monitors/<monitor>
Example 2-1 is a sample Verilog template and Example 2-2 is a sample VHDL template.
28
QVL Monitors Basics

QVL Use Model
Example 2-1. Verilog AHB Master Monitor Template

qvl_ahb_master_monitor #(
.Constraints_Mode(0),
.DATA_BUS_WIDTH(32),
.CANCEL_FOLLOWING_TRANSFER_ON_ERROR_RESPONSE(0),
.Over_Constraints_Mode(0),
.DISABLE_CHKS_ON_IDLE(0) )
qvl_ahb_master_monitor_instance (
.hgrantx(dut_hgrantx),
.hready(dut_hready),
.hresp(dut_hresp),
.hresetn(dut_hresetn),
.hclk(dut_hclk),
.hrdata(dut_hrdata),
.htrans(dut_htrans),
.haddr(dut_haddr),
.hwrite(dut_hwrite),
.hsize(dut_hsize),
.hburst(dut_hburst),
.hprot(dut_hprot),
.hwdata(dut_hwdata)
);
Example 2-2. VHDL AHB Master Monitor Template

qvl_ahb_master_monitor_instance: qvl_ahb_master_monitor
generic map(
Constraints_Mode => 0,
DATA_BUS_WIDTH => 32,
CANCEL_FOLLOWING_TRANSFER_ON_ERROR_RESPONSE => 0,
Over_Constraints_Mode => 0,
DISABLE_CHKS_ON_IDLE => 0)
port map (
hgrantx => dut_hgrantx,
hready => dut_hready,
hresp => dut_hresp,
hresetn => dut_hresetn,
hclk => dut_hclk,
hrdata => dut_hrdata,
htrans => dut_htrans,
haddr => dut_haddr,
hwrite => dut_hwrite,
hsize => dut_hsize,
hburst => dut_hburst,
hprot => dut_hprot,
hwdata => dut_hwdata
);
Adding Monitors to the Simulation Environment

A QVL monitor instance can be added to the simulation environment using any of the following
processes:
29
QVL Monitors Basics

QVL Use Model
Specify the QVL instance in the testbench or design under test (DUT). To make the
monitor visible only during simulation, use the following:
o
Verilog use an `ifdef.
VHDL use a conditional generate or an empty architecture.
Specify the QVL instance as a separate module, then use SVA bind to wire the monitor
signals to your DUT (see Example 2-3 on page 31 and SystemVerilog Bind on
page 32). SystemVerilog declares that by default, each file is a separate compilation
unit.
When bind is specified outside the module file that the program instance is being bound
to, the elaboration process does not recognize the dependency to the bound module and
the bind is not elaborated with the bound module. Therefore, you must use the -cuname
option to name the compilation unit. Then, specify the compilation unit name to vsim to
enable the bind statements to be elaborated, as shown in the following example:
vlog assertion_module.sv bind.v -cuname bind_cu
vsim top bind_cu
Specify the QVL instance in a PSL vunit, and then bind the vunit to the target module to
connect the signals from the target module to the monitor instance. Refer to the Questa
SV/AFV Users Manual, Chapter 18: Verification with Assertions and Cover Directives
for detailed information. This manual is available on the Mentor Graphics SupportNet.
Specify the QVL instance in a separate module, and connect the DUT to the instances
ports using one of the following methods:
o
Verilog hierarchical reference in wire declaration example:

wire
wire
wire
wire [2:0]
clk
reset_n
wr_en
max
=
=
=
=
TB.DUT.clk;
TB.DUT.reset_n;
TB_DUT.wr_en;
TB.DUT.wr_hold_max;
VHDL signal spy example:

init_signal_driver
init_signal_driver
init_signal_driver
init_signal_driver
("/TB/DUT/clk", "/clk", open, open, 0);

("/TB/DUT/reset_n", "/reset_n", open, open, 0);
("/TB/DUT/wr_en", "/wr_en", open, open, 0);
("/TB/DUT/wr_hold_max", "/max", open, open, 0);
Whenever a signal spy command is used, the ModelSim library and package must be
specified as follows:
library modelsim_lib;
use modelsim_lib.util.all;
30
QVL Monitors Basics

QVL Use Model
Specify the instance as a SystemVerilog interface.
Set the +define+QVL_SVA_INTERFACE macro in the filelist.qvl file list or on the

simulator command line. For example:
vlog +define+QVL_SVA_INTERFACE...
This replaces the instances module keyword with the interface keyword.
Add the QVL instance to a ANSI port declaration. and use hierarchical port
references to wire the port signals to your DUT. For example:
module cpu_top (
qvl_pci_monitor pci_mon_if,
. . .
assign pci_mon_if.pci_ad_en_n
assign pci_mon_if.pci_cbe_en_n
= AD_enb;
= 1'b0;
Note that whenever a QVL monitor is instantiated in a VHDL design, the QVL library and the
QVL packages must be specified as follows:
library qvl_lib;
use qvl_lib.qvl_chechers.all;
use qvl_lib.qvl_monitors.all;
Exclude the QVL components from code coverage by adding source code pragmas (coverage
off/coverage on) around the QVL component instantiations as described in the Questa SV/AFV
Users Manual, chapter 16: Coverage.
Example 2-3. Binding an Assertion Module to the DUT in SVA
module assertion_module (clk, reset_n, wr_en, wr_hold_max);
input
clk;
input
reset_n;
input
wr_en;
input [2:0] wr_hold_max;
wire
qvl_clk
= clk;
wire
qvl_reset_n
= reset_n;
wire
qvl_wr_en
= wr_en;
wire [2:0] qvl_max
= wr_hold_max;
// include define file to allow use of QVL defines
include "std_qvl_defines.h"
qvl_change_timer #(
.severity_level(QVL_ERROR),
.property_type(QVL_ASSERT),
.msg("QVL_VIOLATION : "),
.coverage_level(QVL_COVER_ALL),
.width(1),
.min_check(1),
.max_check(1))
qvl_change_timer_instance(
31
QVL Monitors Basics

QVL Use Model
.clk(qvl_clk),
.reset_n(qvl_reset_n),
.active(1b1),
.test_expr(qvl_wr_en),
.max(qvl_max),
.min(1));
endmodule
// Bind assertion_module to DUT with implicit port connections (.* syntax)
module sample_bind;
bind DUT assertion_module bind_instance (.*);
endmodule
SystemVerilog Bind
Many users prefer to instantiate assertions without modifying their RTL. A common way to
define or instantiate assertions into a separate module is to define your assertions in a separate
assertion module and use SystemVerilog bind to wire the assertion (monitor) signals to your
design module:
1. Create a separate assertion module.
2. Instantiate assertions in assertion module.
Note: When using a signal or port from the targeted design module, the signal and port
names must be added to the assertion module port list. Use the same signal and port
name as the design module, so implicit port instantiation can be used with the
SystemVerilog bind.
3. Create the SystemVerilog bind instance to connect the assertion module to the target
module.
Compile QVL Monitor Libraries

VHDL simulation environments require a compiled version of the QVL checker/monitor
library. This step is optional for Verilog simulation environments. To compile a version of the
QVL library, modify and run the standard compile_qvl_lib C-shell script:
questasim_dir/qvl_src/bin/compile_qvl_lib
#!/bin/csh
# Compile QVL packages into qvl_lib
vlib qvl_lib
vcom -work qvl_lib questasim_dir/qvl_src/vhdl_pkgs/qvl_checkers.vhd
questasim_dir/qvl_src/vhdl_pkgs/qvl_monitors.vhd
# Compile Verilog QVL Checker components into qvl_lib
vlog -work qvl_lib +define+QVL_ASSERT_ON+QVL_COVER_ON
+incdir+questasim_dir/qvl_src/qvl_checkers
questasim_dir/qvl_src/qvl_checkers/*.sv
# Compile Verilog QVL Monitor components into qvl_lib
32
QVL Monitors Basics

QVL Use Model
foreach mon ( questasim_dir/qvl_src/qvl_monitors/* )
vlog -work qvl_lib +define+QVL_ASSERT_ON+QVL_COVER_ON
+incdir+questasim_dir/qvl_src/qvl_checkers
questasim_dir/qvl_src/qvl_checkers/std_qvl_defines.h +incdir+$mon
$mon/*.sv
end
To compile a protected (read-only) QVL library to be shared by your project team, add the
-novopt option to the vlog and vcom commands. Users can then compile simulation
environments both with, and without, vopt. Typically, questasim_dir is the same as the install
directory of the Questa executables. However, it can be the install directory of a later Questa
release (for example, if you are frozen into a particular Questa release, but want to use
features/enhancements of the later QVL release).
Caution
Starting with QVL 2009.1, QVL was decoupled from Questa releases. From this release
onward, QVL directs vlog to print the QVL version. However, when using QVL with
vlog version 6.5c (or earlier), you must specify +define+QVL_VERSION_PRINT_OFF
as a vlog argument to prevent a vlog error.
Compile and Simulate the DUT with the QVL Monitor

VHDL
Compile your simulation environment, as you would normally, using the QuestaSim vcom and
vlog commands. Then add references to the QVL library to your simulation arguments. For
example,
vsim <simulation_arguments> L qvl_lib
Run your vsim simulation command and the monitor is run in simulation in a similar way to
other SVA assertions.
Verilog
Add the QVL Verilog arguments to your Verilog compilation arguments. Example 2-4 shows a
sample simulator argument file that references the QVL checkers and the AMBA monitor. The
checkers are located in a single directory (qvl_src/qvl_checkers), but each monitor directory
must be specified separately (for example, qvl_src/qvl_monitors/amba,
qvl_src/qvl_monitors/axi, etc.). For example,
vlog <compile_arguments> -f filelist.qvl
In the QVL Monitors sections of the arguments filelist (see Example 2-4), update the -y and
+incdir options to refer to the appropriate monitor directories. By default, all QVL checkers are
specified through the -y option.
33
QVL Monitors Basics

QVL Use Model
Once the design and testbench are compiled, your vsim simulation command needs no
modifications. Run your vsim simulation command and the QVL components run in simulation
similar to other SVA assertions.
Example 2-4. Verilog Simulator Argument Sample File
// Command line switches
// `DEFINES
+define+QVL_ASSERT_ON
+define+QVL_COVER_ON
//+define+QVL_SV_COVERGROUP_OFF
//+define+QVL_CW_FINAL_COVER
//+define+QVL_MW_FINAL_COVER_OFF
//
//
//
//
//
// File extensions
+libext+.v
+libext+.sv
// Verilog wrapper files

// SystemVerilog wrapper files
Turn on QVL assertions

Turn on QVL coverage
Turn off SV cover groups
Display final checker cover info
Dont display final monitor cover info
// Include directories
// -- QVL checkers
+incdir+<questasim_install_dir>/qvl_src/qvl_checkers
// -- QVL monitors
+incdir+<questasim_install_dir>/qvl_src/qvl_monitors/amba
//
//
-y
//
-y
Library directories
-- QVL checkers
<questasim_install_dir>/qvl_src/qvl_checkers
-- QVL monitors
<questasim_install_dir>/qvl_src/qvl_monitors/amba
Verify and Troubleshoot the QVL Monitor Setup

The easiest way to check that you have correctly setup the QVL monitor in simulation is to
verify that the monitor is recognizing transactions on the protocol interface. The monitor
transactions are tracked in SystemVerilog covergroups and can be reviewed from the coverage
report (see Generate a Coverage Report on page 37).
If the monitor is not recognizing protocol transactions, then troubleshoot the setup are as
follows:
1. Check that the connections to the monitor as well as the monitor generics or parameters
are specified correctly. Check that the two monitor resets (asynchronous and
synchronous) are connected with the correct polarity. Typically, the designs reset signal
is connected to one reset and the other reset is tied to an inactive value.
2. View the resets and clocks in the simulation waveform for the monitor instance. Check
that the reset polarity is correct and the resets are de-asserting properly. Also, check that
the clock is toggling.
34
QVL Monitors Basics

QVL Use Model
3. View all connections to the monitor in the simulation waveforms for the monitor
instance. Check that the monitor signals are not unknown.
4. Recheck the monitor coverage. Verify that the protocol transactions exercised in
simulation are consistent with the transactions recorded by the monitor.
If you are still having setup problems, please send the following to support@mentor.com:
For Verilog designs, the QVL argument list.
QVL monitor instantiation, including generics or parameters.
QuestaSim compilation and simulation log files.
Waveforms that trace the monitor instance with debug access enabled. Use the
+acc vopt argument to enable debug command access to monitor objects (see View
and Debug QVL Monitor Protocol Violations on page 35).
Review and Debug Simulation QVL Monitor Results

Note that the assertion and coverage information is saved to the Unified Coverage Database
(UCDB) and is not saved to the wlf file.
QVL Monitor Protocol Violations Reporting

During simulation, the monitor protocol violations are written to the simulation log file. The
violation messages detail the time, instance, and violation description. Violation messages are
not generated for SVA assume properties that are constraints for formal verification.
View and Debug QVL Monitor Protocol Violations

From the QuestaSim viewer, the monitor protocol violations identified by the QVL monitor can
be reviewed by checking the Assertions tab in the Analysis window. This tab can be invoked
by selecting View > Coverage > Assertions. The enabled value in the Failure column
indicates that the failures are being tracked. The number of protocol violations can be viewed in
the Failure Count column.
To view the waveforms associated with a specific protocol violation, right-click on the
violation in the Assertions tab and select Add to Wave > Selected Objects.
Additionally, find the instance name of the violation in the Assertion tab and select the same
instance in the Workspace window. Right-click in the Objects window and select
Add to Wave > Signals in Region.
In order to view internal signals for the monitor, QuestaSim (vopt) global optimizations should
be disabled. The QuestaSim optimizations should be disabled during vopt using the +acc
option or during vsim using the +acc or -novopt options.
35
QVL Monitors Basics

QVL Use Model
Note that in order to run vsim with the -novopt option and with precompiled libraries, the
libraries must have been compiled with the -novopt option or a user must have write privileges
to the compiled libraries. If the library was not compiled with the -novopt option and the user
does not have write privileges to the compiled libraries, then vsim generates the vcom-19
(Failed to access library) error.
Following is an example for disabling QuestaSim optimizations during vopt for all instances of
a QVL monitor:
vopt +acc+qvl_amba_axi_monitor ...
Following is an example for disabling QuestaSim optimizations during vsim for all instances of
a QVL monitor:
vsim -voptargs="+acc+qvl_amba_axi_monitor" ...
Following is an example for disabling QuestaSim optimizations for the entire simulation
environment (note that it is not recommended to disable all optimizations):
vsim -novopt ...
Disable QVL Monitor Violations

The QVL monitors use SVA properties, so disabling violations is consistent with how
QuestaSim handles SVA properties.
From the QuestaSim command line, disable specific monitor violations using the
assertion fail command as follows (see the Questa AFV Users Manual):
assertion fail [-action {continue | break | exit}] [-enable | -disable]
[-limit {none |<count>}] [-log {on | off}] [-recursive] <path> [<path>...]
For example, if you receive the following error:

# ** Error: Assertion error.
#
Time: 140 ns Started: 140 ns Scope:
ahb_tb.ahb_master_mon.qvl_ahb_master.qvl_assume_ASSERT_NEVER.M_AHB_M17
File: /questasim/qvl_src/qvl_monitors/amba/qvl_ahb_master_monitor_assertions.inc
Line: 365
You can disable this error with the following command:

assertion fail -disable \
/ahb_tb/ahb_master_mon/qvl_ahb_master/qvl_assume_ASSERT_NEVER/M_AHB_M17 -r
QVL Monitor Coverage

The assertion and coverage information is saved to the UCDB and is not saved to the wlf file.
36
QVL Monitors Basics

QVL Use Model
Generate a Coverage Report

When running the QVL monitors in simulation, a text report of the assertion coverage results
can be generated. Use the vsim command coverage report to generate a text report of the
SystemVerilog and PSL assertion coverage. For example,
coverage report -details -file -coverage.rpt -r /*
For Verilog designs using $finish, the simulation might exit before the coverage report
command executes. Add vsim commands that prevent simulation exit and resume vsim
command execution. For example,
set NoQuitOnFinish 1;
onbreak {resume};
run -all;
coverage report -details -file -coverage.rpt -r /*
Refer to the Questa SV/AFV Reference Manual for information on the coverage command.
Save Coverage Results to a Database

Once the simulation has been run, the assertions and coverage results can also be viewed in the
QuestaSim viewer or saved to a Unified Coverage Database (UCDB) for later viewing. For
example,
coverage save coverage.ucdb
View a Coverage Database

Once the coverage information has been saved to a UCDB file, this file can be viewed by the
QuestaSim viewer. For example,
vsim -viewcov coverage.ucdb
View the Monitor Coverage and Statistics

From the QuestaSim viewer, coverage and statistics information specific to the QVL monitor
can be viewed by selecting the monitor instance in the Workspace window, then select
View > Coverage > Covergroups.
Disabling QVL Cover Points

The QVL checkers and monitors use SVA cover points to track coverage, so the mechanism for
controlling coverage collection is consistent with all SVA cover points in Questa. To turn off
specific cover points for a QVL checker, set their weights and goals to 0. For example, suppose
tb/dut contains the following qvl_fifo instantiation:
qvl_fifo #(
.severity_level(QVL_ERROR),
37
QVL Monitors Basics

QVL Use Model
.property_type(QVL_ASSERT),
.msg("QVL_VIOLATION : "),
.coverage_level(QVL_COVER_NONE),
.depth(2**DEPTH_POWER),
.width(WIDTH),
.pass(1),
.registered(1),
.high_water(15),
.full_check(1),
.empty_check(1),
.value_check(1),
.latency(0),
.preload_count(0))
fifo_valid(
.clk(CLK),
.reset_n(reset_n),
.active(1b1),
.enq(DIN_VALID),
.deq(rd_en_i),
.full(full_i),
.empty(empty_i),
.enq_data(din_un_i),
.deq_data(dout_un_i),
.preload(24b0));
The cover groups for the qvl_fifo checker type are defined in the following file:
questasim_dir/qvl_src/qvl_checkers/qvl_fifo_cover.svh
This file shows the Simultaneous Enqueues and Dequeues cover point is defined in the
fifo_cornercases cover group and has the name C3:
covergroup fifo_cornercases @ (posedge clock);
. . .
C3 : coverpoint
(!($stable(simultaneous_enq_deq, @ (posedge clock))))
iff (enable_coverpoint){
bins Simultaneous_Enqueues_and_Dequeues = {1};
type_option.comment = "Simultaneous Enqueues and Dequeues";
}
endgroup : fifo_cornercases
For this example, assume the logic driving the FIFO cannot produce a simultaneous
enqueue/dequeue. So, the fifo_cornercases.C3 cover point for fifo_valid always has coverage
0% and the maximum possible coverage for the fifo_cornercases cover group is 75% (i.e., at
most 3 out of 4 cover points can be hit).
The following code in tb disables the Simultaneous Enqueues and Dequeues cover point
(qvl_fifo_chx is the instance in the qvl_fifo module used to configure an internal version of the
checker):
initial begin
dut.fifo_valid.qvl_fifo_chx.fifo_cornercases.C3.type_option.goal = 0;
dut.fifo_valid.qvl_fifo_chx.fifo_cornercases.C3.type_option.weight = 0;
38
QVL Monitors Basics

Connectivity on the Bi-Directional/Tri-State Buffer Signals
end
Setting the cover point weight to 0 removes the cover point from the calculation of the coverage
for the parent cover group, so fifo_cornercases can attain 100% coverage. Setting the cover
point goal to 0 makes the % of goal measure for the cover point 100% (instead of 0%).
You should not disable all the cover points for a particular cover group. In this case, the weights
of all the cover groups cover points are 0. The calculation for cover group coverage divides by
the total weight of the cover points (in this case 0), which results in a NaN value for the
coverage.
Run Formal Verification with QVL

The QVL monitors are used as assumptions and assertion targets in formal verification (see the
0-In Formal Verification User Guide). The 0-In formal tool supports the inline specification,
SVA bind and PSL vunit methods of QVL monitor instantiation specified in Instantiate QVL
Monitors on page 28 (that is, it does not support hierarchical references and VHDL signal spy
connections).
QVL components are precompiled in the 0-In formal verification tool installation, so the user
does not need to compile the QVL libraries. To compile a DUT with QVL components, add the
-qvl option to the csl command line.
The following example compiles a SystemVerilog bind module with the DUT using single-step
compilation:
0in -cmd csl -d DUT DUT.v assertion_module.v bind.sv . . .
The following example compiles a SystemVerilog bind module with the DUT using 2-step
compilation:
0in -cmd analyze -vhdl DUT.vhdl -work work
0in -cmd analyze \
assertion_module.v bind.sv -cuname bind_cu -work work -qvl
0in -cmd csl -d DUT -cuname bind_cu -work work -qvl
Connectivity on the Bi-Directional/Tri-State

Buffer Signals
RTL designed for a shared BUS environment such as PCI, or for the point-to-point interfaces
such as DDR SDRAM and DDR2 SDRAM, there are many bi-directional signals on the
interface.
For such bi-directional signals, the RTL has three split signals with the following names:
<sig_name>_out/<sig_name>_out_n
39
QVL Monitors Basics

Connectivity on the Bi-Directional/Tri-State Buffer Signals
<sig_name>_out_en/<sig_name>_out_en_n
<sig_name>_in/<sig_name>_in_n
These signals are connected to the tri-state I/O structure on the final chip. To connect to the such
interfaces, the QVL monitors are also designed with split signals (see Figure 2-1 on page 40).
Following is the typical structure and the naming convention:
<sig_name>_out Output signals from the RTL, Active High.
<sig_name>_out_n Output signal from the RTL, Active Low.
<sig_name>_in Input signal to RTL, Active High.
<sig_name>_in_n Input signal to the RTL, Active Low.
<sig_name>_out_en Output enable; output signal from the RTL, Active High.
<sig_name>_out_en_n Output enable; output signal from the RTL, Active Low.
<sig_name> Shared bus signal.

Figure 2-1. RTL Signals and Tri-State Buffer (I/O Structure)
Monitor
<sig_name>_out
<sig_name>_out_en
<sig_name>_in
Tri-State Buffer
<sig_name>_out
<sig_name>
RTL
<sig_name>_out_en
<sig_name>_in
40
Chapter 3
Advanced Microcontroller Bus Architecture
(AMBA)
Introduction
The Advanced Microcontroller Bus Architecture (AMBA), from ARM Limited, is an on-chip
communications standard for designing high-performance embedded microcontrollers. There
are three distinct buses defined within the AMBA specification: Advanced High-performance
Bus, Advanced System Bus, and Advanced Peripheral Bus.
QVL monitors are available for the following:
Advanced High-performance Bus (AHB)
Advanced Peripheral Bus (APB)
Note the following:
AHB monitors are compatible with AHB-Lite, and they also can be used in multilayer
interconnection schemes.
The AHB monitor(s) cannot be used with the ASB.
Reference Documentation
This version of the QVL AMBA monitor is modeled from the requirements provided in the
following documents:
AMBA Specification, Rev 2.0, May 13, 1999, Issue A, ARM IHI0011A.
AMBA FAQ, January 23, 2001.
AHB Monitors
The Advanced High-performance bus (AHB) protocol defines communication between master
and target devices. A typical AHB system design contains the following components: master,
target, arbiter, and decoder. QVL monitors are available for the AHB master and AHB target
components.
Examples of AHB masters are: high-performance ARM processors, DMA bus masters, and so
on. Examples of AHB targets are: high-bandwidth memory interfaces, high-bandwidth on-chip
41
Advanced Microcontroller Bus Architecture (AMBA)

APB Monitor
RAMs, and so on. The APB bridge is also a target on the AHB bus. Figure 3-1 illustrates a
block diagram of an AHB-based system.
Figure 3-1. AHB-Based System Implementation
AHB Master
AHB Target
AHB
Bridge
AHB Bus
AHB Target
AHB Master
APB Monitor
AMBA Advanced Peripheral Bus (APB) is for low power peripherals. AMBA APB is
optimized for minimal power consumption and reduced interface complexity to support
peripheral functions. APB can be used in conjunction with the AHB system bus. The devices on
the APB bus are lower bandwidth peripheral devices such as UARTs, Timers, parallel I/O ports,
etc. Figure 3-2 illustrates a block diagram of an AHB-based system.
Figure 3-2. APB-Based System Implementation
Device 2
Device 1
Bridge
APB Bus
AHB Bus
Device 3
The APB monitor can be instantiated in the
bridge to specify targets and constraints while
searching the bridge. The AHB interface must
be constrained to do this search.
Device 4
The APB monitor can be instantiated in
the peripheral devices to run formal
analysis on these designs.
AHB Master Monitor

and target devices.
42

AHB Master Monitor
Monitor Placement and Instantiation

The user can place AHB master monitors inside the AHB master devices to provide interface
checks. Also, the user can use the AHB master monitors checks as search targets and check
constraints for running formal analysis on the AHB master device.
Monitor Connectivity
Connect the AHB master monitor pins to internal signals as specified in the pin-out Table 3-1
and illustrated in Figure 3-3. Note that hbusreqx and hlockx are not part of the AHB master
monitor because these signals are not used by the monitor.
Figure 3-3. AHB Master Monitor Pins Diagram
hresetn
hclk
haddr[31:0]
hwrite
htrans[1:0]
hsize[2:0]
hburst[2:0]
hwdata[DATA_BUS_WIDTH 1:0]
hrdata[DATA_BUS_WIDTH 1:0]
hready
hresp[1:0]
hprot[3:0]
hgrantx
AMBA
AHB Master
Monitor
Table 3-1. AHB Master Monitor Pins

Pin
Description
haddr[31:0]
32-bit system address bus.
hburst[2:0]
Encoding that indicates if the transfer is a part of a burst and if

so, the type of burst.
hclk
Clock. Times all bus transfers on the rising edge.
hgrantx
Indicates whether the monitored device is currently the highest

priority master.
hprot[3:0]
Encoding for protocol control information about the current

transfer.
Read data bus. Transfers data from target to master via a read
operation.
43

AHB Master Monitor
Table 3-1. AHB Master Monitor Pins (cont.)

Pin
Description
hready
Indicates whether the currently selected target device is ready to

perform the current transfer.
hresetn
Active low bus reset signal. Resets the system and the bus.
hresp[1:0]
Encoding for the response from the target indicating the status
of the current transfer.
hsize[2:0]
Encoding for the size of the transfer.
htrans[1:0]
Encoding for the type of the current transfer.
Write data bus. Transfers data from master to target via a write
operation.
hwrite
Encoding for the type of transfer: HIGH for write transfers and
LOW for read transfers.
Monitor Parameters
The parameters shown in Table 3-2 configure the corresponding AHB master monitor.
Table 3-2. AMBA AHB Master Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode
Set to 1 if the checks in the monitor are to be used as

constraints for formal analysis.
2.
DATA_BUS_WIDTH
32
Width of AHB data bus. The protocol allows widths of: 8,

16, 32, 64, 128, 256, 512, and 1024 bits.
3.
CANCEL_FOLLOWING_
TRANSFER_ON_ERROR_
RESPONSE
Indicates how AHB masters handle ERROR responses:

1 - On an ERROR response, the master cancels the
following transfer (and immediately performs an
IDLE transfer).
0 - Otherwise.
4.
Over_Constraints_Mode 0
5.
DISABLE_CHKS_ON_IDLE
Set to 1 if additional constraints are needed for formal

analysis. See note below.
AHB_M3, AHB_M4, and AHB_M6_control checks are
also performed on IDLE transfers by default. To disable
these checks on IDLE transfer, set this parameter to 1.
The parameters must be specified in the above order.
Note:
For the Over_Constraints_Mode set to 1, the AMBA AHB master monitor has the following
additional constraints:
44

AHB Master Monitor
AHB_NO_ERROR_RESPONSE Formal verification must not introduce error

responses.
AHB_NO_RETRY_RESPONSE Formal verification must not introduce retry

responses.
AHB_NO_SPLIT_RESPONSE Formal verification must not introduce split

responses.
AHB_NO_TWO_CYCLE_RESPONSE Formal verification must not introduce two

cycle responses.
AHB_NO_WAIT_STATES Formal verification must not introduce wait states.
For additional information on Over_Constraints_Mode, see AHB Master Monitor FAQ on

page 51.
AHB Master Monitor Instantiation Example

Example 3-1 instantiates an AHB master monitor with the default parameters
(DATA_BUS_WIDTH set to 32 and CANCEL_FOLLOWING_TRANSFER_ON_ERROR_RESPONSE set to 0).
Example 3-1. AHB Master Monitor Instantiation
qvl_ahb_master_monitor mas_mon (
.hgrantx
(hgrntx),
.hready
(hrdy),
.hresp
(hrsp),
.hresetn
(hrstn),
.hclk
(hclk),
.hrdata
(hrdt),
.htrans
(htrns),
.haddr
(hddr),
.hwrite
(hwrt),
.hsize
(hsz),
.hburst
(hbrst),
.hprot
(hprt),
.hwdata
(hwdt) );
Note that if using the AHB master monitor with an AHB-Lite master, then the user is required
to tie the hgrantx signal to high (1'b1) and the hresp[1] signal to low (1'b0).
45

Monitor Checks
Monitor Checks
Table 3-3 shows the checks performed by an AHB master monitor.
Table 3-3. AMBA AHB Master Checks
46
Check ID
Violation
Description
AHB_M1
A BUSY transfer type was issued when

there was no burst in progress.
The first transfer of a burst or single transfer

must be a NONSEQUENTIAL transfer.
AHB_M2
The first transfer of a burst or a single

transfer cannot have a transfer type of
SEQUENTIAL.
The first transfer of a burst or single transfer

must be a NONSEQUENTIAL transfer.
AHB_M3
The master must never attempt a

transfer where the width (as encoded
by hsize) is wider than the data bus to
which it is connected.
The encoded width of the data being

transferred is larger than the width of the
physical data bus. Although a bus master can
be modified to operate on a bus that is wider
than originally intended, it cannot operate on a
narrower bus.
AHB_M4
All transfers must be aligned to the

address boundary equal to the size of
the transfer.
The transfer must be aligned to the address

boundary equal to the size of the transfer. For
example, word transfers must be aligned to
word address boundaries (i.e., A[1:0] = 00),
halfword transfers must be aligned to halfword
address boundaries (i.e., A[0] = 0).
AHB_M5
The master was granted the bus, but it

did not perform any data transfer
including IDLE. When a master is
granted the bus and it does not wish to
perform any data transfer, then it must
issue an IDLE transfer.
IDLE transfer indicates no data transfer is

required. It is used when a bus master is
granted the bus, but does not wish to perform a
transfer.
AHB_M6_address
The master did not hold the address

(haddr) stable when the target was
inserting wait states.
The bus master holds the address stable

throughout extended cycles.
AHB_M6_control
The master did not hold the control

(htrans, hwrite, hsize, hburst, and
hprot) stable when the target was
inserting wait states.
The bus master holds the control information

stable throughout extended cycles.
AHB_M7
The control information (hwrite, hsize,

hburst, and hprot) of the current
transfer was not identical to the control
information of the previous transfer.
The control information for a BUSY or

SEQUENTIAL transfer is identical to the
control information of the previous transfer.
AHB_M8
The master used a BUSY transfer type.

The address did not reflect the next
transfer in the burst.
The BUSY transfer type indicates that the

master is continuing with a burst of transfers,
but the next transfer cannot take place
immediately. When a master uses the BUSY
transfer type, the address must reflect the next

Monitor Checks
Table 3-3. AMBA AHB Master Checks (cont.)

Check ID
Violation
Description
AHB_M9
The address of the current transfer with

a transfer type of SEQUENTIAL was
not related to the address of the
previous transfer.
The address in a SEQUENTIAL transfer is

related to the address of the previous transfer.
The address is equal to the address of the
previous transfer plus the size (in bytes). In the
case of a wrapping burst, the address of the
transfer wraps at the address boundary equal
to the size (in bytes) multiplied by the number
of beats in the transfer.
AHB_M10
The address of the current transfer was

not equal to the address of the previous
transfer. The address must be the same
on consecutive BUSY(s) or on a
BUSY-SEQ.
The address must be the same on consecutive

BUSY(s) or on a BUSY-SEQ.
AHB_M11
The master did not perform an IDLE

transfer immediately after receiving an
ERROR response.
ERROR response requires at least two cycles.

The two-cycle response is required because of
the pipelined nature of the bus. By the time a
target starts to issue an ERROR response, the
address of the following transfer has already
been broadcast onto the bus. The two-cycle
response allows sufficient time for the master
to cancel this address and drive HTRANS[1:0]
to IDLE before the start of the next transfer.
This check is active and applicable only when
the CANCEL_FOLLOWING_TRANSFER_
ON_ERROR_RESPONSE parameter is set to
1.
AHB_M12

transfer immediately after receiving a
RETRY response.
RETRY response requires at least two cycles.

target starts to issue a RETRY response, the
The protocol requires that a master performs
an IDLE transfer immediately after receiving a
RETRY response.
AHB_M13

transfer immediately after receiving a
SPLIT response.
SPLIT response requires at least two cycles.

target starts to issue a SPLIT response, the
The protocol requires that a master performs
an IDLE transfer immediately after receiving a
SPLIT response.
AHB_M14
The master continued to retry the

transfer that is responded with an
ERROR response. For the ERROR
response, the current transfer is not
repeated.
For an ERROR response, the current transfer

is not repeated. To determine if a master is
repeating a transfer, address (haddr) and
htrans are considered.
47

Monitor Checks
48
Check ID
Violation
Description
AHB_M15
The bus master did not continue to

retry the transfer that was responded
with a RETRY response.
The RETRY response shows the transfer has

not yet completed; therefore, the bus master
should retry the transfer. The master should
continue to retry the transfer until it completes
successfully or terminates with an ERROR
response.
Note that address (haddr) is the only factor
taken into consideration in determining if the
master is continuing to retry a transfer.
AHB_M16
The bus master did not continue to

retry the transfer that was responded
with a SPLIT response.
The SPLIT response shows the transfer has

not yet completed; therefore, the bus master
should retry the transfer when it is next
granted access to the bus. The master should
continue to retry the transfer until it completes
successfully or terminates with an ERROR
response.
Note that address (haddr) is the only factor
taken into consideration in determining if the
master is continuing to retry a transfer.
AHB_M17
Target did not provide a zero wait state

OKAY response to IDLE transfer.
IDLE transfer indicates that no data transfer is

required. It is used when a bus master is
granted the bus, but does not wish to perform a
data transfer. Targets must always provide a
zero wait state OKAY response to IDLE
transfers and the transfer should be ignored by
the target.
AHB_M18
Target did not provide a zero wait state

OKAY response to BUSY transfer.
BUSY transfer allows a bus master to insert

idle cycles in the middle of bursts of transfers.
This transfer should be ignored by the target
and must always provide a zero wait state
OKAY response.
AHB_M19
Target did not drive the response to

OKAY while inserting wait states prior
to deciding its response.
If the target needs more than two cycles to

provide the ERROR, SPLIT, or RETRY
response, then additional wait states may be
inserted at the start of the transfer. During this
time, the HREADY signal is LOW and the
response must be set to OKAY.
AHB_M20
Target violated the two cycle

requirement on the ERROR response.
The ERROR response requires at least two

cycles. To complete with this response, in the
penultimate (one before last) cycle, the target
drives HRESP[1:0] to indicate ERROR while
driving HREADY LOW to extend the transfer
for an extra cycle. In the final cycle,
HREADY is driven HIGH to end the transfer,
while HRESP[1:0] remains driven to indicate
ERROR.

Monitor Checks

Check ID
Violation
Description
AHB_M21

requirement on RETRY response.
The RETRY response requires at least two

drives HRESP[1:0] to indicate RETRY while
RETRY.
AHB_M22

requirement on SPLIT response.
The SPLIT response requires at least two

drives HRESP[1:0] to indicate SPLIT while
SPLIT.
AHB_M23
Width of the data bus must be either 8,

16, 32, 64, 128, 256, 512, or 1024.
The AHB standard requires that the width of

the data bus must be either 8, 16, 32, 64, 128,
256, 512, or 1024.
AHB_M24_hgrantx,
AHB_M24_hready,
AHB_M24_hresp,
AHB_M24_htrans,
AHB_M24_hwrite,
AHB_M24_hsize,
AHB_M24_hburst,
AHB_M24_hprot
Control signal should not be X or Z.
Control signals should not have a X or Z

value.
AHB_M25_haddr
Address signal should not be X or Z.
Address signal should not have a X or Z value.
AHB_M26
The address for any burst must not

cross a 1 KB boundary.
Burst must not cross a 1 KB address boundary.

Therefore, it is important that masters do not
attempt to start a fixed-length incrementing
burst that would cause this boundary to be
crossed.
AHB_M27
The master must drive either IDLE or

NONSEQUENTIAL on HTRANS
when it is not granted the bus.
When a master is not granted the bus, it is not

performing any transfer. However, it cannot
signal SEQ or BUSY as those transfers are
only valid during bursts. Therefore, it must
drive either IDLE or NONSEQUENTIAL
when not granted the bus.
AHB_MX
The ahb master monitor should not be

in an unknown state.
If any of the checks AHB_M1 through

AHB_M22 is fired, then the ahb master
monitor goes into an unknown state. It comes
back into a known state when it detects a low
on the hgrantx.
49

Monitor Corner Cases

Table 3-4 shows the corner cases maintained by the AHB master monitor.
Table 3-4. AMBA AHB Master Monitor Corner Cases
50
Corner Case
Description
Read Transfers
Number of read transfer operations.
Write Transfers
Number of write transfer operations.
IDLE Transfers
Number of IDLE transfers.
BUSY Transfers
Number of BUSY transfers.
OKAY Responses
Number of OKAY responses.
ERROR Responses
Number of ERROR responses.
RETRY Responses
Number of RETRY responses.
SPLIT Responses
Number of SPLIT responses.
SINGLE Burst Type
Number of SINGLE burst transfers.
INCR Burst Type
Number of INCR burst transfers.
WRAP4 Burst Type
Number of WRAP4 burst transfers.
INCR4 Burst Type
Number of INCR4 burst transfers.
WRAP8 Burst Type
INCR8 Burst Type
WRAP16 Burst Type
INCR16 Burst Type
Byte (8 Bits) Transfer Size
Number of 8-bit transfers.
Half Word (16 Bits) Transfer Size
Word (32 Bits) Transfer Size
Double Word (64 Bits) Transfer Size
4-Word (128 Bits) Transfer Size
Number of 256-bit transfers

Monitor Statistics
Monitor Statistics
Table 3-5 shows the statistics maintained by the AHB master monitor.
Table 3-5. AMBA AHB Master Monitor Statistics
Statistic
Description
Total Transfers
Total number of transfer operations.
AHB Master Monitor FAQ

Following are answers to frequently asked questions (FAQ) about the AHB master monitor.
How do I use the Over_Constraints_Mode in formal verification?
The AHB monitor has an Over_Constraints_Mode parameter for use in formal
verification. The Over_Constraints_Mode parameter will add additional constraints
that can be used to prevent formal verification from introducing the behavior listed
below:
Using the Over_Constraints_Mode parameter in simulation will produce incorrect

AHB violations.
Note that the Over_Constraints_Mode parameter will prevent formal verification

from exercising the full set of legal AHB transactions.
In order to verify your design for all legal AHB transactions, formal verification should
also be run with the Over_Constraints_Mode parameter disabled (set to 0).
How do I use only a subset of the Over_Constraints_Mode constraints?
A subset of the Over_Constraints_Mode constraints can be used by disabling
unwanted constraints.
To remove unwanted constraints, add exclude_checker directives to a checker
control file or your monitor instantiation file as follows:
// Remove error response constraint
// 0in exclude_checker -name *AHB_NO_ERROR_RESPONSE
// Remove retry response constraint

// 0in exclude_checker -name *AHB_NO_RETRY_RESPONSE
51

AHB Target Monitor
AHB Target Monitor

and target devices. A typical AHB system design contains the following components.

The user can place AHB target monitors inside the AHB target devices to provide interface
checks. Also, the AHB target monitors checks can be used as search targets and check
constraints for running formal analysis on the AHB target device.
Connect the AHB target monitor pins to internal signals as specified in the pin-out Table 3-6
and illustrated in Figure 3-4.
Note that the AHB target monitor does not support locked transfers.
Figure 3-4. AHB Target Monitor Pins Diagram
hresetn
hclk
hselx
haddr[31:0]
hwrite
htrans[1:0]
hsize[2:0]
hburst[2:0]
hready_in
hready_out
hresp[1:0]
hmaster[3:0]
hmastlock
hsplitx[NUMBER_OF_MASTERS 1:0]
AMBA
AHB Target
Monitor
Table 3-6. AHB Target Monitor Pins
52
Pin
Description
haddr[31:0]
32-bit system address bus.
hburst[2:0]
Encoding that indicates if the transfer is a part of a burst and

if so, the type of burst.
hclk
Clock. Times all bus transfers on the rising edge.

AHB Target Monitor
Table 3-6. AHB Target Monitor Pins (cont.)

Pin
Description
hmaster[3:0]
Encoding that indicates the master that is currently accessing

the target device.
hmastlock
Indicates the current master is performing a locked transfer.
Read data bus. Transfers data from target to master via a read
operation.
hready_in
Indicates whether the currently selected target device is

ready to perform the current transfer (hready on the bus).
hready_out
Signal (hready) driven by the monitored target device.
hresetn
Active low bus reset signal. Resets the system and the bus.
hresp[1:0]
Encoding for the response from the target indicating the

status of the current transfer.
hselx
AHB target device select.
hsize[2:0]
Encoding for the size of the transfer.
hsplitx[NUMBER_OF_MASTERS 1:0]
Signal used by the target device to indicate to the arbiter

which bus masters can attempt a split transaction. Each bit
corresponds to a single bus master.
htrans[1:0]
Encoding for the type of the current transfer.
Write data bus. Transfers data from master to target via a

write operation.
hwrite
Encoding for the type of transfer: HIGH for write transfers

and LOW for read transfers.
Monitor Parameters
The parameters shown in Table 3-7 configure the corresponding AHB target monitor.
Table 3-7. AMBA AHB Target Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode

2.
DATA_BUS_WIDTH
32
Width of AHB data bus. The protocol allows widths

of: 8, 16, 32, 64, 128, 256, 512, and 1024 bits.
3.
NUMBER_OF_MASTERS
16
Number of AHB bus masters in the system (used to

configure the HSPLIT bus width).
4.
CANCEL_FOLLOWING_
TRANSFER_ON_ERROR_
RESPONSE
Indicates how AHB masters handle ERROR

responses:
1- On an ERROR response, the master cancels the
following transfer (and immediately performs
an IDLE transfer).
0 - Otherwise.
53

AHB Target Monitor
Table 3-7. AMBA AHB Target Monitor Parameters (cont.)

Order Parameter
Default Description
5.
Over_Constraints_Mode
Set to 1 if additional constraints are needed for formal

analysis. See note below.
6.
DISABLE_CHKS_ON_IDLE
AHB_T14, AHB_T15, and AHB_T17 checks are also

performed on IDLE transfers by default. To disable
these checks on IDLE transfer, set this parameter to 1.
Note:
For the Over_constraints_Mode set to 1, the AMBA AHB target monitor has the following
additional constraints:
AHB_NO_BURST Formal verification must not introduce burst transfers.
AHB_NO_WRAP Formal verification must not introduce wrap transfers.
AHB_NO_BUSY Formal verification must not introduce busy responses.
AHB_NO_EARLY_BURST_TERMINATION Formal verification must not

terminate burst transfers.
For additional information on Over_Constraints_Mode, see AHB Target Monitor FAQ on

page 61.
AHB Target Monitor Instantiation Example

Example 3-2 instantiates an AHB target monitor with the default data width (32) and the default
number of masters (16).
Example 3-2. AHB Target Monitor Instantiation
qvl_ahb_target_monitor tar_mon (
.hselx
(hslx),
.haddr
(hddr),
.hwrite
(hwrt),
.htrans
(htrns),
.hsize
(hsz),
.hburst
(hbrst),
.hwdata
(hwdt),
.hresetn
(hrstn),
.hclk
(hclk),
.hmaster
(hmstr),
.hmastlock (hmstlck),
.hready_in (hrdy_in),
.hready_out (hrdy_out),
.hresp
(hrsp),
.hrdata
(hrdt),
.hsplitx
(hspltx) );
54

Monitor Checks
Note that if using the AHB target monitor with an AHB-Lite target, then the user must tie the
hresp[1] signal to low (1'b0).
Monitor Checks
Table 3-8 shows the checks performed by an AHB target monitor.
Table 3-8. AMBA AHB Target Checks
Check ID
Violation
Description
AHB_T1
Target did not provide a zero

wait state OKAY response to
IDLE transfer.
IDLE transfer indicates that no data transfer is

required. It is used when a bus master is granted
the bus, but does not wish to perform a data
transfer. Targets must always provide a zero wait
state OKAY response to IDLE transfers, and the
transfer should be ignored by the target.
AHB_T2
Target did not provide a zero

wait state OKAY response to
BUSY transfer.
BUSY transfer allows a bus master to insert idle

cycles in the middle of bursts of transfers. This
transfer should be ignored by the target, and must
always provide a zero wait state OKAY response.
AHB_T3
Target inserted more than 16

wait states. It is recommended
(but not mandatory) that
targets do not insert more than
16 wait states to prevent any
single access locking the bus
for a large number of clock
cycles.
The HREADY signal is used to extend the data

portion of an AHB transfer. When LOW, it
indicates the transfer is to be extended. When
HIGH it indicates that the transfer can complete.
Every target must have a predetermined maximum
number of wait states that it inserts before it backs
off the bus, in order to allow the calculation of the
latency of accessing the bus. It is recommended
(but not mandatory) that targets do not insert more
than 16 wait states to prevent any single access
locking the bus for a large number of clock cycles.
AHB_T4
Target did not drive the

response to OKAY while
inserting wait states prior to
deciding its response.
If the target needs more than two cycles to provide

the ERROR, SPLIT, or RETRY response, then
additional wait states may be inserted at the start of
the transfer. During this time, the HREADY signal
is LOW and the response must be set to OKAY.
AHB_T5

requirement on ERROR
response.
The ERROR response requires at least two cycles.

To complete with this response, in the penultimate
(one before last) cycle, the target drives
HRESP[1:0] to indicate ERROR while driving
HREADY LOW to extend the transfer for an extra
cycle. In the final cycle, HREADY is driven HIGH
to end the transfer, while HRESP[1:0] remains
driven to indicate ERROR.
AHB_T6

requirement on RETRY
response.
The RETRY response requires at least two cycles.

HRESP[1:0] to indicate RETRY while driving
driven to indicate RETRY.
55

Monitor Checks
Table 3-8. AMBA AHB Target Checks (cont.)
56
Check ID
Violation
Description
AHB_T7

requirement on SPLIT
response.
The SPLIT response requires at least two cycles.

HRESP[1:0] to indicate SPLIT while driving
driven to indicate SPLIT.
AHB_T8
Target had issued an ERROR

response. It is now being
accessed by the same master
(that received the ERROR
response) and with the same
address. For ERROR
response, the current transfer
is not repeated.
For an ERROR response, the current transfer is not

repeated. To determine if a master is repeating a
transfer, address (haddr) and htrans are considered.
AHB_T9
Target had issued a RETRY

response. It is now being
assessed by a different master
before completion of the
transfer for which RETRY
response was issued.
A slave that issues RETRY responses must only be

accessed by one master at a time. When a slave
issues a RETRY, it can sample the master number.
Between that point and the time when the transfer
is finally completed, the RETRY slave can check
every transfer attempt that is made to ensure the
master number is the same.
AHB_T10
The bus protocol allows only a

single outstanding transaction
per bus master. A Bus master
received a split response from
the target when it tried to
access the target the last time.
The target has not yet issued a
split completion request to this
master yet. The master must
not access the target until then.
The bus protocol allows only a single outstanding

transaction per bus master. When a target issues a
SPLIT, it can sample the master number. Between
that point and the time when the transfer is finally
completed, the SPLIT target can check every
transfer attempt that is made to ensure the master is
not the same, unless all other masters are waiting
for SPLIT transfers to complete in which case the
default master could be granted the bus.
AHB_T11
Target issued a split

completion request for a
master, even though it did not
issue a split response for that
master.
The target asserted a bit of hsplitx that identified a

master with which the target device does not have
a split transaction pending.
AHB_T12
A BUSY transfer type was

issued when there was no
burst in progress.
The first transfer of a burst or single transfer must

be a NONSEQUENTIAL transfer.
AHB_T13
The first transfer of a burst or

a single transfer cannot have a
transfer type of
SEQUENTIAL.
The first transfer of a burst or single transfer must

be a NONSEQUENTIAL transfer.
AHB_T14
A master must never attempt a

transfer where the width (as
encoded by hsize) is wider
than the data bus to which it is
connected.
The encoded width of the data being transferred is

larger than the width of the physical data bus.
Although a bus master can be modified to operate
on bus that is wider than originally intended, it
cannot operate on a narrower bus.

Monitor Checks

Check ID
Violation
Description
AHB_T15
All transfers must be aligned

to the address boundary equal
to the size of the transfer.
The transfer must be aligned to the address

boundary equal to the size of the transfer. For
example, word transfers must be aligned to word
address boundaries (i.e., A[1:0] = 00), halfword
transfers must be aligned to halfword address
boundaries (i.e., A[0] = 0).
AHB_T16
A master was granted the bus,

but it did not perform any data
transfer including IDLE.
When a master is granted the
bus and it does not wish to
perform any data transfer, it
must issue an IDLE transfer.
IDLE transfer indicates no data transfer is required.

It is used when a bus master is granted the bus, but
does not wish to perform a transfer.
AHB_T17
Master did not hold the

address (haddr) and control
(htrans, hwrite, hsize, hburst,
and hmaster) stable when the
target was inserting wait
states.
The bus master holds the address and control

information stable through out extended cycles.
AHB_T18
The control information

(hwrite, hsize, hburst, and
hmaster) of the current
transfer was not identical to
the control information of the
previous transfer.
The control information for a BUSY or

SEQUENTIAL transfer is identical to the control
information of the previous transfer.
AHB_T19
A master used a BUSY

transfer type. The address did
not reflect the next transfer in
the burst.
The BUSY transfer type indicates that the master is

continuing with a burst of transfers, but the next
transfer cannot take place immediately. When a
master uses the BUSY transfer type, the address
must reflect the next transfer in the burst.
AHB_T20
The address of the current

transfer with a transfer type of
SEQUENTIAL was not
related to the address of the
previous transfer.
The address in a SEQUENTIAL transfer is related

to the address of the previous transfer. The address
is equal to the address of the previous transfer plus
the size (in bytes). In the case of a wrapping burst,
the address of the transfer wraps at the address
boundary equal to the size (in bytes) multiplied by
the number of beats in the transfer.
AHB_T21
The address of the current

The address must be the same on consecutive
transfer was not equal to the
address of the previous
transfer. The address must be
the same on consecutive
57

Monitor Checks
58
Check ID
Violation
Description
AHB_T22
Master did not perform an

IDLE transfer immediately
after receiving a ERROR
response.
ERROR response requires at least two cycles. The

two-cycle response is required because of the
pipelined nature of the bus. By the time a target
starts to issue a ERROR response, the address of
the following transfer has already been broadcast
onto the bus. The two-cycle response allows
sufficient time for the master to cancel this address
and drive HTRANS[1:0] to IDLE before the start
of the next transfer.
Note that this check is active and applicable only
when the CANCEL_FOLLOWING_TRANSFER
_ON_ERROR_RESPONSE parameter is set to 1.
AHB_T23

after receiving a RETRY
response.
RETRY response requires at least two cycles. The

starts to issue a RETRY response, the address of
the following transfer has already been broadcast
onto the bus. The two-cycle response allows
sufficient time for the master to cancel this address
and drive HTRANS[1:0] to IDLE before the start
of the next transfer.
The protocol requires that a master performs an
IDLE transfer immediately after receiving a
RETRY response.
AHB_T24

after receiving a SPLIT
response.
SPLIT response requires at least two cycles. The

starts to issue a SPLIT response, the address of the
following transfer has already been broadcast onto
the bus. The two-cycle response allows sufficient
time for the master to cancel this address and drive
HTRANS[1:0] to IDLE before the start of the next
transfer.
The protocol requires that a master performs an
IDLE transfer immediately after receiving a SPLIT
response.
AHB_T25
A bus master did not continue

to retry the transfer that was
responded with a RETRY
response.
The RETRY response shows the transfer has not

yet completed, so the bus master should retry the
transfer. The master should continue to retry the
transfer until it completes successfully or
terminates with an ERROR response.
Note that address (haddr) and htrans are taken into
consideration in determining if a master is
continuing to retry a transfer.
AHB_T26
A bus master did not continue

to retry the transfer that was
responded with a SPLIT
response.
The SPLIT response shows the transfer has not yet

completed, so the bus master should retry the
transfer when it is next granted access to the bus.
The master should continue to retry the transfer
until it completes successfully or terminates with
an ERROR response.
Note that address (haddr) and htrans are taken into
consideration in determining if a master is
continuing to retry a transfer.

Monitor Checks

Check ID
Violation
Description
AHB_T27
Width of the data bus must be

either 8, 16, 32, 64, 128, 256,
512, or 1024.
The AHB standard requires that the width of the

data bus must be either 8, 16, 32, 64, 128, 256, 512,
or 1024.
AHB_T28
Illegal number of masters on

the bus.
The AHB standard requires a minimum of 1 master

and a maximum of 16 masters on the bus.
AHB_T29_hselx,
AHB_T29_hwrite,
AHB_T29_htrans,
AHB_T29_hsize,
AHB_T29_hburst,
AHB_T29_hmaster,
AHB_T29_hmastlock,
AHB_T29_hready_in,
AHB_T29_hready_out,
AHB_T29_hresp,
AHB_T29_hsplitx
Control signal should not be X

or Z.
Control signals should not have a X or Z value.
AHB_T30_haddr
Address signal should not be

X or Z.
Address signal should not have a X or Z value.
AHB_T31
hselx was not stable when the

target was inserting wait
states.
The bus master holds hselx stable throughout

extended cycles.
AHB_T32
hmaster was not stable when

the target was inserting wait
states.
The bus master holds hselx stable throughout

extended cycles.
AHB_T33
hready_in was not equal to

hready_out when this target
device was active.
When a ahb target is involved in a transaction, no

other ahb target should drive hready.
AHB_T34
Target asserted hready_out

low (inserted wait states)
when it was not selected.
When a ahb target is not involved in a transaction,

it must not drive hready_out.
AHB_T35
The hmaster encoding must

always be less than the
number of masters in the
system.
The hmaster[3:0] encoding indicates the master

that is currently accessing the target device.
AHB_T36
Target must drive HRESP as

When an ahb target is not selected, it must drive
OKAY when it is not selected. HRESP as OKAY.
AHB_T37
Target must not assert

HSPLITx signal for more than
one cycle.
An ahb target must assert HSPLITx only for one

cycle.
AHB_TX
The ahb target monitor should

not be in an unknown state.
If any of the above checks AHB_T1 through

AHB_T26, AHB_T31, or AHB_T32 fires, the ahb
target monitor goes into an unknown state. It
comes back into a known state when it detects a
low on the hselx.
59


Table 3-9 shows the corner cases maintained by the AHB target monitor.
Table 3-9. AMBA AHB Target Monitor Corner Cases
Corner Case
Description
Read Transfers
Write Transfers
IDLE Transfers
Number of IDLE transfers.
BUSY Transfers
Number of BUSY transfers.
OKAY Responses
Number of OKAY responses.
ERROR Responses
Number of ERROR responses.
RETRY Responses
Number of RETRY responses.
SPLIT Responses
Number of SPLIT responses.
SINGLE Burst Type
Number of SINGLE burst transfers.
INCR Burst Type
Number of INCR burst transfers.
WRAP4 Burst Type
INCR4 Burst Type
WRAP8 Burst Type
INCR8 Burst Type
WRAP16 Burst Type
INCR16 Burst Type
Byte (8 Bits) Transfer Size
Half Word (16 Bits) Transfer Size
Word (32 Bits) Transfer Size
Double Word (64 Bits) Transfer Size Number of 64-bit transfers.
60
Number of 256-bit transfers

Monitor Statistics
Monitor Statistics
Table 3-10 shows the statistics maintained by the AHB target monitor.
Table 3-10. AMBA AHB Target Monitor Statistics
Statistic
Description
Total Transfers
AHB Target Monitor FAQ

Following are answers to frequently asked questions (FAQ) about the AHB target monitor.
How do I use the Over_Constraints_Mode in formal verification?
The AHB monitor has an Over_Constraints_Mode parameter for use in formal
verification. The Over_Constraints_Mode parameter will add additional constraints
that can be used to prevent formal verification from introducing the behavior listed
below:
Using the Over_Constraints_Mode parameter in simulation will produce incorrect

AHB violations.
Note that the Over_Constraints_Mode parameter will prevent formal verification

from exercising the full set of legal AHB transactions.
In order to verify your design for all legal AHB transactions, formal verification should
also be run with the Over_Constraints_Mode parameter disabled (set to 0).
How do I use only a subset of the Over_Constraints_Mode constraints?
A subset of the Over_Constraints_Mode constraints can be used by disabling
unwanted constraints.
To remove unwanted constraints, add exclude_checker directives to a checker
control file or your monitor instantiation file as follows:
// Remove burst transfer constraint
// 0in exclude_checker -name *AHB_NO_BURST
// Remove wrap transfer constraint

// 0in exclude_checker -name *AHB_NO_WRAP
// Remove busy response constraint

// 0in exclude_checker -name *AHB_NO_BUSY
61

APB Monitor
APB Monitor
AMBA Advanced Peripheral Bus (APB) is for low power peripherals. AMBA APB is
peripheral functions. APB can be used in conjunction with the AHB system bus.

Place the APB monitor inside the APB peripheral device or inside the bridge to the AHB bus.
The monitor can be instantiated in a checker control file. The APB monitors checks can be
used to search targets and check constraints for running formal analysis.
Connect the APB monitor pins to internal signals as specified in the pin-out Table 3-11 and
illustrated in Figure 3-5.
Figure 3-5. APB Monitor Pins Diagram
pclk
presetn
paddr[ADD_BUS_WIDTH 1:0]
pwrite
pselx
penable
pwdata[DATA_BUS_WIDTH 1:0]
prdata[DATA_BUS_WIDTH 1:0]
AMBA
APB Monitor
Table 3-11. APB Monitor Pins
62
Pin
Description
paddr
Address lines for the bus (maximum width = 32-bits).
pclk
APB clock.
penable
Active high device enable signal.
prdata
Read data bus (maximum width = 32bits).
presetn
Active low APB reset.
pselx
Active high device select signal.
pwdata
Write data bus (maximum width = 32-bits).
pwrite
Encoding for the type of transfer: HIGH for write transfers and LOW
for read transfers.

APB Monitor
Note that the pwdata and prdata buses can be implemented together as a single bidirectional
bus with tri-state capability. Under this configuration, connect the single data bus to both the
pwdata and prdata inputs of the interface monitor.
Monitor Parameters
The parameters shown in Table 3-12 configure the corresponding APB monitor.
Table 3-12. AMBA APB Monitor Parameters
Order
Parameter
Default
Description
1.
Constraints_Mode

2.
ADD_BUS_WIDTH
32
Width of PADDR bus. The default (32-bits) is the

maximum width supported by the APB interface.
3.
DATA_BUS_WIDTH
32
Width of PRDATA and PWDATA buses. The default (32bits) is the maximum width supported by the APB
interface.
APB Monitor Instantiation Example

Example 3-3 instantiates an APB monitor with an address width of 24 and a data width of 16.
Example 3-3. APB Monitor Instantiation
qvl_apb_monitor
#( /* Constraints_Mode */
/* ADD_BUS_WIDTH */
/* DATA_BUS_WIDTH */
)
APB_MONITOR
(.pclk(pclk),
.presetn(presetn),
.paddr(paddr),
.pselx(pselx),
.penable(penable),
.pwrite(pwrite),
.pwdata(pwdata),
.prdata(prdata)
);
0,
24,
16
63

APB Monitor
Monitor Checks
Table 3-13 shows the checks performed by the APB monitor.
Table 3-13. AMBA APB Checks
64
Check ID
Violation
Description
APB_01
The bus should advance to

SETUP state or remain in IDLE
state, but went to ENABLE state.
When the bus is in the IDLE state, it can advance to

the SETUP state or remain in the IDLE state.
Advancing to ENABLE state causes this check to
fire.
APB_02
The bus did not advance to

ENABLE state in one clock
cycle, instead went to an
unknown state.
When the bus is in the SETUP state, it should

advance to the ENABLE state in one clock cycle.
Any other behavior causes this check to fire.
APB_03
The bus should advance to IDLE

or SETUP state, but went to an
unknown state.
When the bus is in the ENABLE state, it should

advance either to the IDLE state or to the SETUP
state (to perform back to back cycles) in one clock
cycle. Any other behavior causes this check to fire.
APB_04

state, but remained in an
unknown state.
When the bus encounters an error condition, it is

required to return to the IDLE state before
attempting subsequent operations. This is enforced
to track accurately any further operation on the bus.
The check fires until the bus transitions from an
UNKNOWN state to the IDLE state.
APB_06
The PADDR address should be

The PADDR signal should be stable when the bus
stable while transitioning from
transitions from SETUP to the ENABLE state.
SETUP to ENABLE state, but has
changed.
APB_07
The PWRITE signal should be

The PWRITE signal should be stable when the bus
stable while transitioning from
transitions from SETUP to the ENABLE state.
SETUP to ENABLE state, but has
changed.
APB_08
The PWDATA should be stable

while transitioning from SETUP
to ENABLE state during write
cycles, but has changed.
The PWDATA signal should be stable when the

bus transitions from SETUP to the ENABLE state.
APB_09_pselx
APB_09_penable
APB_09_pwrite
Control signals should not be X

or Z.
None of the control signals should have a X or Z

value at any time.
APB_10
Width of the APB Address bus is

at most 32.
The AMBA standard requires that the maximum

width of the APB Address bus is 32.
APB_11
Width of the APB Data bus is at

most 32.
The AMBA standard requires that the maximum

width of the APB Data bus is 32.
APB_12_paddr
To reduce power consumption,

PADDR must not change after a
transfer until the next access
occurs.
In order to reduce power consumption, the address

signal will not change after a transfer until the next
access occurs.
APB_12_pwrite

PWRITE must not change after a
occurs.
In order to reduce power consumption, the write

signal will not change after a transfer until the next
access occurs.

APB Monitor

Table 3-14 shows the corner cases maintained by the APB monitor.
Table 3-14. AMBA APB Monitor Corner Cases
Corner Cases
Description
Read Transfers
Write Transfers
Back-to-back Transfers
Number of consecutive read or write transfer operations.
Monitor Statistics
Table 3-15 shows the statistics maintained by the APB monitor.
Table 3-15. AMBA APB Monitor Statistics
Statistic
Description
Total Transfers
Idle State Count
Number of cycles in the IDLE state.
Setup State Count
Number of cycles in the SETUP state.
Enable State Count
Number of cycles in the ENABLE state.
65

APB Monitor
66
Chapter 4
AMBA 3 Advanced Peripheral Bus (APB)
Introduction
AMBA 3 Advanced Peripheral Bus (APB) is for low power peripherals. AMBA 3 APB is
peripheral functions. AMBA 3 APB can be used in conjunction with the AHB and the AXI
system bus.
This version of the AMBA 3 APB monitor is modeled from the requirements provided in the
following document:
AMBA 3 APB Protocol Specification, IHI 0024B, v1.0, 17 August 2004

Place the AMBA 3 APB monitor inside the APB peripheral device or inside the bridge to the
AHB bus. The AMBA 3 APB monitors checks can be run in simulation and can be used as
search targets and check constraints for running formal analysis.
Connect the AMBA 3 APB monitor pins as specified in the pin out Table 4-1 and illustrated in
Figure 4-1.
Figure 4-1. AMBA 3 APB Monitor Pins Diagram
pclk
presetn
paddr[ADD_BUS_WIDTH 1:0]
pwrite
pselx
penable
pwdata[DATA_BUS_WIDTH 1:0]
prdata[DATA_BUS_WIDTH 1:0]
pready
pslverr
AMBA 3
APB Monitor
67

Table 4-1. AMBA 3 APB Monitor Pins

Port
Description
paddr
Address lines for the bus (maximum width = 32-bits).
pclk
AMBA 3 APB clock.
penable
Active high device enable signal.
prdata
Read data bus (maximum width = 32-bits).
presetn
Active low AMBA 3 APB reset.
pselx
Active high device select signal.
pwdata
Write data bus (maximum width = 32-bits).
pwrite
Encoding for the type of transfer: HIGH for write transfers and LOW for read
transfers.
pready
Signal to extend an AMBA 3 APB transaction.
pslverr
Signal to indicate a failure of a transfer.
Note that the pwdata and prdata buses can be implemented together as a single bidirectional
bus with tri-state capability. Under this configuration, connect the single data bus to both the
pwdata and prdata inputs of the interface monitor.
Monitor Parameters
The parameters shown in Table 4-2 configure the AMBA 3 APB monitor.
Table 4-2. AMBA 3 APB Monitor Parameter
Order Parameter
Default Description
1.
Constraints_Mode

constraints for formal analysis of the APB slave.
2.
ADD_BUS_WIDTH
32
Width of PADDR bus. The default (32-bits) is the

maximum width supported by the AMBA 3 APB
interface.
3.
DATA_BUS_WIDTH
32
Width of PRDATA and PWDATA buses. The default

(32-bits) is the maximum width supported by the
AMBA 3 APB interface.
4.
INTERFACE_TYPE
Set this parameter depending on the interface on

which the monitor is instantiated:
0 => Master interface
1 => Slave interface
To verify a master DUT, this parameter must be set to
0, while to verify a slave DUT, this parameter must
be set to 1.
This parameter only works in formal to define the
constraint.
68

Monitor Checks
Table 4-2. AMBA 3 APB Monitor Parameter (cont.)

Order Parameter
Default Description
5.
SLAVE_COUNT
Width of PSELx bus. This parameter represents the

number of slave.
6.
RECOMMENDED_CHECKS_OFF
Disable the recommended checks in APB3. These

recommended checks are AMBA3_APB_13,
AMBA3_APB_12_paddr, and
AMBA3_APB_12_pwrite.
Note that the parameters must be specified in the above order.
AMBA 3 APB Monitor Instantiation Example

Example 4-1 instantiates an AMBA 3 APB monitor with an address width of 24 and a data
width of 16.
Example 4-1. AMBA 3 APB Monitor Instantiation
qvl_amba3_apb_monitor
0,
/* ADD_BUS_WIDTH */
24,
/* DATA_BUS_WIDTH */
16,
/* INTERFACE_TYPE */
0,
/* SLAVE_COUNT */
1,
/* RECOMMENDED_CHECKS_OFF */ 0
)
AMBA3_APB_MONITOR
(.pclk(pclk),
.presetn(presetn),
.paddr(paddr),
.pselx(pselx),
.penable(penable),
.pwrite(pwrite),
.pwdata(pwdata),
.prdata(prdata),
.pready(pready),
.pslverr(pslverr)
);
Monitor Checks
Table 4-3 shows the checks performed by the AMBA 3 APB monitor.
Table 4-3. AMBA 3 APB Monitor Checks
Check ID
Violation
AMBA3_APB_01
The bus should advance to SETUP When the bus is in the IDLE state, it can
state or remain in IDLE state, but advance to the SETUP state or remain in the
went to ACCESS state.
IDLE state. Advancing to ACCESS state
causes this check to fire.
Description
69

Monitor Checks
Table 4-3. AMBA 3 APB Monitor Checks (cont.)
70
Check ID
Violation
Description
AMBA3_APB_02
The bus did not advance to

ACCESS or WAIT state in one
clock cycle from SETUP state,
instead went to an unknown state.
When the bus is in the SETUP state, it should

advance to the ACCESS or WAIT state in
one clock cycle. Any other behavior causes
this check to fire.
AMBA3_APB_03

or SETUP state, but went to an
unknown state.
When the bus is in the ACCESS state, it

should advance either to the IDLE state or to
the SETUP state (to perform back-to-back
cycles) in one clock cycle. Any other
behavior causes this check to fire.
AMBA3_APB_04
The bus should advance to

ACCESS or stay in WAIT state,
but went to an unknown state.
After staying in the WAIT state for some

time, the bus should either move to the
ACCESS state or keep waiting in the WAIT
until the pready signal is seen on the bus. Any
other behaviour cases this check to fire.
AMBA3_APB_UNKN

state, but remained in an unknown
state.
When the bus encounters an error condition,

it is required to return to the IDLE state
before attempting subsequent operations.
This is enforced to track accurately any
further operation on the bus. The check fires
until the bus transitions from an UNKNOWN
state to the IDLE state.
AMBA3_APB_06
The PADDR address should be

The PADDR signal should be stable when the
stable from SETUP until ACCESS bus transitions from SETUP to the ACCESS
state, but has changed.
state.
AMBA3_APB_07
The PWRITE signal should be

The PWRITE signal should be stable when
stable from SETUP until ACCESS the bus transitions from SETUP to the
state, but has changed.
ACCESS state.
AMBA3_APB_08
The PWDATA should be stable

from SETUP until ACCESS state
during write cycles, but has
changed.
The PWDATA signal should be stable when

the bus transitions from SETUP to the
ACCESS state.
AMBA3_APB_09_pselx
AMBA3_APB_09_penable
AMBA3_APB_09_pwrite
AMBA3_APB_09_pready
AMBA3_APB_09_pslverr
Control signals should not be X or

Z.
None of the control signals should have a X

or Z value at any time.
AMBA3_APB_10
Width of the APB Address bus is

at most 32.
The AMBA 3 APB standard requires that the

maximum width of the AMBA 3 APB
Address bus is 32.
AMBA3_APB_11
Width of the APB Data bus is at

most 32.
The AMBA 3 APB standard requires that the

maximum width of the AMBA 3 APB Data
bus is 32.
AMBA3_APB_12_paddr

PADDR must not change after a
occurs.
In order to reduce power consumption, the

address signal will not change after a transfer
until the next access occurs. This check is
disabled when
parameter is set to 1.

Table 4-3. AMBA 3 APB Monitor Checks (cont.)

Check ID
Violation
Description
AMBA3_APB_12_pwrite

PWRITE must not change after a
occurs.
In order to reduce power consumption, the

write signal will not change after a transfer
until the next access occurs. This check is
disabled when
AMBA3_APB_13
The protocol recommends

PSLVERR to be low when any of
PSEL, PENABLE, or PREADY is
low.
It is recommended that PSLVERR be driven

low when it is not being sampled. This check
is disabled when
AMBA3_APB_14
PSELx must not have more than

one bit high.
At one time only one slave is selected. This

check fires if more than one bit in PSELx is
asserted.
AMBA3_APB_15
The PSELx should be stable from

SETUP until ACCESS state, but
has changed.
The PSELx signal should be stable when the

bus transitions from SETUP to the ACCESS
state.

Table 4-4 shows the corner cases maintained by the AMBA 3 APB monitor.
Table 4-4. AMBA 3 APB Corner Cases
Corner Case
Description
Read Transfers
Write Transfers
Back to Back Transfers
Number of consecutive read or write transfer operations.
Monitor Statistics
Table 4-5 shows the statistics maintained by the AMBA 3 APB monitor.
Table 4-5. AMBA 3 APB Protocol Statistics
Statistic
Description
Total Transfers
Idle State Count
Number of cycles in the IDLE state.
Setup State Count
Number of cycles in the SETUP state.
Access State Count
Number of cycles in the ACCESS state.
71

Monitor Statistics
Table 4-5. AMBA 3 APB Protocol Statistics (cont.)
72
Statistic
Description
Transfer Failures
Number of transactions that got pslverr asserted during the access phase.
Chapter 5
AMBA AXI
Introduction
The AXI is the latest generation AMBA interface, targeted at high-performance, high-frequency
system designs and includes a number of features that make it suitable for a high-speed
submicron interconnect. The QVL AMBA AXI monitor is designed for checking the AXI
interface.
This version of the AMBA AXI monitor is modeled from the requirements provided in the
following document:
AMBA AXI protocol specification, IHI 0022B, v1.0, 19 March 2004
Supported Features
Channel Handshake
Channel handshake.
Channel dependencies.
Addressing options
Burst lengths of 2, 4, 8, 16 transfers for wrapping bursts.
Burst lengths of 1 to 16 transfers for sequential incrementing bursts.
Data widths from 1 to 128 bytes.
Wrapping, incrementing, and fixed types of bursts.
Atomic Accesses
Exclusive accesses.
Locked transactions.
Response Signaling
All types of responses.
73
AMBA AXI
Completions
Out of order completions.
Read and write data interleaving.
Data buses
Write strobes.
Narrow transfers and byte lane switching.
Unaligned transfers.
Low Power interface
Peripheral initiated clock control and handshake-based clock control.
Unsupported Features
The monitor will assume the data as-is and will not perform endianness conversion.

The QVL AMBA AXI monitor can be placed on the master or slave side to provide interface
checks. The checks in the AMBA AXI monitor can also be used as search targets and check
constraints while running formal analysis on the AXI master or slave devices. The AMBA AXI
monitor can also be placed on the interconnect. A typical AXI setup is shown in Figure 5-1.
Figure 5-1. AMBA AXI Monitor Implementation
AXI Monitor
INTERFACE_TYPE=0
AXI Monitor for

Slave Interface of I/C
INTERFACE_TYPE=3
AXI Monitor for

Master Interface of I/C
INTERFACE_TYPE=2
AXI Monitor
INTERFACE_TYPE=1
AXI Master Device
AXI Interconnect
AXI Slave Device
Refer to Table 5-2 on page 77, the INTERFACE_TYPE parameter, for descriptions on
monitor instantiations A, B, C, and D.
74
AMBA AXI
Connect the AMBA AXI monitor pins as specified in the pin out Table 5-1 and illustrated in
Figure 5-2.
bid[3:0]
bresp[1:0]
bvalid
bready
READ CHANNEL
WRITE RESP.
aclk
areset_n
reset_n
rvalid
rready
AMBA AXI
Monitor
csysreq
csysack
cactive
wid
wdata
wstrb
wlast
wvalid
wready
L.P. I.
WRITE ADDRESS CHANNEL
awid[3:0]
awaddr
awlen
awsize[2:0]
awburst[1:0]
awlock[1:0]
awcache[3:0]
awprot[2:0]
awvalid
awready
rid[3:0]
rdata
rresp[1:0]
rlast
WRITE CHANNEL
READ ADDRESS CHANNEL
arid[3:0]
araddr
arlen
arsize[2:0]
arburst[1:0]
arlock[1:0]
arcache[3:0]
arprot[2:0]
arvalid
arready
GLOBAL
Figure 5-2. AMBA AXI Monitor Pins Diagram
Table 5-1. AMBA AXI Monitor Pins

Port
Description
aclk
Global clock signal (all signals are sampled on the rising edge of global clock).
araddr
Read address bus (address of the first transfer of the burst).
arburst[1:0]
Read burst type (type of burst - incremental / wrapping / fixed).
75
AMBA AXI
Table 5-1. AMBA AXI Monitor Pins (cont.)
76
Port
Description
arcache[3:0]
Read cache type (attributes - bufferable / cacheable / write through, etc.).
areset_n
Global reset signal (active low).
arid
Read address ID (tag of the read or write transaction).
arlen
Read burst length (number of transfers - 1, 2, 3 .... 32).
arlock[1:0]
Read lock type (type of transaction - normal / exclusive / locked).
arprot[2:0]
Read protection level (normal / privileged / secure protection level).
arready
Read address ready (slave ready to accept an address).
arsize[2:0]
Read burst size (data width of each transfer).
arvalid
Read address valid (valid address and control information available).
awaddr
Write address bus (address of the first transfer of the burst).
awburst[1:0]
Write burst type (type of burst - incremental / wrapping / fixed).
awcache[3:0]
Write cache type (attributes - bufferable / cacheable / write through, etc.).
awid
Write address ID (tag of the read or write transaction).
awlen
Write burst length (number of transfers - 1, 2, 3 .... 32).
awlock[1:0]
Write lock type (type of transaction - normal / exclusive / locked).
awprot[2:0]
Write protection level (normal / privileged / secure protection level).
awready
Write address ready (slave ready to accept an address).
awsize[2:0]
Write burst size (data width of each transfer).
awvalid
Write address valid (valid address and control information available).
bid
Response ID (identification tag of the write response).
bready
Response ready (master ready to accept a write response).
bresp[1:0]
Write response (status of the write transaction - OKAY / EXOKAY, etc.).
bvalid
Write response valid (valid write response available).
cactive
Clock active (peripheral device requires clock signal). Connect it to 1'b1 for normal
operation.
csysack
Low-power request acknowledgement (for a low-power entry request). Connect it to

1'b1 for normal operation.
csysreq
System low-power request (clock controller to peripheral device). Connect it to 1'b1

for normal operation.
rdata
Read data (read data bus - 8-bits to 1024-bits wide).
reset_n
Synchronous reset signal (This active low signal is not part of standard AXI I/F).
rid
Read ID (tag of the read data transfer).
rlast
Read last (last data transfer of the read burst).
rready
Read ready (master ready to accept read data and response).
AMBA AXI
Table 5-1. AMBA AXI Monitor Pins (cont.)

Port
Description
rresp[1:0]
Read response (status of the read transfer - OKAY / SLVERR, etc.).
rvalid
Read valid (valid read data available).
wdata
Write data (write data bus - 8-, 16-, 32-, .... 1024-bits).
wid
Write ID (tag of the write data transaction).
wlast
Write last (last data transfer of the burst).
wready
Write ready (slave ready to accept write data).
wstrb
Write strobe (write data strobe - 1 bit for each 8-bits of write data bus).
wvalid
Write valid (valid write data available on the bus).
Note that the widths of data buses and transaction IDs are implementation specific. Refer to the
Monitor Parameters section below for the appropriate parameter that defines the widths of these
signals.
Monitor Parameters
The parameters shown in Table 5-2 configure the AMBA AXI monitor.
Table 5-2. AMBA AXI Monitor Parameter
Order Parameter
Default Description
1.
Constraints_Mode
This parameter configures the checks in the

monitor as constraints during formal analysis.
2.
INTERFACE_TYPE

0 => Master interface (A in the monitor
implementation diagram)
1 => Slave interface (B in the monitor
implementation diagram)
2=> Master interface of an interconnect (C
in the monitor implementation diagram)
3 => Slave interface of an interconnect (D
in the monitor implementation diagram)
3.
WRITE_DATA_BUS_WIDTH
32
Width of the data bus of the write channel.
4.
READ_DATA_BUS_WIDTH
32
Width of the data bus of the read channel.
5.
TRAN_ID_WIDTH
Width of the transaction IDs - AID, WID, RID,

and BID.
6.
READ_REORDER_DEPTH
This is the read reorder depth of the slave device.

Set this parameter to 1 to indicates that all the
read responses are to be generated in the order of
requests.
77
AMBA AXI
Table 5-2. AMBA AXI Monitor Parameter (cont.)
78
Order Parameter
Default Description
7.
READ_INTERLEAVING_DEPTH
This is the read data interleaving depth of the

device. Set this parameter to 1 to indicate that
read data cannot be interleaved.
8.
WRITE_INTERLEAVING_DEPTH
This is the write data interleaving depth of the

device. Set this parameter to 1 to indicate that
write data cannot be interleaved.
9.
EXCLUSIVE_ACCESS_ENABLE
Set this parameter to 0 to disable exclusive access

tracking. By default, the exclusive access checks
are enabled.
10.
LPI_ENABLE
Set this parameter to 1 to enable LPI checks and

tracking.
11.
MAX_OUTSTANDING_READ_
ADDR
16
This is the maximum number of outstanding read

requests. This indicates the depth of the
outstanding read addresses queue in the monitor.
12.
MAX_OUTSTANDING_WRITE_
ADDR
16
This is the maximum number of outstanding write

requests. This indicates the depth of the
outstanding write addresses queue in the monitor.
13.
CHECK_WRITE_DATA_
FOLLOWS_ADDR_ENABLE
Set this parameter to 1 to enable checking against

write data coming before write address.
14.
ENABLE_RESERVED_VALUE_
CHECKING
Set this parameter to 0 to disable checking for

reserved values on the interface signals.
15.
ENABLE_RECOMMENDATION_
CHECKING
Set this parameter to 1 to enable checking of

compliance to the recommendations in the
specification, which are not mandatory rules to be
adhered to.
16.
LENGTH_WIDTH
This is the width of the ARLEN and AWLEN

signals and indicates the maximum length of read
and write bursts respectively. The default value of
4 indicates the maximum burst length of 16. The
maximum value allowed for this parameter is 5
(i.e., a burst length of 32).
17.
ADDR_WIDTH
32
This is the width of the ARADDR and

AWADDR signals and indicates the width of the
read address and write address, respectively. The
default value is 32.
18.
MAX_UNIQUE_EXCLUSIVE_
ACCESS
16
This is the maximum number of unique exclusive

accesses. The default value of
MAX_OUTSTANDING_READ_ADDR
indicates that the
MAX_OUTSTANDING_READ_ADDR number
of unique accesses can be tracked.
19.
EXCLUSIVE_READ_RESPONSE_
CHECKING_ENABLE
Set this parameter to 0 to disable checking for

expected exclusive read responses.
AMBA AXI
Table 5-2. AMBA AXI Monitor Parameter (cont.)

Order Parameter
Default Description
20.
DATA_X_Z_CHECK_ENABLE
This parameter can be used to enable / disable

checking X / Z on read and/or write data bus. By
default these checks are enabled.
Set this parameter to 0 to disable both write and
read data checks.
Set this parameter to 3 to enable both write and
read data checks.
Set this parameter to 1 to enable only write data
checks.
Set this parameter to 2 to enable only read data
checks.
21.
ALLOW_SLAVE_ERROR_
RESPONSE_AGAINST_
EXCLUSIVE_ACCESS
Normally the monitor expects ok and ex_ok

response from slave against exclusive accesses,
but under certain application circumstances slave
error response may be issued by the slave against
exclusive access such as read only memory
access and so on. Set this parameter to 1 to allow
this.
22.
MAX_OUTSTANDING_WRITE_
DATA
This is the number of data bursts that may be

completed before address controls for any of
these data bursts are issued. This parameter is
applicable when the AXI device supports data
before address scenario.
23.
ENABLE_AWLEN_CHECK_
AGAINST_COMPLETED_DATA_
BEFORE_ADDRESS
Set this parameter to 1 if a delayed check is to be

performed for already finished data phases
against the just issued address phase. This is
relevant for data before scenario.
Note that the parameters must be specified in the above order.
AMBA AXI Monitor Instantiation Examples

Example 1
Example 5-1 instantiates an AMBA AXI monitor on an AMBA AXI master interface with both
read and write channels having the same width of 32 bits, width of all the IDs being 4, and a
maximum of 16 outstanding read and 16 outstanding write addresses. The read reorder depth is
taken as 8 and is therefore the write data interleaving depth. Exclusive access support is
disabled and low power interface support is enabled.
Example 5-1. AMBA AXI Monitor Instantiation for Example 1
qvl_amba_axi_monitor #(
1,
/* Constraints_Mode */
0,
32,
/* WRITE_DATA_BUS_WIDTH */
32,
/* READ_DATA_BUS_WIDTH */
4,
/* TRAN_ID_WIDTH */
8,
/* READ_REORDER_DEPTH */
8,
/* READ_INTERLEAVING_DEPTH */
8,
/* WRITE_INTERLEAVING_DEPTH */
79
AMBA AXI
0,
/* EXCLUSIVE_ACCESS_ENABLE */
1,
/* LPI_ENABLE */
16,
/* MAX_OUTSTANDING_READ_ADDR */
16,
/* MAX_OUTSTANDING_WRITE_ADDR */
1,
/* CHECK_WRITE_DATA_FOLLOWS_ADDR_ENABLE */
1,
/* ENABLE_RESERVED_VALUE_CHECKING */
1,
/* ENABLE_RECCOMENDATION_CHECKING */
4,
/* LENGTH_WIDTH */
32
/* ADDR_WIDTH */
)
AMBA_AXI_MONITOR
(.aclk(aclk),
.areset_n(areset_n),
.reset_n(!reset),
.arvalid(arvalid),
.araddr(araddr),
.arlen(arlen),
.arsize(arsize),
.arburst(arburst),
.arlock(arlock),
.arcache(arcache),
.arprot(arprot),
.arid(arid),
.arready(arready),
.awvalid(awvalid),
.awaddr(awaddr),
.awlen(awlen),
.awsize(awsize),
.awburst(awburst),
.awlock(awlock),
.awcache(awcache),
.awprot(awprot),
.awid(awid),
.awready(awready),
.wvalid(wvalid),
.wlast(wlast),
.wdata(wdata),
.wstrb(wstrb),
.wid(wid),
.wready(wready),
.rvalid(rvalid),
.rlast(rlast),
.rdata(rdata),
.rresp(rresp),
.rid(rid),
.rready(rready),
.bvalid(bvalid),
.bresp(bresp),
.bid(bid),
.bready(bready),
.cactive(cactive),
.csysreq(csysreq),
.csysack(csysack)
);
80
AMBA AXI
Example 2
Example 5-2 instantiates an AMBA AXI monitor on an AMBA AXI slave interface with read
and write channels having different widths of 8-bits and 32-bits, respectively, and the width of
all the IDs is 4 and a maximum of 16 outstanding read and 16 outstanding write addresses. The
read reorder depth is taken as 8 and therefore, is the write data interleaving depth. Exclusive
access support and low power interface support are enabled. Checks pertaining to reserved
values and recommendations are disabled.
Example 5-2. AMBA AXI Monitor Instantiation for Example 2
qvl_amba_axi_monitor #(
1,
1,
32,
/* WRITE_DATA_BUS_WIDTH */
8,
/* READ_DATA_BUS_WIDTH */
4,
/* TRAN_ID_WIDTH */
8,
/* READ_REORDER_DEPTH */
8,
/* READ_INTERLEAVING_DEPTH */
8,
/* WRITE_INTERLEAVING_DEPTH */
1,
/* EXCLUSIVE_ACCESS_ENABLE */
1,
/* LPI_ENABLE */
16,
/* MAX_OUTSTANDING_READ_ADDR */
16,
/* MAX_OUTSTANDING_WRITE_ADDR */
1,
/* CHECK_WRITE_DATA_FOLLOWS_ADDR_ENABLE */
0,
/* ENABLE_RESERVED_VALUE_CHECKING */
0,
/* ENABLE_RECCOMENDATION_CHECKING */
4,
/* LENGTH_WIDTH */
32
/* ADDR_WIDTH */
)
AMBA_AXI_MONITOR
(.aclk(aclk),
.areset_n(areset_n),
.reset_n(!reset),
.arvalid(arvalid),
.araddr(araddr),
.arlen(arlen),
.arsize(arsize),
.arburst(arburst),
.arlock(arlock),
.arcache(arcache),
.arprot(arprot),
.arid(arid),
.arready(arready),
.awvalid(awvalid),
.awaddr(awaddr),
.awlen(awlen),
.awsize(awsize),
.awburst(awburst),
.awlock(awlock),
.awcache(awcache),
.awprot(awprot),
.awid(awid),
.awready(awready),
.wvalid(wvalid),
81
AMBA AXI
Monitor Checks
.wlast(wlast),
.wdata(wdata),
.wstrb(wstrb),
.wid(wid),
.wready(wready),
.rvalid(rvalid),
.rlast(rlast),
.rdata(rdata),
.rresp(rresp),
.rid(rid),
.rready(rready),
.bvalid(bvalid),
.bresp(bresp),
.bid(bid),
.bready(bready),
.cactive(cactive),
.csysreq(csysreq),
.csysack(csysack)
);
Monitor Checks
Table 5-3 shows the general checks performed by the AMBA AXI monitor.
Table 5-3. AMBA AXI Monitor Checks
82
Check ID
Violation
Description
AMBA_AXI_ADDR_ACROSS_
4K_WITHIN_LOCKED_READ_
SEQUENCE
Transactions within a locked

read sequence should be
within the same 4K
boundary.
Since the locked sequences can have an

impact on the interconnect performance, it
is recommended to keep the locked read
sequences within the same 4K address
region. Although this is strictly not a
violation, this check fires whenever a read
transaction within a locked window is
addressed to a different 4K byte region
compared to the previous transaction. This
check is active only when the parameter
ENABLE_
RECOMMENDATION_CHECKING is
set to 1.
AMBA_AXI_ADDR_ACROSS_
4K_WITHIN_LOCKED_WRITE_
SEQUENCE
Transactions within a locked

write sequence should be
within the same 4K
boundary.
Since the locked sequences can have an

impact on the interconnect performance, it
is recommended to keep locked write
sequences within the same 4K address
region. Although this is strictly not a
violation, this check fires whenever a write
transaction within a locked window is
addressed to a different 4K byte region
compared to the previous transaction. This
ENABLE_
set to 1.
AMBA AXI
Monitor Checks
Table 5-3. AMBA AXI Monitor Checks (cont.)

Check ID
Violation
Description
AMBA_AXI_ADDR_FOR_
READ_BURST_ACROSS_4K_
BOUNDARY
The read address/control

signals issued should not
result in data access across a
4K boundary.
To prevent incrementing type read bursts

from crossing boundaries between slaves
and to limit the size of the address
incrementer required within a slave, read
data bursts must not cross 4K boundaries.
This check fires if the starting address,
length, and size issued is such that the read
burst crosses the applicable 4K boundary.
AMBA_AXI_ADDR_FOR_
WRITE_BURST_ACROSS_4K_
BOUNDARY
The write address/control

signals issued should not
result in data access across a
4K boundary.
To prevent incrementing type write bursts

from crossing boundaries between slaves
and to limit the size of the address
incrementer required within a slave, write
data bursts must not cross 4K boundaries.
This check fires if the starting write
address, length, and size issued is such that
the burst crosses the applicable 4K
boundary.
AMBA_AXI_ARADDR_UNKN
ARADDR signal should not

be X or Z.
Checks that ARADDR is both known (not

X) and driven (not Z). This check is active
only when ARVALID is high.
AMBA_AXI_ARBURST_UNKN
ARBURST signal should

not be X or Z.
Checks that ARBURST is both known (not

AMBA_AXI_ARCACHE_UNKN
ARCACHE signal should

not be X or Z.
Checks that ARCACHE is both known

(not X) and driven (not Z). This check is
active only when ARVALID is high.
AMBA_AXI_ARID_CHANGED_
WITHIN_LOCKED_READ_
SEQUENCE
All transactions within a

locked read sequence should
have the same ARID.
The master must ensure that all

transactions within a locked read sequence
have the same ARID value. This check
fires whenever this requirement is violated.
AMBA_AXI_ARID_UNKN
ARID signal should not be X Checks that ARID is both known (not X)
or Z.
and driven (not Z). This check is active
AMBA_AXI_ARLEN_UNKN
ARLEN signal should not be Checks that ARLEN is both known (not X)
X or Z.
AMBA_AXI_ARLOCK_UNKN
ARLOCK signal should not

be X or Z.
Checks that ARLOCK is both known (not

AMBA_AXI_ARPROT_
ARCACHE_CHANGED_
WITHIN_LOCKED_SEQUENCE
It is recommended that a
master should not change
ARPROT or ARCACHE
during a sequence of locked
accesses.
Locked accesses require that the

interconnect prevents other transactions
occurring while the locked sequence is in
progress and can therefore have an impact
on the interconnect performance. It is
recommended that the read cache
(ARCACHE) and read protection unit
(ARPROT) information be held steady
during a locked sequence. This check fires
when any of these change during a locked
sequence and ENABLE_
set to 1.
83
AMBA AXI
Monitor Checks
84
Check ID
Violation
Description
AMBA_AXI_ARPROT_UNKN
ARPROT signal should not

be X or Z.
Checks that ARPROT is both known (not

AMBA_AXI_ARREADY_UNKN
ARREADY signal should

not be X or Z.
Checks that ARREADY is both known

(not X) and driven (not Z).
AMBA_AXI_ARSIZE_UNKN
ARSIZE signal should not

be X or Z.
Checks that ARSIZE is both known (not

AMBA_AXI_ARVALID_
DEASSERTED_BEFORE_
ARREADY
ARVALID should be held

asserted until the slave
asserts ARREADY.
The master can assert ARVALID only

when it drives valid read address and
control information on the bus. It must be
held asserted until the slave accepts the
address and control information and
indicates the same by asserting the
ARREADY signal. This check fires if
ARVALID is detected de-asserted (after
being sampled asserted) even before
ARREADY is asserted.
AMBA_AXI_ARVALID_UNKN
ARVALID signal should not Checks that ARVALID is both known (not
be X or Z.
X) and driven (not Z).
AMBA_AXI_AWADDR_UNKN
AWADDR signal should not Checks that AWADDR is both known (not
be X or Z.
only when AWVALID is high.
AMBA_AXI_AWBURST_UNKN
AWBURST signal should

not be X or Z.
Checks that AWBURST is both known

active only when AWVALID is high.
AMBA_AXI_AWCACHE_UNKN
AWCACHE signal should

not be X or Z.
Checks that AWCACHE is both known

active only when AWVALID is high.
AMBA_AXI_AWID_CHANGED_
WITHIN_LOCKED_WRITE_
SEQUENCE
All transactions within a

locked write sequence
should have the same
AWID.
The master must ensure that all

transactions within a locked write
sequence have the same AWID value. This
check fires whenever this requirement is
violated.
AMBA_AXI_AWID_UNKN
AWID signal should not be

X or Z.
Checks that AWID is both known (not X)

AMBA_AXI_AWLEN_
MISMATCHED_WITH_
ACTUAL_LENGTH_OF_WRITE_
DATA_BURST
Address follows data

scenario: Awlen value in
address control for
outstanding data does not
match actual length of data
burst
This assertion verifies the awlen field

when address is issued later than data. This
check keeps track of data burst length
actually transferred when data completes
before address and matches the same when
address control (mainly awlen)
information is available. This check
applies only when the parameter
ENABLE_AWLEN_CHECK_
AGAINST_COMPLETED_DATA_
BEFORE_ADDRESS is set to 1.
AMBA AXI
Monitor Checks

Check ID
Violation
Description
AMBA_AXI_AWLEN_UNKN
AWLEN signal should not

be X or Z.
Checks that AWLEN is both known (not

AMBA_AXI_AWLOCK_UNKN
AWLOCK signal should not

be X or Z.
Checks that AWLOCK is both known (not

AMBA_AXI_AWPROT_
AWCACHE_CHANGED_
WITHIN_LOCKED_SEQUENCE
It is recommended that a
master should not change
AWPROT or AWCACHE
during a sequence of locked
accesses.
Locked accesses require that the

interconnect prevents other transactions
occurring while the locked sequence is in
progress and can therefore have an impact
on the interconnect performance. It is
recommended that the write cache
(AWCACHE) and protection unit
(AWPROT) information be held steady
during a locked sequence. This check fires
when any of these change during a locked
sequence and ENABLE_
set to 1.
AMBA_AXI_AWPROT_UNKN
AWPROT signal should not

be X or Z.
Checks that AWPROT is both known (not

AMBA_AXI_AWREADY_UNKN
AWREADY signal should

not be X or Z.
Checks that AWREADY is both known

AMBA_AXI_AWSIZE_UNKN
AWSIZE signal should not

be X or Z.
Checks that AWSIZE is both known (not

AMBA_AXI_AWVALID_
DEASSERTED_BEFORE_
AWREADY
AWVALID should be held

asserts AWREADY.
The master can assert AWVALID only

when it drives valid write address and
control information on the bus. It must be
held asserted until the slave accepts the
write address and control information, and
indicates the same by asserting the
AWREADY signal. This check fires if
AWVALID is detected de-asserted (after
AWREADY is asserted.
AMBA_AXI_AWVALID_UNKN
AWVALID signal should

not be X or Z.
Checks that AWVALID is both known

AMBA_AXI_BID_CHANGED_
BEFORE_BREADY
Once BVALID is asserted,

BID should not change until
BREADY is asserted.
Once the slave asserts BVALID indicating

availability of a valid write response on the
bus, it must hold the BID value stable until
the master accepts the same with
BREADY. This check fires if the BID
value changes even before the master
asserts BREADY.
AMBA_AXI_BID_UNKN
BID signal should not be X

or Z.
Checks that BID is both known (not X) and

driven (not Z). This check is active only
when BVALID is high.
AMBA_AXI_BREADY_UNKN
BREADY signal should not

be X or Z.
Checks that BREADY is both known (not

85
AMBA AXI
Monitor Checks
86
Check ID
Violation
Description
AMBA_AXI_BRESP_UNKN
BRESP signal should not be

X or Z.
Checks that BRESP is both known (not X)

only when BVALID is high.
AMBA_AXI_BVALID_
DEASSERTED_BEFORE_
BREADY
BVALID should be held

asserted until the master
asserts BREADY.
The slave can assert BVALID only when it

drives a valid write response on the bus. It
must be held asserted until the master
accepts the response and indicates the
same by asserting the BREADY signal.
This check fires if BVALID is detected deasserted (after being sampled asserted)
even before BREADY is asserted.
AMBA_AXI_BVALID_UNKN
BVALID signal should not

be X or Z.
Checks that BVALID is both known (not

AMBA_AXI_CACTIVE_UNKN
CACTIVE signal should not

be X or Z.
Checks that CACTIVE is both known (not

only when the parameter LPI_ENABLE is
set to 1.
AMBA_AXI_CSYSACK_
ASSERTION_VIOLATION
CSYSACK should not be

asserted before CSYSREQ
is asserted.
An exit from low-power state begins with

the clock controller asserting CSYSREQ.
The peripheral should then assert
CSYSACK acknowledging the exit. This
check fires if the peripheral indicates an
exit by asserting CSYSACK even before
being directed by the controller. This check
is active only when LPI_ENABLE is set to
1.
AMBA_AXI_CSYSACK_
DEASSERTION_VIOLATION
Once asserted, CSYSACK

should not be de-asserted
before CSYSREQ is deasserted.
To request that the peripheral enter a lowpower state, the system clock controller
drives the CSYSREQ signal low. Only
then the peripheral can drive the
CSYSACK signal low to acknowledge the
entry to low-power state. This check fires
if this relationship is violated. This check
is active only when LPI_ENABLE is set to
1.
AMBA_AXI_CSYSACK_UNKN
CSYSACK signal should

not be X or Z.
Checks that CSYSACK is both known (not

set to 1.
AMBA_AXI_CSYSREQ_
ASSERTION_VIOLATION
Once de-asserted,
CSYSREQ should not be
asserted before CSYSACK
acknowledged the request
for entry into the low-power
state.
The clock controller requests the

peripheral device to enter a low-power
state by de-asserting CSYSREQ. This is
then acknowledged by the peripheral by
de-asserting CSYSACK. This check fires
if the clock controller asserts CSYSREQ
(requests an exit from low-power state)
even before the peripheral acknowledges
entry to the low-power state. This check is
active only when LPI_ENABLE is set to 1.
AMBA AXI
Monitor Checks

Check ID
Violation
Description
AMBA_AXI_CSYSREQ_
DEASSERTION_VIOLATION
CSYSREQ should not be deasserted to indicate new

request for entry to lowpower state even before the
previous exit from lowpower state was
acknowledged.
Once the clock controller indicates an exit

from low-power state, it must wait until the
peripheral asserts CSYSACK to
acknowledge the exit and only then deassert CSYSREQ to indicate a new lowpower entry request. This check fires if this
requirement is violated. This check is
active only when LPI_ENABLE is set to 1.
AMBA_AXI_CSYSREQ_UNKN
CSYSREQ signal should not Checks that CSYSREQ is both known (not
be X or Z.
set to 1.
AMBA_AXI_DATA_ISSUED_
EXCEEDS_MAX_ALLOWED_
OUTSTANDING_DATA_
BEFORE_ADDRESS
Address follows data

scenario: New data burst
should not be initiated while
number of completed data
burst has reached allowed
maximum outstanding data.
This check fires when number of

completed data bursts without addresses
exceeds the allowed number of outstanding
completed data before address. The
allowed number of outstanding completed
data before address is set by the parameter
MAX_OUTSTANDING_WRITE_DATA.
AMBA_AXI_DECODE_ERROR_
RESPONSE_BY_SLAVE
A slave should not issue

DECERR response.
In a system without a fully decoded

address map, the interconnect must provide
a suitable decode error response for
addresses at which there are no slaves to
respond to a transactions. A slave cannot
respond with a decode error as it is unable
to identify the address in the first place.
This check fires if a decode error is
detected on the slave side. This check is
active only when INTERFACE_TYPE is
set to 1.
AMBA_AXI_EX_WRITE_
BEFORE_EX_READ_RESPONSE
An exclusive write access

should not be performed
until the previously issued
exclusive read has been
responded.
The exclusive access consists of two parts:

the exclusive read followed by the
exclusive write (typically done only if the
exclusive read returns an EXOKAY
response). This check fires if the master
attempts the exclusive write even before an
exclusive read. This check is active only
when the parameter EXCLUSIVE_
ACCESS_ENABLE is set to 1.
Note that this check activates after a valid
EXREAD waiting of a response.
AMBA_AXI_EXCLUSIVE_
ACCESS_ADDRESS_
VIOLATION
The address and control

signals of an exclusive write
should be identical to that of
the exclusive read.
A requirement for an exclusive write

access to be successful is that all the
address and control signals, except for
AWRITE must be identical with the one
that is being monitored. This check fires
whenever an exclusive write access is
performed on a location other than the one
being monitored against that ID. This
check is active only when both
EXCLUSIVE_ACCESS_ENABLE and
INTERFACE_TYPE are set to 1.
87
AMBA AXI
Monitor Checks

Check ID
Violation
Description
AMBA_AXI_EXCLUSIVE_
ACCESS_WHILE_EXCLUSIVE_
ACCESS_NOT_SUPPORTED
Exclusive access may not be This check fires if the exclusive access is
tried by a master as the
tried by a master as the exclusive access
exclusive access
functionality is set.
functionality is configured to
be not supported by setting
EXCLUSIVE_ACCESS_
ENABLE to 0
AMBA_AXI_EXCLUSIVE_
READ_ACCESS_CACHEABLE
An exclusive read access

should not have the
cacheable attribute set.
An exclusive read access being monitored

by a slave must not be cacheable, to ensure
that it sees this transaction. This check
fires if an exclusive read access has the
cacheable attribute set. This check is active
only when the parameter
EXCLUSIVE_ACCESS_ENABLE is set
to 1.
AMBA_AXI_EXCLUSIVE_
READ_RESPONSE_MISMATCH
The exclusive read response

detected should match the
expected response.
A master starts an exclusive operation by

performing an exclusive read, for which
the slave returns an EXOKAY (success) or
an OKAY (failure). The monitor tracks the
exclusive access and internally determines
the expected response for a particular
exclusive read access. This check fires if
the response from the slave does not match
the expected response.
In case of a SLVERR response from the
slave or interconnect during exclusive
access monitoring, this check fails as the
monitor expects only OKAY or EXOKAY
during exclusive access transactions.
88
AMBA_AXI_EXCLUSIVE_
READ_SIZE_EXCEEDS_128
The number of bytes

transferred in an exclusive
read burst should not exceed
128.
The maximum number of bytes that can be

transferred in an exclusive burst is 128.
This check fires when this requirement is
violated.
AMBA_AXI_EXCLUSIVE_
READ_SIZE_NON_POWER_
OF_2
The number of bytes

read access should be a
power of 2.
The total number of bytes to be transferred

in an exclusive read burst must be a power
of 2, that is, 1, 2, 4, 8, 16, 32, 64, or 128
bytes. This effectively puts the restriction
that the burst length of the exclusive read
access must be a power of 2, since burst
size is always a power of 2. This check
fires when this requirement is violated.
AMBA_AXI_EXCLUSIVE_
WRITE_ACCESS_CACHEABLE
An exclusive write access

should not have the
cacheable attribute set.
An exclusive write access being monitored

by a slave must not be cacheable, to ensure
that it sees this transaction. This check
fires if an exclusive write access has the
cacheable attribute set. This check is active
only when the parameter EXCLUSIVE_
ACCESS_ENABLE is set to 1.
AMBA AXI
Monitor Checks

Check ID
Violation
Description
The exclusive write response Once the master receives an EXOKAY

AMBA_AXI_EXCLUSIVE_
response for the exclusive read, it can
WRITE_RESPONSE_MISMATCH detected should match the
expected response.
perform an exclusive write to that location.
The monitor tracks the exclusive access
and internally determines the expected
response for a particular exclusive read
access. The slave returns an EXOKAY
indicating a success or an OKAY
indicating a failure. This check fires if the
response from the slave does not match the
expected response.
In case of a SLVERR response from the
slave or interconnect during exclusive
access monitoring, this check fails as the
monitor expects only OKAY or EXOKAY
during exclusive access transactions.
AMBA_AXI_EXCLUSIVE_
WRITE_SIZE_EXCEEDS_128
The number of bytes

write burst should not
exceed 128.
The maximum number of bytes that can be

transferred in an exclusive burst is 128.
violated.
AMBA_AXI_EXCLUSIVE_
WRITE_SIZE_NON_POWER_
OF_2
The number of bytes

write access should be a
power of 2.
The number of bytes to be transferred in an

exclusive access burst must be a power of
2, that is, 1, 2, 4, 8, 16, 32, 64, or 128
bytes. This check fires when this
requirement is violated.
AMBA_AXI_ILLEGAL_
LENGTH_WRAPPING_READ_
BURST
Burst length for a wrapping

read burst should be 2, 4, 8,
or 16.
The legal values of burst length in case of

wrapping read bursts are 2, 4, 8, and 16.
This check fires whenever the length
specified for a wrapping type read burst
transaction violates this requirement.
AMBA_AXI_ILLEGAL_
LENGTH_WRAPPING_WRITE_
BURST
Burst length for a wrapping

write burst should be 2, 4, 8,
or 16.
The legal values of burst length in the case

of wrapping write bursts are 2, 4, 8, and 16.
This check fires whenever the length
specified for a wrapping type write burst
transaction violates this requirement.
AMBA_AXI_ILLEGAL_
RESPONSE_EXCLUSIVE_READ
Response for an exclusive

read should not be other than
OKAY or EXOKAY.
A slave that supports exclusive operations

must return either an OKAY (to indicate a
failure) or EXOKAY (to indicate a
success). This check fires when an
exclusive read returns a response other
than OKAY and EXOKAY.
AMBA_AXI_ILLEGAL_
RESPONSE_EXCLUSIVE_
WRITE
Response for an exclusive

write should not be other
than OKAY or EXOKAY.
A slave that supports exclusive write

operations must return either an OKAY (to
indicate a failure) or EXOKAY (to indicate
a success). This check fires when an
exclusive write returns a response other
than OKAY and EXOKAY.
AMBA_AXI_ILLEGAL_
RESPONSE_NORMAL_READ
An EXOKAY response
should not be returned for a
normal (nonexclusive) read
operation.
The EXOKAY is an invalid response for

normal (nonexclusive) operations. This
check fires if an EXOKAY response is
detected for a nonexclusive read access.
89
AMBA AXI
Monitor Checks
90
Check ID
Violation
Description
AMBA_AXI_ILLEGAL_
RESPONSE_NORMAL_WRITE
An EXOKAY response
should not be returned for a
normal (nonexclusive) write
operation.
The EXOKAY is an invalid response for

normal (nonexclusive) operations. This
check fires if an EXOKAY response is
detected for a nonexclusive write access.
AMBA_AXI_INCORRECT_
LOW_POWER_SIGNAL_LEVEL
Any of the low power signal For low power interface disabled, the three
is not tied HIGH for disabled low power interface signals must be tied to
low power configuration.
HIGH. This check fires when any of the
low power interface signals is not sampled
HIGH.
AMBA_AXI_LOCKED_READ_
BEFORE_COMPLETION_OF_
PREVIOUS_READS
A locked read sequence

should not commence before
completion of all previously
issued read addresses.
When a master starts a locked sequence of

read transactions, it must ensure that it has
no other outstanding transactions waiting
to complete. This check fires when a
locked sequence of read transactions is
started when one or more previously issued
read transactions are waiting for response
from the slave.
AMBA_AXI_LOCKED_READ_
PREVIOUS_WRITES
A locked read sequence

issued write addresses.

read transactions, it must ensure that it has
locked sequence of read transactions is
write transactions are waiting for response
from the slave.
AMBA_AXI_LOCKED_WRITE_
PREVIOUS_READS
A locked write sequence

issued read addresses.

write transactions, it must ensure that it has
locked sequence of write transactions is
read transactions are waiting for response
from the slave.
AMBA_AXI_LOCKED_WRITE_
PREVIOUS_WRITES
A locked write sequence

issued write addresses.

write transactions, it must ensure that it has
locked sequence of write transactions is
read transactions were waiting for a
response from the slave.
AMBA_AXI_NUMBER_OF_
LOCKED_READ_ACCESSES_
EXCEEDS_2
Number of accesses within a

locked read sequence should
not be more than two.
To reduce the impact of long locked read

data sequences on interconnect
performance (since no other master can
access that slave region until the current
master performs an unlocked transaction),
it is recommended to limit locked read
sequences to two transactions. Although
strictly not a violation, this check fires to
indicate locked sequences exceeding two
transactions. This check is active only
when the parameter ENABLE_
set to 1.
AMBA AXI
Monitor Checks

Check ID
Violation
AMBA_AXI_NUMBER_OF_
LOCKED_WRITE_ACCESSES_
EXCEEDS_2
Number of accesses within a To reduce the impact of long locked write

locked write sequence
data sequences on interconnect
should not be more than two. performance (since no other master can
access that slave region until the current
master performs an unlocked transaction),
it is recommended to limit locked
sequences to two transactions. Although
strictly not a violation, this check fires to
indicate locked write sequences exceeding
two transactions. This check is active only
when ENABLE_
set to 1.
AMBA_AXI_PARAM_READ_
DATA_BUS_WIDTH
READ_DATA_BUS_
WIDTH parameter should
be one of 8, 16, 32, 64, 128,
256, 512, or 1024.
The AMBA AXI specification provides for

a configurable read data bus width. The
legal values of read data bus width are 8,
16, 32, 64, 128, 256, 512, and 1024 bits.
This check fires if this requirement is
violated.
AMBA_AXI_PARAM_WRITE_
DATA_BUS_WIDTH
WRITE_DATA_BUS_
WIDTH parameter should
be one of 8, 16, 32, 64, 128,
256, 512, or 1024.
The AMBA AXI specification provides for

a configurable write data bus width. The
legal values of write data bus width are 8,
16, 32, 64, 128, 256, 512, and 1024 bits.
This check fires if this requirement is
violated.
AMBA_AXI_READ_ADDR_
UNLOCK_TRANSACTION
The unlocking transaction of

a locked read sequence
should be completed before
further transactions are
initiated.
The master must ensure that the final

unlocking read transaction has fully
completed before any further transactions
are initiated. This check fires when this
AMBA_AXI_READ_ADDR_
CNTRL_CHANGED_BEFORE_
ARREADY
Once ARVALID is asserted,

the read address/control
signals {araddr, arlen, arsize,
arburst, arlock, arcache,
arprot, arid} should not
change until ARREADY is
asserted.
Once the master asserts ARVALID

indicating the availability of the valid read
address and control information on the bus,
it must hold these values stable until the
slave accepts them with ARREADY. This
check fires if the address/control values
change even before the slave asserts
ARREADY.
AMBA_AXI_READ_
ALLOCATE_WHEN_NON_
CACHEABLE
Read allocate bit of a read

address should not be HIGH
when the cacheable bit is
LOW.
When the read allocate bit is HIGH, it

indicates that a read access that misses
cache hit can be allocated in the cache.
This cannot be done when the access is not
cacheable in the first place. This check
fires if the attributes specified violates this
requirement.
AMBA_AXI_READ_BURST_
LENGTH_VIOLATION
Length of the read burst

detected should match the
expected length.
The number of transfers in a read burst

should equal the requested length
(ALEN+1). This check fires if the actual
number of transfers detected in a read burst
differs from the requested length.
Description
91
AMBA AXI
Monitor Checks
92
Check ID
Violation
Description
AMBA_AXI_READ_BURST_
SIZE_VIOLATION
Read burst size should not

exceed the data bus width.
The burst size indicates the maximum

number of data bytes to transfer in each
read data transfer within a burst. This must
not exceed the read data bus width of the
components in the transaction. This check
AMBA_AXI_READ_DATA_
BEFORE_ADDRESS
Read data transfer should

not be performed before the
corresponding read address.
A read data/response from a slave should

always follow the address (request from
the master). This check fires when a read
response is detected for which an
outstanding read address with AID the
same as the RID does not exist.
AMBA_AXI_READ_DATA_
RESP_CHANGED_BEFORE_
RREADY
Once RVALID is asserted,

read data/response should
not change until RREADY
is asserted.
Once the slave asserts RVALID indicating

availability of valid read data/response on
the bus, it must hold these values stable
until the master accepts them with
RREADY. This check fires if the read
data/response values change even before
the master asserts RREADY.
AMBA_AXI_READ_DATA_
UNKN
Read data should not be

driven with X or Z.
This check fires when the AXI slave

device returns X or Z on the read data bus.
The parameter
DATA_X_Z_CHECK_ENABLE controls
enabling of the check. By default, this
check is OFF. Refer to parameter
DATA_X_Z_CHECK_ENABLE for
enabling the check. This check supports
narrow transfers on the read data bus;
checks only the byte lanes that matter.
AMBA_AXI_READ_
INTERLEAVE_DEPTH_
VIOLATION
Read interleaving depth has

exceeded the allowed read
interleaving depth.
This check fires when read interleaving

depth exceeds the allowed read
interleaving depth set by the parameter
READ_INTERLEAVING_DEPTH.
AMBA_AXI_READ_REORDER_
DEPTH_VIOLATION
Read data should not be

reordered beyond the read
data reordering depth.
The read data reordering depth is a static

value that indicates the maximum
reordering capability of the slave. This
check fires if a read data is detected for
which the corresponding address is beyond
the reordering depth. This depth is
configured using
READ_REORDER_DEPTH.
AMBA_AXI_RESERVED_
ARLOCK_ENCODING
The reserved encoding of

2'b11 should not be used for
ARLOCK.
To enable the implementation of atomic

access primitives, the ARLOCK or
AWLOCK signal provides exclusive
access and locked access. The ARLOCK
signal being 2-bit wide, it indicates
whether the access is a normal / locked /
exclusive access. The unused encoding of
2'b11 is reserved. This checks if this
encoding is used and the parameter
CHECKING is set to 1.
AMBA AXI
Monitor Checks

Check ID
Violation
Description
AMBA_AXI_RESERVED_
AWLOCK_ENCODING
The reserved encoding of

2'b11 should not be used for
AWLOCK.
To enable the implementation of atomic

access primitives, the ARLOCK or
AWLOCK signal provides exclusive
access and locked access. The AWLOCK
signal being 2-bit wide, it indicates
whether the access is a normal / locked /
exclusive access. The unused encoding of
2'b11 is reserved. This check if this
AMBA_AXI_RESERVED_
READ_BURST_TYPE
Read burst type encoding

should not be a reserved
value of 2'b11.
The burst-type control signals define the

type of read burst. The AXI protocol
provides for three types of read bursts:
Fixed, Incrementing, and Wrapping. This
being a 2-bit field, the unused encoding of
2'b11 is reserved. This check fires if this
AMBA_AXI_RESERVED_
WRITE_BURST_TYPE
Write burst type encoding

should not be a reserved
value of 2'b11.
The burst-type control signals define the

type of write burst. The AXI protocol
provides for three types of write bursts:
Fixed, Incrementing, and Wrapping. This
being a 2-bit field, the unused encoding of
2'b11 is reserved. This check fires if this
encoding is used and ENABLE_
RESERVED_VALUE_CHECKING is set
to 1.
AMBA_AXI_RID_CHANGED_
BEFORE_RREADY

RID should not change until
RREADY is asserted.
Once the slave asserts RVALID indicating

availability of a valid read data on the bus,
it must hold the RID value stable until the
master accepts them with RREADY. This
check fires if the RID value changes even
before the master asserts RREADY.
AMBA_AXI_RID_UNKN
RID signal should not be X

or Z.
Checks that RID is both known (not X) and

driven (not Z). This check is active only
when RVALID is high.
AMBA_AXI_RLAST_
CHANGED_BEFORE_RREADY

RLAST should not change
until RREADY is asserted.
The slave can assert RLAST only when it

drives RVALID. Once the slave asserts
RVALID indicating availability of a valid
read data on the bus, it must hold RLAST
stable until the master accepts them with
RREADY. This check fires if RLAST is
toggled even before RREADY is sampled
asserted.
AMBA_AXI_RLAST_UNKN
RLAST signal should not be

X or Z.
Checks that RLAST is both known (not X)

only when RVALID is high.
93
AMBA AXI
Monitor Checks
94
Check ID
Violation
Description
AMBA_AXI_RLAST_
VIOLATION
RLAST signal should be

asserted along with the final
transfer of the read data
burst.
In case of read accesses, the slave must

drive a burst of data and response starting
from the address issued and indicate the
final data transfer by asserting the RLAST
signal. This check fires when the RLAST
signal is not sample asserted along with the
last transfer of the read burst.
AMBA_AXI_RREADY_UNKN
RREADY signal should not

be X or Z.
Checks that RREADY is both known (not

AMBA_AXI_RRESP_UNKN
RRESP signal should not be

X or Z.
Checks that RRESP is both known (not X)

only when RVALID is high.
AMBA_AXI_RVALID_
DEASSERTED_BEFORE_
RREADY
RVALID should be held

asserted until the master
asserts RREADY.
The slave can assert RVALID only when it

drives valid data on the bus. It must be held
asserted until the master accepts the data
and indicates the same by asserting the
RREADY signal. This check fires if
RVALID is detected de-asserted (after
RREADY is asserted.
AMBA_AXI_RVALID_UNKN
RVALID signal should not

be X or Z.
Checks that RVALID is both known (not

AMBA_AXI_SIMULTANEOUS_
LOCK_WRITE_AND_LOCK_
READ_ACCESS
A master must not execute

This check fires is the lock write and lock
both lock write and lock read read are executed at the same time.
access at the same time.
AMBA_AXI_UNALIGNED_
ADDR_FOR_WRAPPING_
READ_BURST
Starting address of a
wrapping read burst should
be aligned to the size of the
transfer.
Wrapping read data bursts have the

restriction that the starting address must be
aligned to the size of the data transfer. This
check fires if this requirement is violated
(starting address is unaligned).
AMBA_AXI_UNALIGNED_
ADDR_FOR_WRAPPING_
WRITE_BURST
Starting address of a
wrapping write burst should
be aligned to the size of the
transfer.
Wrapping write bursts have the restriction

that the starting write address must be
aligned to the size of the data transfer. This
check fires if this requirement is violated
(starting address is unaligned).
AMBA_AXI_UNALIGNED_
ADDRESS_FOR_EXCLUSIVE_
READ
The start address of an

exclusive read should be
aligned to the total number
of bytes in the transaction.
The address of an exclusive read access

must be aligned to the total number of
bytes in the transaction. This check fires
when this requirement is violated.
AMBA_AXI_UNALIGNED_
ADDRESS_FOR_EXCLUSIVE_
WRITE
The start address of an

exclusive write should be
aligned to the total number
of bytes in the transaction.
The address of an exclusive write access

must be aligned to the total number of
bytes in the transaction. This check fires
when this requirement is violated.
AMBA AXI
Monitor Checks

Check ID
Violation
Description
AMBA_AXI_UNLOCKED_
READ_WHILE_
OUTSTANDING_LOCKED_
READS
All previous locked read

transactions should be
completed before unlocking
a locked read sequence.
Any transaction with ARLOCK[1:0] set to

indicate a locked sequence forces the
interconnect to lock the read transaction
that follows. Therefore, a locked sequence
must always complete with a final
transaction that does not have
ARLOCK[1:0] set to indicate a locked
access. This final transaction removes the
lock. When completing a locked sequence,
a master must ensure that all previous
locked transactions are complete before
issuing the final unlocking transaction.
violated.
AMBA_AXI_UNLOCKED_
READ_WHILE_
OUTSTANDING_LOCKED_
WRITES
Unlocking read transaction

is detected while current
locked write transaction is
not yet complete.
If the bus / interconnect is locked by a

write from a master already, then the same
can be unlocked by a read or write
unlocking transaction by the same master
only after completion of the current lock
write transaction. This check fires when an
unlocking read transaction issued by a
master is detected while there is an
incomplete lock write transaction exists
issued by the same master.
AMBA_AXI_UNLOCKED_
WRITE_WHILE_
OUTSTANDING_LOCKED_
READS
Unlocking write transaction

is detected while current
locked read transaction is
not yet complete.
If the bus / interconnect is locked by a read

from a master already, then the same can
be unlocked by a read or write unlocking
transaction by the same master only after
completion of the current lock read
transaction. This check fires when an
unlocking write transaction issued by a
master is detected while there is an
incomplete lock read transaction exists
issued by the same master.
AMBA_AXI_UNLOCKED_
WRITE_WHILE_
OUTSTANDING_LOCKED_
WRITES
All previous locked write

transactions should be
completed before unlocking
a locked write sequence.
Any transaction with AWLOCK[1:0] set to

indicate a locked write sequence forces the
interconnect to lock the following write
transaction. Therefore, a locked sequence
must always complete with a final
transaction that does not have
AWLOCK[1:0] set to indicate a locked
access. This final transaction removes the
lock. When completing a locked sequence,
a master must ensure that all previous
locked transactions are complete before
issuing the final unlocking transaction.
violated.
95
AMBA AXI
Monitor Checks
96
Check ID
Violation
Description
AMBA_AXI_UNLOCKING_
TRANSACTION_WITH_AN_
EXCLUSIVE_ACCESS
Unlocking transaction can

not be an exclusive access
transaction.
If the bus / interconnect is locked by a

write or read from a master already, then
the same can be unlocked by non-exclusive
read or write unlocking transaction by the
same master after completion of the
current lock read or lock write transaction.
This check fires when an exclusive access
unlocking transaction is tried by the same
master that already did the existing lock
access on the bus/interconnect.
AMBA_AXI_VALID_HIGH_ON_
FIRST_CLOCK
A master interface should

not drive ARVALID,
AWVALID, or WVALID on
the first rising edge of
ACLK after ARESET_n.
The AXI protocol includes a single active

LOW reset signal, ARESETn. The reset
signal can be asserted asynchronously, but
de-assertion must be synchronous after the
rising edge of ACLK. A master interface
must begin driving ARVALID,
AWVALID, or WVALID HIGH only at a
rising ACLK edge after ARESETn is
HIGH. This check fires if any of the
ARVALID, AWVALID, or WVALID
signals are asserted on the first clock after
ARESETn is HIGH.
AMBA_AXI_WID_CHANGED_
BEFORE_WREADY
Once WVALID is asserted, Once the master asserts WVALID

WID should not change until indicating availability of a valid write data
WREADY is asserted.
on the bus, it must hold the WID value
stable until the slave accepts them with
WREADY. This check fires if the WID
value changes even before the slave asserts
WREADY.
AMBA_AXI_WID_UNKN
WID signal should not be X

or Z.
Checks that WID is both known (not X)

only when WVALID is high.
AMBA_AXI_WLAST_
CHANGED_BEFORE_WREADY
Once WVALID is asserted,

WLAST should not change
until WREADY is asserted.
The master can assert WLAST only when

it drives WVALID. Once the master
asserts WVALID indicating availability of
a valid write data on the bus, it must hold
WLAST stable until the slave accepts them
with WREADY. This check fires if
WLAST is toggled even before WREADY
is sampled asserted.
AMBA_AXI_WLAST_
ASSERTED_DURING_DATA_
PHASE_OTHER_THAN_LAST
WLAST must only be

asserted during the last data
phase
In case of write transactions, the master

must drive a burst of data starting from the
address issued with the write request and
indicate the final data transfer by asserting
the WLAST signal. This check fires when
the WLAST signal is not sample asserted
along with the last transfer of the write
burst.
AMBA_AXI_WLAST_UNKN
WLAST signal should not

be X or Z.
Checks that WLAST is both known (not

only when WVALID is high.
AMBA_AXI_WREADY_UNKN
WREADY signal should not

be X or Z.
Checks that WREADY is both known (not

AMBA AXI
Monitor Checks

Check ID
Violation
Description
AMBA_AXI_WRITE_ADDR_
UNLOCK_TRANSACTION
The unlocking transaction of

a locked write sequence
should be completed before
further transactions are
initiated.
The master must then ensure that the final

unlocking transaction has fully completed
before any further transactions are
commenced.
AMBA_AXI_WRITE_ADDR_
CNTRL_CHANGED_BEFORE_
AWREADY
Once AWVALID is
asserted, the write
address/control signals
{awaddr, awlen, awsize,
awburst, awlock, awcache,
awprot, awid} should not
change until AWREADY is
asserted.
Once the master asserts AWVALID

indicating availability of valid write
address and control information on the bus,
it must hold these values stable until the
slave accepts them with AWREADY. This
check fires if the write address/control
values change even before the slave asserts
AWREADY.
AMBA_AXI_WRITE_ADDRESS_
PHASE_WHILE_MAXIMUM_
OUTSTANDING_WRITES_
ALREADY_REACHED
Write address phase should

not occur while maximum
allowed outstanding write
transactions are already
waiting for response.
A write address transaction requested by

an AXI Master cannot be entertained by an
AXI Slave in an AXI system where the
current number of write address
transactions waiting for write response is
equal to the maximum allowed outstanding
write transactions. This check fires when
the current number of outstanding write
address transactions is equal to the
parameter value
MAX_OUTSTANDING_WRITE_ADDR,
and a new write address transaction occurs
on the write address channel.
AMBA_AXI_WRITE_
ALLOCATE_WHEN_
NON_CACHEABLE
Write allocate bit for a write

address should not be HIGH
when the cacheable bit is
LOW.
When the write allocate bit is HIGH, it

indicates that a write access that misses a
cache hit can be allocated in the cache.
This cannot be done when the access is not
cacheable in the first place. This check
fires if the attributes specified violates this
requirement.
AMBA_AXI_WRITE_BURST_
SIZE_VIOLATION
Write burst size should not

exceed the data bus width.
The burst size indicates the maximum

number of data bytes to be written in each
data transfer within a burst. This must not
exceed the data bus width of the
components in the transaction. This check
AMBA_AXI_WRITE_DATA_
BEFORE_ADDRESS
Write data should not be

transferred before the
corresponding address.
Although the relationship between the

address and write data channels is flexible
where data can come before the address, in
simple cases the write data would follow
the corresponding address. This check fires
if write data precedes the address. This
CHECK_WRITE_DATA_
FOLLOWS_ADDR_ENABLE is set to 1.
97
AMBA AXI
Monitor Checks
98
Check ID
Violation
Description
PHASE_WHILE_MAXIMUM_
OUTSTANDING_WRITES_
ALREADY_REACHED
Write data phase should not

occur while maximum
allowed outstanding write
transactions are already
waiting for response.
A write data burst transaction requested by

an AXI Master cannot be entertained by an
AXI Slave in an AXI system where the
current number of completed write data
burst transactions waiting for write
response is equal to the maximum allowed
outstanding write transactions. This check
fires when the current number of
outstanding write data burst transactions is
equal to the parameter value
MAX_OUTSTANDING_WRITE_ADDR,
and a new write data burst transaction
occurs on the write data channel.
REORDER_DEPTH_VIOLATION

reordered beyond the write
data reordering depth.
This check fires if the write data reordering

depth is exceeded.
STROBE_CHANGED_BEFORE_
WREADY
Once WVALID is asserted,

write data/strobe should not
change until WREADY is
asserted.
Once the master asserts WVALID

indicating availability of a valid write data
on the bus, it must hold these values stable
until the slave accepts them with
WREADY. This check fires if the write
data values change even before the slave
asserts WREADY.
UNKN

driven with X or Z for valid
byte-lanes.
This check fires when the AXI master

interface drives X or Z on the write data
bus. The parameter
disabling of the check. By default, this
check is ON.
This check honors the write strobe enable
only checking the valid byte-lanes for X
and Z.
AMBA_AXI_WRITE_
INTERLEAVE_DEPTH_
VIOLATION
Write data bursts should not

be interleaved beyond the
write interleaving depth.
The slave declares a write data interleaving

depth, which is a static value that indicates
the maximum data interleaving that it can
accept. This check fires if more than the
interleaving depth number of write data
bursts are interleaved. This depth can be
configured using
WRITE_INTERLEAVING_DEPTH.
AMBA_AXI_WRITE_RESP_
CHANGED_BEFORE_BREADY
Once BVALID is asserted,

write response should not
change until BREADY is
asserted.
Once the slave asserts BVALID indicating

availability of a valid write response on the
bus, it must hold these values stable until
the master accepts them with BREADY.
This check fires if the write response
values change even before the master
asserts BREADY.
AMBA_AXI_WRITE_
RESPONSE_VALID_
WITHOUT_DATA
Write response valid should

not be sent before the
corresponding write data
burst have completed.
This check fires whenever a write response

is detected for which data has not been
already received.
AMBA AXI

Check ID
Violation
Description
AMBA_AXI_WRITE_
RESPONSE_WITHOUT_ADDR
Write response should not be This check fires whenever a write response
sent before the
is detected for which the corresponding
corresponding address is
address has not been already received.
completed.
This check is active only if the
CHECK_WRITE_DATA_FOLLOWS_
ADDR_ENABLE parameter is set to 1.
AMBA_AXI_WRITE_
RESPONSE_WITHOUT_DATA
Write response should not be

sent before the
corresponding write data
burst is completed.
In case of write accesses, the slave can

issue a write response only when it has
completely received the write data. This
check fires whenever a write response is
detected for which data has not been
already received.
AMBA_AXI_WRITE_STROBE_
ON_INVALID_BYTE_LANES
Write data strobes should

not be asserted for byte lanes
that do not contain valid
data.
There is one write strobe for each eight bits

of the write data bus. A master must ensure
that the write strobes are asserted only for
byte lanes that contain valid data. This
check fires if write strobe is asserted for
any of the lanes that contain invalid data.
AMBA_AXI_WSTRB_UNKN
WSTRB signal should not

be X or Z.
Checks that WSTRB is both known (not

only when WVALID is high
AMBA_AXI_WVALID_
DEASSERTED_BEFORE_
WREADY
WVALID should be held

asserts WREADY.
The master can assert WVALID only when

it drives valid write data on the bus. It must
be held asserted until the slave accepts the
data and indicates the same by asserting
the WREADY signal. This check fires if
WVALID is detected de-asserted (after
WREADY is asserted.
AMBA_AXI_WVALID_UNKN
WVALID signal should not

be X or Z.
Checks that WVALID is both known (not


Table 5-4 shows the general checks performed by the AMBA AXI monitor.
Table 5-4. AMBA AXI Corner Cases
Corner Case
Description
Bufferable only reads
Number of bufferable only read accesses.
Bufferable only writes
Number of bufferable only write accesses.
Cacheable and bufferable but nonallocatable reads
Number of cacheable, bufferable but non allocatable read

accesses.
Cacheable and bufferable but nonallocatable writes
Number of cacheable, bufferable but non allocatable write

accesses.
99
AMBA AXI
Table 5-4. AMBA AXI Corner Cases (cont.)

Corner Case
Description
Cacheable but non-allocatable reads
Number of cacheable but non-allocatable read accesses.
Cacheable but non-allocatable writes
Number of cacheable but non-allocatable write accesses.
Cacheable write-back read allocate

reads
Number of cacheable write-back read allocatable read accesses.
Cacheable write-back read and write

allocatable reads
Number of cacheable write-back both read and write

allocatable read accesses.
Cacheable write-back read and write

allocatable writes
Number of cacheable write-back both read and write

allocatable write accesses.
Cacheable write-back write allocate

writes
Number of cacheable write-back write allocatable write

accesses.
Cacheable write-through read allocate Number of cacheable write-through read allocatable read
reads
accesses.
Cacheable write-through read and
write allocatable reads
Number of cacheable write-through both read and write

allocatable read accesses.
Cacheable write-through read and

write allocatable writes
Number of cacheable write-through both read and write

allocatable write accesses.
Cacheable write-through write

allocate writes
Number of cacheable write-through write allocatable write

accesses.
Exclusive read accesses
Number of exclusive read accesses.
Exclusive write accesses
Number of exclusive write accesses.
Fixed read addresses
Number of addresses for fixed read bursts.
Fixed write addresses
Number of addresses for fixed write bursts.
Incrementing read addresses
Number of addresses for incrementing read bursts.
Incrementing write addresses
Number of addresses for incrementing write bursts.
Locked read accesses
Number of locked read accesses.
Locked write accesses
Number of locked write accesses.
Narrow read transfers
Number of narrow read transfers.
Narrow write transfers
Number of narrow write transfers.
Non-cacheable non-bufferable reads
Number of non-cacheable non-bufferable read accesses.
Non-cacheable non-bufferable writes
Number of non-cacheable non-bufferable write accesses.
Normal nonsecure data read accesses
Number of normal nonsecure read data accesses. This relates to

protection levels specified by ARPROT[2:0].
Normal nonsecure data write accesses Number of normal nonsecure data write accesses. This relates
to protection levels specified by AWPROT[2:0].
100
Normal nonsecure instruction read

access
Number of normal nonsecure instruction read accesses. This

relates to protection levels specified by ARPROT[2:0].
Normal nonsecure instruction write

access
Number of normal nonsecure instruction write accesses. This

relates to protection levels specified by AWPROT[2:0].
AMBA AXI

Corner Case
Description
Normal read accesses
Number of unlocked, nonexclusive read accesses. This relates

to atomic access specified by ARLOCK[1:0].
Normal secure data read accesses
Number of normal secure read data accesses. This relates to

Normal secure data write accesses
Number of normal secure data write accesses. This relates to

protection levels specified by AWPROT[2:0].
Normal secure instruction read

accesses
Number of normal secure instruction read accesses. This relates

to protection levels specified by ARPROT[2:0].
Normal secure instruction write

accesses
Number of normal secure instruction write accesses. This

Normal write accesses
Number of unlocked, non-exclusive write accesses. This relates

to atomic access specified by AWLOCK[1:0].
Privileged nonsecure data read

accesses
Number of privileged nonsecure read data accesse.This relates

to protection levels specified by ARPROT[2:0].
Privileged nonsecure data write

accesses
Number of privileged nonsecure data write accesses.This

Privileged nonsecure instruction read

access
Number of privileged secure instruction read accesses. This

Privileged nonsecure instruction write Number of privileged secure instruction write accesses. This
access
Privileged secure data read accesses
Number of privileged secure read data accesses. This relates to

Privileged secure data write accesses
Number of privileged secure data write accesses. This relates to

protection levels specified by AWPROT[2:0].
Privileged secure instruction read

accesses
Number of privileged secure instruction read accesses. This

Privileged secure instruction write

accesses
Number of privileged secure instruction write accesses. This

Read addresses
Total number of read addresses.
Read data bursts
Number of read data bursts.
Read responses with decode error
Number of read responses with decode error.
Read responses with slave error
Number of read responses with slave error.
Simultaneous read write accesses
Number of simultaneous read and write accesses in the same

clock, in the entire simulation.
Unaligned read accesses
Number of unaligned read accesses.
Unaligned write accesses
Number of unaligned write accesses.
Wrapping read addresses
Number of addresses for wrapping read bursts.
Wrapping write addresses
Number of addresses for wrapping write bursts.
Write addresses
Total number of write addresses.
Write bursts with all data masked
Number of write data bursts with all data masked.
101
AMBA AXI
Monitor Statistics

Corner Case
Description
Write data bursts
Number of write data bursts.
Write responses with decode error
Number of write responses with decode error.
Write responses with slave error
Number of write responses with slave error.
Monitor Statistics
Table 5-5 shows the statistics maintained by the AMBA AXI monitor.
Table 5-5. AMBA AXI Protocol Statistics
Statistic
Description
Back to back read data bursts
Number of back to back read data bursts.
Back to back write data bursts
Number of back to back write data bursts.
Cacheable write-back read allocate writes
Number of cacheable write-back read allocatable write

accesses.
Cacheable write-back write allocate reads
Number of cacheable write-back write allocatable read

accesses.
Cacheable write-through read allocate writes
Number of cacheable write-through read allocatable write

accesses.
Cacheable write-through write allocate reads
Number of cacheable write-through write allocatable read

accesses.
Exclusive access failures
Number of exclusive access failures.
Exclusive access successes
Number of exclusive access successes.
Exclusive read accesses to unsupported slave
Number of exclusive read accesses to an unsupported

slave.
Exclusive write accesses to unsupported slave
Number of exclusive write accesses to an unsupported

slave.
Incomplete exclusive accesses
Number of incomplete exclusive accesses.
Locked read sequences across 4K boundary
Number of times the read transactions within a locked

read sequence crossed the 4K address boundary.
Locked read sequences exceeding two accesses
Number of times more than two read transactions were

performed within a locked read sequence.
Locked write sequences across 4K boundary
Number of times the write transactions within a locked

write sequence crossed the 4K address boundary.
Locked write sequences exceeding two accesses Number of times more than two write transactions were
performed within a locked write sequence.
102
Chapter 6
Double Data Rate SDRAM (DDR SDRAM)
Introduction
The QVL Double Data Rate SDRAM (DDR SDRAM) monitor provides a method of debugging
DDR SDRAM system designs by checking that the operation of the design is compliant with
the JEDEC standard. This monitor can also be configured for custom requirements. The
monitor can be used to guarantee that your controller design cannot perform an illegal operation
to the memory subsystem.
The DDR SDRAM monitor tracks all operations to the DDR SDRAM subsystem for a single
row of DDR SDRAMs. To check multiple memory rows, the user can instantiate multiple
instances of the DDR SDRAM monitor. Each DDR SDRAM monitor instance checks
operations on a virtual four-bank DDR SDRAM by monitoring the states of each bank, and by
setting and relaxing cycle-based timing checks on all operations on the banks.
The DDR SDRAM monitor instance determines illegal command sequences by comparing
bank-state against command issues. Checks for illegal commands and cycle-based timing
problems can be used as search targets. Use formal analysis to find legal stimulus sequences
(that is, corner-case behavior) that direct your controller design to violate legal DDR SDRAM
memory subsystem operations.
V1.0 Monitor
This DDR SDRAM monitor is modeled from the requirements provided in the following
documents:
JEDEC Standard, Double Data Rate (DDR) SDRAM Specification, JESD79,

(Release 2) JEDEC Solid State Technology Association, May 2002.
Micron, DOUBLE DATA RATE (DDR) SDRAM, 64Mb: x32 DDR SDRAM,
2M32DDR-07.p65-Rev. 9/01.
Mode Register Programming

For mode register programming, the DDR SDRAM monitor supports the following:
Burst lengths 2, 4, 8, 16, 32, 64, 128 and Full Page Mode (FPM).
103

V1.0 Monitor
CAS latencies 0.5, 1, 1.5, 2, 2.5, 3, and 4.
Sequential and interleaved burst types.
DLL reset, if DLL is enabled.
Normal operating mode.
The DDR SDRAM monitor does not support the following:
Interleaved burst type in Full Page Mode (FPM) burst.
Any reserved states and vendor-specific test modes.
Full Page mode burst and CAS Latency of 4 in NON JEDEC mode.
Extended Mode Register Programming

For extended mode register programming, the DDR SDRAM monitor supports the following:
DLL enable/disable.
The DDR SDRAM monitor does not support the following:
Any reserved states.
Initialization Sequence Bypass

The DDR monitor can be used in cases where the initialization sequence is bypassed to save
simulation cycles. The parameter BYPASS_INIT determines this mode of operation as follows:
Normal mode.
By default (i.e., BYPASS_INIT = 0), the monitor tracks the initialization sequence and
validates the requirements described in the specification during the initialization
sequence. For example, the monitor fires if it does not detect at least two auto refresh
commands between a reset and an active command. In this mode, the monitor tracks the
MRS and EMRS commands and configures itself accordingly. The monitor ports
mode_register and extended_mode_register can be left unconnected.
Initialization bypass mode.

In this mode (i.e., BYPASS_INIT = 1), the monitor does not validate the requirements
described in the specification during the initialization sequence and does not track the
MRS and EMRS commands. However, for proper operation, the monitor requires the
information regarding the mode register settings. This information is passed through the
monitor ports mode_register and extended_mode_register. The values passed to
these ports must reflect the actual mode register setting in the DDR SDRAM memory.
104

V1.0 Monitor

To use the DDR SDRAM monitor, place one instance of the monitor inside the part of the
design that is searchable (a block of synthesizable code for formal analysis). For example, in a
DDR SDRAM memory controller chip design that has a DDR SDRAM memory interface for
the DDR SDRAM memory chips and an application interface for connecting other controllers,
the monitor should be instantiated inside the DDR SDRAM memory controller design with the
port signals connected to the DDR SDRAM memory interface (see Figure 6-1). Instantiations of
the DDR SDRAM monitors in a checker control file can be included.
Figure 6-1. DDR SDRAM System Implementation
Address
address
pipe
Control
control
DDR SDRAM
Memory
Application
Interface
Controller
DDR SDRAM
Memory
data
in/out
Data
DDR SDRAM Memory Controller
Connect the DDR SDRAM monitor pins to internal signals of the target design as specified in
the pin-out Table 6-1 and illustrated in Figure 6-2. The clock, reset, and asynchronous reset
should be available inside the target design. The remaining signals can be attached to the
outbound control and address signals of the target design.
105

V1.0 Monitor
Figure 6-2. DDR SDRAM Monitor Pin-Out Diagram
clock
clock_n
reset
areset
CKE[CS_CKE_WIDTH - 1:0]
CS_n[CS_CKE_WIDTH - 1:0]
RAS_n
CAS_n
WE_n
BA[1:0]
A[ADDR_WIDTH - 1:0]
DM[DM_WIDTH - 1:0]
DQ[DATA_WIDTH - 1:0]
DQS
mode_register
extended_mode_register
DDR SDRAM
Monitor
Table 6-1. DDR SDRAM Monitor Pin-Out
106
Pin
Description
A[ADDR_WIDTH 1:0]
Address.
areset
Asynchronous reset (active high).
BA[1:0]
Bank address.
CAS_n
Column address strobe (active low).
CKE[CS_CKE_WIDTH - 1:0]
Clock enable (active high).
clock
Clock (positive edge is active).
clock_n
Complementary clock, 180 degree out of phase with

clock.
CS_n[CS_CKE_WIDTH - 1:0]
Chip select (active low).
DM[DM_WIDTH - 1:0]
Data mask lines (active high).
Data lines.
DQS
Data strobe.

V1.0 Monitor
Table 6-1. DDR SDRAM Monitor Pin-Out (cont.)

Pin
Description
extended_mode_register[ADDR_WIDTH 1:0]
Extended mode register input. Leave this port

unconnected if BYPASS_INIT = 0. The width of this
register is equal to ADDR_WIDTH + Bank Address
width (i.e., 2). This width reflects the actual width of the
mode register in DDR SDRAM memory.
mode_register[ADDR_WIDTH +1:0]
Mode register input. Leave this port unconnected if

BYPASS_INIT = 0. The width of this register is equal to
ADDR_WIDTH + Bank Address width (i.e., 2). This
width reflects the actual width of the mode register in
DDR SDRAM memory.
RAS_n
Row address strobe (active low).
reset
Reset (active high).
WE_n
Write enable (active low).
Note that the timing value between a WRITE command and the first DQS latching transition is
called the tdqss value. For formal analysis, the DDR SDRAM monitor only supports tdqss
values equal to the clock period. This means that the DQS signal edges should be in line with
the clock signal for formal analysis. The monitor supports tdqss values from 75% to 125% of
the total clock period.
DDR SDRAMs Stacking

If the memory controller supports n stacked DDR SDRAMs (with data widths width and
memory sizes mem), then connect the monitors as follows (see Figure 6-3 and Figure 6-4):
If the memory controller supports n DDR SDRAMs stacked by data width (for a total
data width of n x width and memory size mem), then connect only one instance of the
monitor to track the controller. Set the CS_CKE_WIDTH parameter to the width of the
CS_n and CKE pins.
If the memory controller supports n DDR SDRAMs stacked by address width (for a
total data width of width and memory size n x mem), then connect n instances of the
monitor to track the controller. The CS_n and CKE pins of each monitor are connected
to the appropriate bits of the controllers chip select and clock enable pins.
Use the above scheme also when stacking by both data width and address width.
107

V1.0 Monitor
Figure 6-3. Stacking DDR SDRAMs by Data Width

Data
DDR SDRAM
Memory Controller
DDR SDRAM
Monitor
Address
...
DDR SDRAM
Memory #1
DDR SDRAM
Memory #2
...
DDR SDRAM
Memory #n
Figure 6-4. Stacking DDR SDRAMs by Address Width

Data
DDR SDRAM
Memory Controller
DDR SDRAM
Memory #1
Address
DDR SDRAM
Memory #2
...
...
DDR SDRAM
Monitor
Address
...
DDR SDRAM
Monitor
DDR SDRAM
Monitor
Address
DDR SDRAM
Memory #n
Monitor Parameters
The parameters shown in Table 6-2 configure the corresponding DDR SDRAM monitor. The
override parameters set timing parameters for the monitor. Refer to Table 6-5 for the JEDEC
standard compliant values of the parameters, which are used as default values.
Table 6-2. DDR SDRAM Monitor Parameters
Order
Parameter
Default Description
1.
Constraints_Mode
108
Set to 1 if the checks in the monitor are to be used

as constraints for formal analysis.

V1.0 Monitor
Table 6-2. DDR SDRAM Monitor Parameters (cont.)

Order
Parameter
Default Description
2.
CONTROLLER_SIDE
Set this parameter to 1 if the monitor is

instantiated on the DDR SDRAM controller side.
This parameter and the Constraints_Mode
parameter turn all checks in the monitor to
constraints (checks those connected on the input
signals to the controller) or targets (checks those
connected on output signals from the controller),
and checks those connected on the bidirectional
signals during formal analysis.
3.
CS_CKE_WIDTH
Width of chip select and clock enable signals.

Only use a nondefault value if all devices in the
stack are accessed simultaneously.
4.
ADDR_WIDTH
12
Width of address bus signals. Minimum value for

this parameter is 12. If your designs ADDR
WIDTH is less than 12, then for the upper address
lines of the monitor that are not available in the
design, connect with 1'b0.
5.
DM_WIDTH
Width of data mask signal.
6.
DATA_WIDTH
Width of data bus signals. Minimum value for this

parameter is 4.
7.
DLL_TRACKING_ENABLE
Set this parameter to 1 to enable the

DDR_SDRAM_no_dll_reset and
DDR_SDRAM_violates_tDLL checks.
8.
TRC_OVERRIDE
RAS# cycle timeminimum time interval

between successive ACTIVE commands to the
same bank. Set this parameter to 0 if you want the
JEDEC default value to be used.
9.
TRAS_OVERRIDE
RAS# active timeminimum time to precharge a

bank after it was previously issued an ACTIVE
command without losing read/write data. Set this
parameter to 0 if you want the JEDEC default
value to be used.
10.
TRP_OVERRIDE
RAS# precharge timeminimum time to

precharge a bank. Set this parameter to 0 if you
want the JEDEC default value to be used.
11.
TRCD_OVERRIDE
RAS# to CAS# delayminimum time to legally

issue a READ or WRITE command to a row after
opening it by issuing an ACTIVE command. Set
this parameter to 0 if you want the JEDEC default
value to be used.
12.
TRRD_OVERRIDE
RAS# to RAS# bank activate delayminimum

time interval between successive ACTIVE
commands to different banks. Set this parameter to
0 if you want the JEDEC default value to be used.
13.
TMRD_OVERRIDE
MODE REGISTER SET command cycle time

minimum time interval for any new command
issue after the MODE REGISTER SET command
was previously issued. Set this parameter to 0 if
you want the JEDEC default value to be used.
109

V1.0 Monitor

Order
Parameter
Default Description
14.
TRFC_OVERRIDE
AUTO REFRESH to ACTIVE command time

minimum time between AUTO REFRESH
command and an ACTIVE command to any bank.
Set this parameter to 0 if you want the JEDEC
default value to be used.
15.
TXSNR_OVERRIDE
SELF REFRESH to non-READ command time

minimum time interval between SELF REFRESH
command to any non-READ command to any
bank. Set this parameter to 0 if you want the
JEDEC default value to be used.
16.
TXSRD_OVERRIDE
SELF REFRESH to READ command time

command to a READ command to any bank. Set
value to be used.
17.
TWR_OVERRIDE
WRITE burst end to PRECHARGE time

(minimum time interval between WRITE burst
end to PRECHARGE command). Set this
value to be used.
18.
TWTR_OVERRIDE
WRITE burst end to READ command time.

Minimum time interval between a WRITE burst
end to the READ command issue. Set this
value to be used.
19.
AUTOPRECHARGE_ENABLE_
ADDRESS_BIT
10
Bit-index specifying the auto precharge address

line. The address bit, specified by this parameter,
is used to enable/disable the auto precharge
function during a Read or Write command. This is
also used to decode a Single bank precharge and
all banks precharge during a precharge command
issue.
20.
COL_ADDRESS_WIDTH
Number of Column address lines. This parameter

is used to decode the size of the full page for Full
Page Mode (FPM) burst.
21.
READ_BEFORE_WRITE_
CHECK_ENABLE
Enables the check that ensures no read is

performed to a location when there was no
previous write to the same location. Set this
parameter to 0 to disable this check. Check ID:
DDR_SDRAM_read_before_write.
22.
CON_AUTO_PRECHARGE
Set this parameter to 1 if the device in which the

monitor is instantiated supports Concurrent Auto
Precharge. By default, the monitor assumes that
the device in which it is instantiated does not
support Concurrent Auto Precharge.
23.
ENABLE_WHY_PRECHARGE_
AN_IDLE_BANK
Set this parameter to 1 to enable the check that

ensures a PRECHARGE command is not issued to
an idle bank. By default, this check (Check ID:
DDR_SDRAM_why_precharge_an_idle_bank) is
turned off.
110

V1.0 Monitor

Order
Parameter
Default Description
24.
BYPASS_INIT
Set this parameter to 1 to bypass the initialization

sequence. If this parameter is set to 1, then the
complete initialization sequence need not be
performed. Nevertheless, valid operational values
must be passed to the mode register and extended
mode register inputs (otherwise, the monitor
behavior is undefined. By default, the monitor
requires the proper initialization sequence to be
performed as stated in the specification.
25.
NON_JEDEC
Set this parameter to 1 to enable the usage of the

non JEDEC values for the configuration of Burst
length, CAS Latency, and timing parameters. By
default, use of JEDEC values are only allowed.
26.
DATA_CHECK_ENABLE
This parameter enables or disables the following

data integrity checks: DDR_SDRAM_bad_data
and DDR_SDRAM_read_before_write.
Set this parameter to 1 to enable the data integrity
checks.
Setting to 0 removes the checks by completely
removing the data-checker module,
qvl_ddr_sdram_data_checker.

Time is measured in terms of number of clock cycles.
Programming the DQS Delay

Note the following about the `define compiler directive:
Name: QVL_DQS_DELAY
Default: 2
Description:
This is used to delay the DQS signal during read cycles in order to align the DQS signal edges at
the center of the DQ signal to guarantee the proper latching of DQ.
By default, the DQS signal is delayed by 2 time units (i.e., #2) internally.
The user should override this with a larger value if the DQS signal that is driven by the DDR
Memory should be delayed more than #2 to guarantee proper DQ latching.
111

V1.0 Monitor
JEDEC Mode
Full Page mode burst can be configured only in JEDEC mode (that is, when NON_JEDEC = 0).
When NON_JEDEC =1, the Burst Length configuration is as shown in Table 6-3.
Table 6-3. JEDEC Mode Burst Length Configuration
A[2:0]
BURST LENGTH
000
RSVD
001
010
011
100
16
101
32
110
64
111
128
CAS latency of 4 can be configured only in JEDEC mode (that is, when NON_JEDEC = 0).
When NON_JEDEC =1, the CAS Latency configuration is as shown in Table 6-4.
Table 6-4. JEDEC Mode CAS Latency Configuration
A[6:4]
CAS LATENCY
000
RSVD
001
1.0
010
2.0
011
3.0
100
0.5
101
1.5
110
2.5
111
RSVD
When constraints mode is disabled, all checks are used as targets during formal analysis. To use
the checks as constraints for formal analysis, do the following:
112
Set the Constraints_Mode parameter to 1.
Set the CONTROLLER_SIDE parameter as follows:

V1.0 Monitor
o
If the monitor is instantiated in the DDR SDRAM controller, then set

CONTROLLER_SIDE to 1.
If the monitor is instantiated in the DDR SDRAM memory, then set

Table 6-5. JEDEC Standard Compliant Timing

Timing Parameter
JEDEC Standard Timing Value
TRC_OVERRIDE
TRAS_OVERRIDE
TRP_OVERRIDE
TRCD_OVERRIDE
TRRD_OVERRIDE
TMRD_OVERRIDE
TRFC_OVERRIDE
10
TXSNR_OVERRIDE
10
TXSRD_OVERRIDE
200
TWR_OVERRIDE
TWTR_OVERRIDE
Time is measured by an integer number of clock cycles.
Instantiation Examples
Example 1
Example 6-1 instantiates a JEDEC standard compliant DDR SDRAM monitor on the DDR
SDRAM controller side for unconstraint search with CS_CKE_WIDTH of 1, ADDR_WIDTH of 12,
DM_WIDTH of 1, DATA_WIDTH of 8, 8th bit of Address line as Auto precharge enable, Lower 8
Column Address lines are to be used for Full Page Mode burst, and DLL_TRACKING_ENABLE set
to 1.
Note that all timing parameters are the default values specified by JEDEC. The monitor is in
normal mode of operation, which enables the monitor to track the initialization sequence.
Example 6-1. DDR SDRAM Monitor Instantiated in the Controller
qvl_ddr_sdram_monitor
/* CONTROLLER_SIDE */
/* CS_CKE_WIDTH */
/* ADDR_WIDTH */
/* DM_WIDTH */
0,
1,
1,
12,
1,
113

V1.0 Monitor
/* DATA_WIDTH */
8)
DDR_SDRAM_MONITOR0 (
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable_1),
.CS_n
(chip_select_1_n),
.RAS_n
(row_address_strobe_n),
.CAS_n
(column_address_strobe_n),
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(data_mask_1),
.DQ
(data_bus_8),
.DQS
(data_strobe)
.mode_register (),
.extended_mode_register ());
Example 2
Example 6-2 instantiates two DDR SDRAM monitors for a JEDEC standard DDR SDRAM
controller design. The example has the following characteristics:
The controller design interfaces two stacked DDR SDRAMs, each having 16 bits of
DATA_WIDTH to form a 32-bit data bus.
The other input signals widths are as follows:

of 4, two for each row of DDR SDRAMs. One monitor is required
for each row of DDR SDRAM.
CS_CKE_WIDTH
ADDR_WIDTH
DM_WIDTH
of 12.
of 4, one for each byte of data.
The DLL tracking is enabled. Hence the DLL_TRACKING_ENABLE parameter is set to 1.
The monitor is instantiated for unconstrained formal analysis. Therefore, the

Constraints_Mode parameter is set to 0.
Initialization sequence tracking is enabled (by default).

Example 6-2. Two DDR SDRAM Monitors
/* CS_CKE_WIDTH */
/* ADDR_WIDTH */
/* DM_WIDTH */
/* DATA_WIDTH */
.clock
(clock),
114
0,
1,
2,
12,
2,
16)

V1.0 Monitor
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable_4[1:0]),
.CS_n
(chip_select_4_n[1:0]),
.RAS_n
.CAS_n
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(data_mask_4[1:0]),
.DQ
(data_bus_32[15:0]),
.DQS
(data_strobe),
.mode_register (),
.extended_mode_register () ;
#( /* Constraints_Mode */ 0,
1,
/* CS_CKE_WIDTH */
2,
/* ADDR_WIDTH */
12,
/* DM_WIDTH */
2,
/* DATA_WIDTH */
16)
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
.CS_n
.RAS_n
.CAS_n
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(data_mask_4[3:2]),
.DQ
(data_bus_32[31:16]),
.DQS
(data_strobe),
.mode_register (),
.extended_mode_register () ;
Example 3
Example 6-3 instantiates a DDR SDRAM monitor for a Micron 64 Mb compatible controller
design. The example has the following characteristics:
The controller design interfaces a DDR SDRAM having 32-bit DATA_WIDTH and 11-bit
ADDR_WIDTH.

o
1-bit CS_CKE_WIDTH.
DM_WIDTH
115

V1.0 Monitor
DLL tracking is enabled. Therefore, the DLL_TRACKING_ENABLE parameter is set to 1.
The timing parameter values are as follows:

TRC
10
TRFC
11
TRAS
7
TXSNR
10
TRP
3
TXSRD
200
TRCD
3
TWR
2
TRRD
2
TWTR
1
TMRD
2
Autoprecharge is enabled through address bit 8; therefore, the

AUTOPRECHARGE_ENABLE_ADDRESS_BIT parameter is 8.
FPM mode is supported. FPM size is 256 and the number of address lines required to
burst up to 256 is 8. Therefore, the COL_ADDRESS_WIDTH is set to 8.
The DLL tracking is enabled. Therefore, the DLL_TRACKING_ENABLE parameter is set to

1.
The monitor is instantiated for unconstrained search. Therefore, the Constraints_Mode

Example 6-3. DDR SDRAM Monitor Instantiated in the Controller
0,
1,
/* CS_CKE_WIDTH */
1,
/* ADDR_WIDTH */
12,
/* DM_WIDTH */
1,
/* DATA_WIDTH */
8,
/* DLL_TRACKING_ENABLE */
1,
/* TRC_OVERRIDE */
10,
/* TRAS_OVERRIDE */
7,
/* TRP_OVERRIDE */
3,
/* TRCD_OVERRIDE */
3,
/* TRRD_OVERRIDE */
2,
/* TMRD_OVERRIDE */
2,
/* TRFC_OVERRIDE */
11,
/* TXSNR_OVERRIDE */
10,
/* TXSRD_OVERRIDE */
200,
/* TWR_OVERRIDE */
2,
/* TWTR_OVERRIDE */
1,
/* AUTOPRECHARGE_ENABLE_ADDRESS_BIT */ 8,
/* COL_ADDRESS_WIDTH */
8,
/* READ_BEFORE_WRITE_CHECK_ENABLE */
1,
/* CON_AUTO_PRECHARGE */
0,
/* ENABLE_WHY_PRECHARGE_AN_IDLE_BANK */0,
/* BYPASS_INIT*/
1)
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable),
.CS_n
(chip_select_n),
116

V1.0 Monitor
.RAS_n
.CAS_n
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_11),
.DM
(data_mask_4),
.DQ
(data_bus_32),
.DQS
(data_strobe),
.mode_register
(internal_mode_register),
.extended_mode_register (internal_mode_register) );
The monitor is instantiated with BYPASS_INIT = 1 and the internal signals are connected to
the monitor ports mode_register and extended_mode_register.
Example 4
Example 6-4 on page 117 instantiates a DDR SDRAM monitor to check a controller with NON
JEDEC timing parameter values. The example has the following characteristics:
ADDR_WIDTH.

o
1-bit CS_CKE_WIDTH.
DM_WIDTH
The timing parameters are set to NON JEDEC values. Therefore, the NON_JEDEC
parameter is 1. The NON JEDEC timing parameter values are as follows
TRC
12
TRFC
16
TRAS
9
TXSNR
14
TRP
4
TXSRD
300
TRCD
4
TWR
3
TRRD
5
TWTR
1
TMRD
3
Autoprecharge is enabled through address bit 8. Therefore, the


1.

Example 6-4. DDR SDRAM Monitor Instantiated with NON JEDEC Timing
Parameter Values
0,
1,
117

V1.0 Monitor
/* CS_CKE_WIDTH */
1,
/* ADDR_WIDTH */
12,
/* DM_WIDTH */
1,
/* DATA_WIDTH */
8,
1,
/* TRC_OVERRIDE */
12,
/* TRAS_OVERRIDE */
9,
/* TRP_OVERRIDE */
4,
/* TRCD_OVERRIDE */
4,
/* TRRD_OVERRIDE */
5,
/* TMRD_OVERRIDE */
3,
/* TRFC_OVERRIDE */
16,
14,
300,
/* TWR_OVERRIDE */
3,
/* TWTR_OVERRIDE */
1,
8,
1,
0,
/* BYPASS_INIT*/
1,
/* NON_JEDEC*/
1)
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable),
.CS_n
(chip_select_n),
.RAS_n
.CAS_n
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_11),
.DM
(data_mask_4),
.DQ
(data_bus_32),
.DQS
(data_strobe),
.mode_register (internal_mode_register),
.extended_mode_register (internal_mode_register) );
The monitor is instantiated with BYPASS_INIT = 1 and internal signals are connected to the
monitor ports mode_register and extended_mode_register.
118

V1.0 Monitor
Monitor Checks
Table 6-6 shows the checks performed by a DDR SDRAM monitor.
Table 6-6. DDR SDRAM Monitor Checks
Check ID
Violation
Description
DDR_SDRAM_ADDRESS
Address bus, A, has a X or Z

value.
Address bus, A, should have a valid

value when mode register
set/extended mode register
set/read/write/read with auto
precharge/write with auto
precharge/bank activation command is
issued.
DDR_SDRAM_BA
Bank address bus, BA, has a X Bank address bus, BA, should have a
or Z value.
valid value when read/write/read with
auto precharge/write with auto
precharge/bank activation/single bank
precharge command is issued.
DDR_SDRAM_BYPASS_INIT
BYPASS_INIT should be
either 1 or 0.
The value of the BYPASS_INIT

parameter should be either 1 or 0.
DDR_SDRAM_CAS_n
Column address strobe,

CAS_n, has a X or Z value.
Column address strobe, CAS_n, must

always have a valid value. This check
is active only if CKE is high and CS_n
is low.
DDR_SDRAM_CKE
Clock enable, CKE, has a X or

Z value.
Clock enable, CKE, must always have

a valid value.
DDR_SDRAM_Constraint_Mode
Constraints_Mode should be
either 1 or 0.
The value of the Constraints_Mode

DDR_SDRAM_CONTROLLER_
SIDE
CONTROLLER_SIDE should The value of the

be either 1 or 0.
CONTROLLER_SIDE parameter
should be either 1 or 0.
DDR_SDRAM_CS_CKE_WIDTH
Chip select (cs_n) and clock

The value of CS_CKE_WIDTH
enable (cke) widths should not parameter should not be specified to
be less than the minimum
be less than 1.
limit of 1.
DDR_SDRAM_CS_n
Chip select, CS_n, has a X or

Z value.
Chip select, CS_n, must always have a

valid value. This check is active only
if CKE is high.
DDR_SDRAM_DATA_WIDTH
Data bus width should not be

less than the minimum limit of
4.
The value of the DATA_WIDTH

parameter should not be specified to
be less than 4.
DDR_SDRAM_DLL_TRACKING_
ENABLE
DLL_TRACKING_ENABLE
The value of the

DLL_TRACKING_ENABLE
DDR_SDRAM_DM
Data mask, DM, has a X or Z

value.
Data mask, DM, must always have a

valid value. This check is active only
if CKE is high and a valid write data
phase is in progress.
119

V1.0 Monitor
Table 6-6. DDR SDRAM Monitor Checks (cont.)

Check ID
Violation
Description
DDR_SDRAM_DM_WIDTH
Data mask width should not

be less than the minimum
limit of 1.
The value of the DM_WIDTH

parameter should not be less than 1.
DDR_SDRAM_incorrect_
command_before_mode_reg_set
A command that should not be

issued before the mode
register set command is
issued.
This check is applicable only if

BYPASS_INIT is set to 0 (i.e., a
proper MRS cycle is performed).
NOP, precharge, and refresh are the
only commands that are valid before
the MODE REGISTER SET. You
should check the designs reset
sequencing.
DDR_SDRAM_invalid_burst_
length
The burst length field of the

input mode register is invalid.

BYPASS_INIT is set and
NON_JEDEC is 0. As per the JEDEC
specification, the valid burst length
values are 2 (3'b001), 4 (3'b010), 8
(3'b011), and Full Page Mode (FPM)
(3'b111). This check fires if a burst
length value other than the ones listed
above is passed through the
mode_register input.
length_value_in_mode_reg_set
Invalid burst length value

during mode register set
command.
This check is applicable only when the

NON_JEDEC parameter is set to 0. As
per the JEDEC specification, the valid
burst length values are 2 (3'b001), 4
(3'b010), 8 (3'b011), and Full Page
Mode (FPM) (3'b111). This check
fires if a burst length value other than
the ones listed above is programmed.
DDR_SDRAM_invalid_cas_latency
The CAS latency field of the


specification, the valid CAS latency
values are 1.5 (3'b101), 2 (3'b010), 2.5
(3'b110), 3 (3'b011) and 4 (3'b100).
This check fires if a CAS latency
value other than the ones listed above
is passed through the mode_register
input.
DDR_SDRAM_invalid_cas_
latency_value_in_mode_reg_set
Invalid CAS latency value

during mode register set
command.

CAS latency values are 1.5 (3'b101), 2
(3'b010), 2.5 (3'b110), 3 (3'b011), and
4 (3'b100). This check fires if a CAS
latency value other than the ones listed
above is programmed.
120

V1.0 Monitor

Check ID
Violation
Description
DDR_SDRAM_invalid_operating_
mode
The operating mode field in

the mode register or extended
mode register input is invalid.

BYPASS_INIT is set and an incorrect
value is passed to the mode_register
input. As per the JEDEC specification,
for normal operation, A[11:7] should
be either 5'b00000 or 5'b00010 in the
mode register and A[11:3] should be
9'b000000000 in the extended mode
register. EXTENDED MODE
REGISTER SET command. This
check fires if values other than the
above are passed to the corresponding
inputs.
mode_bits_mrs_or_emrs
Invalid operating mode bits

are programmed during the
mode register set or extended
mode register set command.
As per the JEDEC specification, for

normal operation, A[11:7] should be
either 5'b00000 or 5'b00010 during
MODE REGISTER SET command,
and A[11:3] should be 9'b000000000
during EXTENDED MODE
REGISTER SET command. This
check fires if a value other than the
ones listed above is driven on address
bus (A) during MODE REGISTER
SET or EXTENDED MODE
REGISTER SET command is issued.
DDR_SDRAM_RAS_n
Row address strobe, RAS_n,

has a X or Z value.
Row address strobe, RAS_n, must

is low.
DDR_SDRAM_TMRD
TMRD value should not be

2.

NON_JEDEC parameter is set to 0.
The value of the TMRD timing
be less than 2.
DDR_SDRAM_TRAS
TRAS value should not be less This check is applicable only when the
than the minimum limit of 6.
The value of the TRAS timing
be less than 6.
DDR_SDRAM_TRC
TRC value should not be less


The value of the TRC timing
be less than 9.
DDR_SDRAM_TRCD
TRCD value should not be

3.

The value of the TRCD timing
be less than 3.
121

V1.0 Monitor

Check ID
Violation
Description
DDR_SDRAM_TRFC
TRFC value should not be less


The value of the TRFC timing
be less than 10.
DDR_SDRAM_TRP
TRP value should not be less


The value of the TRP timing
be less than 3.
DDR_SDRAM_TRRD
TRRD value should not be

2.

The value of the TRRD timing
be less than 2.
DDR_SDRAM_TWR
TWR value should not be less


The value of the TWR timing
be less than 2.
DDR_SDRAM_TXSNR
TXSNR value should not be

10.

The value of the TXSNR timing
be less than 10.
DDR_SDRAM_TXSRD
TXSRD value should not be

200.

The value of the TXSRD timing
be less than 200.
DDR_SDRAM_violates_tRRD
An activate command is
issued too quickly after the
prior activate command.
The command just issued violates

tRRD (RAS to RAS delay timing).
This is an ACTIVATE command
ACTIVATE command for another
bank. You should determine why the
commands are too close together.
DDR_SDRAM_WE_n
Write enable, WE_n, has a X

or Z value.
Write enable, WE_n, must always

have a valid value. This check is
active only if CKE is high and CS_n is
low.
122

V1.0 Monitor
Table 6-7 shows the checks for each bank performed by a DDR SDRAM monitor.
Table 6-7. DDR SDRAM Monitor Checks for Each Bank
Check ID
Violation
Description
DDR_SDRAM_ADDRESS

value.

value when mode register
set/extended mode register
set/read/write/read with auto
precharge/write with auto
precharge/bank activation
command is issued.
DDR_SDRAM_BA
Bank address bus, BA, has a X or

Z value.
Bank address bus, BA, should have

a valid value when read/write/read
with auto precharge/write with auto
precharge/bank activation/single
bank precharge command is issued.
DDR_SDRAM_bad_data
One or more bytes of data read

from the addressed DDR
SDRAM location did not match
the data byte(s) written to the
Data read from the DDR SDRAM

did not match the data written to the
corresponding address. The data
check is performed only on reads to
locations that were previously
written at least once. Data checking
is done on a byte basis and the
bitmap indicates the data
inconsistency between the
corresponding bytes. This check
fires when at least one byte of read
data does not match the
corresponding valid data byte that
was written to that location.
DDR_SDRAM_CAS_n
Column address strobe, CAS_n,

has a X or Z value.
Column address strobe, CAS_n,

must always have a valid value.
This check is active only if CKE is
high.
DDR_SDRAM_CKE
Clock enable, CKE, has a X or Z

value.
Clock enable, CKE, must always

have a valid value.
DDR_SDRAM_con_auto_
precharge_min_delay_violation
Concurrent Auto Precharge

minimum delay violation.
Some devices support the

Concurrent Auto Precharge feature
such that when a read with auto
precharge or write with auto
precharge is enabled to one bank,
then any command to other banks
can be issued as long as this
command does not interrupt the
earlier command. The minimum
delay between the read/write
command with auto precharge to a
command to a different bank has to
be met in this case. This check fires
when the minimum delay in terms
of a clock cycle is violated. This
check is enabled only if the
CON_AUTO_PRECHARGE
123

V1.0 Monitor
Table 6-7. DDR SDRAM Monitor Checks for Each Bank (cont.)
124
Check ID
Violation
Description
DDR_SDRAM_Constraints_Mode
either 1 or 0.
The value of Constraints_Mode

parameter value should be either 1
or 0.
SIDE
CONTROLLER_SIDE should be
either 1 or 0.
The value of
CONTROLLER_SIDE parameter
value should be either 1 or 0.
DDR_SDRAM_CS_CKE_WIDTH
Chip select (cs_n) and clock

enable (cke) widths should not be
less than the minimum limit of 1.
The value of CS_CKE_WIDTH

be less than 1.
DDR_SDRAM_CS_n
Chip select, CS_n, has a X or Z

value.
Chip select, CS_n, must always

active only if CKE is high.
DDR_SDRAM_DATA_WIDTH
Data bus width should not be less


parameter should not be specified
as less than 4.
DDR_SDRAM_DLL_
TRACKING_ENABLE
DLL_TRACKING_ENABLE
The value of the

DLL_TRACKING_ENABLE
DDR_SDRAM_DM

value.
Data mask, DM, must always have

a valid value. This check is active
only if CKE is high.
DDR_SDRAM_DM_WIDTH
Data mask width should not be

The value of DM_WIDTH

be less than 1.
DDR_SDRAM_illegal_command_
active
Illegal command is issued when

the bank is in ACTIVE state.
The command just issued is not

legal when the bank is in ACTIVE
state. All the valid commands for
ACTIVE state are listed in the
JEDEC specification under TRUTH
TABLE 2, 3, and 4. Any command
other than these are treated as
illegal commands by the monitor.
When this check fires, the current
state of the bank is encoded in the
state_string signal of the module
qvl_ddr_sdram_bank_monitor.
aref

all the banks are in AUTO
REFRESH state.

legal when the bank is in AUTO
REFRESH state. All the valid
commands for AUTO REFRESH
state are listed in the JEDEC
specification under TRUTH
TABLE 2, 3 and 4. Any command

V1.0 Monitor
Check ID
Violation
Description
emrs

all the banks are in
EXTENDENDED MODE
REGISTER SET state.

legal when the bank is in
EXTENDENDED MODE
REGISTER SET state. All the valid
commands for EXTENDENDED
MODE REGISTER SET state are
listed in the JEDEC specification
under TRUTH TABLE 2, 3, and 4.
Any command other than these are
treated as illegal commands by the
monitor. When this check fires, the
current state of the bank is encoded
in the state_string signal of the
module
idle

the bank is in IDLE state.

legal when the bank is in IDLE
IDLE state are listed in the JEDEC
mrs

all the banks are in MODE
REGISTER SET state.

legal when the bank is in MODE
REGISTER SET state. All the valid
commands for MODE REGISTER
SET state are listed in the JEDEC
pall

all the banks are in
PRECHARGE state.

PRECHARGE ALL state. All the
valid commands for PRECHARGE
ALL state are listed in the JEDEC
125

V1.0 Monitor
126
Check ID
Violation
Description
pre

the bank is in PRECHARGE
state.

PRECHARGE state. All the valid
commands for PRECHARGE state
are listed in the JEDEC
read

the bank is in READ state.

legal when the bank is in READ
READ state are listed in the JEDEC
reada

the bank is in READ WITH
AUTO PRECHARGE state.

legal when the bank is in READ
WITH AUTO PRECHARGE state.
All the valid commands for READ
WITH AUTO PRECHARGE state
write

the bank is in WRITE state.

legal when the bank is in WRITE
WRITE state are listed in the

V1.0 Monitor
Check ID
Violation
Description
writea

the bank is in WRITE WITH
AUTOPRECHARGE state.

legal when the bank is in WRITE
WITH AUTOPRECHARGE state.
All the valid commands for WRITE
WITH AUTOPRECHARGE state
A command that should not be

issued before the mode register
set command is issued.

only commands that are valid
before the MODE REGISTER SET.
You should check the designs reset
sequencing.
Invalid burst length value during

the mode register set command.
As per the JEDEC specification, the

valid burst length values are 2
(3'b001), 4 (3'b010), and 8 (3'b011).
This check fires if a burst length
value other than the ones listed
Invalid CAS latency value during

the mode register set command.
As per the JEDEC specification, the

valid CAS latency values are 1.5
(3'b101), 2 (3'b010), 2.5 (3'b110),
and 3 (3'b011). This check fires if a
CAS latency value other than the
ones listed above is programmed.
Invalid operating mode bits are

programmed during the mode
register set or the extended mode
register set command.

normal operation, A[11:7] should
be 5'b00000 or 5'b00010 during the
and A[11:3] should be
9'b000000000 during EXTENDED
MODE REGISTER SET command.
This check fires if a value other
than the ones listed above is driven
on address bus (A) during MODE
REGISTER SET or EXTENDED
MODE REGISTER SET command
is issued.
DDR_SDRAM_invalid_self_ref
_or_power_down_exit
Only NOP or DSEL command

should be issued during SELF
REFRESH or POWER DOWN
exit.
When DDR SDRAM is exited from

SELF REFRESH or POWER
DOWN mode, only the NOP or
DESELECT command should be
issued along with the SELF
REFRESH EXIT or POWER
DOWN EXIT command. This
check fires if a NOP or DESELECT
command is not issued during
DOWN exit.
127

V1.0 Monitor
128
Check ID
Violation
Description
DDR_SDRAM_no_auto_ refresh
At least two auto refresh

commands should be issued after
reset and before first active
command.
Minimum two auto refresh

commands should be issued after
reset and before the first activate
command is issued. This check fires
if there is no auto refresh command
or only one auto refresh command
is issued before the first active
command issue.
DDR_SDRAM_no_dll_ reset
DLL is not reset after it was

enabled.
If DLL is enabled through

EXTENDED MODE REG SET
command, then there should be a
DLL reset command issued before
an activate command is issued.
DDR_SDRAM_RAS_n
Row address strobe, RAS_n, has

a X or Z value.

always have a valid value. This
check is active only if CKE is high.
DDR_SDRAM_read_before_write
A read operation was performed Data was read from a DDR

on the DDR SDRAM that was not SDRAM address that was not
previously written into.
previously written into. This check
fires whenever a location being read
was previously not written into.
DDR_SDRAM_TMRD
TMRD value should not be less


as less than 2.
DDR_SDRAM_TRAS
TRAS value should not be less


as less than 6.
DDR_SDRAM_TRC
TRC value should not be less than The value of the TRC timing
the minimum limit of 9.
as less than 9.
DDR_SDRAM_TRCD
TRCD value should not be less


as less than 3.
DDR_SDRAM_TRFC


as less than 10.
DDR_SDRAM_TRP
TRP value should not be less than

the minimum limit of 3.

as less than 3.
DDR_SDRAM_TRRD
TRRD value should not be less


as less than 2.
DDR_SDRAM_TWR


as less than 2.
DDR_SDRAM_TXSNR
TXSNR value should not be less


as less than 10.

V1.0 Monitor
Check ID
Violation
Description
DDR_SDRAM_TXSRD
TXSRD value should not be less


as less than 200.
DDR_SDRAM_violates_CKE_
signal_P
CKE is low when control signals

and/or the monitor state machine
are not pointing to SELF
REFRESH or POWER DOWN
mode.
CKE should not go low when the

DDR SDRAM is performing a
READ or WRITE burst. The user
should determine why CKE goes
low when the DDR SDRAM is
performing a READ or WRITE
burst.
signal_N * (see the note at the end
of this table)
CKE is low when control signals

and/or the state machine are not
computing to SELF REFRESH or
POWER DOWN mode.
CKE should not go low when the

DDR SDRAM is performing a
READ or WRITE burst. The user
should determine why CKE goes
low when the DDR SDRAM is
performing a READ or WRITE
burst.
DDR_SDRAM_violates_tDLL
At least 200 clocks delay should

be given between the DLL enable
and a read/read with auto
precharge command.
If DLL is enabled, then there should

be a minimum of 200 clocks delay
before a read command or read with
autoprecharge command is issued.
DDR_SDRAM_violates_tMRD
A command that violates tMRD

timing is issued.

tMRD (minimum time delay
between MODE REGISTER SET
command and any other command)
timing. The new command is issued
too quickly after the MODE
REGISTER SET command. The
user should determine why the
DDR_SDRAM_violates_tRAS
A command that violates RAS

timing is issued.

tRAS (RAS to precharge timing).
This is a PRECHARGE command
ACTIVATE command for this
bank. The user should determine
why the commands are too close
together.
DDR_SDRAM_violates_tRC
TRC timing violation: Bank

Activate / Refresh is issued
sooner than tRC cycles from the
last bank activate command.

tRC (RAS cycle timing). This is an
ACTIVATE/REFRESH command
issued too quickly after the last
together.
signal_N
129

V1.0 Monitor
130
Check ID
Violation
Description
DDR_SDRAM_violates_tRCD
A command that violates RAS to

CAS delay timing is issued.

tRCD (RAS to CAS delay timing).
This is a READ/WRITE command
together.
DDR_SDRAM_violates_tRFC
A command that violates tRFC

timing is issued.

tRFC (minimum time delay
between AUTO REFRESH
command and any other command).
The new command is issued too
quickly after the AUTO REFRESH
command. The user should
determine why the commands are
too close together.
DDR_SDRAM_violates_tRP
A command that violates RAS

precharge timing is issued.

tRP (RAS precharge timing). This
is an ACTIVATE/REFRESH
command issued too quickly after
the last precharge command for this
together.
An activate command is issued

too quickly after the prior activate
command.

together.
DDR_SDRAM_violates_tXSNR
A command that violates tXSNR

timing is issued.

tXSNR (minimum time delay
between SELF REFRESH EXIT
command and any other non-READ
command) timing. A non-READ
command is issued too quickly after
the SELF REFRESH EXIT
too close together.
DDR_SDRAM_violates_tXSRD
A read/read with auto precharge

command that violates tXSRD
timing is issued.
The READ command just issued

violates tXSRD (minimum time
delay between SELF REFRESH
EXIT command and a READ
command) timing. A READ
command is issued too quickly after
the SELF REFRESH EXIT
too close together.

V1.0 Monitor
Check ID
Violation
Description
DDR_SDRAM_WE_n
Write enable, WE_n, has a X or Z

value.
Write enable, WE_n, must always

DDR_SDRAM_why_precharge_
an_idle_bank
A PRECHARGE command is
issued while the bank is already
in a precharged state.
The design is precharging (not an

all-bank PRECHARGE) a bank that
has already been precharged.
Although not illegal, this is
inefficient. You should examine
why the extra PRECHARGE
command is issued. This check is
enabled only when ENABLE_
WHY_PRECHARGE_AN_IDLE_
BANK parameter is set to 1.
* The DDR_SDRAM_violates_CKE_signal_N check is active on the positive edge of the clock_n

(complementary clock) signal. All other checks are active on the positive edge of the clock signal.
The minimum delay from a read/write with auto precharge command to any command to a
different bank is calculated as shown in Table 6-8.
Table 6-8. Calculate Minimum Delay From a Read/Write
From Command
To Command
Minimum Delay in Cycles
Write with AP
Read or Read AP
(BL/2) + tWR +1
Write or Write AP
BL/2
Precharge or Active
Read or Read AP
BL/2
Write or Write AP
CL + (BL/2)
Precharge or Active
Read with AP
BL = burst length
CL = CAS latency rounded up to next integer
131

V1.0 Monitor

Table 6-9 shows the corner cases captured by the DDR SDRAM monitor for the protocol.
Table 6-9. DDR SDRAM Monitor Corner Cases
Corner Case
Description
Read Commands
Number of read operations from any bank in the DDR SDRAM.
Write Commands
Number of write operations to any bank in the DDR SDRAM.
Precharge Commands
Number of Precharge commands issued to the DDR SDRAM.
Burst Stop Commands
Number of times a Burst Stop command is issued to the DDR

SDRAM.
Mode Register Set Commands
Number of times a Mode Register Set command is issued to the DDR

SDRAM.
CBR (auto) Refresh Commands
Number of times a CBR (auto) Refresh is issued to the DDR

SDRAM.
Self Refresh Commands
Number of times a Self Refresh command is issued to the DDR

SDRAM.
Power Down Commands
Number of times a Power Down command is issued to the DDR

SDRAM.
Extended Mode Register Set

Commands
Number of times EXTENDED MODE REGISTER SET is issued to

DDR SDRAM.
Precharge all Commands
Number of times PRECHARGE ALL command is issued to DDR

SDRAM.
NOP Commands
Number of times a NOP command is issued to the DDR SDRAM.
Deselect Commands
Number of times the chip select signal (CS_n) of the DDR SDRAM
is de-asserted.
Table 6-10 shows the corner cases captured by the DDR SDRAM monitor for each DDR
SDRAM bank.
Table 6-10. DDR SDRAM Monitor Corner Cases Maintained for Each Bank
132
Corner Case
Description
Read Commands
Number of read operations from the bank in the DDR SDRAM.
Write Commands
Number of write operations to the bank in the DDR SDRAM.
Read without auto precharge

Commands
Number of read (without auto-precharge) operations from the bank in the

DDR SDRAM.
Read with auto precharge

Commands
Number of read (with auto-precharge) operations from the bank in the

DDR SDRAM.
Write without auto precharge

Commands
Number of write (without auto-precharge) operations from the bank in the

DDR SDRAM.

V1.0 Monitor
Table 6-10. DDR SDRAM Monitor Corner Cases Maintained for Each Bank
Corner Case
Description
Write with auto precharge

Commands
Number of write (with auto-precharge) operations from the bank in the

DDR SDRAM.
Read after Read in Page
Number of times a read operation was issued to a page that was already
opened for read in the bank.
Read after Write in Page
Number of times a read operation was issued to a page that was already
opened for write in the bank.
Write after Read in Page
Number of times a write operation was issued to a page that was already
Write after Write in Page
Number of times a write operation was issued to a page that was already
Precharge Commands
Number of precharge commands issued to the bank.
Burst Operations Terminated
Number of times a burst operation to the bank was terminated before it

was completed. This could be due to a Burst Stop command or if another
read or write command to the bank was issued before a current burst
operation was completed.
Monitor Statistics
Table 6-11 shows the corner cases captured by the DDR SDRAM monitor for the protocol.
Table 6-11. DDR SDRAM Monitor Statistics
Statistic
Description
Active Commands
Number of times any bank in the DDR SDRAM is selected.
Table 6-12 shows the corner cases captured by the DDR SDRAM monitor for each DDR
SDRAM bank.
Table 6-12. DDR SDRAM Monitor Statistics Maintained for Each Bank
Statistic
Description
Active Commands
Number times the bank in the DDR SDRAM is selected.
133

V2.0 Monitor
V2.0 Monitor
This DDR SDRAM 2.0 monitor is modeled from the requirements provided in the following
document:
JEDEC Standard, Double Data Rate (DDR) SDRAM Specification, JESD79C, (Revision
of JESD79B) JEDEC Solid State Technology Association, March 2003.
JEDEC Standard, Double Data Rate (DDR) SDRAM Specification, JESD79, (Release
2) JEDEC Solid State Technology Association, May 2002.
Micron, DOUBLE DATA RATE (DDR) SDRAM, 64Mb: x32 DDR SDRAM, 2M32DDR07.p65-Rev. 9/01.
JEDEC Standard, Double Data Rate (DDR) Specification, JESD79E, JEDEC Solid
State Technology Association, May 2005.

For mode register programming, the DDR SDRAM 2.0 monitor supports the following:
Burst lengths 2, 4, 8, 16, 32, 64, 128, and Full Page Mode (FPM).
CAS latencies 0.5, 1, 1.5, 2, 2.5, 3, and 4.
Clock frequency change
The DDR SDRAM 2.0 monitor does not support the following:
Interleaved burst type in Full Page Mode (FPM) burst.
Full Page Mode burst and CAS latency of 4 in NON JEDEC mode.

For extended mode register programming, the DDR SDRAM 2.0 monitor supports the
following:
134
DLL enable/disable.

V2.0 Monitor
Data interface and Configurations
Data width configurations of x4, x8, and x16.
Data strobe DQS for x4 and x8 configurations.
Data strobes (LDQS, UDQS) for lower and upper data bytes in x16 configuration.
Write data masks LDM and UDM for lower and upper data bytes in x16 mode.

The DDR monitor can be used in cases where the initialization sequence is bypassed to save
simulation cycles. The parameter BYPASS_INIT determines this mode of operation as follows:
Normal mode.
By default (i.e., BYPASS_INIT = 0), the monitor tracks the initialization sequence and
validates the requirements described in the specification during the initialization
sequence. For example, the monitor fires if it does not detect at least two auto refresh
commands between a reset and an active command. In this mode, the monitor tracks the
MRS and EMRS commands and configures itself accordingly. The monitor ports
mode_register and extended_mode_register can be left unconnected.

In this mode (i.e., BYPASS_INIT = 1), the monitor does not validate the requirements
described in the specification during the initialization sequence and does not track the
MRS and EMRS commands. However, for proper operation, the monitor requires the
information regarding the mode register settings. This information is passed through the
monitor ports mode_register and extended_mode_register. The values passed to
these ports must reflect the actual mode register setting in the DDR SDRAM memory.

To use the DDR SDRAM 2.0 monitor, place one instance of the monitor inside the part of the
design that is searchable (a block of synthesizable code for formal analysis). For example, in a
DDR SDRAM memory controller chip design that has a DDR SDRAM memory interface for
the DDR SDRAM memory chips and an application interface for connecting other controllers,
the monitor should be instantiated inside the DDR SDRAM memory controller design with the
port signals connected to the DDR SDRAM memory interface (see Figure 6-5). Instantiations of
the DDR SDRAM 2.0 monitor in a checker control file can be included.
135

V2.0 Monitor
Figure 6-5. DDR SDRAM System Implementation
Address
address
pipe
Control
control
DDR SDRAM
Memory
Application
Interface
Controller
DDR SDRAM
Monitor
Data
data
in/out
DDR SDRAM Memory Controller
Connect the DDR SDRAM 2.0 monitor pins to internal signals of the target design as specified
in the pin-out Table 6-13 and illustrated in Figure 6-6. The clock, reset, and asynchronous reset
should be available inside the target design. The remaining signals can be attached to the
outbound control and address signals of the target design.
136

V2.0 Monitor
Figure 6-6. DDR SDRAM 2.0 Monitor Pin-Out Diagram

clock
clock_n
reset
areset
CKE
CS_n
RAS_n
CAS_n
WE_n
BA[1:0]
A[ADDR_WIDTH - 1:0]
DM
DQS
mode_register
LDQS
LDM
UDQS
UDM
TMRD
DDR SDRAM
Monitor
TRAS
TRC
TRCD
TRFC
TRP
TRRD
TWR
TWRT
TXSNR
TXSRD
Table 6-13. DDR SDRAM 2.0 Monitor Pin-Out

Pin
Description
A[ADDR_WIDTH 1:0]
Address.
areset
BA[1:0]
Bank address.
137

V2.0 Monitor
Table 6-13. DDR SDRAM 2.0 Monitor Pin-Out (cont.)
138
Pin
Description
CAS_n
CKE
Clock enable signal(s).
clock
Clock (positive edge is active).
clock_n
Complementary clock, 180 degree out of phase with clock.
CS_n
Chip select (active low signal(s)).
DM
Data mask lines (active high).
Data lines.
DQS
Data strobe.
[ADDR_WIDTH 1:0]
Extended mode register input. Leave this port unconnected if

BYPASS_INIT = 0. The width of this register is equal to
ADDR_WIDTH + Bank Address width (i.e., 2). This width reflects
the actual width of the mode register in DDR SDRAM memory.
LDM
Data mask for port {DQ7:DQ0}.
LDQS
Data strobe for {DQ7:DQ0}.
mode_register[ADDR_WIDTH +1:0]
Mode register input. Leave this port unconnected if BYPASS_INIT

= 0. The width of this register is equal to ADDR_WIDTH + Bank
Address width (i.e., 2). This width reflects the actual width of the
mode register in DDR SDRAM memory.
RAS_n
reset
TCLK
Represents minimum cycles to be lapsed before the clock frequency

can change in precharge power down mode after the clock enable
signal (CKE) is sampled LOW. This input is valid when both
CLOCK_CHANGE_TRACKING_ENABLE and
USE_PORTS_TO_CONFIGURE are set to 1.
TMRD
SELF REFRESH to non-READ command time parameter input

minimum time interval between SELF REFRESH command to any
non-READ command to any bank. This input is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 1.
TRAS
RAS# active time parameter inputminimum time to precharge a

bank after it was previously issued an ACTIVE command without
losing read/write data.This input is valid only when the
TRC
RAS# cycle time parameter inputminimum time interval between

successive ACTIVE commands to the same bank. This input is valid
only when the USE_PORTS_TO_CONFIGURE parameter is set to
1.
TRCD
RAS# to CAS# delay parameter inputminimum time to legally

issue a READ or WRITE command to a row after opening it by
issuing an ACTIVE command. This input is valid only when the

V2.0 Monitor
Table 6-13. DDR SDRAM 2.0 Monitor Pin-Out (cont.)

Pin
Description
TRFC
SELF REFRESH to READ command time parameter input

minimum time interval between SELF REFRESH command to a
READ command to any bank.This input is valid only when the
TRP
RAS# precharge time parameter inputminimum time to precharge

a bank. This input is valid only when the
TRRD
RAS# to RAS# bank activate delay parameter inputminimum time

interval between successive ACTIVE commands to different banks.
This input is valid only when the USE_PORTS_TO_CONFIGURE
TWR
MODE REGISTER SET command cycle time parameter input

minimum time interval for any new command issue after the MODE
REGISTER SET command was previously issued. This input is
valid only when the USE_PORTS_TO_CONFIGURE parameter is
set to 1.
TWRT
AUTO REFRESH to ACTIVE command time parameter input

minimum time between AUTO REFRESH command and an
ACTIVE command to any bank. This input is valid only when the
TXSNR
WRITE burst end to PRECHARGE time parameter input

minimum time interval between WRITE burst end to PRECHARGE
command. This input is valid only when the
TXSRD
WRITE burst end to READ command time parameter input.

Minimum time interval between a WRITE burst end to the READ
command issue. This input is valid only when the
UDM
Data mask for port {DQ15:DQ8}.
UDQS
Data strobe for port {DQ15:DQ8}.
WE_n
Note that the timing value between a WRITE command and the first DQS latching transition is
called the tdqss value. For formal analysis, the DDR SDRAM 2.0 monitor only supports
tdqss values equal to the clock period. This means that the DQS signal edges should be in line
with the clock signal for formal analysis. The monitor supports tdqss values from 75% to
125% of the total clock period.
Monitor Parameters
The parameters shown in Table 6-14 configure the corresponding DDR SDRAM 2.0 monitor.
The override parameters set timing parameters for the monitor.
139

V2.0 Monitor
Refer to Table 6-17 on page 145 for the JEDEC standard compliant values of the parameters
that are used as default values.
Table 6-14. DDR SDRAM 2.0 Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode
Set to 1 if the checks in the monitor are to be used

as constraints for formal analysis.
2.
CONTROLLER_SIDE
Set this parameter to 1 if the monitor is instantiated

on the DDR SDRAM controller side. This
parameter and the Constraints_Mode parameter
turn all checks in the monitor to constraints (checks
those connected on the input signals to controller)
or targets (checks those connected on output signals
from controller), and checks those connected on the
bidirectional signals during formal analysis.
3.
ADDR_WIDTH
12
Width of address bus signals. Minimum value for

this parameter is 12. If your designs ADDR
WIDTH is less than 12, then for the upper address
lines of the monitor that are not available in the
design, connect with 1'b0.
4.
DATA_WIDTH
Width of data bus signals. Minimum value for this

parameter is 4.
5.
DLL_TRACKING_ENABLE
Set this parameter to 1 to enable the

DDR_SDRAM_no_dll_reset and
DDR_SDRAM_violates_tDLL checks.
6.
TRC_OVERRIDE
RAS# cycle timeminimum time interval between

successive ACTIVE commands to the same bank.
default value or the timing parameter from the port
to be used. This parameter is applicable only when
the USE_PORTS_TO_CONFIGURE is 0.
7.
TRAS_OVERRIDE
RAS# active timeminimum time to precharge a

bank after it was previously issued an ACTIVE
command without losing read/write data. Set this
parameter to 0 if you want the JEDEC default value
or the timing parameter from the port to be used.
This parameter is applicable only when the
USE_PORTS_TO_CONFIGURE is 0.
8.
TRP_OVERRIDE
RAS# precharge timeminimum time to precharge

a bank. Set this parameter to 0 if you want the
JEDEC default value or the timing parameter from
the port to be used. This parameter is applicable
only when the USE_PORTS_TO_CONFIGURE is
0.
9.
TRCD_OVERRIDE
RAS# to CAS# delayminimum time to legally

issue a READ or WRITE command to a row after
opening it by issuing an ACTIVE command. Set
value or the timing parameter from the port to be
used. This parameter is applicable only when the
140

V2.0 Monitor
Table 6-14. DDR SDRAM 2.0 Monitor Parameters (cont.)

Order Parameter
Default Description
10.
TRRD_OVERRIDE
RAS# to RAS# bank activate delayminimum

time interval between successive ACTIVE
commands to different banks. Set this parameter to
0 if you want the JEDEC default value or the timing
parameter from the port to be used. This parameter
is applicable only when the
11.
TMRD_OVERRIDE
MODE REGISTER SET command cycle time

minimum time interval for any new command issue
after the MODE REGISTER SET command was
previously issued. Set this parameter to 0 if you
want the JEDEC default value or the timing
12.
TRFC_OVERRIDE
AUTO REFRESH to ACTIVE command time

minimum time between AUTO REFRESH
command and an ACTIVE command to any bank.
13.
TXSNR_OVERRIDE

command to any non-READ command to any bank.
14.
TXSRD_OVERRIDE
SELF REFRESH to READ command time

command to a READ command to any bank. Set
value or the timing parameter from the port to be
used. This parameter is applicable only when the
15.
TWR_OVERRIDE
WRITE burst end to PRECHARGE time (minimum

time interval between WRITE burst end to
PRECHARGE command). Set this parameter to 0 if
you want the JEDEC default value or the timing
16.
TWTR_OVERRIDE
WRITE burst end to READ command time.

Minimum time interval between a WRITE burst
end to the READ command issue. Set this
parameter to 0 if you want the JEDEC default value
or the timing parameter from the port to be used.
This parameter is applicable only when the
141

V2.0 Monitor

Order Parameter
Default Description
17.
AUTOPRECHARGE_ENABLE_
ADDRESS_BIT
10
Bit-index specifying the auto precharge address

line. The address bit, specified by this parameter is
used to enable/disable the auto precharge function
during a Read or Write command. This is also used
to decode a Single bank precharge and all banks
precharge during a precharge command issue.
18.
COL_ADDRESS_WIDTH
Number of Column address lines. This parameter is

used to decode the size of the full page for Full
Page Mode (FPM) burst.
19.
READ_BEFORE_WRITE_
CHECK_ENABLE
Enables the check that ensures no read is performed

to a location when there is no previous write to the
same location. Set this parameter to 0 to disable this
check. Check ID:
20.
CON_AUTO_PRECHARGE
Set this parameter to 1 if the device in which the

monitor is instantiated supports the Concurrent
Auto Precharge. By default, the monitor assumes
that the device in which it is instantiated does not
support Concurrent Auto Precharge.
21.
ENABLE_WHY_PRECHARGE_
AN_IDLE_BANK
Set this parameter to 1 to enable the check that

ensures a PRECHARGE command is not issued to
an idle bank. By default, this check (Check ID:
DDR_SDRAM_why_precharge_an_idle_bank) is
turned off.
22.
BYPASS_INIT

sequence. If this parameter is set to 1, then the
complete initialization sequence need not be
performed. Nevertheless, valid operational values
must be passed to the mode register and extended
mode register inputs (otherwise, the monitor
behavior is undefined). By default, the monitor
requires the proper initialization sequence to be
performed as stated in the specification.
23.
NON_JEDEC
Set this parameter to 1 to enable the usage of NON

JEDEC values for the configuration of Burst length,
CAS Latency, and timing parameters. By default,
the use of JEDEC values are only allowed.
24.
USE_PORTS_TO_CONFIGURE
Set this parameter to 1 to enable the usage of the

input ports to configure the various timing
parameter values. By default, the monitor uses the
defined JEDEC values.
25.
DATA_CHECK_ENABLE
This parameter enables or disables the following

data integrity checks: DDR_SDRAM_bad_data and
checks.
142

V2.0 Monitor

Order Parameter
Default Description
26.
TCLK_OVERRIDE
27.
CLOCK_CHANGE_TRACKING_ 0
ENABLE
Set this parameter to 1 to enable support of the

change of input clock frequency on the fly as per
JESD79E May 2005 specification update.
28.
TCLK_CHECK_ENABLE
Set this parameter to 1 to enable checking for the

minimum clock cycles to be lapsed before the clock
frequency can change after CKE is sampled LOW.
This parameter is valid only when parameter
CLOCK_CHANGE_TRACKING_ENABLE is set
to 1.
29.
CLOCK_FREQUENCY_RANGE_ 0
CHECK_ENABLE
Set this parameter to 1 to enable checking for the

clock frequency if it is within the allowed ranges,
which is specified by another set of parameters
CLOCK_PERIOD_MAX and
CLOCK_PERIOD_MIN. This parameter is valid
to 1.
30.
CLOCK_PERIOD_MAX
10
Set the highest allowed clock period specified in

nanoseconds (ns), which is a measure of the lowest
clock frequency supported by the DDR SDRAM.
The default value is set to 10 (ns). The default value
means a supported clock of 100 MHz, which is the
slowest clock supported for DDR SDRAM as per
JESD79E. The user can alter this value for nonJEDEC applications.
31.
CLOCK_PERIOD_MIN
Set the lowest allowed clock period specified in

nanoseconds (ns), which is a measure of the lowest
clock frequency supported by the DDR SDRAM.
The default value is set to 5 (ns). The default value
means a supported clock of 200 MHz, which is the
fastest clock supported for DDR SDRAM as per
JESD79E. The user can alter this value for nonJEDEC applications.
Represents the value for the minimum cycles to be

lapsed before the clock frequency can change in
precharge power down mode after the clock enable
signal (CKE) is sampled LOW. This parameter is
valid only when parameter
to 1 and parameter
USE_PORTS_TO_CONFIGURE is set to 0.


Name: QVL_DQS_DELAY
Default: 2
143

V2.0 Monitor
Description:
JEDEC Mode
Full Page mode burst can be configured only in JEDEC mode (that is, when NON_JEDEC = 0).
When NON_JEDEC =1, the Burst Length configuration is as shown in Table 6-15.
Table 6-15. JEDEC Mode Burst Length Configuration
A[2:0]
BURST LENGTH
000
RSVD
001
010
011
100
16
101
32
110
64
111
128
CAS latency of 4 can be configured only in JEDEC mode (that is, when NON_JEDEC = 0).
When NON_JEDEC =1, the CAS Latency configuration is as shown in Table 6-16.
Table 6-16. JEDEC Mode CAS Latency Configuration
144
A[6:4]
CAS LATENCY
000
RSVD
001
1.0
010
2.0
011
3.0
100
0.5
101
1.5
110
2.5
111
RSVD

V2.0 Monitor
the checks as constraints for formal analysis, do the following:

o
If the monitor is instantiated in the DDR SDRAM controller, then set

If the monitor is instantiated in the DDR SDRAM memory, then set

Table 6-17. JEDEC Compliant Min. Timing for DDR SDRAM Speed Grade 266
Timing Parameter
TRC
TRAS
TRP
TRCD
TRRD
TMRD
TRFC
TXSNR
TXSRD
200
TWR
TWTR
Example 1
Example 6-5 instantiates a JEDEC standard compliant DDR SDRAM 2.0 monitor on the DDR
SDRAM controller side for unconstraint search with ADDR_WIDTH of 12, DATA_WIDTH of 8,
8th bit of Address line as Auto precharge enable, Lower 8 Column Address lines are to be used
for Full Page Mode burst, and DLL_TRACKING_ENABLE set to 1. Note that all timing parameters
are the default values specified by JEDEC. The monitor is in normal mode of operation, which
enables the monitor to track the initialization sequence.
Example 6-5. DDR SDRAM 2.0 Monitor Instantiated in the Controller
qvl_ddr_sdram_2_0_monitor
145

V2.0 Monitor
1,
/* ADDR_WIDTH */
12,
/* DATA_WIDTH */
8)
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable_1),
.CS_n
(chip_select_1_n),
.RAS_n
.CAS_n
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(data_mask_1),
.DQ
(data_bus_8),
.DQS
(data_strobe)
.mode_register (),
.extended_mode_register (),
.LDQS (1'b0),
.LDM (1'b0),
.UDQS (1'b0),
.UDM (1'b0)
.TRC(32'b0),
.TRAS(32'b0),
.TRP(32'b0),
.TRCD(32'b0),
.TRRD(32'b0),
.TWR(32'b0),
.TWTR(32'b0),
.TMRD(32'b0),
.TRFC(32'b0),
.TXSNR(32'b0),
.TXSRD(32'b0),
.TCLK(32'b0) );
Example 2
Example 6-6 instantiates two DDR SDRAM 2.0 monitors for a JEDEC standard DDR SDRAM
controller design. The example shows the following:
The controller design interfaces two DDR SDRAMs, each having 16 bits of
DATA_WIDTH to form a 32-bit data bus.
146
ADDR_WIDTH
DM_WIDTH
of 12.

1.

V2.0 Monitor
The monitor is instantiated for unconstrained formal analysis. Therefore, the


Example 6-6. Two DDR SDRAM 2.0 Monitors
0,
1,
/* ADDR_WIDTH */
12,
/* DATA_WIDTH */
16)
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
.CS_n
.RAS_n
.CAS_n
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(1'b0),
.DQ
(data_bus_32[15:0]),
.DQS
(1'b0),
.mode_register (),
.LDQS (data_strobe),
.LDM (data_mask_4[0]),
.UDQS (data_strobe),
.UDM (data_mask_4[1]),
.TRC(32'b0),
.TRAS(32'b0),
.TRP(32'b0),
.TRCD(32'b0),
.TRRD(32'b0),
.TWR(32'b0),
.TWTR(32'b0),
.TMRD(32'b0),
.TRFC(32'b0),
.TXSNR(32'b0),
.TXSRD(32'b0),
.TCLK(32'b0) );
1,
/* ADDR_WIDTH */
12,
/* DATA_WIDTH */
16)
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
147

V2.0 Monitor
.CS_n
.RAS_n
.CAS_n
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(1'b0),
.DQ
(data_bus_32[31:16]),
.DQS
(1'b0),
.mode_register (),
.LDQS (data_strobe),
.LDM (data_mask_4[2]),
.UDQS (data_strobe),
.UDM (data_mask_4[3]),
.TRC(32'b0),
.TRAS(32'b0),
.TRP(32'b0),
.TRCD(32'b0),
.TRRD(32'b0),
.TWR(32'b0),
.TWTR(32'b0),
.TMRD(32'b0),
.TRFC(32'b0),
.TXSNR(32'b0),
.TXSRD(32'b0),
.TCLK(32'b0) );
Example 3
Example 6-7 instantiates a DDR SDRAM 2.0 monitor for a Micron 64 Mb compatible
controller design. The example has the following characteristics:
ADDR_WIDTH.
The other input signal width is as follows:

o
DM_WIDTH
The timing parameter values are as follows:

TRC
10
TRFC
11
148
of 1.
TRAS
7
TXSNR
10
TRP
3
TXSRD
200
TRCD
3
TWR
2
TRRD
2
TWTR
1
TMRD
2

FPM mode is supported. FPM size is 256 and the number of address lines required to
burst up to 256 is 8. Therefore, the COL_ADDRESS_WIDTH is set to 8.

V2.0 Monitor

1.

Example 6-7. DDR SDRAM 2.0 Monitor Instantiated in the Controller
qvl_ddr_sdram__2_0_monitor
0,
1,
/* ADDR_WIDTH */
12,
/* DATA_WIDTH */
8,
1,
/* TRC_OVERRIDE */
10,
/* TRAS_OVERRIDE */
7,
/* TRP_OVERRIDE */
3,
/* TRCD_OVERRIDE */
3,
/* TRRD_OVERRIDE */
2,
/* TMRD_OVERRIDE */
2,
/* TRFC_OVERRIDE */
11,
10,
200,
/* TWR_OVERRIDE */
2,
/* TWTR_OVERRIDE */
1,
8,
1,
0,
/* BYPASS_INIT*/
1)
.clock
(clock),
.clock_n
clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable),
.CS_n
(chip_select_n),
.RAS_n
.CAS_n
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(data_mask_1),
.DQ
(data_bus_8),
.DQS
(data_strobe),
.extended_mode_register (internal_mode_register),
.LDQS (1'b0),
.LDM (1'b0),
.UDQS (1'b0),
.UDM (1'b0),
.TRC(32'b0),
.TRAS(32'b0),
.TRP(32'b0),
.TRCD(32'b0),
149

V2.0 Monitor
.TRRD(32'b0),
.TWR(32'b0),
.TWTR(32'b0),
.TMRD(32'b0),
.TRFC(32'b0),
.TXSNR(32'b0),
.TXSRD(32'b0),
.TCLK(32'b0) );
Example 4
Example 6-8 on page 150 instantiates a DDR SDRAM 2.0 monitor to check the controller with
NON JEDEC timing values configured through parameters. The example has the following
characteristics:
ADDR_WIDTH.

o
DM_WIDTH of 1
The timing parameters are set to NON JEDEC values through the parameters. Therefore, the
NON_JEDEC parameter is 1 and USE_PORTS_TO_CONFIGURE parameter is 0. The NON JEDEC
timing parameter values are as follows:
TRC
12
TRFC
15
TRAS
8
TXSNR
13
TRP
4
TXSRD
250
TRCD
4
TWR
3
TRRD
4
TWTR
2
TMRD
4


1.

Example 6-8. DDR SDRAM 2.0 Monitor Instantiated with NON JEDEC Timing
Values Configured Through Parameters
/* ADDR_WIDTH */
/* DATA_WIDTH */
150
0,
1,
12,
8,

V2.0 Monitor
1,
/* TRC_OVERRIDE */
12,
/* TRAS_OVERRIDE */
8,
/* TRP_OVERRIDE */
4,
/* TRCD_OVERRIDE */
4,
/* TRRD_OVERRIDE */
4,
/* TMRD_OVERRIDE */
4,
/* TRFC_OVERRIDE */
15,
13,
250,
/* TWR_OVERRIDE */
3,
/* TWTR_OVERRIDE */
2,
8,
1,
0,
/* BYPASS_INIT*/
1,
/* NON_JEDEC*/
1,
/* USE_PORTS_TO_CONFIGURE*/
0,
/* DATA_CHECK_ENABLE */
0,
/* ZI_DDR_SDRAM_2_0 */
1,
/* DM_WIDTH */
1,
/* CLOCK_CHANGE_TRACKING_ENABLE */
1,
/* TCLK_CHECK_ENABLE */
1,
/* TCLK_OVERRIDE */
3,
/* CLOCK_FREQUENCY_RANGE_CHECK_ENABLE*/1,
/* CLOCK_PERIOD_MAX */
10,
/* CLOCK_PERIOD_MIN */
5,
/* NO_SET_CAS_LATENCY_CHECK_ENABLE */ 1)
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable),
.CS_n
(chip_select_n),
.RAS_n
.CAS_n
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(data_mask_1),
.DQ
(data_bus_8),
.DQS
(data_strobe),
.LDQS (1'b0),
.LDM (1'b0),
.UDQS (1'b0),
.UDM (1'b0),
.TRC(32'b0),
.TRAS(32'b0),
.TRP(32'b0),
.TRCD(32'b0),
.TRRD(32'b0),
.TWR(32'b0),
.TWTR(32'b0),
151

V2.0 Monitor
.TMRD(32'b0),
.TRFC(32'b0),
.TXSNR(32'b0),
.TXSRD(32'b0),
.TCLK(32'b0) );
Note that this example also shows parameter configuration for enabling clock frequency change
support model of the monitor.
Example 5
Example 6-9 on page 152 instantiates a DDR SDRAM 2.0 monitor to check the controller with
NON JEDEC timing values configured through input ports. The example has the following
characteristics:
ADDR_WIDTH.

o
DM_WIDTH
of 1.
The timing parameters are set to NON JEDEC values through the input ports. Therefore,
the NON_JEDEC parameter is 1 and the USE_PORTS_TO_CONFIGURE parameter is 1. The
NON JEDEC timing parameter values are as follow:
TRC
12
TRFC
15
TRAS
8
TXSNR
13
TRP
4
TXSRD
250
TRCD
4
TWR
3
TRRD
4
TWTR
2
TMRD
4


1.

Example 6-9. DDR SDRAM 2.0 Monitor Instantiated with NON JEDEC Timing
Values Configured Through Input Ports
/* ADDR_WIDTH */
152
0,
1,
12,

V2.0 Monitor
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
DATA_WIDTH */
8,
DLL_TRACKING_ENABLE */
1,
TRC_OVERRIDE */
12,
TRAS_OVERRIDE */
8,
TRP_OVERRIDE */
4,
TRCD_OVERRIDE */
4,
TRRD_OVERRIDE */
4,
TMRD_OVERRIDE */
4,
TRFC_OVERRIDE */
15,
TXSNR_OVERRIDE */
13,
TXSRD_OVERRIDE */
250,
TWR_OVERRIDE */
3,
TWTR_OVERRIDE */
2,
AUTOPRECHARGE_ENABLE_ADDRESS_BIT */ 8,
COL_ADDRESS_WIDTH */
8,
READ_BEFORE_WRITE_CHECK_ENABLE */
1,
CON_AUTO_PRECHARGE */
0,
ENABLE_WHY_PRECHARGE_AN_IDLE_BANK */0,
BYPASS_INIT*/
1,
NON_JEDEC*/
1,
USE_PORTS_TO_CONFIGURE*/
1,
DATA_CHECK_ENABLE */
0,
ZI_DDR_SDRAM_2_0 */
1,
DM_WIDTH */
1,
CLOCK_CHANGE_TRACKING_ENABLE */
1,
TCLK_CHECK_ENABLE */
1,
TCLK_OVERRIDE */
2, // This parameter will
// not be effective as the
// port TCLK will be used
// to configure
// this timing parameter.
/* CLOCK_FREQUENCY_RANGE_CHECK_ENABLE*/1,
10, // Specified in
// nanoseconds for a
// 100 MHz clock.
5) // Specified in
// nanoseconds for a
// 200 MHz clock.
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable),
.CS_n
(chip_select_n),
.RAS_n
.CAS_n
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(data_mask_1),
.DQ
(data_bus_8),
.DQS
(data_strobe),
.LDQS (1'b0),
.LDM (1'b0),
.UDQS (1'b0),
153

V2.0 Monitor
.UDM (1'b0),
.TRC(32'd11),
.TRAS(32'd7),
.TRP(32'd3),
.TRCD(32'd3),
.TRRD(32'd3),
.TWR(32'd2),
.TWTR(32'd1),
.TMRD(32'd3),
.TRFC(32'd14),
.TXSNR(32'd12),
.TXSRD(32'd249),
.TCLK(32'd3) );
Note that this example also shows parameter configuration for enabling clock frequency change
support model of the monitor.
Monitor Checks
Table 6-18 shows the checks performed by a DDR SDRAM 2.0 monitor.
Table 6-18. DDR SDRAM 2.0 Monitor Checks
Check ID
Violation
Description
DDR_SDRAM_ADDRESS

value.

value when mode register set/extended
mode register set/read/write/read with
precharge/bank activation command is
issued.
DDR_SDRAM_BA
Bank address bus, BA, has a X

or Z value.
Bank address bus, BA, should have a

valid value when read/write/read with
precharge/bank activation/single bank
precharge command is issued.
DDR_SDRAM_BYPASS_INIT
BYPASS_INIT should be
either 1 or 0.
The value of the BYPASS_INIT

DDR_SDRAM_CAS_n
Column address strobe,

CAS_n, has a X or Z value.
Column address strobe, CAS_n, must

is low.
DDR_SDRAM_CKE
Clock enable, CKE, has a X or

Z value.
Clock enable, CKE, must always have

a valid value.
DDR_SDRAM_Constraint_Mode
either 1 or 0.
The value of Constraints_Mode

parameter value should be either 1 or 0.
SIDE
CONTROLLER_SIDE should The value of CONTROLLER_SIDE

be either 1 or 0.
parameter value should be either 1 or 0.
154

V2.0 Monitor
Table 6-18. DDR SDRAM 2.0 Monitor Checks (cont.)

Check ID
Violation
Description
DDR_SDRAM_CS_n
Chip select, CS_n, has a X or

Z value.
Chip select, CS_n, must always have a

valid value. This check is active only if
CKE is high.
DDR_SDRAM_DATA_CONFIG
Data bus width should be

either 4, 8, or 16.

parameter should not be specified to be
other than 4, 8, or 16 since this
indicates the configuration of the data
bus and the allowed configurations are
x4, x8, or x16.
DDR_SDRAM_DLL_TRACKING_
ENABLE
DLL_TRACKING_ENABLE
The value of the

DLL_TRACKING_ENABLE
DDR_SDRAM_DM

value.
Data mask, DM, must always have a

valid value. This check is active only if
CKE is high and a valid write data
phase is in progress.
DDR_SDRAM_DM_WIDTH
Data mask width should not be

1.
The value of the DM_WIDTH

parameter should not be less than 1.
A command that should not be This check is applicable only if

issued before the mode
BYPASS_INIT is set to 0 (that is, a
register set command is issued. proper MRS cycle is performed). NOP,
precharge, and refresh are the only
commands that are valid before the
MODE REGISTER SET. The user
sequencing.
length
The burst length field of the


specification, the valid burst length
values are 2 (3b001), 4 (3'b010), 8
(3'b011), and Full Page Mode (FPM)
(3'b111). This check fires if a burst
length value other than the ones listed
above is passed through the
mode_register input.
Invalid burst length value

during the mode register set
command.

burst length values are 2 (3'b001), 4
(3'b010), 8 (3'b011), and Full Page
Mode (FPM) (3'b111). This check fires
if a burst length value other than the
ones listed above is programmed.
155

V2.0 Monitor

Check ID
Violation
Description
DDR_SDRAM_invalid_cas_latency


specification, the valid CAS latency
values are 1.5 (3'b101), 2 (3'b010), 2.5
(3'b110), 3 (3'b011), and 4 (3'b100).
This check fires if a CAS latency value
other than the ones listed above is
passed through the mode_register
input.
Invalid CAS latency value

during the mode register set
command.

CAS latency values are 1.5 (3'b101), 2
(3'b010), 2.5 (3'b110), 3 (3'b011), and 4
(3'b100). This check fires if a CAS
latency value other than the ones listed
mode
The operating mode field in

the mode register or extended
mode register input is invalid.

value is passed to the mode_register
input. As per the JEDEC specification,
for normal operation, A[11:7] should
be either 5'b00000 or 5'b00010 in the
mode register and A[11:3] should be
9'b000000000 in the extended mode
register. EXTENDED MODE
REGISTER SET command. This check
fires if values other than the above are
passed to the corresponding inputs.
Invalid operating mode bits

are programmed during mode
register set or extended mode
register set command.

normal operation, A[11:7] should be
either 5'b00000 or 5'b00010 during
and A[11:3] should be 9'b000000000
during EXTENDED MODE
REGISTER SET command. This check
fires if a value other than the ones listed
above is driven on address bus (A)
during MODE REGISTER SET or
EXTENDED MODE REGISTER SET
command is issued.
DDR_SDRAM_RAS_n
Row address strobe, RAS_n,

has a X or Z value.

is low.
DDR_SDRAM_TMRD
TMRD value should not be

2.

less than 2.
156

V2.0 Monitor

Check ID
Violation
Description
DDR_SDRAM_TRAS
TRAS value should not be less


less than 4.
DDR_SDRAM_TRC
TRC value should not be less


The value of the TRC timing parameter
should not be specified to be less than
5.
DDR_SDRAM_TRCD
TRCD value should not be less This check is applicable only when the
less than 2.
DDR_SDRAM_TRFC


less than 6.
DDR_SDRAM_TRP
TRP value should not be less


The value of the TRP timing parameter
2.
DDR_SDRAM_TRRD
TRRD value should not be less This check is applicable only when the
less than 1.
DDR_SDRAM_TWR


less than 1.
DDR_SDRAM_TXSNR
TXSNR value should not be

6.

less than 6.
DDR_SDRAM_TXSRD
TXSRD value should not be

200.

less than 200.
An activate command is issued The command just issued violates

too quickly after the prior
tRRD (RAS to RAS delay timing). This
activate command.
is an ACTIVATE command issued too
quickly after the ACTIVATE
command for another bank. The user
should determine why the commands
are too close together.
157

V2.0 Monitor

Check ID
Violation
Description
DDR_SDRAM_WE_n
Write enable, WE_n, has a X

or Z value.
Write enable, WE_n, must always have

a valid value. This check is active only
if CKE is high and CS_n is low.
Table 6-19 shows the checks for each bank performed by a DDR SDRAM 2.0 monitor.
Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank
Check ID
Violation
Description
A_DDR_SDRAM_clock_change_
during_non_ppd_mode
Clock frequency has changed

while the DDR SDRAM is not
in precharge power down
mode.
The input clock frequency can change

only in precharge power down mode
while the clock enable signal CKE is
LOW. This check fires when the DDR
SDRAM clock changes while the DDR
SDRAM is not operating in idle or
precharge power down mode. This
check is functional only when the
parameter CLOCK_CHANGE_
TRACKING_ENABLE is set to 1.
A_DDR_SDRAM_clock_change_
during_illegal_cke

while CKE is not LOW.

SDRAM clock changes while CKE is
not LOW. This check is functional only
when the parameter CLOCK_
CHANGE_TRACKING_ENABLE is
set to 1.
A_DDR_SDRAM_violates_tCLK
A command that violates

TCLK cycle timing is issued.

SDRAM clock changes before elapse of
a minimum of clock cycles specified by
port TCLK (subject to the setting of
USE_PORTS_CONFIGURE = 1) or
parameter TCLK_OVERRRIDE after
CKE is LOW. This check is functional
only when both the parameter
CLOCK_CHANGE_TRACKING_
ENABLE and
TCLK_CHECK_ENABLE are set to 1.
158

V2.0 Monitor
Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank (cont.)
Check ID
Violation
Description
A_DDR_SDRAM_clock_
frequency_out_of_range
The clock frequency is out of

the allowed range in the
current speed grade of DDR
SDRAM.

only within the allowed range in a speed
grade. This check fires when the DDR
SDRAM clock changes beyond the
allowed clock frequency range specified
by the parameters
CLOCK_PERIOD_MIN. By default,
the monitor verifies a range of 100Mhz
to 200 MHz. This check is functional
only when both the parameters
ENABLE and
CLOCK_FREQUENCY_RANGE_
CHECK_ENABLE are set to 1.
A_DDR_SDRAM_CKE_changed_
during_unstable_clock
CKE changed state while the

clock is not yet stable.

LOW. This check fires when after a
clock frequency change, CKE changes
its state before a stable clock is
available. This check is functional only
when the parameter
ENABLE is set to 1.
A_DDR_SDRAM_ppd_exit_
during_unstable_clock
Precharge power down mode

exited during an unstable
clock.

LOW. This check fires when after a
clock frequency change, precharge
power down mode is exited before a
stable clock is available. This check is
functional only when the parameter
ENABLE is set to 1.
A_DDR_SDRAM_dll_not_reset_
after_ppd_exit_after_clock_change
DLL is not reset after

precharge power down exit
after clock change.
This check fires when a DLL reset

command is not executed after a clock
frequency change. This check is
functional only when both the
parameters CLOCK_CHANGE_
TRACKING_ENABLE and
DLL_TRACKING_ENABLE are set to
1.
DDR_SDRAM_bad_data
One or more bytes of data

read from the addressed DDR
SDRAM location did not
match the data byte(s) written
to the corresponding address.
Data read from the DDR SDRAM did

not match the data written to the
corresponding address. The data check
is performed only on reads to locations
that were previously written at least
once. Data checking is done on a byte
basis and the bitmap indicates the data
inconsistency between the
corresponding bytes. This check fires
when at least one byte of read data does
not match the corresponding valid data
byte that is written to that location.
159

V2.0 Monitor
Check ID
Violation
Description
DDR_SDRAM_con_auto_
precharge_min_delay_violation
Concurrent Auto Precharge

minimum delay violation.
Some devices support Concurrent Auto

Precharge feature such that when a read
with auto precharge or write with auto
precharge is enabled to one bank, any
command to other bank can be issued as
long as this command does not interrupt
the earlier command. The minimum
delay between the read/write command
with auto precharge to a command to a
different bank has to be met in this case.
This check fires when the minimum
delay in terms of clock cycle is violated.
This check is enabled only if the
CON_AUTO_PRECHARGE parameter
is set to 1.
active
Illegal command is issued

when the bank is in ACTIVE
state.
The command just issued is not legal

when the bank is in ACTIVE state. All
the valid commands for ACTIVE state
are listed in the JEDEC specification
under TRUTH TABLE 2, 3, and 4. Any
command other than these are treated as
illegal commands by the monitor. When
this check fires, the current state of the
bank is encoded in the state_string
signal of the module
aref

when all the banks are in
AUTO REFRESH state.

when the bank is in AUTO REFRESH
AUTO REFRESH state are listed in the
other than these are treated as illegal
commands by the monitor. When this
check fires, the current state of the bank
is encoded in the state_string signal of
the module
emrs

EXTENDENDED MODE
REGISTER SET state.

when the bank is in EXTENDENDED
MODE REGISTER SET state. All the
valid commands for EXTENDENDED
MODE REGISTER SET state are listed
in the JEDEC specification under
TRUTH TABLE 2, 3, and 4. Any
160

V2.0 Monitor
Check ID
Violation
Description
idle

when the bank is in IDLE
state.

when the bank is in IDLE state. All the
valid commands for IDLE state are
listed in the JEDEC specification under
mrs

MODE REGISTER SET
state.

when the bank is in MODE REGISTER
SET state. All the valid commands for
MODE REGISTER SET state are listed
in the JEDEC specification under
pall

PRECHARGE state.

when the bank is in PRECHARGE ALL
PRECHARGE ALL state are listed in
the JEDEC specification under TRUTH
the module
pre

when the bank is in
PRECHARGE state.

when the bank is in PRECHARGE
PRECHARGE state are listed in the
the module
161

V2.0 Monitor
Check ID
Violation
Description
read

when the bank is in READ
state.

when the bank is in READ state. All the
valid commands for READ state are
listed in the JEDEC specification under
reada

WITH AUTO PRECHARGE
state.

when the bank is in READ WITH
AUTO PRECHARGE state. All the
valid commands for READ WITH
AUTO PRECHARGE state are listed in
the module
write

when the bank is in WRITE
state.

when the bank is in WRITE state. All
the valid commands for WRITE state
are listed in the JEDEC specification
under TRUTH TABLE 2, 3, and 4. Any
writea

WITH AUTOPRECHARGE
state.

when the bank is in WRITE WITH
AUTOPRECHARGE state. All the
valid commands for WRITE WITH
AUTOPRECHARGE state are listed in
the module
162

V2.0 Monitor
Check ID
Violation
Description
DDR_SDRAM_invalid_self_ref_or_ Only NOP or DSEL command

power_down_exit
should be issued during SELF
REFRESH or POWER
DOWN exit.
When DDR SDRAM is exited from the

SELF REFRESH or POWER DOWN
mode, only NOP or DESELECT
command should be issued along with
the SELF REFRESH EXIT or POWER
DOWN EXIT command. This check
fires if a NOP or DESELECT command
is not issued during SELF REFRESH or
POWER DOWN exit.
DDR_SDRAM_no_auto_ refresh
At least two auto refresh

commands should be issued
after reset and before first
active command.
Minimum two auto refresh commands

should be issued after reset and before
the first activate command is issued.
This check fires if there is no auto
refresh command or only one auto
refresh command is issued before the
first active command issue.
DDR_SDRAM_no_dll_ reset
DLL is not reset after it is

enabled.
If DLL is enabled through EXTENDED

MODE REG SET command, then there
should be a DLL reset command issued
before an activate command is issued.
A read operation was

performed on the DDR
SDRAM address that was not
Data is read from a DDR SDRAM

address that was not previously written
into. This check fires whenever a
location being read was previously not
written into.
DDR_SDRAM_violates_tDLL
At least 200 clocks delay

should be given between the
DLL enable and a read/read
with auto precharge
command.
If DLL is enabled, then there should be

a minimum of 200 clocks delay before a
read command or read with
autoprecharge command is issued.
signal_P
CKE is low when the control

signals and/or the monitor
state machine are not pointing
to SELF REFRESH or
POWER DOWN mode.
CKE should not go low when the DDR

SDRAM is performing a READ or
WRITE burst. The user should
determine why CKE goes low when the
DDR SDRAM is performing a READ
or WRITE burst.
signal_N * (see the note at the end of
this table)
CKE is low when the control

signals and/or the state
machine are not computing to
DOWN mode.
CKE should not go low when the DDR

WRITE burst. You should determine
why CKE goes low when the DDR
WRITE burst.
DDR_SDRAM_violates_tMRD

tMRD timing is issued.

tMRD (minimum time delay between
MODE REGISTER SET command and
any other command) timing. The new
command is issued too quickly after the
MODE REGISTER SET command.
The user should determine why the
signal_N
163

V2.0 Monitor
Check ID
Violation
DDR_SDRAM_violates_tRAS
A command that violates RAS The command just issued violates tRAS
timing is issued.
(RAS to precharge timing). This is a
PRECHARGE command issued too
quickly after the ACTIVATE command
for this bank. The user should determine
together.
DDR_SDRAM_violates_tRC
A command that violates RAS The command just issued violates tRC
cycle timing is issued.
(RAS cycle timing). This is an
ACTIVATE command for this bank.
DDR_SDRAM_violates_tRCD
A command that violates RAS The command just issued violates tRCD
to CAS delay timing is issued. (RAS to CAS delay timing). This is a
READ/WRITE command issued too
quickly after the ACTIVATE command
for this bank. The user should determine
together.
DDR_SDRAM_violates_tRFC

tRFC timing is issued.
DDR_SDRAM_violates_tRP
A command that violates RAS The command just issued violates tRP
precharge timing is issued.
(RAS precharge timing). This is an
precharge command for this bank. The
DDR_SDRAM_violates_tXSNR

tXSNR timing is issued.

tXSNR (minimum time delay between
SELF REFRESH EXIT command and
any other non-READ command)
timing. A non-READ command is
issued too quickly after the SELF
REFRESH EXIT command. The user
DDR_SDRAM_violates_tXSRD
A read/read with auto

precharge command that
violates tXSRD timing is
issued.

violates tXSRD (minimum time delay
command and a READ command)
timing. A READ command is issued too
quickly after the SELF REFRESH
EXIT command. The user should
determine why the commands are too
close together.
164
Description
The command just issued violates tRFC

(minimum time delay between AUTO
REFRESH command and any other
command). The new command is issued
too quickly after the AUTO REFRESH
command. The user should determine
together.

V2.0 Monitor
Check ID
Violation
Description
DDR_SDRAM_why_precharge_
an_idle_bank
A PRECHARGE command is
issued while the bank is
already in a precharged state.
The design is precharging (not an allbank PRECHARGE) a bank that has

already been precharged. Although not
illegal, this is inefficient. The user
should examine why the extra
PRECHARGE command is issued. This
check is enabled only when ENABLE_
WHY_PRECHARGE_AN_IDLE_
BANK parameter is set to 1.
* The DDR_SDRAM_violates_CKE_signal_N check is active on the positive edge of the clock_n

(complementary clock) signal. All other checks are active on the positive edge of the clock signal.
The minimum delay from a read/write with auto precharge command to any command to a
different bank is calculated as shown in Table 6-20.
Table 6-20. Calculate Minimum Delay From a read/Write
From Command
To Command
Minimum Delay in Cycles
Write with AP
Read or Read AP
(BL/2) + tWR +1
Write or Write AP
BL/2
Precharge or Active
Read or Read AP
BL/2
Write or Write AP
CL + (BL/2)
Precharge or Active
Read with AP
BL = burst length
CL = CAS latency rounded up to next integer

Table 6-21 shows the corner cases captured by the DDR SDRAM 2.0 monitor for the protocol.
Table 6-21. DDR SDRAM 2.0 Monitor Corner Cases
Corner Case
Description
Read Commands
Number of read operations from any bank in the DDR SDRAM.
Write Commands
Number of write operations to any bank in the DDR SDRAM.
Precharge Commands
Number of Precharge commands issued to the DDR SDRAM.
Burst Stop Commands
Number of times a Burst Stop command is issued to the DDR SDRAM.
Mode Register Set Commands
Number of times a Mode Register Set command is issued to the DDR

SDRAM.
165

V2.0 Monitor
Table 6-21. DDR SDRAM 2.0 Monitor Corner Cases (cont.)

Corner Case
Description
CBR (auto) Refresh Commands
Number of times a CBR (auto) Refresh is issued to the DDR SDRAM.
Number of times a Self Refresh command is issued to the DDR

SDRAM.
Power Down Commands
Number of times a Power Down command is issued to the DDR

SDRAM.

Commands
Number of times EXTENDED MODE REGISTER SET is issued to

DDR SDRAM.
Precharge all Commands
Number of times PRECHARGE ALL command is issued to DDR

SDRAM.
NOP Commands
Number of times a NOP command is issued to the DDR SDRAM.
Deselect Commands
Number of times the chip select signal (CS_n) of the DDR SDRAM is
de-asserted.
Table 6-22 shows the corner cases captured by the DDR SDRAM 2.0 monitor for each DDR
SDRAM bank.
Table 6-22. DDR SDRAM 2.0 Monitor Corner Cases Maintained for Each Bank
166
Corner Case
Description
Read Commands
Number of read operations from the bank in the DDR SDRAM.
Write Commands
Number of write operations to the bank in the DDR SDRAM.
Read without auto precharge

Commands
Number of read (without auto-precharge) operations from the bank in

the DDR SDRAM.
Read with auto precharge

Commands
Number of read (with auto-precharge) operations from the bank in

the DDR SDRAM.
Write without auto precharge

Commands
Number of write (without auto-precharge) operations from the bank

in the DDR SDRAM.
Write with auto precharge

Commands
Number of write (with auto-precharge) operations from the bank in

the DDR SDRAM.
Number of times a read operation is issued to a page that is already

Number of times a read operation is issued to a page that is already

Number of times a write operation is issued to a page that is already

Number of times a write operation is issued to a page that is already

Precharge Commands
Number of precharge commands issued to the bank.

V2.0 Monitor
Table 6-22. DDR SDRAM 2.0 Monitor Corner Cases Maintained for Each Bank
Corner Case
Description
Burst Operations Terminated
Number times a burst operation to the bank is terminated before it is

completed. This could be due to a Burst Stop command or if another
read or write command to the bank is issued before a current burst
operation is completed.
Monitor Statistics
Table 6-23 shows the corner cases captured by the DDR SDRAM 2.0 monitor for the protocol.
Table 6-23. DDR SDRAM 2.0 Monitor Statistics
Statistic
Description
Active Commands
Number of times any bank in the DDR SDRAM is selected.
Table 6-24 shows the corner cases captured by the DDR SDRAM 2.0 monitor for each DDR
SDRAM bank.
Table 6-24. DDR SDRAM 2.0 Monitor Statistics Maintained for Each Bank
Statistic
Description
Active Commands
Number times the bank in the DDR SDRAM is selected.
167

V2.0 Monitor
168
Chapter 7
Double Data Rate-II SDRAM (DDR-II SDRAM)
Introduction
The QVL Double Data Rate-II SDRAM (DDR-II SDRAM) monitor provides a method of
debugging DDR-II SDRAM system designs by checking that the operation of the design is
compliant with the JEDEC standard.
The DDR-II SDRAM monitor tracks all operations to the DDR-II SDRAM subsystem for a
single row of DDR-II SDRAMs. To check multiple memory rows, the user can instantiate
multiple instances of the DDR-II SDRAM monitor. Each DDR-II SDRAM monitor instance
checks operations on a virtual four-bank DDR-II SDRAM by monitoring the states of each bank
and by setting and relaxing cycle-based timing checks on all operations on the banks.
The DDR-II SDRAM monitor instance determines illegal command sequences by comparing
the bank-state against command issue. Checks for illegal commands and cycle-based timing
problems can be used as formal targets. The user can use formal analysis to find legal stimulus
sequences (that is, corner case behavior) that direct your controller design to violate legal DDRII SDRAM memory subsystem operations.
V1.0 Monitor
This DDR-II SDRAM 1.0 monitor is modeled on the requirements provided in the following
document:
JEDEC Double Data Rate - II (DDR-II) SDRAM Specification, JC 42.3, JEDEC Solid
State Technology Association, December 2000.

For mode register programming, the DDR-II SDRAM 1.0 monitor supports the following:
Burst length 4.
CAS latencies 2, 3, 4, and 5.
169

V1.0 Monitor

For extended mode register programming, the DDR-II SDRAM 1.0 monitor supports the
following:
DLL enable/disable.

To use the DDR-II SDRAM 1.0 monitor, place one instance of the monitor inside the part of the
design (that is, a block of synthesizable code) that can be analyzed by the formal tools. For
example, in a DDR-II SDRAM memory controller chip design that has a DDR-II SDRAM
memory interface for the DDR-II SDRAM memory chips and an application interface for
connecting other controllers, then the monitor should be instantiated inside the DDR-II
SDRAM memory controller design with the port signals connected to the DDR-II SDRAM
memory interface (see Figure 7-1). The user can include instantiations of the DDR-II SDRAM
1.0 monitors in a checker control file.
170

V1.0 Monitor
Figure 7-1. DDR-II SDRAM 1.0 Block Diagram
Address
address
pipe
Control
control
DDR-II SDRAM
Memory
Application
Interface
Controller
DDR-II SDRAM
1.0 Monitor
data
in/out
Data
DDR-II SDRAM Memory Controller
Connect the DDR-II SDRAM 1.0 monitor pins to internal signals of the target design as
specified in the pin-out Table 7-1 and illustrated in Figure 7-2. The clock, reset, and
asynchronous reset signals should be available inside the target design. The remaining signals
can be attached to the outbound control and address signals of the target design.
Figure 7-2. DDR-II SDRAM 1.0 Monitor Pin-Out Diagram
ck
ck_n
reset
areset
cke
cs_n
ras_n
cas_n
we_n
ba[1:0]
a[ROW_ADDR_WIDTH - 1:0]
dm[DM_WIDTH - 1:0]
dq[DATA_BUS_WIDTH - 1:0]
dqs
DDR-II SDRAM
Monitor
171

V1.0 Monitor
Table 7-1. DDR-II SDRAM 1.0 Monitor Pin-Out

Pin
Description
a[ROW_ADDR_WIDTH 1:0]
Address.
areset
ba[1:0]
Bank address.
cas_n
ck
Clock, active edge is the rising edge.
ck_n
Complementary clock, 180 degree out of phase with the clock.
cke
cs_n
dm[DM_WIDTH -1:0]
Data mask line (active high).
dq[DATA_BUS_WIDTH - 1:0]
Data lines.
dqs
Data strobe.
ras_n
reset
we_n
Note that the timing value between a WRITE command and the first dqs latching transition is
called the tdqss value.
In simulation, the monitor uses the dqs signal to latch the dq bus, and it supports tdqss
values from 75% to 125% of the total clock period.
For formal analysis, the DDR-II SDRAM 1.0 monitor does not use the dqs signal to latch data
from the dq bus; instead, the monitor uses the ck/ck_n signals to latch the dq bus. Note that
the monitor assumes the tdqss value to be 100%, which is equal to one clock cycle width.
This indirectly means that during write operation, the designs should drive the dq and dqs
signals such that the dqs transitions are in-line with ck/ck_n transitions.
Also note that in simulation the monitor uses only the dqs signal to latch both odd and even
data from the dq bus, and it does not need the dqs_n in the monitor. That is, the monitor uses
the posedge of dqs to latch odd data from the dq bus, and it uses the negedge of the dqs
signal to latch even data, instead of using the posedge of dqs_n. Similarly, the monitor does not
use ldqs_n, udqs_n, and rdqs_n signals; instead, it uses both edges of ldqs, udqs, and
rdqs, respectively.
172

V1.0 Monitor
DDR-II SDRAMs Stacking

If the memory controller supports n stacked DDR-II SDRAMs (with data widths width and
memory sizes mem), then connect the monitors as follows (see Figure 7-3 and Figure 7-4):
If the memory controller supports n DDR-II SDRAMs stacked by data width (for a
total data width of n x width and memory size mem), then connect only one instance
of the monitor to track the controller.
If the memory controller supports n DDR-II SDRAMs stacked by address width (for a
total data width of width and memory size n x mem), then connect n instances of the
monitor to track the controller.
Use the above scheme also when stacking by both data width and address width.
Figure 7-3. Stacking DDR-II SDRAMs by Data Width
Data
DDR-II SDRAM
Memory Controller
DDR-II SDRAM
Monitor
Address
...
DDR-II SDRAM
Memory #1
DDR-II SDRAM . . .
Memory #2
DDR-II SDRAM
Memory #n
Figure 7-4. Stacking DDR-II SDRAMs by Address Width

Data
DDR-II SDRAM
Memory Controller
DDR-II SDRAM
Monitor
DDR-II SDRAM
Memory #1
Address
DDR-II SDRAM
Memory #2
Address
...
...
DDR-II SDRAM
Monitor
Address
...
DDR-II SDRAM
Monitor
DDR-II SDRAM
Memory #n
173

V1.0 Monitor
Monitor Parameters
The parameters shown in Table 7-2 configures the DDR-II SDRAM 1.0 monitor. Refer to
Table 7-3 on page 176 for the JEDEC standard compliant values of the timing parameters,
which are used as default values.
Table 7-2. DDR-II SDRAM 1.0 Monitor Parameters
174
Order Parameter
Default Description
1.
Constraints_Mode
Set this parameter to 1 if the checks in the monitor are

to be used as constraints for formal analysis.
2.
CONTROLLER_SIDE
Set this parameter to 1 if the monitor is instantiated on

the DDR-II SDRAM controller side. This parameter
and Constraints_Mode parameter configure checks
that are connected to inputs as constraints.
3.
ROW_ADDR_WIDTH
13
Width of the address bus.
4.
DATA_BUS_WIDTH
Width of data bus. Minimum value for this parameter

is 4.
5.
DM_WIDTH
Width of data mask lines. Minimum value for this

parameter is 1.
6.
DLL_TRACKING_ENABLE
Set this parameter to 1 to enable the DLL

enable/disable tracking by the monitor.
7.
TRAS
RAS# active time. Minimum time between an

ACTIVATE and a PRECHARGE command.
8.
TRCD
RAS# to CAS# delay. Minimum time between an

ACTIVATE command and a READ/WRITE
command to that row.
9.
TRP
RAS# precharge command period. Minimum time to

precharge a bank.
10.
TRRD
RAS# to RAS# bank activate delay. Minimum time

between successive ACTIVATE commands to
different banks.
11.
TCCD
CAS# to CAS# delay. Minimum time between

READ/WRITE commands to different banks.
12.
TRTW
Read to Write turn-around-time. Minimum time

required between a READ and WRITE command to
the same bank.
13.
TWTR
Write to Read turn-around-time. The minimum time

between a WRITE and READ command is TWTR +
1+ cas_latency.
14.
TWR
Write recovery time. This is the minimum spacing

between completion of write burst and precharge.
15.
TRFC
10
AUTO REFRESH to ACTIVE / AUTO REFRESH

command time. Minimum time between the AUTO
REFRESH command and an ACTIVE or AUTO
REFRESH command to any bank.

V1.0 Monitor
Table 7-2. DDR-II SDRAM 1.0 Monitor Parameters (cont.)

Order Parameter
Default Description
16.
TXSNR
10
SELF REFRESH to non-READ command time.

Minimum time between the SELF REFRESH
command and any non-READ command to any bank.
17.
TXSRD
200
SELF REFRESH to READ command time. Minimum

time between the SELF REFRESH command and a
READ command to any bank.
18.
TMRD
MODE REGISTER SET command cycle time.

Minimum time for any new command to be issued
after the MODE REGISTER SET command.
19.
AUTOPRECHARGE_
ENABLE_ADDRESS_BIT
10
Selects the address line to use as the auto precharge

enable for READ or WRITE commands and to
distinguish between PRECHARGE and
PRECHARGE ALL commands. By default, A10 is
used.
20.
READ_BEFORE_WRITE_
CHECK_ENABLE
Set this parameter to 0 to disable the READ BEFORE

WRITE check. By default, this check is enabled.
21.
DATA_CHECK_ENABLE
This parameter enables or disables the following data

integrity checks: DDR_SDRAM_bad_data and
checks.

Time is measured in terms of the number of clock cycles.
When constraints mode is not enabled, all checks are used as targets during formal verification.
To use the checks as constraints for formal analysis, do both of the following:

o
If the monitor is instantiated in the DDR-II SDRAM controller, then set

If the monitor is instantiated in the DDR-II SDRAM memory, then set


Name: QVL_DQS_DELAY
175

V1.0 Monitor
Default: 2
Description:
JEDEC Standard Compliant Values of the Timing Parameters

Table 7-3. JEDEC Standard Compliant Timing
Timing Parameter
TRAS
TRCD
TRP
TRRD
TCCD
TRTW
TWTR
TWR
TRFC
10
TXSNR
10
TXSRD
200
TMRD
Example 1
Example 7-1 instantiates a DDR-II SDRAM 1.0 monitor on the DDR-II SDRAM controller
side with ROW_ADDR_WIDTH of 13, DATA_BUS_WIDTH of 8, and DLL_TRACKING_ENABLE set to
1.
176

V1.0 Monitor
Example 7-1. DDR-II SDRAM 1.0 Monitor Instantiation

qvl_ddr2_sdram_monitor
#( 0,
1,
13,
/* ROW_ADDR_WIDTH */
8,
/* DATA_BUS_WITH */
1,
/* DM_WIDTH */
1)
DDR2_SDRAM_MONITOR0 (
.ck
(clock),
.ck_n
(clock_n),
.reset
(reset),
.areset (areset),
.cke
(clock_enable_1),
.cs_n
(chip_select_n_1)
.ras_n, (row_address_strobe_n)
.cas_n, (column_address_strobe_n)
.we_n,
(write_enable_n),
.ba
(bank_address),
.a
(address_bus_13),
.dm
(data_mask_1),
.dq
(data_bus_8),
.dqs
(data_strobe) );
Example 2
Example 7-2 instantiates two instances of the DDR-II SDRAM 1.0 monitor for a DDR-II
SDRAM memory. The example has the following characteristics:
The controller design interfaces two stacked DDR-II SDRAMs, each having 12-bits of
ROW_ADDR_WIDTH (4K address space) and 32-bits of DATA_BUS_WIDTH.
The cs_n, cke, ras_n, cas_n, and we_n signals of width 2-bits each, one for each
DDR-II SDRAM.
Two bank addresses of width 2-bits each, one for each DDR-II SDRAM memory.
The DM_WIDTH of 4, one for each byte of data.

1.
The monitor is instantiated for constrained formal verification. Therefore, the

Constraints_Mode

#( 1,
0,
12,
32,
/* DATA_BUS_WITH */
4,
/* DM_WIDTH */
177

V1.0 Monitor
1)
.ck
(clock),
.ck_n
(clock_n),
.reset
(reset),
.areset (areset),
.cke
(clock_enable_0),
.cs_n
(chip_select_n_0),
.ras_n
(row_address_strobe_n_0),
.cas_n
(column_address_strobe_n_0),
.we_n
(write_enable_n_0),
.ba
(bank_address_0),
.a
(address_bus_12_0),
.dm
(data_mask_4),
.dq
(data_bus_32),
.dqs
(data_strobe) );
#( 1,
0,
12,
32,
/* DATA_BUS_WITH */
4,
/* DM_WIDTH */
1)
.ck
(clock),
.ck_n
(clock_n),
.reset
(reset),
.areset (areset),
.cke
(clock_enable_1),
.cs_n
(chip_select_n_1),
.ras_n
.cas_n
.we_n
(write_enable_n_1),
.ba
(bank_address_1),
.a
(address_bus_12_1),
.dm
(data_mask_4),
.dq
(data_bus_32),
.dqs
(data_strobe) );
Monitor Checks
Table 7-4 shows the checks performed by a DDR-II SDRAM 1.0 monitor.
Table 7-4. Checks Performed by a DDR-II SDRAM 1.0 Monitor
Check ID
Violation
Description
DDR2_SDRAM_ADDITIVE_
LATENCY_INVALID
Invalid Additive latency value

is programmed in the extended
mode register during EMRS
command.
Additive latency values supported are

0, 1, and 2. Any other value is invalid.
Check the additive_latency value
programmed during the last EMRS
command.
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V1.0 Monitor
Table 7-4. Checks Performed by a DDR-II SDRAM 1.0 Monitor (cont.)

Check ID
Violation
Description
DDR2_SDRAM_ADDRESS_
LEVEL
Address lines are not driven to

valid levels.
Checks that address lines are both

known (not X) and driven (not Z). This
check is active only during MRS,
EMRS, Activate and memory Read
and Write commands.
DDR2_SDRAM_AUTO_
REFRESH_PRECHARGE
An auto refresh command is

issued when one or more banks
are not in precharge state.
An auto refresh command can be

issued only when all banks are in
precharged condition.
DDR2_SDRAM_BANK_LEVEL
Bank Address lines are not

driven to valid levels.
Checks that bank address lines are both

known (not X) and driven (not Z). This
check is active only during Precharge,
Activate and memory Read and Write
commands.
DDR2_SDRAM_CAS_LATENCY_
INVALID
Invalid CAS latency value is

CAS latency can be 2, 3, 4, or 5. Any
programmed in the mode
other value is invalid or reserved.
register during MRS command. Check the cas_latency value
programmed during the last MRS
command.
DDR2_SDRAM_CAS_LEVEL
cas_n is not driven to a valid

level.
Checks that CAS_n is both known (not

X) and driven (not Z). This check is
DDR2_SDRAM_CKE_LEVEL
cke is not driven to a valid

level.
Checks that CKE is both known (not

active after the first active edge of the
clock.
DDR2_SDRAM_CONSTRAINTS_
MODE
Constraints_Mode parameter
The value of the CONSTRAINTS_

MODE parameter should be either 1 or
0. It is to be made 1 to make checks as
constraints and 0 to have them as
targets for formal analysis.
DDR2_SDRAM_CONTROLLER_
SIDE
CONTROLLER_SIDE
parameter should be either 1 or
0.
The value of the CONTROLLER_

SIDE parameter should be either 1 or
0.
DDR2_SDRAM_CS_LEVEL
cs_n is not driven to a valid

level.
Checks that CS_n is both known (not

X) and driven (not Z). Active only if
CKE is high.
DDR2_SDRAM_DATA_WIDTH
DATA_BUS_WIDTH
parameter should not be less
The value of the DATA_BUS_

WIDTH parameter should not be
specified to be less than 4.
DDR2_SDRAM_DLL_NOT_RESET
DLL not reset prior to the first

activation command.
If DLL is enabled during the

initialization sequence, then it must be
reset before issuing an activation
command to any bank. This check is
active only if
DLL_TRACKING_ENABLE is 1.
DDR2_SDRAM_DLL_TRACKING
DLL_TRACKING_ENABLE
0.
The value of the

DLL_TRACKING_ENABLE
179

V1.0 Monitor

Check ID
Violation
Description
DDR2_SDRAM_DM_LEVEL
dm is not driven to a valid

level.
Checks that DM is both known (not X)

and driven (not Z). Active only during
write bursts if CKE is high.
DDR2_SDRAM_DM_WIDTH
DM_WIDTH parameter should The value of the DM_WIDTH, which

not be less than the minimum
specifies the data_mask width, should
limit of 1.
not be specified less than 1.
DDR2_SDRAM_INCORRECT_
COMMAND_BEFORE_MRS
An invalid command is issued

before programming the mode
register (only NOP,
DESELECT and
PRECHARGE are valid at this
point).

only commands that are valid before
the Mode register is set. The user
sequencing.
DDR2_SDRAM_INSUFFICIENT_
AUTO_REFRESH_ACTIVATE
Sufficient number (2) of auto

refresh commands are not
issued prior to the first
activation command.
During the initialization sequence, a

minimum of 2 auto refresh commands
should be issued before the first
activation command.
DDR2_SDRAM_MODE_
REGISTER_NOT_SET
Mode register was not

programmed prior to the first
activation command.
Mode register must be configured for

burst type, CAS latency, etc. during
initialization sequence, before the first
activation.
DDR2_SDRAM_MRS_
PRECHARGE
A mode register set command

is issued when one or more
banks are not in precharge
state.
A mode register set command can be

DDR2_SDRAM_RAS_LEVEL
ras_n is not driven to a valid

level.
Checks that RAS_n is both known (not

DDR2_SDRAM_ROW_ADDRESS
ROW_ADDRESS_WIDTH
The value of the ROW_ADDRESS_

WIDTH parameter should not be
specified to be less than 12.
DDR2_SDRAM_SELF_REFRESH_
PRECHARGE
A self refresh command is

A self refresh command can be issued

only when all banks are in precharged
condition.
DDR2_SDRAM_TCCD
TCCD timing parameter should The value of the TCCD timing

limit of 2.
less than 2.
DDR2_SDRAM_TDLL_
VIOLATION_AFTER_DLL_RESET
A Read or Read with

Autoprecharge command is
issued before 200 clock cycles
after DLL reset.
A Mode Register Set command must

be issued for the Mode Register to
reset the DLL and to program the
operating parameters. Once the DLL
reset command is issued, a minimum
of 200 clock cycles are required before
any read command is issued.
DDR2_SDRAM_TMRD
TMRD timing parameter

should not be less than the
minimum limit of 2.

less than 2.
DDR2_SDRAM_TRAS
TRAS timing parameter should

limit of 6.

less than 6.
180

V1.0 Monitor

Check ID
Violation
Description
DDR2_SDRAM_TRCD
TRCD timing parameter should The value of the TRCD timing

limit of 3.
less than 3.
DDR2_SDRAM_TRFC
TRFC timing parameter should

limit of 10.

less than 10.
DDR2_SDRAM_TRP
TRP timing parameter should

limit of 3.
The value of the TRP timing parameter

3.
DDR2_SDRAM_TRRD
TRRD timing parameter should The value of the TRRD timing

limit of 2.
less than 2.
DDR2_SDRAM_TRRD_
VIOLATION
The command issued violates

the tRRD timing between
activation commands to
different banks.

bank. The user should determine why
the commands are too close together.
DDR2_SDRAM_TRTW
TRTW timing parameter

minimum limit of 4.
The value of the TRTW timing

less than 4.
DDR2_SDRAM_TWR
TWR timing parameter should

limit of 3.

less than 3.
DDR2_SDRAM_TWTR
TWTR timing parameter

minimum limit of 2.
The value of the TWTR timing

less than 2.
DDR2_SDRAM_TXSNR
TXSNR timing parameter

minimum limit of 10.

less than 10.
DDR2_SDRAM_TXSRD
TXSRD timing parameter


less than 200.
DDR2_SDRAM_WE_LEVEL
we_n is not driven to a valid

level.
Checks that WE_n is both known (not

Table 7-5 shows the checks for each bank performed by a DDR-II SDRAM 1.0 monitor.
Table 7-5. DDR-II SDRAM 1.0 Monitor Bank Checks
Check ID
Violation
Description
DDR2_SDRAM_ACTIVATE
An ACTIVATE command is
issued to an already open
bank without an intervening
PRECHARGE.
An open bank must be closed before

issuing another activation command to
that bank.
181

V1.0 Monitor
Table 7-5. DDR-II SDRAM 1.0 Monitor Bank Checks (cont.)

Check ID
Violation
Description
DDR2_SDRAM_BAD_DATA
One or more bytes of data

read from the addressed
DDR2 SDRAM location did
not match the data bytes
written to the corresponding
address.
Data read from the DDR2 SDRAM did

not match the data written to the
corresponding address. The data check
is performed only on the reads to
locations that were previously written
at least once. Data checking is done on
a byte basis and the bitmap indicates
the data inconsistency between the
corresponding bytes. The check fires
when at least one byte of read data
does not match the corresponding valid
data byte that was written to that
location.
DDR2_SDRAM_BURST_
ABORTED_P
A read or write is aborted.
In DDR2 SDRAMs, burst interruption

is prohibited. Once a 4-n burst has
started, then it has to be completed
before the start of a new burst.
DDR2_SDRAM_CKE_LOW
CKE is driven low during a

cycle other than self refresh
or power down.
Clock Enable can be driven low only

during self refresh and power down
commands, and it has to be maintained
high during all other cycles.
DDR2_SDRAM_ILLEGAL_
COMMAND_ACT_PWR_DN
An illegal command is issued

when the bank is in Active
Power Down state.
The command just issued is not a legal

command when the bank is in the
Active Power Down state. All the valid
commands from this state are outlined
in the state diagram in the reference
material. The user should trace why an
illegal command is issued.
DDR2_SDRAM_ILLEGAL_
COMMAND_ACTIVE

when the bank is in
ACTIVATE state.

ACTIVATE state. All the valid
DDR2_SDRAM_ILLEGAL_
COMMAND_CBR

when the memory is in
AUTO REFRESH state.

AUTO_REFRESH state. All the valid
DDR2_SDRAM_ILLEGAL_
COMMAND_EMRS
An illegal command is issued The command just issued is not a legal

command when the bank is in
EX_MODE_REG_SET state. EX_MODE_REG_SET state. All the
valid commands from this state are
outlined in the state diagram in the
reference material. The user should
trace why an illegal command is
issued.
DDR2_SDRAM_BURST_
ABORTED_N
182

V1.0 Monitor

Check ID
Violation
Description
DDR2_SDRAM_ILLEGAL_
COMMAND_IDLE

when the bank is in IDLE
state.

command when the bank is in IDLE
state. All the valid commands from this
state are outlined in the state diagram
in the reference material. The user
should trace why an illegal command
is issued.
DDR2_SDRAM_ILLEGAL_
COMMAND_IDLE_PWR_DN

when the bank is in Idle
Power Down state.

IDLE Power Down state. All the valid
DDR2_SDRAM_ILLEGAL_
COMMAND_MRS

MODE_REG_SET
state.

MODE_REG_SET state. All the valid
DDR2_SDRAM_ILLEGAL_
COMMAND_NOP

when the bank is in NOP
state.

SELF_REFRESH state. All the valid
illegal command is issued. For this, the
user can also look at
r_from_state_string.
DDR2_SDRAM_ILLEGAL_
COMMAND_PRE

when the bank is in
PRECHARGE state.

PRECHARGE state. All the valid
DDR2_SDRAM_ILLEGAL_
COMMAND_PRE_ALL

when all banks are in
PRECHARGE state.

PRECHARGE_ALL state. All the
issued.
DDR2_SDRAM_ILLEGAL_
COMMAND_READ

state.

READ state. All the valid commands
from this state are outlined in the state
diagram in the reference material. The
user should trace why an illegal
command is issued.
183

V1.0 Monitor

Check ID
Violation
Description
DDR2_SDRAM_ILLEGAL_
COMMAND_READ_AP

when the bank is in the
READ_AUTO_
PRECHARGE state.

READ_AUTO_PRECHARGE state.
All the valid commands from this state
are outlined in the state diagram in the
issued.
DDR2_SDRAM_ILLEGAL_
COMMAND_SFR

SELF_REFRESH
state.

SELF_REFRESH state. All the valid
DDR2_SDRAM_ILLEGAL_
COMMAND_WRITE

state.

WRITE state. All the valid commands
from this state are outlined in the state
diagram in the reference material. The
user should trace why an illegal
command is issued.
DDR2_SDRAM_ILLEGAL_
COMMAND_WRITE_AP

WRITE_AUTO_
PRECHARGE state.

WRITE_AUTO_PRECHARGE state.
All the valid commands from this state
are outlined in the state diagram in the
issued.
DDR2_SDRAM_PRECHARGE_
TO_IDLE_BANK
A Precharge command is
issued to an idle bank.
A PRECHARGE command was just

issued to an already idle bank.
Although this is not an illegal
operation, it is redundant. The user can
check why redundant commands are
issued.
DDR2_SDRAM_READ_AP_
VIOLATION

the timing between read with
auto precharge and the
activation command issued to
the same bank.
The DDR2 SDRAM starts an auto

precharge operation on the rising edge
that is (AL + BL/2) cycles later than
the read with AP command if tRAS
and tRTP are satisfied. A new bank
activate command may be issued to the
same bank if tRP has been satisfied
from the clock at which auto precharge
begins, and tRC from the previous
bank activation has been satisfied.
DDR2_SDRAM_READ_BEFORE_
WRITE
Data was read from the

address, Bank bank, Row
row, and Column column of
the DDR-II SDRAM that was
not previously written into.
Data was read from the DDR-II

SDRAM from an address that was not
184

V1.0 Monitor

Check ID
Violation
Description
DDR2_SDRAM_READ_TO_IDLE_
BANK
A read command is issued to

an idle bank.
The bank to which the READ

command was just issued is in
precharged idle condition. The user
should determine why a READ
command is issued to an idle bank
without issuing an ACTIVATE
command.
DDR2_SDRAM_TCCD_VIOLATION The command issued violates

the tCCD timing between two
Read/Write commands.

tCCD (CAS to CAS delay timing).
issued too quickly after a
READ/WRITE command for another
DDR2_SDRAM_TCKE_VIOLATION CKE signal should be held at

a valid input level for at least
tCKE clock cycles.
The DDR2 standard specifies that the

CKE signal should be held at valid
input level (either 1 or 0) for a
minimum of three clock cycles. This
check fires if CKE changes its value
within three clock cycles.
DDR2_SDRAM_TMRD_
VIOLATION

the tMRD timing after a
MRS/EMRS command was
issued.
Once a Mode Register Set, or

Extended Mode Register Set command
is issued, there cannot be any
command issued, including another
MRS or EMRS command until TMRD
number of clock cycles expire.
DDR2_SDRAM_TRAS_VIOLATION The command issued violates

the tRAS timing between an
activation and precharge
command.

tRAS (RAS to precharge timing). This
is a PRECHARGE command issued
too quickly after the ACTIVATE
command for this bank. The user
DDR2_SDRAM_TRC_VIOLATION
Once an activation command is issued

to the bank, another activation
command cannot be issued to the same
bank until tRC cycles.

the tRC timing between an
activation command and
another activation command
issued to the same bank.
DDR2_SDRAM_TRCD_VIOLATION The command issued violates

the tRCD timing between an
activation and Read/Write
command.

ACTIVATE command for this bank.
DDR2_SDRAM_TRFC_VIOLATION

tRFC (minimum time delay between
AUTO REFRESH command and any
other command). The new command is
issued too quickly after the AUTO
REFRESH command. The user should
close together.

the tRFC timing between
Auto Refresh and Auto
Refresh/Activate command.
185

V1.0 Monitor

Check ID
Violation
Description
DDR2_SDRAM_TRP_VIOLATION

the precharge command
period (tRP).
The command just issued violates tRP

(RAS precharge timing). This is an
precharge command for this bank. The
DDR2_SDRAM_TRTP_VIOLATION

the tRTP timing between a
Read and Precharge
command.

Read to Precharge delay timing. This is
a PRECHARGE command issued too
quickly after a previous READ
command to the same bank. The
minimum delay should be additive
latency + 2. The user should determine
together.
DDR2_SDRAM_TRTR_VIOLATION The command issued violates

the tRTR timing between two
Read commands.

Read to Read delay timing. This is a
READ command issued too quickly
after a previous READ command to
the same bank. The minimum delay
should be 2 clocks since the 4-n bursts
cannot be interrupted. The user should
close together.
DDR2_SDRAM_TRTW_
VIOLATION

the tRTW timing between a
READ and WRITE
command.

tRTW (Read to Write delay timing).
This is a WRITE command issued too
command to the same bank. The user
DDR2_SDRAM_TWTP_VIOLATION The command issued violates

the tWTP timing between a
Write and Precharge
command.

Write to Precharge delay timing. This
is a PRECHARGE command issued
too quickly after a previous WRITE
minimum delay should be WL (write
latency) + TWR (write recovery time)
+ 2. The user should determine why
DDR2_SDRAM_TWTR_
VIOLATION

Write to Read delay timing. This is a
READ command issued too quickly
after a previous WRITE command to
should be tWTR (write to read turnaround-time) + CAS latency + 1. The
186

the tWTR timing between a
Write and Read command.

V1.0 Monitor

Check ID
Violation
Description
DDR2_SDRAM_TWTW_
VIOLATION

the tWTW timing between
two Write commands.

Write to Write delay timing. This is a
WRITE command issued too quickly
after a previous WRITE command to
should be 2 clocks since the 4-n bursts
cannot be interrupted. The user should
close together.
DDR2_SDRAM_TXSNR_
VIOLATION

the tXSNR timing required
between a Self Refresh Exit
and a Non-Read command.

tXSNR (minimum time delay between
SELF REFRESH EXIT command and
any other non-READ command)
timing. A non-READ command is
issued too quickly after the SELF
REFRESH EXIT command. The user
DDR2_SDRAM_TXSRD_
VIOLATION

the tXSRD timing between a
Self Refresh Exit and a Read
command.

violates tXSRD (minimum time delay
command and a READ command)
timing. A READ command is issued
too quickly after the SELF REFRESH
close together.
DDR2_SDRAM_UNKNOWN_
STATE
The bank state machine went

to UNKNOWN_STATE.
The command just issued has caused

the monitor state machine to go to an
UNKNOWN state. This can be due to
an illegal command. The user should
look at the state machine transitions
and check as to why it entered this
state.
DDR2_SDRAM_WRITE_TO_IDLE_
BANK
A write command is issued to

an idle bank.
The bank to which the WRITE

should determine why a WRITE
command.

Table 7-6 shows the corner cases captured by the DDR-II SDRAM 1.0 monitor for the protocol.
Table 7-6. DDR-II SDRAM 1.0 Monitor Corner Cases
Corner Case
Description
Multiple Banks Activation
Number of times more than one bank is in the activated state.
187

V1.0 Monitor
Table 7-6. DDR-II SDRAM 1.0 Monitor Corner Cases (cont.)

Corner Case
Description
Precharge All Banks
Number of Precharge All commands issued to the DDR-II SDRAM.
CBR Refresh Commands
Number of times CBR Auto Refresh commands are issued.
Interleaved Bursts
Number of times Mode Register is programmed for Interleaved burst.
Sequential Bursts
Number of times Mode Register is programmed for Sequential burst.
Number of times Self Refresh command is issued.
Power Down Commands
Number of times Power Down command is issued.
NOP Commands
Number of times NOP command is issued.
Deselect Commands
Number of times Deselect command is issued.
Table 7-7 shows the corner cases captured by the DDR-II SDRAM 1.0 monitor for the DDR-II
SDRAM banks.
Table 7-7. DDR-II SDRAM 1.0 Bank Corner Cases
Corner Case
Description
Reads Without Precharge
Number of read without precharge commands issued to a bank.
Writes Without Precharge
Number of write without precharge commands issued to a bank.
Single Bank Precharges
Number of single bank Precharge commands issued to a bank.
Seamless Reads
Number of times a Read is immediately followed by another Read from the

same bank.
Seamless Writes
Number of times a Write is immediately followed by another Write to the

same bank.
Reads with Precharge
Number of times Read with Auto Precharge operation is performed to a

bank.
Writes with Precharge
Number of times Write with Auto Precharge operation is performed to a

bank.
Posted Reads
Number of times Posted Read cycles are exercised.
Posted Writes
Number of times Posted Write cycles are exercised.
Number of times a read operation is issued to a page that is already opened

for read in the bank.
Number of times a read operation is issued to a page that is already opened

for write in the bank.
Number of times a write operation is issued to a page that is already opened

for read in the bank.
Number of times a write operation is issued to a page that is already opened

for write in the bank.
188

V1.0 Monitor
Monitor Statistics
Table 7-8 lists the statistics collected for the protocol.
Table 7-8. DDR-II SDRAM 1.0 Monitor Statistics
Statistic
Description
Total Number of Memory Accesses
Total number of data accesses to the DDR-II SDRAM for all banks.
Table 7-9 lists the statistics collected for each bank.

Table 7-9. DDR-II SDRAM 1.0 Bank Statistics
Statistic
Description
Total Number of Bank Accesses
Total number of times a bank is activated and data accesses performed on the
bank.
189

V2.0 Monitor
V2.0 Monitor
This DDR-II SDRAM 2.0 monitor is modeled on the requirements provided in the following
document:
JESD79-2 DDR2 SDRAM Specification, JEDEC Solid State Technology Association,

September 2003.
JEDEC Double Data Rate - II (DDR-II) SDRAM Specification, JC 42.3, JEDEC Solid
State Technology Association, December 2000.
JEDEC Standard, Double Data Rate-II (DDR) Specification, JESD79-2C, JEDEC Solid
State Technology Association, May 2006.

For mode register programming, the DDR-II SDRAM 2.0 monitor supports the following:
Burst length 4 and 8.
CAS latencies 2, 3, 4, 5, and 6.
Write recovery for auto precharge.
Active power down exit time.
EMRS2 and EMR3 programming (Extended Mode Register Set commands).
On-die-termination (ODT) 50 Ohm restriction.
Off-chip driver (OCD) calibration cycles.
Clock frequency change.
The DDR-II SDRAM 2.0 monitor does not support the following:

For extended mode register programming, the DDR-II SDRAM 2.0 monitor supports the
following:
190

V2.0 Monitor
DLL enable/disable.
Additive latencies of 0, 1, 2, 3, and 4.
RDQS using the DM pin as read data strobe for x8 configuration.
Strobe function matrix.
The DDR-II SDRAM 2.0 monitor does not support the following:

The DDR-II SDRAM 2.0 monitor can be used in cases when you want to bypass the
initialization sequence. The BYPASS_INIT parameter sets this mode of operation as follows:
Normal mode.
By default (BYPASS_INIT=0), the monitor tracks the initialization sequence. In this
mode, the monitor validates the requirements described in the JEDEC specification
during the initialization sequence. For example, in the normal mode of operation, the
monitor fires if it does not detect an EMRS(2) command followed by an EMRS(3)
command.
In the normal mode of operation, the monitor tracks the MRS and EMRS commands and
configures itself accordingly. The monitor ports mode_register_in and
ex_mode_register_in can be left unconnected.

The user can configure the monitor into the initialization bypass mode by setting the
BYPASS_INIT parameter to 1. In this mode, the monitor does not validate the
requirements described in the JEDEC specification during the initialization sequence
and does not track the MRS and EMRS commands. However, for proper operation, the
monitor requires the information regarding the mode register settings. The mode-related
information must be passed through the monitor ports mode_register_in and
ex_mode_register_in. Be sure that the values passed to these ports reflect the actual
mode register setting in the DDR-II SDRAM memory.

To use the DDR-II SDRAM 2.0 monitor, place one instance of the monitor inside the part of the
design (that is, a block of synthesizable code) that can be analyzed by the formal tools. For
example, in a DDR-II SDRAM memory controller chip design that has a DDR-II SDRAM
memory interface for the DDR-II SDRAM memory chips and an application interface for
connecting other controllers, then the monitor should be instantiated inside the DDR-II
191

V2.0 Monitor
SDRAM memory controller design with the port signals connected to the DDR-II SDRAM
memory interface (see Figure 7-5). The user can include instantiations of the DDR-II SDRAM
2.0 monitors in a checker control file.
Figure 7-5. DDR-II SDRAM 2.0 Block Diagram
Address
address
pipe
Control
control
DDR-II SDRAM
Memory
Application
Interface
Controller
DDR-II SDRAM
2.0 Monitor
Data
data
in/out
DDR-II SDRAM Memory Controller
Connect the DDR-II SDRAM 2.0 monitor pins to internal signals of the target design as
specified in the pin-out Table 7-10 and illustrated in Figure 7-6. The clock, reset, and
asynchronous reset signals should be available inside the target design. The remaining signals
can be attached to the outbound control and address signals of the target design.
192

V2.0 Monitor
Figure 7-6. DDR-II SDRAM 2.0 Monitor Pin-Out Diagram

ck
ck_n
reset
areset
cke
cs_n
ras_n
cas_n
we_n
ba[1:0]
ba[BANK_ADDR_WIDTH - 1:0]
a[ROW_ADDR_WIDTH - 1:0]
dm_rdqs
dq
dqs
ldqs
ldm
udqs
udm
mode_register_in
ex_mode_register_in
odt
tras_inp
trcd_inp
trp_inp
trrd_inp
tccd_inp
trtw_inp
twtr_inp
twr_inp
trfc_inp
txsnr_inp
txsrd_inp
tmrd_inp
txp_inp
txard_inp
DDR-II SDRAM
Monitor
193

V2.0 Monitor
Table 7-10. DDR-II SDRAM 2.0 Monitor Pin-Out
194
Pin
Description
a[ROW_ADDR_WIDTH 1:0]
Address.
areset
ba[BANK_ADDR_WIDTH-1:0]
Bank address.
cas_n
ck
Clock, active edge is the rising edge.
ck_n
Complementary clock, 180 degree out of phase with the clock.
cke
cs_n
dm_rdqs
Data mask for port dq / Read data strobe (only in x8 mode).
dq
Data bus.
dqs
Data strobe for port dq.
ex_mode_register_in
Extended mode register input. Leave this port unconnected if

BYPASS_INIT=0. The width of this register is equal to
ADDR_WIDTH + BANK_ADDR_WIDTH. This width reflects the
actual width of the mode register in the DDR-II SDRAM memory.
ldm
Data mask for port {dq7:dq0}.
ldqs
Data strobe for {dq7:dq0}.
mode_register_in
Mode register input. Leave this port unconnected if BYPASS_INIT=0.

The width of this register is equal to ADDR_WIDTH +
BANK_ADDR_WIDTH. This width reflects the actual width of the
mode register in the DDR-II SDRAM memory.
odt
On-die-termination.
ras_n
reset
tccd_inp[31:0]
Port for tCCD timing input. This input is valid only when
tmrd_inp[31:0]
Port for tMRD timing input. This input is valid only when
tras_inp[31:0]
Port for tRAS timing input. This input is valid only when
trcd_inp[31:0]
Port for tRCD timing input. This input is valid only when
trfc_inp[31:0]
Port for tRFC timing input. This input is valid only when
trp_inp[31:0]
Port for tRP timing input. This input is valid only when

V2.0 Monitor
Table 7-10. DDR-II SDRAM 2.0 Monitor Pin-Out (cont.)

Pin
Description
trrd_inp[31:0]
Port for tRRD timing input. This input is valid only when
trtw_inp[31:0]
Port for tRTW timing input. This input is valid only when
twr_inp[31:0]
Port for tWR timing input. This input is valid only when
twtr_inp[31:0]
Port for tWTR timing input. This input is valid only when
txard_inp[31:0]
Port for tXARD timing input. This input is valid only when
txp_inp[31:0]
Port for tXP timing input. This input is valid only when
txsnr_inp[31:0]
Port for tXSNR timing input. This input is valid only when
txsrd_inp[31:0]
Port for tXSRD timing input. This input is valid only when
udm
Data mask for port {dq15:dq8}.
udqs
Data strobe for port {dq15:dq8}.
we_n
The timing value between a WRITE command and the first dqs latching transition is called the
tdqss value.
In simulation, the monitor uses the dqs signal to latch the dq bus, and it supports tdqss
values from 75% to 125% of the total clock period.
For formal analysis, the DDR-II SDRAM 2.0 monitor does not use the dqs signal to latch data
from the dq bus; instead, the monitor uses the ck/ck_n signals to latch the dq bus. Note that
the monitor assumes the tdqss value to be 100%, which is equal to one clock cycle width.
This indirectly means that during write operation, the designs should drive the dq and dqs
signals such that the dqs transitions are in-line with the ck/ck_n transitions.
Also note that in simulation the monitor uses only the dqs signal to latch both odd and even
data from the dq bus, and it does not need the dqs_n in the monitor. That is, the monitor uses
the posedge of dqs to latch odd data from the dq bus, and it uses the negedge of the dqs
signal to latch even data, instead of using the posedge of dqs_n. Similarly, the monitor does not
use ldqs_n, udqs_n, and rdqs_n signals; instead, it uses both edges of ldqs, udqs, and
rdqs, respectively.
In x8 mode, if RDQS is enabled, then the DM pin can be used as the read data strobe, RDQS. In
this case, the DM function is disabled for x8 writes. Therefore, if operating in x8 configuration
and RDQS is enabled, connect DQS to DM. For writes, DQS is the data strobe and for reads RDQS
(using the DM pin) is the data strobe. DQ is the data bus for both operations.
195

V2.0 Monitor
The x4 and x16 configurations are not affected by the RDQS function of the DM pin. In x16
mode, LDQS corresponds to the data on DQ0-DQ7 and UDQS corresponds to the data on
DQ8-DQ15. The corresponding data masks are LDM and UDM.
Monitor Parameters
The parameters shown in Table 7-11 configure the DDR-II SDRAM 2.0 monitor. Refer to
Table 7-12 for the JEDEC standard compliant values of the timing parameters, which are used
as default values.
Table 7-11. DDR-II SDRAM 2.0 Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode
Set this parameter to 1 if the checks in the monitor are to

be used as constraints for formal analysis.
2.
CONTROLLER_SIDE

the DDR-II SDRAM controller side. This parameter and
Constraints_Mode parameter configure checks that are
connected to inputs as constraints.
3.
ROW_ADDR_WIDTH
16
Width of the address bus.
4.
DATA_BUS_WIDTH
Width of data bus. Use this parameter to set the data bus
configuration to x4, x8, or x16. These are the only valid
values of this parameter.
5.
DLL_TRACKING_ENABLE
Set this parameter to 1 to enable the DLL enable and

disable tracking by the monitor.
6.
TRAS
RAS# active time (minimum time between an

ACTIVATE and a PRECHARGE command).
This parameter is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 0,
which is the default value of the parameter
USE_PORTS_TO_CONFIGURE.
7.
TRCD
RAS# to CAS# delay (minimum time between an

ACTIVATE command and a READ/WRITE command
to that row). This parameter is valid only when the
8.
TRP
RAS# precharge command period (minimum time to

precharge a bank). This parameter is valid only when the
9.
TRRD
RAS# to RAS# bank activate delay (minimum time

between successive ACTIVATE commands to different
banks). This parameter is valid only when the
196

V2.0 Monitor

Order Parameter
Default Description
10.
TCCD
CAS# to CAS# delay (minimum time between

READ/WRITE commands to different banks).
11.
TRTW
Read to Write turn-around-time (minimum time required

between a READ and WRITE command to the same
bank). This parameter is valid only when the
12.
TWTR
Write to Read turn-around-time. The minimum time

between a WRITE and READ command is TWTR + 1 +
cas_latency. This parameter is valid only when the
13.
TWR
Write recovery time. This is the minimum spacing

between completion of write burst and precharge.
14.
TRFC
AUTO REFRESH to ACTIVE / AUTO REFRESH

command time (minimum time between AUTO
REFRESH command and an ACTIVE or AUTO
REFRESH command to any bank). This parameter is
valid only when the USE_PORTS_TO_CONFIGURE
parameter is set to 0, which is the default value of the
parameter USE_PORTS_TO_CONFIGURE.
15.
TXSNR
10

(minimum time between SELF REFRESH command and
any non-READ command to any bank). This parameter
is valid only when the USE_PORTS_TO_CONFIGURE
16.
TXSRD
200
SELF REFRESH to READ command time (minimum

time between SELF REFRESH command and a READ
command to any bank). This parameter is valid only
when the USE_PORTS_TO_CONFIGURE parameter is
set to 0, which is the default value of the parameter
17.
TMRD
MODE REGISTER SET command cycle time (minimum

time for any new command to be issued after the MODE
REGISTER SET command). This parameter is valid only
when the USE_PORTS_TO_CONFIGURE parameter is
set to 0, which is the default value of the parameter
18.
AUTOPRECHARGE_
ENABLE_ADDRESS_BIT
10
Selects the address line to use as the auto precharge

enable for READ or WRITE commands and to
distinguish between PRECHARGE and PRECHARGE
ALL commands. By default, A10 is used.
197

V2.0 Monitor

Order Parameter
Default Description
19.
READ_BEFORE_WRITE_
CHECK_ENABLE
Set this parameter to 0 to disable the READ BEFORE

WRITE check. By default, this check is enabled.
20.
TXP
Precharge power down exit to nonread latency, in

number of clocks. This parameter is valid only when the
21.
TXARD
Active power down exit, with fast exit to a read

command latency, in number of clocks. This parameter is
valid only when the USE_PORTS_TO_CONFIGURE
22.
BANK_ADDR_WIDTH
Configures the Bank Address line width. Configure this

parameter with the value 2 to track designs with 4 banks.
Configure with the value 3 to track designs with 8 banks.
The maximum allowed value is 3.
23.
ENABLE_PRECHARGE_
TO_IDLE_BANK
Set this parameter to include the check to fire on multiple

precharge commands to a bank that is already in idle
condition. By default, this check is turned off.
24.
BYPASS_INIT

sequence. If this parameter is set to 1, then the complete
initialization sequence need not be performed.
Nevertheless, valid operational values must be passed to
the mode register/extended mode register inputs, failing
which the monitor behavior is undefined. By default, the
monitor requires the proper initialization sequence to be
performed as described in the JEDEC specification.
25.
DATA_CHECK_ENABLE
This parameter enables or disables the following data

integrity checks: DDR_SDRAM_bad_data and
Set this parameter to 1 to enable the data integrity checks.
Setting to 0 removes the checks by completely removing
the data-checker module, qvl_ddr_sdram_data_checker.
26.
OPTIONAL_ADDITIVE_
LATENCY_ENABLE
If optional additive latency is supported to enable

verification of setting of the same while programming
EMR(1), then set this parameter to 1.
27.
IMPEDANCE_
CALIBRATION_CHECKS_
ENABLE
Set this parameter to 1 if OCD impedance calibration is

supported.
28.
PARTIAL_SELF_
REFRESH_ENABLE
Set this parameter to 1 if partial Self Refresh related

values need to be verified in EMR programming while
initializing DDR2 SDRAM.
29.
DUTY_CYCLE_
CONTROL_ENABLE
Set this parameter to if clock duty cycle control is

supported and related initialization values need to be
verified during EMR programming.
30.
DDR2_SPEED_GRADE
400
This parameter is used to enable any speed grade specific

checks. For example, ODT value of 50 ohms for speed
grade 800 setting while EMRS1 is programming.
198

V2.0 Monitor

Order Parameter
Default Description
31.
HIGH_TEMP_SELF_
REFRESH_RATE_ENABLE
Set this parameter to 1 to switch on checking of the high

temperature Self Refresh bit setting during EMR(2)
programming.
32.
CLOCK_CHANGE_
TRACKING_ENABLE
Set this parameter to 1 to enable support of the change of

input clock frequency on the fly as per JESD79-2C May
2005 specification update.
33.
TCLK_CHECK_ENABLE
Set this parameter to 1 to enable checking for minimum

clock cycles to be lapsed before the clock frequency can
change after CKE is sampled LOW. This parameter is
valid only when the parameter
CLOCK_CHANGE_TRACKING_ENABLE is set to 1.
34.
TCLK
Represents the value for minimum cycles to be lapsed

before the clock frequency can change in precharge
power down mode after clock enable signal (CKE) is
sampled LOW. This parameter is valid only when the
parameter CLOCK_CHANGE_TRACKING_ENABLE
is set to 1.
35.
CLOCK_FREQUENCY_
RANGE_CHECK_ENABLE
Set this parameter to 1 to enable checking for the clock

frequency if it is within allowed ranges, which is
specified by the other set of parameters
CLOCK_PERIOD_MAX and CLOCK_PERIOD_MIN.
This parameter is valid only when the parameter
CLOCK_CHANGE_TRACKING_ENABLE is set to 1.
36.
CLOCK_PERIOD_MAX
2500
Set the highest allowed clock period specified in

picoseconds (ps), which is a measure of the lowest clock
frequency supported by the DDR2 SDRAM. The default
value is set to 2500 (ps). The default value means a
supported clock of 400 MHz, which is the slowest clock
supported for DDR2 SDRAM as per JESD79-2C. The
user can alter this value for non-JEDEC applications.
37.
CLOCK_PERIOD_MIN
1250
Set the lowest allowed clock period specified in

picoseconds (ps), which is a measure of the lowest clock
frequency supported by the DDR2 SDRAM. The default
value is set to 1250 (ps). The default value means a
supported clock of 800 MHz, which is the fastest clock
supported for DDR2 SDRAM as per JESD79-2C. The
user can alter this value for non-JEDEC applications.
38.
USE_PORTS_TO_
CONFIGURE
Set this parameter to 1 to enable the usage of the input

ports to configure the various timing parameter values.
By default, the monitor uses the defined JEDEC values.

the checks as constraints for formal analysis, do both of the following:
199

V2.0 Monitor
o
If the monitor is instantiated in the DDR-II SDRAM controller, then set

If the monitor is instantiated in the DDR-II SDRAM memory, then set


Name: QVL_DQS_DELAY
Default: 2
Description:
200

V2.0 Monitor
JEDEC Standard Compliant Values of the Timing Parameters

Table 7-12. JEDEC Standard Compliant Timing for DDR2 400 Speed Grade
Timing Parameter
TRAS
TRCD
TRP
TRRD
TCCD
TRTW
TWTR
TWR
TRFC
TXSNR
10
TXSRD
200
TMRD
TXP
TXARD
TCLK
Time is measured by an integer number of clock cycles obtained by dividing the absolute
AC timing parameter by tCK (clock period) and rounding off to the nearest integer.
Example 1
Example 7-3 instantiates a DDR-II SDRAM 2.0 monitor on the DDR-II SDRAM controller
side with ROW_ADDR_WIDTH of 16, DATA_BUS_WIDTH of 8, and DLL_TRACKING_ENABLE set to
1. The timing parameters are the default values specified by JEDEC. The monitor is instantiated
with BYPASS_INIT = 1. Internal signals are connected to the monitor ports
mode_register_in and ex_mode_register_in.
qvl_ddr2_sdram_2_0_monitor
#( 1,
1,
16,
8,
/* DATA_BUS_WITH */
1,
6,
/* TRAS */
201

V2.0 Monitor
2,
2,
1,
2,
4,
1,
2,
9,
10,
200,
2,
10,
1,
2,
2,
3,
0,
1,
1,
1,
0,
1,
/* TRCD */
/* TRP */
/* TRRD */
/* TCCD */
/* TRTW */
/* TWTR */
/* TWR */
/* TRFC */
/* TXSNR */
/* TXSRD */
/* TMRD */
/* AUTOPRECHARGE_ENABLE_ADDRESS_BIT*/
/* TXP */
/* TXARD */
/* BANK_ADDR_WIDTH */
/* ENABLE_PRECHARGE_TO_IDLE_BANK */
/* BYPASS_INIT */
/* ZI_DDR2_SDRAM_2_0 */
/* ZI_DM_WIDTH */
/*OPTIONAL_ADDITIVE_LATENCY_ENABLE*/
/*IMPEDANCE_CALIBRATION_CHECKS_ENABLE*/ // OCD Calibration
// enabled
0,
/* PARTIAL_SELF_REFRESH_ENABLE*/
0,
/*DUTY_CYCLE_CONTROL_ENABLE*/
800,
/*DDR2_SPEED_GRADE*/
0,
/*HIGH_TEMP_SELF_REFRESH_RATE_ENABLE*/
0,
/* CLOCK_CHANGE_TRACKING_ENABLE */
0,
/* TCLK_CHECK_ENABLE */
2,
/* TCLK*/
0,
/* CLOCK_FREQUENCY_RANGE_CHECK_ENABLE*/
2500,
1250)
.ck
(clock),
.ck_n
(clock_n),
.reset
(reset),
.areset
(areset),
.cke
(clock_enable_1),
.cs_n
(chip_select_n_1),
.ras_n
.cas_n
.we_n
(write_enable_n),
.ba
(bank_address),
.a
(address_bus_16),
.dm
(data_mask_1),
.dq
(data_bus_8),
.dqs
(data_strobe)
.ldqs
(1'b0),
.ldm
(1'b0)
.udqs
(1'b0),
.udm
(1'b0),
.mode_register_in
(internal_mode_register),
.ex_mode_register_in (internal_ex_mode_register), // If any
.odt(odt) ); // On-die-termination
202

V2.0 Monitor
Example 2
Example 7-4 instantiates two instances of the DDR-II SDRAM 2.0 monitor for a DDR-II
SDRAM memory. The example has the following characteristics:
The controller design interfaces two stacked DDR-II SDRAMs, each having 12-bits of
ROW_ADDR_WIDTH (4K address space) and 16-bits of DATA_BUS_WIDTH.
The cs_n, cke, ras_n, cas_n, and we_n signals of width 2-bits each, one for each
DDR-II SDRAM.
Two bank addresses of width 2-bits each, one for each DDR-II SDRAM memory.

1.
The monitor is instantiated for constrained formal verification. Therefore, the

Mode register and extended mode register ports are left unconnected.
#( 1,
0,
12,
16)
/* DATA_BUS_WITH */
.ck
(clock),
.ck_n
(clock_n),
.reset
(reset),
.areset
(areset),
.cke
(clock_enable_0),
.cs_n
(chip_select_n_0),
.ras_n
.cas_n
.we_n
(write_enable_n_0),
.ba
(bank_address_0),
.a
(address_bus_12_0),
.dm_rdqs
(1'b0),
.dq
(upper_data_byte_0,lower_data_byte_0),
.dqs
(1'b0)
.ldqs
(lower_data_strobe_0),
.ldm
(lower_data_mask_0),
.udqs
(upper_data_strobe_0),
.udm
(upper_data_mask_0),
.mode_register_in
(),
.ex_mode_register_in
(),
#( 1,
203

V2.0 Monitor
0,
12,
16)
/* DATA_BUS_WITH */
.ck
(clock),
.ck_n
(clock_n),
.reset
(reset),
.areset
(areset),
.cke
(clock_enable_1)
.cs_n
(chip_select_n_1),
.ras_n
.cas_n
.we_n
(write_enable_n_1),
.ba
(bank_address_1),
.a
(address_bus_12_1),
.dm_rdqs
(1'b0),
.dq
(upper_data_byte_1,lower_data_byte_1),
.dqs
(1'b0)
.ldqs
(lower_data_strobe_1),
.ldm
(lower_data_mask_1),
.udqs
(upper_data_strobe_1),
.udm
(upper_data_mask_1),
.mode_register_in
(),
.ex_mode_register_in
(),
Monitor Checks
Table 7-13 shows the checks performed by a DDR-II SDRAM 2.0 monitor.
Table 7-13. DDR-II SDRAM 2.0 Monitor Checks
Check ID
Violation
Description
A_DDR2_SDRAM_ILLEGAL_
RESERVED_STATES_IN_EMR1
Bits BA2 and A13-A15 are

reserved for future use, and
they must be set to 0 when
programming EMR1.
Reserved bit fields in the extended

mode register 1 must be set to 0 during
initialization. This check fires if the
reserved bits are not set to 0 during
EMR1 programming.
OCD_VALUE_FOR_DDR2_800_
EMR1
Incorrect programming for bits

A2 and A6 in the EMR1 for
DDR2 SDRAM speed grade
800.
For DDR2 SDRAM with speed grade

800 Mhz, it is a mandatory
requirement that during initialization
extended mode register 1 must be
programmed to reflect a 50 ohm
impedance against the setting of bits
A2 and A6. The requirement is that
both of these bits are set HIGH for
this. If any of these two bit settings
violates this requirement for such an
DDR2 SDRAM, then this check fires.
This check is functional only when the
parameter DDR2_SPEED_GRADE is
set to 800.
204

V2.0 Monitor
Table 7-13. DDR-II SDRAM 2.0 Monitor Checks (cont.)

Check ID
Violation
Description
Bits BA2, A4-A6, and A8A15 are reserved for future use,
and they must be set to 0 when
programming EMR2.
Reserved bit fields in the extended

mode register 2 must be set to 0 during
initialization. This check fires if the
reserved bits are not set to 0 during
EMR2 programming.
HTSRR_BIT_STATE_IN_EMR2
When high temperature Self

Refresh is not supported, the
respective bit in EMR2
programming should be set to
0.
The parameter HIGH_TEMP_SELF_

REFRESH_RATE_ENABLE enables
or disables high temperature Self
Refresh support. This check fires
when this parameter is set to 0
reflecting a non-supported model for
this feature, but EMR2 is programmed
incorrectly with a nonzero value in the
respective bit A7. This check is
HIGH_TEMP_SELF_REFRESH_
RATE_ENABLE is set to 0.
PASR_BIT_STATES_IN_EMR2
When partial Self Refresh is

not supported, the pasr bits
should always be set to 0s to
represent full page access
during EMR2 programming.
The parameter PARTIAL_SELF_

REFRESH_ENABLE enables or
disables partial array Self Refresh
support. This check fires when this
parameter is set to 0 reflecting a nonsupported model for this feature, but
EMR2 is programmed incorrectly
with a nonzero value in the respective
bits A2-A0. This check is functional
PARTIAL_SELF_REFRESH_
ENABLE is set to 0.
DCC_BIT_STATE_IN_EMR2
When duty cycle control is not

supported, the relevant bit
should always be set to 0
The parameter DUTY_CYCLE_

CONTROL_ENABLE enables or
disables duty cycle control of the
clock. This check fires when this
parameter is set to 0 reflecting a nonsupported model for this feature, but
EMR2 is programmed incorrectly
with a nonzero value in the respective
bit A3. This check is functional only
when the parameter DUTY_CYCLE_
CONTROL_ENABLE is set to 0.
Bits BA2 and A0-A15 are

reserved for future use, and
they must be set to 0 when
programming EMR3.
Except for bits BA0 and BA1, all

other bits in extended mode register 3
are reserved for future use. Reserved
bit fields in EMR3 must be set to 0
during initialization. This check fires
if the reserved bits are not set to 0
A_DDR2_SDRAM_ODT_
VIOLATION_DURING_DLL_
STABILIZATION
ODT should be LOW while

DLL is within its lock period.
The on-die-termination signal input

ODT should be driven LOW while
DLL is within its lock period. This
check fires when ODT is sampled
with a value other than 0 during the
DLL lock period.
205

V2.0 Monitor

Check ID
Violation
Description
A_DDR2_SDRAM_FIRST_
EMRS_NOT_ISSUED_WITH_
OCD_EXIT
First EMR command during

initialization should be issued
with OCD exit mode.
During initialization sequence, when

the very first EMR set command is
issued, it should have OCD mode
settings as exit mode. This check
monitors this requirement.
A_DDR2_SDRAM_EMRS2_IS_
NOT_ISSUED_AFTER_FIRST_
PRECHARGE_ALL
EMR2 set command is not

issued after the first precharge
all.
During initialization sequence, the

first precharge all command must be
followed by an EMR2 set command.
This check monitors this requirement.
A_DDR2_SDRAM_OCD_
DEFAULT_CALIBRATION_NOT_
SET_AFTER_SECOND_MRS
OCD default calibration mode

is not set after the second MRS
during initialization.
During initialization sequence, after

the second MRS command, there
should follow a OCD default
calibration mode entry. This check
monitors this requirement.
A_DDR2_SDRAM_INVALID_BL_
BEFORE_ENTERING_OCD_
ADJUST_MODE
The burst length is not set to 4

before OCD adjust mode entry
During initialization, before off-chip

driver (OCD) impedance adjustment,
the burst length must be set to 4 by an
MSR command. Failing to set this
accordingly will trigger this check.
parameter IMPEDANCE_
CALIBRATION_CHECKS_
ENABLE is set to 1.
A_DDR2_SDRAM_OCD_
DRIVE0_MODE_NOT_
FOLLOWED_BY_OCD_CALI_
EXIT_MODE
OCD drive0 mode is not

followed by OCD calibration
exit during initialization.
Every OCD mode must be followed

by an OCD calibration mode exit. This
check fires if OCD drive0 mode is not
followed by OCD calibration mode
exit. This check is functional only
when the parameter
IMPEDANCE_CALIBRATION_
CHECKS_ENABLE is set to 1.
A_DDR2_SDRAM_OCD_
DRIVE1_MODE_NOT_
EXIT_MODE
OCD drive1 mode is not


check fires if OCD drive1 mode is not
when the parameter
A_DDR2_SDRAM_OCD_
ADJUST_MODE_NOT_
EXIT_MODE
OCD adjust mode is not


check fires if OCD adjust mode is not
when the parameter
206

V2.0 Monitor

Check ID
Violation
Description
DQ_DQS_IN_OCD_DRIVE0_
MODE
The data and data strobe

signals are not driven LOW
while in OCD drive0 mode

LOW. This check fires when the
DDR2 SDRAM clock changes while
the DDR2 SDRAM is not operating in
idle or precharge power down mode.
DQ_DQS_IN_OCD_DRIVE1_
MODE
The data and data strobe

signals are not driven HIGH in
OCD drive1 mode during
initialization.

LOW. This check fires when the
DDR2 SDRAM clock changes while
CKE is not LOW. This check is
ENABLE is set to 1.
LATENCY_INVALID
Invalid Additive latency value

is programmed in the extended
mode register during the
EMRS command.

BYPASS_INIT is 0 (i.e., normal
initialization sequence). Supported
additive latency values are 0, 1, 2, 3,
and 4. Any other value is invalid.
Check the additive_latency value
programmed during the last EMRS
command.
LATENCY_INVALID_BYPASS
The additive latency field of

the input extended mode
register is invalid.

value is passed to the
ex_mode_register_in input. Supported
additive latency values are 0, 1, 2, 3,
and 4. Any other value is invalid. This
check fires if an additive latency value
passed through the
ex_mode_register_in input.
DDR2_SDRAM_ADDRESS_
LEVEL
Address lines are not driven to

valid levels.
Checks that address lines are both

known (not X) and driven (not Z).
This check is active only during MRS,
EMRS, Activate and memory Read ad
Write commands.
DDR2_SDRAM_AUTO_
REFRESH_PRECHARGE
An auto refresh command is

An auto refresh command can be

DDR2_SDRAM_BANK_LEVEL
Bank Address lines are not

driven to valid levels.
Checks that bank address lines are

both known (not X) and driven (not
Z). This check is active only during
Precharge, Activate and memory Read
and Write commands.
207

V2.0 Monitor

Check ID
Violation
Description
INVALID
Invalid CAS latency value is

programmed in the mode
register during the MRS
command.

initialization sequence). CAS latency
can be either 2, 3, 4, or 5. Any other
value is invalid or reserved. Check the
cas_latency value programmed during
the last MRS command.
INVALID_BYPASS


value is passed to the
mode_register_in input. As per
JEDEC specification, the valid CAS
latency values are 2, 3, 4, and 5. This
check fires if a CAS latency value
passed through the mode_register_in
input.
DDR2_SDRAM_CAS_LEVEL
cas_n is not driven to a valid

level.
Checks that CAS_n is both known

(not X) and driven (not Z). This check
is active only if CKE is high.
DDR2_SDRAM_CKE_LEVEL
cke is not driven to a valid

level.
Checks that CKE is both known (not

active after the first active edge of the
clock.
DDR2_SDRAM_CONSTRAINTS_
MODE
Constraints_Mode parameter
The value of the

CONSTRAINTS_MODE parameter
should be either 1 or 0. It is to be made
1 to make checks as constraints and 0
to have them as targets during formal
analysis.
DDR2_SDRAM_CONTROLLER_
SIDE
CONTROLLER_SIDE
0.
The value of CONTROLLER_SIDE

DDR2_SDRAM_CS_LEVEL
cs_n is not driven to a valid

level.
Checks that CS_n is both known (not

X) and driven (not Z). Active only if
CKE is high.
DDR2_SDRAM_DATA_CONFIG
DATA_BUS_WIDTH
parameter should be either 4, 8,
or 16.
The value of the

DATA_BUS_WIDTH parameter
should not be specified to be other
than 4, 8, or 16 since this indicates the
configuration of the data bus and the
allowed configurations are x4, x8, or
x16.
DDR2_SDRAM_DLL_NOT_RESET
DLL not reset prior to the first

activation command.

BYPASS_INIT is 0 (i.e, normal
initialization sequence). If DLL is
enabled during the initialization
sequence, then it must be reset before
issuing an activation command to any
bank. This check is active only if
DLL_TRACKING_ENABLE is 1.
208

V2.0 Monitor

Check ID
Violation
Description
DDR2_SDRAM_DLL_TRACKING
DLL_TRACKING_ENABLE
0
The value of the

DLL_TRACKING_ENABLE
DDR2_SDRAM_DM_RDQS_
LEVEL
dm_rdqs is not driven to a valid Checks that DM_RDQS is both

level.
Active only during write bursts in x4
and x16 configurations and 8x
configuration when RDQS is disabled,
if CKE is high.
DDR2_SDRAM_EMRS_3_
BEFORE_EMRS_2
An EMRS(3) command is
issued prior to an EMRS(2)
command during initialization
sequence.

initialization sequence). During the
initialization sequence, an EMRS(2)
command followed by an EMRS(3)
command should be issued even
before the DLL is enabled using the
EMRS command.
DDR2_SDRAM_EMRS_BEFORE_
EMRS_3
An EMRS command to enable

DLL is issued prior to an
EMRS(3) during initialization
sequence.

initialization sequence, an EMRS(2)
command followed by an EMRS(3)
command should be issued even
before the DLL is enabled using the
EMRS command.
DDR2_SDRAM_EMRS_
PRECHARGE
An extended mode register set

command is issued when one
or more banks are not in
precharge state.
An extended mode register set

command can be issued only when all
banks are in a precharged condition.
DDR2_SDRAM_INCORRECT_
COMMAND_BEFORE_MRS
An invalid command is issued

before programming the mode
register (only NOP,
DESELECT, and
PRECHARGE are valid at this
point).

initialization sequence). NOP,
precharge, and refresh are the only
commands that are valid before the
Mode register is set. Check the
designs reset sequencing.
DDR2_SDRAM_INSUFFICIENT_
AUTO_REFRESH_ACTIVATE
Sufficient number (2) of auto

refresh commands are not
issued prior to the first
activation command.

initialization sequence, at least 2 auto
refresh commands must be issued
before the first activation command.
DDR2_SDRAM_LDM_LEVEL
ldm is not driven to a valid

level.
Checks that LDM is both known (not

X) and driven (not Z). Active only
during write bursts if CKE is high.
DDR2_SDRAM_MODE_
REGISTER_NOT_SET
Mode register is not

programmed prior to the first
activation command.

initialization sequence). The mode
register must be configured for burst
type, CAS latency, etc. during the
initialization sequence, before the first
activation.
209

V2.0 Monitor

Check ID
Violation
Description
DDR2_SDRAM_MRS_
PRECHARGE
A mode register set command

is issued when one or more
banks are not in precharge
state.
A mode register set command can be

DDR2_SDRAM_RAS_LEVEL
ras_n is not driven to a valid

level.
Checks that RAS_n is both known

(not X) and driven (not Z). This check
is active only if CKE is high.
DDR2_SDRAM_ROW_ADDRESS
ROW_ADDRESS_WIDTH
The value of the

ROW_ADDRESS_WIDTH parameter
12.
DDR2_SDRAM_SELF_REFRESH_
PRECHARGE
A self refresh command is

A self refresh command can be issued

only when all banks are in precharged
condition.
DDR2_SDRAM_SEQUENTIAL_
ACTIVATION_VIOLATION
The number of activation

commands in a rolling window
of (4*tRRD + 2tCK) exceeded
4.
In order to ensure that 8 bank devices

do not exceed the instantaneous
current supplying capability of 4 bank
devices, the following restriction must
be observed: no more than 4 banks can
be activated in a rolling (4 * tRRD + 2
* tCK) window, and a rolling window
is often also called a sliding window.
DDR2_SDRAM_TCCD
TCCD timing parameter should The value of the TCCD timing

limit of 2.
be less than 2.
DDR2_SDRAM_TDLL_
VIOLATION_AFTER_DLL_RESET
A Read or Read with

Autoprecharge command is
issued before 200 clock cycles
after DLL reset.

initialization sequence). A Mode
Register Set command must be issued
for the Mode Register to reset the
DLL and to program the operating
parameters. Once the DLL reset
command is issued, a minimum of 200
clock cycles are required before any
read command is issued.
DDR2_SDRAM_TMRD
TMRD timing parameter

minimum limit of 2.

be less than 2.
DDR2_SDRAM_TRAS
TRAS timing parameter should The value of the TRAS timing

limit of 6.
be less than 6.
DDR2_SDRAM_TRCD
TRCD timing parameter should The value of the TRCD timing

limit of 2.
be less than 2.
DDR2_SDRAM_TRFC
TRFC timing parameter should

limit of 9.

be less than 9.
DDR2_SDRAM_TRP
TRP timing parameter should

limit of 2.

be less than 2.
210

V2.0 Monitor

Check ID
Violation
DDR2_SDRAM_TRRD
TRRD timing parameter should The value of the TRRD timing

limit of 1.
be less than 1.
DDR2_SDRAM_TRRD_
VIOLATION

the tRRD timing between
activation commands to
different banks.

DDR2_SDRAM_TRTW
TRTW timing parameter

minimum limit of 4.
The value of the TRTW timing

be less than 4.
DDR2_SDRAM_TWR
TWR timing parameter should

limit of 2.

be less than 2.
DDR2_SDRAM_TWTR
TWTR timing parameter

minimum limit of 1.
The value of the TWTR timing

be less than 1.
DDR2_SDRAM_TXARD
TXARD timing parameter

minimum limit of 2.
The value of the TXARD timing

be less than 2.
DDR2_SDRAM_TXP
TXP timing parameter should

limit of 2.
The value of the TXP timing

be less than 2.
DDR2_SDRAM_TXSNR
TXSNR timing parameter


be less than 10.
DDR2_SDRAM_TXSRD
TXSRD timing parameter


be less than 200.
DDR2_SDRAM_UDM_LEVEL
udm is not driven to a valid

level.
Checks that UDM is both known (not

X) and driven (not Z). Active only
during write bursts if CKE is high.
DDR2_SDRAM_WE_LEVEL
we_n is not driven to a valid

level.
Checks that WE_n is both known (not

Description
211

V2.0 Monitor
Table 7-14 shows the checks for each bank performed by a DDR-II SDRAM 2.0 monitor.
Table 7-14. DDR-II SDRAM 2.0 Monitor Bank Checks
Check ID
Violation
Description
A_DDR2_SDRAM_CLOCK_
CHANGE_DURING_NON_PPD_
MODE

while the DDR2 SDRAM is not
in precharge power down
mode.
The input clock frequency can

change only in precharge power
down mode while the clock enable
signal CKE is LOW. This check
fires when the DDR2 SDRAM
clock changes while the DDR2
SDRAM is not operating in idle or
precharge power down mode. This
check is functional only when the
A_DDR2_SDRAM_CLOCK_
CHANGE_DURING_ILLEGAL_CKE

while CKE is not LOW.

clock changes while CKE is not
LOW. This check is functional
CLOCK_CHANGE_
A_DDR2_SDRAM_CLOCK_
FREQUENCY_OUT_OF_RANGE
The clock frequency is out of

the allowed range in current
change only within the allowed
speed grade of DDR2 SDRAM. range in a speed grade. This check
clock changes beyond the allowed
clock frequency range specified by
the parameters
CLOCK_PERIOD_MIN. By
default, the monitor verifies a range
of 400 Mhz - 800 MHz. This check
is functional only when both the
parameters CLOCK_CHANGE_
TRACKING_ENABLE and
CLOCK_FREQUENCY_
RANGE_CHECK_ENABLE are
set to 1.
A_DDR2_SDRAM_CKE_
CHANGED_DURING_UNSTABLE_
CLOCK
CKE changed state while the

clock is not yet stable.
212

fires when after a clock frequency
change, CKE changes its state
before a stable clock is available.
This check is functional only when
the parameter CLOCK_CHANGE_

V2.0 Monitor

Check ID
Violation
A_DDR2_SDRAM_PPD_EXIT_
DURING_UNSTABLE_CLOCK
Precharge power down mode

exited during an unstable clock. change only in precharge power
fires when after a clock frequency
change, precharge power down
mode is exited before a stable clock
is available. This check is
ENABLE is set to 1.
A_DDR2_SDRAM_DLL_NOT_
RESET_AFTER_PPD_EXIT_
AFTER_CLOCK_CHANGE
DLL is not reset after precharge

power down exit after clock
change.
This check fires when a DLL reset

command is not executed after a
clock frequency change. This
check is functional only when both
the parameters
ENABLE and
DLL_TRACKING_ENABLE are
set to 1.
DDR2_SDRAM_ACTIVATE
An ACTIVATE command is
issued to an already open bank
without an intervening
PRECHARGE.
An open bank must be closed

before issuing another activation
command to that bank.
DDR2_SDRAM_BAD_DATA
One or more bytes of data read

from the addressed DDR2
SDRAM location did not match
the data bytes written to the
Data read from the DDR2 SDRAM

did not match the data written to
the corresponding address. The
data check is performed only on the
reads to locations that were
previously written at least once.
Data checking is done on a byte
basis and the bitmap indicates the
data inconsistency between the
corresponding bytes. The check
fires when at least one byte of read
data does not match the
corresponding valid data byte that
was written to that location.
DDR2_SDRAM_BURST_
ABORTED_P
A read or write is aborted.
In DDR2 SDRAMs, burst

interruption is prohibited. Once a
4-n burst has started, then it has to
be completed before the start of a
new burst.
CKE de-asserted while an

operation is in progress.
CKE is not allowed while mode

register or extended mode register
command time, or read or write
operation is in progress. The
behavior of the system for an
asynchronous low on CKE is
undefined.
DDR2_SDRAM_BURST_
ABORTED_N
DDR2_SDRAM_CKE_DRIVEN_
LOW
Description
213

V2.0 Monitor

Check ID
Violation
Description
DDR2_SDRAM_CKE_LOW
CKE is driven low during a

cycle other than self refresh or
power down.
Clock Enable can be driven low

only during self refresh and power
down commands and has to be
maintained high during all other
cycles.
DDR2_SDRAM_ILLEGAL_
COMMAND_ACT_PWR_DN

when the bank is in the Active
Power Down state.
The command just issued is not a

legal command when the bank is in
the Active Power Down state. All
the valid commands from this state
are outlined in the state diagram in
the reference material. The user
should trace why an illegal
command is issued.
DDR2_SDRAM_ILLEGAL_
COMMAND_ACTIVE

ACTIVATE state.

the ACTIVATE state. All the valid
commands from this state are
issued.
DDR2_SDRAM_ILLEGAL_
COMMAND_CBR

when the memory is in the
AUTO REFRESH state.

the AUTO_REFRESH state. All
command is issued.
DDR2_SDRAM_ILLEGAL_
COMMAND_EMRS

EX_MODE_REG_SET state.

the EX_MODE_REG_SET state.
All the valid commands from this
state are outlined in the state
diagram in the reference material.
The user should trace why an
DDR2_SDRAM_ILLEGAL_
COMMAND_IDLE

when the bank is in the IDLE
state.

IDLE state. All the valid
issued.
DDR2_SDRAM_ILLEGAL_
COMMAND_IDLE_PWR_DN

when the bank is in the Idle
Power Down state.

the IDLE Power Down state. All
command is issued.
214

V2.0 Monitor

Check ID
Violation
Description
DDR2_SDRAM_ILLEGAL_
COMMAND_MRS

MODE_REG_SET state.

the MODE_REG_SET state. All
command is issued.
DDR2_SDRAM_ILLEGAL_
COMMAND_NOP

when the bank is in the NOP
state.

the SELF_REFRESH state. All the
issued. For this, you can also look
at r_from_state_string.
DDR2_SDRAM_ILLEGAL_
COMMAND_PRE

PRECHARGE state.

the PRECHARGE state. All the
issued.
DDR2_SDRAM_ILLEGAL_
COMMAND_PRE_ALL

when all banks are in the
PRECHARGE state.

the PRECHARGE_ALL state. All
command is issued.
DDR2_SDRAM_ILLEGAL_
COMMAND_READ

when the bank is in the READ
state.

the READ state. All the valid
trace why an illegal command was
issued.
DDR2_SDRAM_ILLEGAL_
COMMAND_READ_AP

READ_AUTO_PRECHARGE
state.

the READ_AUTO_PRECHARGE
state. All the valid commands from
this state are outlined in the state
215

V2.0 Monitor

Check ID
Violation
Description
DDR2_SDRAM_ILLEGAL_
COMMAND_SFR

SELF_REFRESH
state.

the SELF_REFRESH state. All the
issued.
DDR2_SDRAM_ILLEGAL_
COMMAND_WRITE

when the bank is in the WRITE
state.

the WRITE state. All the valid
issued.
DDR2_SDRAM_ILLEGAL_
COMMAND_WRITE_AP

WRITE_AUTO_
PRECHARGE state.

WRITE_AUTO_PRECHARGE
state. All the valid commands from
this state are outlined in the state
DDR2_SDRAM_ILLEGAL_RD_
BURST_8B_INTERRUPTION
A read burst of length 8 from a

bank is interrupted at a 4-bit
boundary by a non-Read or
Read with the Autoprecharge
command.
A read burst of length 8 can only be

interrupted by another read, or read
with auto precharge enabled, at a 4bit burst boundary. This check fires
whenever a non-Read or Read with
Autoprecharge command interrupts
a read burst.
DDR2_SDRAM_ILLEGAL_WR_
BURST_8B_INTERRUPTION
A Write burst of length 8 from

a bank is interrupted at a 4-bit
boundary by a non-Write or
Write with the Autoprecharge
command.
A write burst of length 8 can only

be interrupted by another write, or
write with auto precharge enabled,
at a 4-bit burst boundary. This
check fires whenever a non-Write
or Write with Autoprecharge
command interrupts a write burst.
DDR2_SDRAM_PRECHARGE_
TO_IDLE_BANK
A Precharge command is issued A PRECHARGE command was

to an idle bank.
just issued to an already idle bank.
Although this is not an illegal
operation, it is redundant. The user
can check why such redundant
commands are issued.
DDR2_SDRAM_RD_BURST_8B_
INTERRUPTED_AT_6B

boundary by a command.
216
A read burst can only be

interrupted by another read, or read
with auto precharge enabled, at a 4bit burst boundary. Any other form
of read interrupt is not allowed.
This check fires whenever a read
burst is interrupted at a 6-bit
boundary (typically the third clock
after the read command).

V2.0 Monitor

Check ID
Violation
Description
DDR2_SDRAM_READ_AP_
VIOLATION

the timing between read with
auto precharge and activation
command issued to the same
bank.
The DDR2 SDRAM starts an auto

precharge operation on the rising
edge which is (AL + BL/2) cycles
later than the read with AP
command if tRAS(min) and
tRTP(min) are satisfied. A new
bank activate command may be
issued to the same bank if, tRP has
been satisfied from the clock at
which auto precharge begins and
tRC from the previous bank
activation has been satisfied.
DDR2_SDRAM_READ_BEFORE_
WRITE
A read operation is performed

on the DDR2 SDRAM address
at Row row and Column
column of Bank bank that was
Data is read from the DDR-II

SDRAM from an address that was
DDR2_SDRAM_READ_TO_IDLE_
BANK
A read command is issued to an

idle bank.
The bank to which the READ

should determine why a READ
command.
DDR2_SDRAM_READA_BURST_
8B_INTERRUPTED

bank with autoprecharge
enabled is interrupted by a
command.
A read burst of length 8 with auto

precharge enabled must not be
interrupted and should be allowed
to go through the automatic
sequence to precharge.
DDR2_SDRAM_TCCD_VIOLATION

the tCCD timing between two
Read/Write commands.

tCCD (CAS to CAS delay timing).
issued too quickly after a
READ/WRITE command for
another bank. The user should
too close together.
DDR2_SDRAM_TCKE_VIOLATION
CKE signal should be held at a

valid input level for at least
tCKE clock cycles.
The DDR2 standard specifies that

the CKE signal should be held at
valid input level (either 1 or 0)
for a minimum of three clock
cycles. This check fires if CKE
changes its value within three clock
cycles.
DDR2_SDRAM_TMRD_VIOLATION The command issued violates

the tMRD timing after a
MRS/EMRS command was
issued.
Once a Mode Register Set, or

command is issued, there cannot be
any command issued, including
another MRS or EMRS command
until TMRD number of clock
cycles expire.
217

V2.0 Monitor

Check ID
Violation
Description
DDR2_SDRAM_TRAS_VIOLATION

the tRAS timing between an
activation and precharge
command.

tRAS (RAS to precharge timing).
together.
DDR2_SDRAM_TRC_VIOLATION

the tRC timing between an
activation command and
another activation command
issued to the same bank.
Once an activation command is

issued to the bank, another
activation command can be issued
only after tRC cycles.
DDR2_SDRAM_TRCD_VIOLATION

the tRCD timing between an
activation and Read/Write
command.

together.
DDR2_SDRAM_TRFC_VIOLATION

the tRFC timing between Auto
Refresh and Auto
Refresh/Activate command.

tRFC (minimum time delay
between AUTO REFRESH
command and any other
command). The new command is
issued too quickly after the AUTO
REFRESH command. The user
should determine why the
DDR2_SDRAM_TRP_VIOLATION

the precharge command period
(tRP).

tRP (RAS precharge timing). This
is an ACTIVATE/REFRESH
command issued too quickly after
the last precharge command for
this bank. The tRP for a precharge
all command to an 8 bank device is
equal to tRP + 1. The user should
too close together.
DDR2_SDRAM_TRTP_VIOLATION

the tRTP timing between a
Read and Precharge command.

Read to Precharge delay timing.
issued too quickly after a previous
READ command to the same bank.
The minimum delay should be
additive latency + BL/2 (burst
length / 2). You should determine
together.
218

V2.0 Monitor

Check ID
Violation
Description
DDR2_SDRAM_TRTR_VIOLATION

the tRTR timing between two
Read commands.

Read to Read delay timing. This is
a READ command issued too
minimum delay should be 2 clocks
since the 4-n bursts cannot be
interrupted. The user should
too close together.
DDR2_SDRAM_TRTW_VIOLATION The command issued violates

the tRTW timing between a
READ and WRITE command.

tRTW (Read to Write delay
timing). This is a WRITE
command issued too quickly after a
previous READ command to the
same bank. The user should
too close together.
DDR2_SDRAM_TWTP_VIOLATION

the tWTP timing between a
Write to Precharge delay timing.
Write and Precharge command. This is a PRECHARGE command
issued too quickly after a previous
WRITE command to the same
bank. The minimum delay should
be WL (write latency) + TWR
(write recovery time) + BL/2 (burst
length / 2). The user should
too close together.
DDR2_SDRAM_TWTR_
VIOLATION

the tWTR timing between a
Write and Read command.

Write to Read delay timing. This is
a READ command issued too
quickly after a previous WRITE
minimum delay should be tWTR
(write to read turn-around-time) +
CAS latency + BL/2 (burst length /
2) 1. The user should determine
together.
DDR2_SDRAM_TWTW_
VIOLATION

the tWTW timing between two
Write commands.

Write to Write delay timing. This is
a WRITE command issued too
quickly after a previous WRITE
minimum delay should be 2 clocks
since the 4-n bursts cannot be
interrupted. The user should
too close together.
DDR2_SDRAM_TXARD_
VIOLATION

the tXARD timing between
Exit ACTIVE POWER DOWN
with fast exit and a READ
command.
The fast exit latency from an

Active power down exit to a read
command is violated.
219

V2.0 Monitor

Check ID
Violation
Description
DDR2_SDRAM_TXARDS_
VIOLATION

the tXARDS timing between
Exit ACTIVE POWER DOWN
with slow exit and a READ
command.
The slow exit latency from an

Active power down exit to a read
DDR2_SDRAM_TXP_VIOLATION

the tXP timing between a
PRECHARGE POWER
DOWN exit and a NON-READ
command.
The latency from an Idle power

down exit to any nonread
DDR2_SDRAM_TXSNR_
VIOLATION

the tXSNR timing required
between a Self Refresh Exit and
a No-Read command.

tXSNR (minimum time delay
command and any other nonREAD command) timing. A nonREAD command is issued too
quickly after the SELF REFRESH
too close together.
DDR2_SDRAM_TXSRD_
VIOLATION

the tXSRD timing between a
Self Refresh Exit and a Read
command.

violates tXSRD (minimum time
delay between SELF REFRESH
EXIT command and a READ
command) timing. A READ
command is issued too quickly
after the SELF REFRESH EXIT
too close together.
DDR2_SDRAM_UNKNOWN_
STATE
The bank state machine went to

the UNKNOWN_STATE.
The command just issued has

caused the monitor state machine
to go to an UNKNOWN state. This
can be due to an illegal command.
You should look at the state
machine transitions and check why
it entered this state.
DDR2_SDRAM_WR_BURST_8B_
INTERRUPTED_AT_6B
A write burst of length 8 from a

boundary by a command.
A write burst can only be

interrupted by another write, or
write with auto precharge enabled,
at a 4-bit burst boundary. Any other
form of write interrupt is not
allowed. This check fires whenever
a write burst is interrupted at a 6-bit
boundary (typically the third clock
after the write command).
DDR2_SDRAM_WRITE_TO_IDLE_
BANK
A write command is issued to

an idle bank.
The bank to which the WRITE

precharged idle condition. You
should determine why a WRITE
command was issued to an idle
bank without issuing an
ACTIVATE command.
220

V2.0 Monitor

Check ID
Violation
Description
DDR2_SDRAM_WRITEA_BURST_
8B_INTERRUPTED
A write burst of length 8 from a

bank with autoprecharge
enabled is interrupted by a
command.
A write burst of length 8 with auto

precharge enabled must not be
interrupted and should be allowed
to go through the automatic
sequence to precharge.

Table 7-15 shows the corner cases captured by the DDR-II SDRAM 2.0 monitor for the
protocol.
Table 7-15. DDR-II SDRAM 2.0 Monitor Corner Cases
Corner Case
Description
Multiple Banks Activation
Number of times more than one bank is in activated state.
Precharge All Banks
Number of Precharge All commands issued to the DDR-II SDRAM.
CBR Refresh Commands
Number of times CBR Auto Refresh commands are issued.
Interleaved Bursts
Number of times Mode Register is programmed for Interleaved burst.
Sequential Bursts
Number of times Mode Register is programmed for Sequential burst.
Number of times Self Refresh command is issued.
Power Down Commands
Number of times Power Down command is issued.
NOP Commands
Number of times NOP command is issued.
Deselect Commands
Number of times Deselect command is issued.
Table 7-16 shows the corner cases captured by the DDR-II SDRAM 2.0 monitor for the DDR-II
SDRAM banks.
Table 7-16. DDR-II SDRAM 2.0 Bank Corner Cases
Corner Case
Description
Reads Without Precharge
Number of read without precharge commands issued to a bank.
Writes Without Precharge
Number of write without precharge commands issued to a bank.
Single Bank Precharges
Number of single bank Precharge commands issued to a bank.
Seamless Reads
Number of times a Read is immediately followed by another Read from the same
bank.
Seamless Writes
Number of times a Write is immediately followed by another Write to the same

bank.
Reads with Precharge
Number of times Read with Auto Precharge operation is performed to a bank.
221

V2.0 Monitor
Table 7-16. DDR-II SDRAM 2.0 Bank Corner Cases (cont.)

Corner Case
Description
Writes with Precharge
Number of times Write with Auto Precharge operation is performed to a bank.
Posted Reads
Number of times Posted Read cycles are exercised.
Posted Writes
Number of times Posted Write cycles are exercised.
Number of times a read operation is issued to a page that is already opened for
read in the bank.
Number of times a read operation is issued to a page that is already opened for
write in the bank.
Number of times a write operation is issued to a page that is already opened for
read in the bank.
Number of times a write operation is issued to a page that is already opened for
write in the bank.
Monitor Statistics
Table 7-17 lists the statistics collected for the protocol.
Table 7-17. DDR-II SDRAM 2.0 Monitor Statistics
Statistic
Description
Total Number of Memory

Accesses
Total number of data accesses to the DDR-II SDRAM for all banks.
Table 7-18 lists the statistics collected for each bank.

Table 7-18. DDR-II SDRAM 2.0 Bank Statistics
222
Statistic
Description
Total Number of Bank Accesses
Total number of times a bank is activated and data accesses

performed on the bank.
Chapter 8
Gigabit Ethernet
Introduction
The Ethernet Standard ISO/IEC 8802-3 (CSMA/CD MAC) is a comprehensive International
Standard for Local Area Networks (LANs) employing CSMA/CD as the access method. This
International Standard encompasses several media types and techniques for signal rates from
1 Mb/s to 100 Mb/s.
Gigabit Ethernet couples an extended version of the ISO/IEC 8802-3 (CSMA/CD MAC) to a
family of 1000 Mb/s Physical Layers by extending the ISO/IEC 8802-3 MAC beyond 100 Mb/s
to 1000 Mb/s. The 10 Gigabit Ethernet further extends the IEEE 802.3 MAC beyond 1000 Mb/s
to 10 Gb/s. Similarly, 40G and 100G further extends the IEEE 802.3 MAC beyond 10Gb/s to
40Gb/s and 100Gb/s, respectively. The bit rate is faster and the bit times are shorter both in
proportion to the change in bandwidth. The minimum packet transmission time has been
reduced by a factor of ten. Achievable topologies for 10 Gb/s operation are comparable to those
found in 1000BASE-X Full Duplex mode and equivalent to those found in WAN applications.
The IEEE 802.3 and IEEE 802.3ae Standards define these interfaces as follows:
10/100M Ethernet Media Independent Interface (MII) between a MAC and PHY.
Gigabit Media Independent Interface (GMII) between a 1Gb/s MAC and PHY.
Ten Gigabit Media Independent Interface (XGMII) between a 10 Gb/s MAC and PHY.
40G or 100G Ethernet Media Independent Interface (XLGMII/CGMII) between a

40Gb/s or 100Gb/s MAC and PHY.
Gigabit Interface (TBI) between PCS and PMA (in the case of 1000BASE-X PHYs).
Ten Gigabit Attachment Unit Interface (XAUI) between two 10 Gigabit Extenders.
PCS to PMA interface (in case of 10GBASE-X PHYs).
Ten Gigabit Sixteen Bit Interface (XSBI) between PCS and PMA (in the case of
10GBASE-R PHYs).
Hundred Gigabit Interface (XLAUI) and Forty Gigabit interface (CAUI) (in the case of
100GBASE-R and 40GBASE-R PHYs).
Optional forward error correction (FEC) layer.
40G or 100G Auto negotiation Interface.
The QVL Gigabit Ethernet monitor is designed for checking these Gigabit Ethernet interfaces.
223
Gigabit Ethernet
In addition to the above interfaces, QVL Gigabit Ethernet Monitor also checks Low pin count
Reduced Media Independent Interface (RMII) between a MAC and PHY and Reduced Gigabit
Media Independent Interface (RGMII) for 1G speed. Also, it supports Gigabit Serial Interface
(SGMII for 1G speed only) and Reduced Ten Bit Interface (RTBI) between PCS and PMA.
This version of the Gigabit Ethernet monitor is modeled from the requirements provided in the
following documents:
802.3 IEEE Standard for Information Technology, CSMA/CD access method and
physical layer specifications, 2002.
802.3ae Amendment: Media Access Control (MAC) Parameters and Physical Layers for
10 Gb/s Operation, 2002.
P802.3ba D2.1 draft Amendment: Media Access Control Parameters, Physical Layers
and Management Parameters for 40 Gb/s and 100 Gb/s Operation.
Reduced Gigabit Media Independence Interface (RGMII) version 2.0.
Supported Features
Gigabit Media Independent Interface (GMII)
Half Duplex and Full Duplex modes
Data frames Untagged, VLAN tagged, and Priority tagged frames
Control frames Pause and Reserved frames
Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame
Inter-packet gap requirements
Data integrity (FCS)
Reduced Gigabit Media Independent Interface (RGMII)
224
Reduced pin count interface for 1G speed only.
Single clock reference sourced from MAC to PHY (or from an external source)
Gigabit Ethernet
Supported Features
Media Independent Interface (MII)
Reduced Media Independent Interface (RMII)
Reduced pin count interface
Single clock reference sourced from MAC to PHY (or from an external source)
10 Gigabit Media Independent Interface (XGMII)
64-bit single data rate and 32-bit dual data rate modes
Control character alignment requirements
225
Gigabit Ethernet
Supported Features
Ordered sets Sequence and Idle
40/100 Gigabit Media Independent Interface

(XLGMII/CGMII)
64-bit wide data path
Control character alignment requirements
Ordered sets Sequence and Idle
1000BASE-X Ten bit Interface (TBI) between PCS and

PMA
Support for 1000BASE-X technology
1-bit serial and 10-bit symbol modes
Link synchronization
8b/10b decoding
Reduced Ten bit Interface (RTBI) between PCS and PMA
226
Gigabit Ethernet
Supported Features
Link synchronization
8b/10b decoding
10 Gigabit Attachment Unit Interface (XAUI)
4-bit serial (1-bit per lane) and 10-bit symbol (10-bits per lane) modes
Lane synchronization
Lane-to-lane deskew, link alignment, and realignment
8b/10b decoding
Align, Sync, Skip, and Sequence ordered sets
XAUI Limitation
The XAUI monitor is designed to support dual data rate (DDR) mode only. There is a
workaround if the user is using the single data rate (SDR) mode on the parallel interface. If your
serial interface uses a DDR mode, then use the monitors serial interface. To implement an SDR
workaround for the parallel interface, the user can hook-up a divide-by-2 clock to simulate the
DDR mode.
10 Gigabit Sixteen Bit Interface (XSBI)
Data blocks and Control blocks
227
Gigabit Ethernet
Supported Features
All defined block types
Descrambling
64b/66b decoding
Block synchronization
40G/100G Attachment Unit Interface (XLAUI, CAUI)
1, 2, and 4 lanes for 40G and 1, 2, 4, 5, 10, and 20 lanes for 100G
Lane lock state machine
Lane-to-lane bit level and symbol level automatic deskew
Link alignment state machine
Alignment marker support
All defined block types
Descrambling
64b/66b decoding
40G or 100G Auto Negotiation Interface
228
Supports 1000BASE-KX, 10GBASE-KX4, 10GBASE-KR, 40GBASE-KR4,

40GBASE-CR4, and 100GBASE-CR10 technologies
Priority resolution function over above interfaces and FEC layer
Base page and next pages
DME timing
Arbitration state machine
Gigabit Ethernet
Supported Control Characters
Start 8'hFB
Terminate 8'hFD
Error 8'hFE
Idle 8'h07
Sequence 8'h9C
10GBASE-W PHYs
MDIO Interface

The QVL Gigabit Ethernet monitor can be placed on either side of a GMII link to provide
interface checks. This can be on the Reconciliation Sublayer (MAC side) or the PHY side of the
link. The 10 Gigabit Ethernet monitor can be placed on the Reconciliation sublayer (RS) side or
the XGXS side of the XGMII interface to provide interface checks. Similarly, the monitor can
be placed on either of the two XGXSs of the XAUI interface. Likewise, the monitor can be
instantiated on the XSBI (10 Gigabit Sixteen Bit Interface) in case of the 10GBASE-R family of
PHYs. The 40/100 Gigabit Ethernet monitor can be placed on either side of a XLGMII/CGMII
link to provide interface checks.
In all of the above interfaces, the MAC_SIDE parameter in the monitor can be used to configure
the monitor instance to be on the interface closer to the MAC or closer to the medium. The
checks in the Gigabit Ethernet monitor can also be used as search targets and check constraints
while running formal analysis on the 1 Gb/s, 10 Gb/s, and 40/100 Gb/s ethernet components.
A typical Gigabit Ethernet setup is illustrated in Figure 8-1.
229
Gigabit Ethernet
Figure 8-1. Gigabit Ethernet Monitor Implementation

XGMII
XGMII
QVL
Monitor
MAC/ RS
XAUI
QVL
Monitor
XAUI
XGXS
GMII
XGMII
MII
RMII
XLGMII
CGMII
QVL
Monitor
XGMII
XGMII
QVL
Monitor
XGMII
QVL
Monitor
XAUI
QVL
Monitor
XGXS
XGMII
QVL
Monitor
TBI
SGMII
XAUI
XSBI
XLAUI
CAUI
QVL
Monitor
GMII
XGMII
MII
RMII
XLGMII
CGMII
QVL
Monitor
GMII / MII / RMII / XGMII / XLGMII / CGMII
MAC
XAUI /
XSBI
TBI
SGMII
XAUI
XSBI
XLAUI
CAUI
QVL
Monitor
PMA
PHY
The QVL 10/100M Ethernet monitor can be placed on either side of a MII link to provide
interface checks. This can be on the Reconciliation Sublayer (MAC side) or the PHY side of the
link.
In the above interface, the MAC_SIDE parameter in the monitor can be used to configure the
monitor instance to be on the interface closer to the MAC or closer to the medium. The checks
in the 10/100M Ethernet monitor can also be used as search targets and check constraints while
running formal analysis on the 10/100M Ethernet components.
Connect the Gigabit Ethernet monitor pins as shown in Figure 8-2. Refer to pin-out Table 8-1
on page 232 through Table 8-10 on page 236 for the pin descriptions.
230
Gigabit Ethernet
tx_clk
txd[63:0]
txc[7:0]
40/100G GIGABIT
ETHERNET
(XLGMII/CGMII)
Monitor
rx_clk
rxd[63:0]
rxc[7:0]
areset
reset
an_clk
tx_clk
rx_clk
tx_data[19:0]
rx_data[19:0]
Auto-Negotiation
Monitor
SOURCE
sl_clk
sl0_p
sl1_p
sl2_p
sl3_p
10 GIGABIT
ETHERNET
(XAUI) Monitor
dl_clk
dl0_p
dl1_p
dl2_p
dl3_p
areset
reset
TBI
Monitor
tx_clk
txd
rx_clk
rxd
areset
reset
txc
td[3:0]
tx_ctl
RTBI
Monitor
rxc
rd[3:0]
rx_ctl
areset
reset
tx_clk
txd
DESTINATION
TRANSMIT
RECEIVE
areset
reset
areset
reset
10/100M
ETHERNET
(RMII) Monitor
10 GIGABIT
ETHERNET
(XSBI) Monitor
rx_clk
rxd
bypass_descramble
TRANSMIT
rx_clk
rxd
rxc
TRANSMIT
10 GIGABIT
ETHERNET
(XGMII) Monitor
10/100M
ETHERNET
(MII) Monitor
areset
reset
ref_clk
txd[1:0]
tx_en
txd[1:0]
crs_dv
rx_er
RECEIVE
tx_clk
txd
txc
areset
reset
tx_clk
txd[3:0]
tx_en
tx_er
rx_clk
rxd[3:0]
rx_dv
rx_er
col
crs
RECEIVE TRANSMIT
areset
reset
TRANSMIT
1 GIGABIT
ETHERNET
(GMII) Monitor
RECEIVE
areset
reset
tx_clk
txd[7:0]
tx_en
tx_er
rx_clk
rxd[7:0]
rx_dv
rx_er
col
crs
RECEIVE
RECEIVE
TRANSMIT RECEIVE
TRANSMIT
RECEIVE
TRANSMIT
RECEIVE TRANSMIT
RECEIVE
TRANSMIT
Figure 8-2. Gigabit Ethernet Monitor Pin-Out Diagram
areset
reset
tx_clk
tx_lane[PHYSICAL_
LANE_COUNT-1:0]
rx_clk
rx_lane[PHYSICAL_
LANE_COUNT-1:0]
caui_interface
fec_enable
40/100M GIGABIT
ETHERNET
(XLAUI/CAUI)
Monitor
231
Gigabit Ethernet
Table 8-1. GMII Monitor Pin Descriptions

Port
Description
areset
Asynchronous reset signal (not part of standard I/F signals).
col
Collision detect.
crs
Carrier sense.
half_duplex
Dynamic configuration to switch between half_duplex and full_duplex mode.

Monitor considers a half duplex mode when the value on this pin is 1 and
consider a full duplex mode when the value is 0.
reset
Synchronous reset signal (not part of standard I/F signals).
rx_clk
Receive clock signal (used to sample all Rx interface signals).
rx_dv
Receive data valid.
rx_er
Receive error.
rxd[7:0]
Receive data (8-bits).
tx_clk
Transmit clock signal (used to sample all Tx interface signals).
tx_en
Transmit enable.
tx_er
Transmit error.
txd[7:0]
Transmit data (8-bits).
Table 8-2. RGMII Monitor Pin Descriptions
232
Port
Description
areset
half_duplex

reset
rxc
rxd[3:0]
rx_ctl
Receive Control.
txc
tx_ctl
Transmit Control.
txd[3:0]
Gigabit Ethernet
Table 8-3. MII Monitor Pin Descriptions

Port
Description
areset
col
Collision detect.
crs
Carrier sense.
half_duplex

reset
rx_clk
rx_dv
Receive data valid.
rx_er
Receive error.
rxd[3:0]
tx_clk
tx_en
Transmit enable.
tx_er
Transmit error.
txd[3:0]
Table 8-4. RMII Monitor Pin Descriptions

Port
Description
areset
crs_dv
Carrier Sense/Receive Data Valid.
half_duplex
Dynamic configuration to switch between half_duplex and full_duplex

mode. Monitor considers a half duplex mode when the value on this pin is 1
and consider a full duplex mode when the value is 0.
reset
ref_clk
Synchronous clock reference for receive and transmit interface.
rxd[1:0]
rx_er
Receive Error.
txd[1:0]
tx_en
Transmit enable.
233
Gigabit Ethernet
Table 8-5. XGMII Monitor Pin Descriptions

Port
Description
areset
reset
rx_clk
rxc[3:0] / [7:0]
Receive control lines (1 line for each lane (byte) of RXD, 4 bits in case of
DDR mode and 8 bits in case of SDR mode).
rxd[31:0] / [63:0]
Receive data (4 lanes of 1 byte each in case of DDR 32-bit mode and 8 lanes
of 1 byte each in case of SDR 64-bit mode).
tx_clk
txc[3:0] / [7:0]
Transmit control lines (1 line for each lane (byte) of TXD, 4 bits in case of
DDR mode and 8 bits in case of SDR mode).
txd[31:0] / [63:0]
Transmit data (4 lanes of 1 byte each in case of DDR 32-bit mode and 8 lanes
of 1 byte each in case of SDR 64-bit mode).
Table 8-6. XLGMII/CGMII Monitor Pin Descriptions

Port
Description
areset
reset
tx_clk
txd[63:0]
Transmit data (8 lanes of 1 byte each).
txc[7:0]
Transmit control lines (1 line for each lane (byte) of TXD).
rx_clk
rxd[63:0]
Receive data (8 lanes of 1 byte each).
rxc[7:0]
Receive control lines (1 line for each lane (byte) of RXD).
Table 8-7. 1000BASE-X Ten bit Interface Monitor Pin Descriptions
234
Port
Description
areset
half_duplex

Monitor considers a half duplex mode when the value on this pin is 1 and consider a
full duplex mode when the value is 0.
Gigabit Ethernet
Table 8-7. 1000BASE-X Ten bit Interface Monitor Pin Descriptions (cont.)
Port
Description
reset
tx_clk
Transmit interface clock.
txd
Transmit data (10-bit or 1-bit).
rx_clk
Receive interface clock.
rxd
Receive data (10-bit or 1-bit).
Table 8-8. Reduced Ten bit Interface Monitor Pin Descriptions

Port
Description
areset
half_duplex
Dynamic configuration to switch between half_duplex and full_duplex mode. Monitor

considers a half duplex mode when the value on this pin is 1 and consider a full duplex
mode when the value is 0.
reset
txc
Transmit interface clock.
td[3:0]
Transmit data (4-bit).
tx_ctl
Transmit control.
rxc
Receive interface clock.
rd[3:0]
Receive data (4-bit).
rx_ctl
Receive control,
Table 8-9. XAUI Monitor Pin Descriptions

Port
Description
areset
dl0_p
Destination lane 0.
dl1_p
Destination lane 1.
dl2_p
Destination lane 2.
dl3_p
Destination lane 3.
dl_clk
Destination lanes clock (used to sample all destination lanes).
reset
sl0_p
Source lane 0.
sl1_p
Source lane 1.
235
Gigabit Ethernet
Table 8-9. XAUI Monitor Pin Descriptions (cont.)

Port
Description
sl2_p
Source lane 2.
sl3_p
Source lane 3.
sl_clk
Source lanes clock (used to sample all source lanes).
Note that if SYMBOL_MODE = 1, then sl0_p, sl1_p, sl2_p, sl3_p, dl0_p, dl1_p, dl2_p, and dl3_p are 10-bits
wide; otherwise 1-bit wide.
Table 8-10. XSBI Monitor Pin Descriptions

Port
Description
areset
bypass_descramble
Enables bypass of descrambler.
reset
rx_clk
Receive clock (used to sample all Rx interface signals).
rxd
Receive data lines.
tx_clk
Transmit clock (used to sample all Tx interface signals).
txd
Transmit data lines.
Note that if SYMBOL_MODE = 1, then both rxd and txd are 16-bits wide; otherwise 1-bit wide.
Table 8-11. XLAUI/CAUI Monitor Pin Descriptions

Port
Description
areset
reset
rx_clk
rx_lanes[PHYSICAL_LANE_COUNT-1:0]
Receive data lines.
tx_clk
tx_lanes[PHYSICAL_LANE_COUNT-1:0]
caui_interface
Enables 100G mode (not part of standard I/F signals).
fec_enable
Enables optional FEC layer (not part of standard I/F signals).
236
Gigabit Ethernet
Table 8-12. 40/100G Auto-Negotiation Monitor Pin Descriptions

Port
Description
areset
reset
an_clk
Sampling clock (not part of standard I/F signals). It is used to sample DME
encoded data.
rx_clk
rx_data[19:0]
Receive data lines.
tx_clk
tx_data[19:0]
Notes:
1. In 64-bit SDR mode of operation of the XGMII monitor, one clock of data in the DDR
mode comprising of two columns are mapped to one column of twice the length. If say
the two columns of data in the 32-bit (DDR) mode are denoted as {d00, d01, d02,
d03} and {d10, d11, d12, d13} where d00 and d10 are the lane0 data
respectively, then the corresponding 64-bit (SDR) data is {d00, d01, d02, d03,
d10, d11, d12, d13}, where d00 is lane0 data.
2. In Full Duplex mode of operation, the CRS (carrier sense) and COL (collision detect)
signals have no meaning and can be left unconnected.
3. In TBI/RTBI/XAUI mode, the monitor only takes in the lane_p component of the
balanced differential pair {lane_p, lane_n}.
4. If {a,b,c,d,e,i,f,g,h,j} is the 10-bit encoded data, then the TBI/RTBI/XAUI
assumes the first bit received to be a and the last bit to be j in the serial mode of
operation, and the most significant bit as j and the least significant bit as a in the 10bit symbol mode of operation.
5. In XLAUI/CAUI mode, caui_interface and fec_enable are used when auto
negotiation mode is enabled to dynamically change the values. Otherwise, they are
ignored and can be tied to any value.
237
Gigabit Ethernet
Monitor Parameters
The parameters shown in the following tables configure the Gigabit Ethernet monitor.
Table 8-13. GMII Monitor Parameters
Order
Parameter
Default
Description
1.
Constraints_Mode

2.
MAC_SIDE
Set this parameter to 0 if the monitor is instantiated on the

PHY side of an interface. By default, the monitor is
instantiated on the MAC side or the Reconciliation
Sublayer side of the interface.
3.
JUMBO_FRAME_DATA_
LENGTH
9216
Set this parameter to the desired length of Jumbo frames.

The default length of Jumbo frames is taken to be 9K
bytes (9216 bytes). Note that the upper limit for the
Jumbo frame size is 12K bytes, since this is the maximum
possible payload for 32-bit CRC.
4.
RESERVED_VALUE_
CHECK_ENABLE
By default, the monitor checks for any reserved values.

Set this parameter to 0 to disable checking of reserved
fields.
5.
MAC_MIN_TAGGED_
FRAME_SIZE_68
Set this parameter to 1 if the minimum size of tagged

frame is 68. In this case, QTag Prefix is not included in
the MAC client data. Therefore, the minimum tagged
frame size is 68 after auto-padding.
6.
RESERVED_CONTROL_
FRAME_SUPPORTED
Set this parameter to 1 if Reserved Control Frame is

supported.
7.
SLOT_TIME
512
Set this parameter to value of the Slot Time for Half

Duplex mode.
8.
JAM_SIZE
32
Set this parameter to the value of JAM Size for HAlf

Duplex mode.
9.
BURST_LIMIT
65536
Set this parameter to the total burst limit. By default, it is

65536 for Half Duplex mode.
Notes:
1. The parameters must be specified in the above order.
2. The HALF_DUPLEX parameter is deprecated; instead a pin is added for dynamic switch between
half duplex and full duplex modes. See Table 8-1 on page 232 for a detailed description.
Table 8-14. RGMII Monitor Parameters

Order
Parameter
Default
Description
1.
Constraints_Mode

2.
MAC_SIDE

238
Gigabit Ethernet
Table 8-14. RGMII Monitor Parameters (cont.)

Order
Parameter
Default
Description
3.
JUMBO_FRAME_DATA_
LENGTH
9216

4.
RESERVED_VALUE_
CHECK_ENABLE

fields.
5.
MAC_MIN_TAGGED_
FRAME_SIZE_68

6.
RESERVED_CONTROL_
FRAME_SUPPORTED

supported.
7.
SLOT_TIME
512

Duplex mode.
8.
JAM_SIZE
32

Duplex mode.
9.
BURST_LIMIT
65536

10.
DUPLEX_MODE_
INDICATION
Set this parameter to 1 if optional duplex mode indication

is enabled.
11.
CLK_SPEED_
INDICATION
Set this parameter to 1if optional Clock speed indication

is enabled.
Notes:
Table 8-15. MII Monitor Parameters

Order
Parameter
Default
Description
1.
Constraints_Mode

2.
MAC_SIDE

the PHY side of an interface. By default, the monitor is
3.
JUMBO_FRAME_DATA_
LENGTH
9216

bytes (9216 bytes).
Note that the upper limit for the Jumbo frame size is 12K
bytes, since this is the maximum possible payload for
32-bit CRC.
239
Gigabit Ethernet
Table 8-15. MII Monitor Parameters (cont.)

Order
Parameter
Default
Description
4.
RESERVED_VALUE_
CHECK_ENABLE

fields.
5.
MAC_MIN_TAGGED_
FRAME_SIZE_68

6.
RESERVED_CONTROL_
FRAME_SUPPORTED

supported.
7.
SLOT_TIME
64

Duplex mode.
8.
JAM_SIZE
32

Duplex mode.
Notes:
Table 8-16. RMII Monitor Parameters

Order Parameter
Default
Description
1.
Constraints_Mode

2.
MAC_SIDE

the PHY side of an interface. By default, the monitor is
3.
JUMBO_FRAME_DATA_
LENGTH
9216

bytes (9216 bytes).
Note that the upper limit for the Jumbo frame size is 12K
32-bit CRC.
4.
RESERVED_VALUE_
CHECK_ENABLE

fields.
5.
MAC_MIN_TAGGED_
FRAME_SIZE_68

6.
RESERVED_CONTROL_
FRAME_SUPPORTED

supported.
240
Gigabit Ethernet
Table 8-16. RMII Monitor Parameters (cont.)

Order Parameter
Default
Description
Notes:
Table 8-17. XGMII Monitor Parameters

Order
Parameter
Default
Description
1.
Constraints_Mode

2.
MAC_SIDE

the PHY side of an interface. By default, the monitor
is instantiated on the MAC side or the Reconciliation
3.
JUMBO_FRAME_DATA_
LENGTH
9216
Set this parameter to the desired length of Jumbo

frames. The default length of Jumbo frames is taken to
be 9K bytes (9216 bytes).
Note that the upper limit for Jumbo frame size is 12K
32-bit CRC.
4.
RESERVED_VALUE_
CHECK_ENABLE
By default, the monitor checks for any reserved

values. Set this parameter to 0 to disable checking of
reserved fields.
5.
DDR
Set this parameter to 0 to indicate a single-edge

XGMII with a 64-bit data bus instead of the standard
dual-edge 32-bit data interface. The default value of 1
indicates a dual edge 32-bit data XGMII interface.
6.
DIC_SUPPORTED
Set this parameter to 1 if Deficient Idle Count (DIC) is

supported. In this case, the minimum interframe gap
requirement is 72-bits instead of 96-bits.
7.
MAC_MIN_TAGGED_
FRAME_SIZE_68

frame is 68. In this case, QTag Prefix is not included
in the MAC client data. Therefore, the minimum
tagged frame size is 68 after auto-padding.
8.
RESERVED_CONTROL_
FRAME_SUPPORTED

supported.
241
Gigabit Ethernet
Table 8-18. XLGMII/CGMII Monitor Parameters

Order
Parameter
Default Description
1.
Constraints_Mode

2.
MAC_SIDE

3.
JUMBO_FRAME_DATA_
LENGTH
9216

Note that the upper limit for Jumbo frame size is 12K
32-bit CRC.
4.
RESERVED_VALUE_
CHECK_ENABLE

reserved fields.
5.
DIC_SUPPORTED

6.
MAC_MIN_TAGGED_
FRAME_SIZE_68

7.
RESERVED_CONTROL_
FRAME_SUPPORTED

supported.
Table 8-19. TBI Monitor Parameters

Order
Parameter
Default
Description
1.
Constraints_Mode

2.
MAC_SIDE

3.
SYMBOL_MODE
Set this parameter to 1 if the monitor is instantiated on a

parallel 10-bit (symbol) interface. The default value of 0
indicates a serial interface.
4.
JUMBO_FRAME_DATA_
LENGTH
9216

242
Gigabit Ethernet
Table 8-19. TBI Monitor Parameters (cont.)

Order
Parameter
Default
Description
5.
RESERVED_VALUE_
CHECK_ENABLE

fields.
6.
MAC_MIN_TAGGED_
FRAME_SIZE_68

7.
RESERVED_CONTROL_
FRAME_SUPPORTED

supported.
8.
SLOT_TIME
512

Duplex mode.
9.
JAM_SIZE
32

Duplex mode.
10.
BURST_LIMIT
65536

Notes:
Table 8-20. RTBI Monitor Parameters

Order
Parameter
Default
Description
1.
Constraints_Mode

2.
MAC_SIDE

3.
JUMBO_FRAME_DATA_
LENGTH
9216

4.
RESERVED_VALUE_
CHECK_ENABLE

fields.
5.
MAC_MIN_TAGGED_
FRAME_SIZE_68

6.
RESERVED_CONTROL_
FRAME_SUPPORTED

supported.
243
Gigabit Ethernet
Table 8-20. RTBI Monitor Parameters (cont.)

Order
Parameter
Default
Description
7.
SLOT_TIME
512

Duplex mode.
8.
JAM_SIZE
32

Duplex mode.
9.
BURST_LIMIT
65536

Notes:
Table 8-21. XAUI Monitor Parameters
244
Order
Parameter
Default
Default
1.
Constraints_Mode

2.
MAC_SIDE

3.
JUMBO_FRAME_DATA_
LENGTH
9216

Note that the upper limit for the Jumbo frame size is
12K bytes, since this is the maximum possible
payload for 32-bit CRC.
4.
RESERVED_VALUE_
CHECK_ENABLE

reserved fields.
5.
SYMBOL_MODE

a parallel 10-bit (symbol) interface. The default value
of 0 indicates a serial interface.
6.
BYPASS_DESKEW
Set this parameter to 1 to bypass the deskew logic.

This can be done when the input data stream is
guaranteed to be free of skew between lanes. The
default value of 1 attempts to deskew the lanes before
processing the data further.
7.
DIC_SUPPORTED

8.
MAC_MIN_TAGGED_
FRAME_SIZE_68

Gigabit Ethernet
Table 8-21. XAUI Monitor Parameters (cont.)

Order
Parameter
Default
Default
9.
RESERVED_CONTROL_
FRAME_SUPPORTED

supported.
Table 8-22. XSBI Monitor Parameters

Order
Parameter
Default
Description
1.
Constraints_Mode
Set this parameter to 1 if the checks in the monitor

are to be used as constraints for formal analysis.
2.
MAC_SIDE

instantiated on the PHY side of an interface. By
default, the monitor is instantiated on the MAC
side or the Reconciliation Sublayer side of the
interface.
3.
JUMBO_FRAME_DATA_LENGTH 9216

frames. The default length of Jumbo frames is
taken to be 9K bytes (9216 bytes).
Note that the upper limit for the Jumbo frame size
is 12K bytes, since this is the maximum possible
payload for 32-bit CRC.
4.
RESERVED_VALUE_CHECK_
ENABLE

values. Set this parameter to 0 to disable checking
of reserved fields.
5.
BYPASS_BLOCK_SYNC
Set this parameter to 0 to enable the block

synchronization process that will determine block
boundaries and obtain synchronization. The
default value of 1 will bypass the block
synchronization process.
6.
DIC_SUPPORTED
Set this parameter to 1 if Deficient Idle Count

(DIC) is supported. In this case, the minimum
interframe gap requirement is 72-bits instead of
96-bits.
7.
MAC_MIN_TAGGED_FRAME_
SIZE_68
Set this parameter to 1 if the minimum size of

tagged frame is 68. In this case, QTag Prefix is not
included in the MAC client data. Therefore, the
minimum tagged frame size is 68 after autopadding.
8.
RESERVED_CONTROL_FRAME_
SUPPORTED
Set this parameter to 1 if Reserved Control Frame

is supported.
9.
SYMBOL_MODE
Parameter SYMBOL_MODE = 1 indicates a

parallel (symbol) 16-bit interface. The default of 1
implies a parallel interface. A value 0 configures
the serial interface.
245
Gigabit Ethernet
Table 8-23. XLAUI/CAUI Monitor Parameters

Order Parameter
Default Description
1.
Constraints_Mode
Set this parameter to 1 if the checks in the

monitor are to be used as constraints for formal
analysis.
2.
MAC_SIDE

instantiated on the PHY side of an interface.
By default, the monitor is instantiated on the
MAC side or the Reconciliation Sublayer side
of the interface.
3.
JUMBO_FRAME_DATA_LENGTH
9216
Set this parameter to the desired length of

Jumbo frames. The default length of Jumbo
frames is taken to be 9K bytes (9216 bytes).
Note that the upper limit for the Jumbo frame
size is 12K bytes, since this is the maximum
4.
RESERVED_VALUE_CHECK_ENABLE
By default, the monitor checks for any

reserved values. Set this parameter to 0 to
disable checking of reserved fields.
5.
CAUI_INTERFACE
Set this parameter to 1 for interface type to

40G (XLAUI) and 0 for 100G (CAUI). This
parameter is ignored if AUTONEG_MODE is
set to 1.
6.
FEC_ENABLE
Set this parameter to 1 for fec layer support.

This parameter is ignored if
AUTONEG_MODE is set to 1.
7.
AM_COUNTER_16383
800
This parameter defines the number of blocks

between two alignment marker.
8.
AM_LOCK_ON_FIRST_AM
Set this parameter to 1 to have AM lock

achieved on detection of first alignment
marker. Otherwise, lock is achieved based on
state machine.
9.
AUTONEG_MODE
Set this parameter to 1 to configure autoneg

mode. If this parameter is set to 1, then
CAUI_INTERFACE and FEC_ENABLE
parameters are ignored and caui_interface and
fec_enable wires will be used to determine
interface type.
10.
PHYSICAL_LANE_COUNT
Sets the physical lane count. Valid values are

XLAUI: 1, 2, and 4.
CAUI: 1, 2, 4, 5, 10, and 20
11.
DIC_SUPPORTED
Set this parameter to 1 if Deficient Idle Count

(DIC) is supported. In this case, the minimum
interframe gap requirement is 72-bits instead
of 96-bits.
12.
MAC_MIN_TAGGED_FRAME_SIZE_68
Set this parameter to 1 if the minimum size of

tagged frame is 68. In this case, QTag Prefix is
not included in the MAC client data.
Therefore, the minimum tagged frame size is
68 after auto-padding.
246
Gigabit Ethernet
Table 8-23. XLAUI/CAUI Monitor Parameters (cont.)

Order Parameter
Default Description
13.
RESERVED_CONTROL_FRAME_
SUPPORTED
Set this parameter to 1 if Reserved Control

Frame is supported.
Table 8-24. 40/100G Auto-Negotiation Monitor Parameters

Order Parameter
Default
Description
1.
Constraints_Mode
Set this parameter to 1 if the checks in the

monitor are to be used as constraints for
formal analysis.
2.
MAC_SIDE

instantiated on the PHY side of an interface.
By default, the monitor is instantiated on the
MAC side or the Reconciliation Sublayer
side of the interface.
3.
CLK_TO_CLK_MIN_CYCLES
62
Holds the minimum number of an_clk

(sampling clock) posedge that must be
sampled for considering valid clock
transition to clock transition (and hence a
valid Data bit 0). A default value 62
corresponds to minimum T2 value 6.2 ns
assuming an_clk to be of period 0.1 ns.
4.
CLK_TO_CLK_MAX_CYCLES
66
Holds the maximum number of an_clk

posedge that can be sampled for considering
valid clock transition to clock transition
(and hence a valid Data bit 0). A default
value 66 corresponds to maximum T2 value
6.6 ns assuming an_clk to be of period 0.1
ns.
5.
CLK_TO_DATA_MIN_CYCLES
30

transition to data transition (and hence a
6.
CLK_TO_DATA_MAX_CYCLES
34
Holds the maximum number of an_clk

(sampling clock) posedge that can be
transition to data transition (and hence a
corresponds to maximum T3 value 3.4 ns
7.
MANCHESTER_DELIMITER_MIN_
CYCLES
126

sampled for considering valid Manchester
violation delimiter. The default value 126
247
Gigabit Ethernet
Table 8-24. 40/100G Auto-Negotiation Monitor Parameters (cont.)

Order Parameter
Default
Description
8.
MANCHESTER_DELIMITER_MAX_
CYCLES
130
Parameter MANCHESTER_
DELIMITER_MAX_CYCLES holds the
maximum number of an_clk (sampling
clock) posedge that must be sampled for
considering valid Manchester violation
delimiter. The default value 130
corresponds to maximum T6 value 13.0 ns
9.
REMAINING_ACK_COUNT_MIN
Specifies the minimum number of

additional link codewords with the
Acknowledge bit set to logical one that are
sent by local device to ensure that the link
partner receives the acknowledgement.
10.
REMAINING_ACK_COUNT_MAX
Specifies the maximum number of

additional link codewords with the
Acknowledge bit set to logical one that are
sent by local device to ensure that the link
partner receives the acknowledgement.
11.
BREAK_LINK_TIMER_CYCLES
100000
After the auto-negotiation completion, break

link timer is started. If a valid page is
detected with in
BREAK_LINK_TIMER_CYCLES number
of an_clk posedge samples, the monitor
fires.
12.
PHYSICAL_LANE_COUNT
Sets the physical lane count. Valid values

are
XLAUI: 1, 2, and 4.
CAUI: 1, 2, 4, 5, 10, and 20.
13.
JUMBO_FRAME_DATA_LENGTH
9216
Set this parameter to the desired length of

Jumbo frames. The default length of Jumbo
frames is taken to be 9K bytes (9216 bytes).
Note that the upper limit for the Jumbo
frame size is 12K bytes, since this is the
maximum possible payload for 32-bit CRC.
14.
By default, the monitor checks for any

reserved values. Set this parameter to 0 to
disable checking of reserved fields.
15.
BYPASS_BLOCK_SYNC
BYPASS_BLOCK_SYNC = 1 will bypass

the block synchronization process and
assume that the blocks are coming in
aligned from first data. To enable block
synchronization set this parameter to 0.
16.
DIC_SUPPORTED
Set this parameter to 1 if Deficient Idle

Count (DIC) is supported. In this case, the
minimum interframe gap requirement is 72bits instead of 96-bits.
17.
MAC_MIN_TAGGED_FRAME_
SIZE_68
Set this parameter to 1 if the minimum size

of tagged frame is 68. In this case, QTag
Prefix is not included in the MAC client
data. Therefore, the minimum tagged frame
size is 68 after auto-padding.
248
Gigabit Ethernet
Table 8-24. 40/100G Auto-Negotiation Monitor Parameters (cont.)

Order Parameter
Default
Description
18.
BYPASS_DESKEW
Set this parameter to 1 to bypass the deskew

logic. This can be done when the input data
stream is guaranteed to be free of skew
between lanes. The default value of 1
attempts to deskew the lanes before
processing the data further.
19.
AM_COUNTER_16383
800
This parameter defines the number of block

between two alignment marker.
20.
AM_LOCK_ON_FIRST_AM
Set this parameter to 1 to have AM lock

achieved on detection of first alignment
marker. Otherwise, lock is achieved based
on state machine.
NOTE:
One can use user type frame (Len/Type) by defining the following:
QVL_GBIT_USER_TYPES_COUNT as number of user type frames.
QVL_GBIT_USER_TYPES as Len/Type field specifying all the supported user types.
Example:
The user can configure QVL to support two types, say 16'h0800 and 16'h0900, by defining the
above defines as follows:
+define+QVL_GBIT_USER_TYPES_COUNT=2
+define+QVL_GBIT_USER_TYPES="32'h08000900"
Example 1
Example 8-1 instantiates a 1 Gigabit Ethernet GMII monitor on the MAC side (on the
Reconciliation Sublayer) with the Jumbo frame size configured as 9216. The reserved value
checking is disabled and the monitor is instantiated in Half Duplex mode.
Example 8-1. 1 Gigabit Ethernet GMII Monitor Instantiation
qvl_gigabit_ethernet_gmii_monitor #(
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.MAC_MIN_TAGGED_FRAME_SIZE_68(0),
249
Gigabit Ethernet
.RESERVED_CONTROL_FRAME_SUPPORTED(1),
.SLOT_TIME(512),
.JAM_SIZE(32),
.BURST_LIMIT(65536)
)
GMII_MONITOR
(.areset (areset),
.reset (reset),
.tx_clk (tx_clk),
.txd (txd),
.tx_en (tx_en),
.tx_er (tx_er),
.rx_clk (rx_clk),
.rxd (rxd),
.rx_dv (rx_dv),
.rx_er (rx_er),
.col (col),
.crs (crs),
.half_duplex(half_duplex));
Example 2
Example 8-2 instantiates a 1G RGMII monitor on the MAC side (on the Reconciliation
Sublayer) with the Jumbo frame size configured as 9216. The reserved value checking is
disabled and the monitor is instantiated in Half Duplex mode.
Example 8-2. Reduced Gigabit Ethernet RGMII Monitor Instantiation
qvl_gigabit_ethernet_rgmii_monitor #(
.MAC_SIDE(1),
.SLOT_TIME(512),
.JAM_SIZE(32),
.DUPLEX_MODE_INDICATION(0),
.CLK_SPEED_INDICATION(0)
)
RGMII_MONITOR
(.areset (areset),
.reset (reset),
.txc (txc),
.td (td),
.tx_ctl (tx_ctl),
.rxc (rxc),
.rd (rd),
.rx_ctl (rx_ctl),
250
Gigabit Ethernet
Example 3
Example 8-3 instantiates a 10/100M MII monitor on the MAC side (on the Reconciliation
Sublayer) with the Jumbo frame size configured as 9216. The reserved value checking is
disabled and the monitor is instantiated in Half Duplex mode.
Example 8-3. 10/100M Gigabit Ethernet MII Monitor Instantiation
qvl_gigabit_ethernet_mii_monitor #(
.MAC_SIDE(1),
.SLOT_TIME(64),
.JAM_SIZE(32)
)
MII_MONITOR
(.areset (areset),
.reset (reset),
.tx_clk (tx_clk),
.txd (txd),
.tx_en (tx_en),
.tx_er (tx_er),
.rx_clk (rx_clk),
.rxd (rxd),
.rx_dv (rx_dv),
.rx_er (rx_er),
.col (col),
.crs (crs),
Example 4
Example 8-4 instantiates a RMII monitor on the MAC side (on the Reconciliation Sublayer)
with the Jumbo frame size configured as 9216. The reserved value checking is disabled and the
monitor is instantiated in Half Duplex mode.
Example 8-4. 10/100M Gigabit Ethernet RMII Monitor Instantiation
qvl_gigabit_ethernet_rmii_monitor #(
.MAC_SIDE(1),
.RESERVED_CONTROL_FRAME_SUPPORTED(1)
)
RMII_MONITOR
(.areset (areset),
.reset (reset),
.ref_clk (ref_clk),
251
Gigabit Ethernet
.txd (txd),
.tx_en (tx_en),
.rxd (rxd),
.crs_dv (crs_dv),
.rx_er (rx_er),
Example 5
Example 8-5 instantiates a 10 Gigabit Ethernet XGMII monitor on the PHY side (on the XGMII
interface of the first XGXS from MAC or XGMII interface of PCS) with the Jumbo frame size
configured as 4096. The reserved value checking is enabled and the monitor is instantiated in
the single edge 64-bit mode.
Example 8-5. 10 Gigabit Ethernet XGMII Monitor Instantiation
qvl_gigabit_ethernet_xgmii_monitor #(
.MAC_SIDE(1),
.DIC_SUPPORTED(1),
)
XGMII_MONITOR
(.areset (areset),
.reset (reset),
.tx_clk (tx_clk),
.txd (txd),
.txc (txc),
.rx_clk (rx_clk),
.rxd (rxd),
.rxc (rxc));
Example 6
Example 8-6 instantiates a 40/100 Gigabit Ethernet XLMGMII/CGMII monitor on the PHY
side (on the MAC side) with the Jumbo frame size configured as 9216. The reserved value
checking is enabled.
Example 8-6. 40/100 Gigabit Ethernet XLGMII/CGMII Monitor Instantiation
qvl_gigabit_ethernet_xlgmii_cgmii_monitor #(
.MAC_SIDE(1),
.DIC_SUPPORTED(1),
252
Gigabit Ethernet
)
XGMII_MONITOR
(.areset (areset),
.reset (reset),
.tx_clk (tx_clk),
.txd (txd),
.txc (txc),
.rx_clk (rx_clk),
.rxd (rxd),
.rxc (rxc));
Example 7
Example 8-7 instantiates a 1000BASE-X TBI monitor on the MAC side with symbol model set
to 1 with the Jumbo frame size configured as 9216. The reserved value checking is disabled and
the monitor is instantiated in Half Duplex mode.
Example 8-7. 1000BASE-X TBI Monitor
qvl_gigabit_ethernet_tbi_monitor #(
.MAC_SIDE(1),
.SYMBOL_MODE(1),
.SLOT_TIME(512),
.JAM_SIZE(32),
.BURST_LIMIT(65536))
TBI_MONITOR (
(.areset(1'b0),
.reset(reset),
.tx_clk(tx_clk),
.txd(txd_10b),
.rx_clk(rx_clk),
.rxd(rxd_10b),
Example 8
Example 8-8 instantiates a Reduced Ten bit interface monitor on the MAC side with the Jumbo
frame size configured as 9216. The reserved value checking is disabled and the monitor is
instantiated in Half Duplex mode.
Example 8-8. Reduced Ten bit Interface Monitor
qvl_gigabit_ethernet_rtbi_monitor #(
253
Gigabit Ethernet
.MAC_SIDE(1),
.SLOT_TIME(512),
.JAM_SIZE(32),
.BURST_LIMIT(65536))
RTBI_MONITOR (
(.areset(1'b0),
.reset(reset),
.txc(txc),
.td(td),
.tx_ctl(tx_ctl),
.rxc(rxc),
.rd(rd),
.rx_ctl(rx_ctl),
Example 9
Example 8-9 instantiates a 10 Gigabit Ethernet XAUI monitor on the MAC side (on the XAUI
interface of the first XGXS from MAC or XAUI interface of PCS) with the Jumbo frame size
configured as 9216. The reserved value checking is enabled and the monitor is instantiated in
symbol mode (ten-bit interface) with deskew enabled.
Example 8-9. 10 Gigabit Ethernet XAUI Monitor Instantiation
qvl_gigabit_ethernet_xaui_monitor #(
.MAC_SIDE(1),
.BYPASS_DESKEW(0),
.DIC_SUPPORTED(1),
)
XAUI_MONITOR
(.areset (areset),
.reset (reset),
.dl_clk (dl_clk),
.sl_clk (sl_clk),
.sl0_p (sl0_p),
.sl1_p (sl1_p),
.sl2_p (sl2_p),
.sl3_p (sl3_p),
.dl0_p (dl0_p),
.dl1_p (dl1_p),
.dl2_p (dl2_p),
.dl3_p (dl3_p));
254
Gigabit Ethernet
Example 10
Example 8-10 instantiates a 10 Gigabit Ethernet XSBI monitor on the PHY side (on the XSBI
interface of PMA) with the Jumbo frame size configured as 1024. The reserved value checking
is disabled and the monitor is instantiated with block synchronization disabled and
descrambling enabled.
Example 8-10. 10 Gigabit Ethernet XSBI Monitor Instantiation
qvl_gigabit_ethernet_xsbi_monitor #(
.MAC_SIDE(1),
.BYPASS_BLOCK_SYNC(0),
.DIC_SUPPORTED(1),
)
XSBI_MONITOR
(areset (areset),
.reset (reset),
.tx_clk (tx_clk),
.rx_clk (rx_clk),
.txd (txd),
.rxd (rxd),
.bypass_descramble (bypass_descramble));
Example 11
Example 8-11 instantiates a 100 Gigabit Ethernet XLAUI monitor on the PHY side (on the
CAUI interface of PMA) with the am counter value 1200 and physical lane count 5. The
reserved value checking is disabled.
Example 8-11. 100 Gigabit Ethernet CAUI Monitor Instantiation
qvl_gigabit_ethernet_xlaui_caui_monitor #
(.Constraints_Mode(0),
.MAC_SIDE(1),
.CAUI_INTERFACE(1),
.FEC_ENABLE(0),
.AM_COUNTER_16383(1200),
.AM_LOCK_ON_FIRST_AM(1),
.AUTONEG_MODE(0),
.PHYSICAL_LANE_COUNT(5),
.DIC_SUPPORTED(1),
.RESERVED_CONTROL_FRAME_SUPPORTED(0))
CAUI_MONITOR
.areset(areset),
.reset (reset ),
255
Gigabit Ethernet
Monitor Checks
.tx_clk(tx_clk),
.rx_clk(rx_clk),
.caui_interface(1'b0),
.fec_enable(1'b0),
.tx_lanes(tx_lanes),
.rx_lanes(rx_lanes));
Example 12
Example 8-12 instantiates a 40/100G Auto-Negotiation monitor on the PHY side. The reserved
value checking is disabled.
Example 8-12. 100 Gigabit Ethernet Auto-Negotiation Monitor Instantiation
qvl_gigabit_ethernet_an_monitor #
(.Constraints_Mode(0),
.MAC_SIDE(1),
.AM_COUNTER_16383(1200),
.AM_LOCK_ON_FIRST_AM(1),
.DIC_SUPPORTED(1),
.RESERVED_CONTROL_FRAME_SUPPORTED(0))
AN_MONITOR
.areset(areset),
.reset (reset ),
.an_clk(an_clk),
.tx_clk(tx_clk),
.rx_clk(rx_clk),
.tx_data(tx_data),
.rx_data(rx_data));
Monitor Checks
The checks performed by the Gigabit Ethernet monitor are classified as follows:
MAC checks
These validate frame formation with regards to the size, type, address, FCS, and
interframe gap requirements. These are listed in Table 8-25 on page 258.
GMII checks
These validate 1Gb/s specific requirements, mainly with regards to the Half Duplex
mode of operation. These are listed in Table 8-26 on page 261
256
RGMII checks
Gigabit Ethernet
Monitor Checks
These validate RGMII specific requirements (for 1 Gbps speed), mainly with regards to
the Half Duplex mode of operation. These are listed in Table 8-27 on page 263.
MII checks
These validate 10/100M specific requirements, mainly with regards to the Half Duplex
mode of operation. These are listed in Table 8-28 on page 265.
RMII checks
These validate 10/100M specific requirements of RMII Interface, mainly with regards to
the Half Duplex mode of operation. These are listed in Table 8-29 on page 268.
XGMII checks
These validate lane alignment, frame encapsulation, and control character related
requirements in an XGMII interface. These are listed in Table 8-30 on page 269.
XLGMII/CGMII checks
These validate lane alignment, frame encapsulation, and control character related
requirements in an XLGMII/CGMII interface These are listed in Table 8-31 on
page 272.
TBI/RTBI checks
These validate 8B/10B encoding, link synchronization, ordered set location, and code
group requirements. These are listed in Table 8-32 on page 273.
XAUI checks
These validate 8B/10B encoding, link synchronization and alignment, ordered set
location, and spacing requirements. These are listed in Table 8-33 on page 275.
BASER checks for XSBI, XLAUI, and CAUI

These validate 64B/66B encoding, synchronization headers, block types, and null fields.
These are listed in Table 8-34 on page 280.
XLAUI/CAUI checks
These validate lane synchronization, alignment marker and deskew error. These are
listed in Table 8-35 on page 282.
40/100G Auto-Negotiation Checks

These validate DME timing, arbitration state machine, and valid priority resolution.
These are listed in Table 8-36 on page 283.
257
Gigabit Ethernet
Monitor Checks
Table 8-25. MAC Checks

Check ID
Violation
Description
GIGABIT_ETHERNET_
CONTROL_FRAME_
LENGTH_VIOLATION_P
The length of MAC control

frames should be 64 octets
(MinFrameSize - 32 bits +
FCS).
MAC Control frames are of fixed length,

containing MinFrameSize-32 bits. The
underlying MAC appends the FCS. This
maps to overall frame size of 64 octets (64
octets - 32 bits/8 + 4 octets). This check
fires when this requirement is violated. This
check is active only if the parameter
is set to 1.
The CRC computed by the

receiving station should be
the same as the one
appended to the frame.
The frame check sequence (FCS) field

contains a 4-octet (32-bit) cyclic
redundancy check (CRC) value. This check
fires when the CRC appended to a frame
does not match the CRC computed on the
frame.
The length of the frame

should be equal to the
expected length (2 x address
fields + len_type field +
length + fcs field).
In case of untagged data frames, the

LEN/TYPE field indicates the length of the
subsequent data in octets. The overall frame
size is the sum of the length of data field, 6
octets each of destination address, and
source address and 4 octets of FCS. This
check fires if the actual frame size does not
match the above sum.
The LEN/TYPE field should

be lesser than or equal to
16'd1500 or greater than
16'd1535.
If the value of LEN/TYPE field is less than

or equal to 1500 (decimal), then it indicates
the number of MAC client data octets
contained in the subsequent data.
If the value of this field is greater than or
equal to 1536 (decimal), then it indicates the
nature of the MAC client protocol. Values
between these bounds are invalid and not to
be used.
This check fires when a LEN/TYPE value
within this range is detected.
The size of an untagged

Ethernet MAC frame should
be lesser than the maximum
allowed size of 1518 octets.
The maximum number of octets of data that

can be transmitted on an untagged data
frame is 1500. This comes from the
LEN/TYPE field value restrictions. This
check fires whenever an untagged data
frame exceeds this upper limit.
GIGABIT_ETHERNET_
CONTROL_FRAME_
LENGTH_VIOLATION_N
GIGABIT_ETHERNET_
CRC_VIOLATION_P
GIGABIT_ETHERNET_
CRC_VIOLATION_N
GIGABIT_ETHERNET_
FRAME_LENGTH_
MISMATCH_VIOLATION_P
GIGABIT_ETHERNET_
FRAMELENGTH_
MISMATCH_VIOLATION_N
GIGABIT_ETHERNET_
LENGTH_TYPE_VIOLATION_P
GIGABIT_ETHERNET_
LENGTH_TYPE_VIOLATION_N
GIGABIT_ETHERNET_
MAX_FRAME_SIZE_
VIOLATION_P
GIGABIT_ETHERNET_
MAX_FRAME_SIZE_
VIOLATION_N
258
Gigabit Ethernet
Monitor Checks
Table 8-25. MAC Checks (cont.)

Check ID
Violation
Description
GIGABIT_ETHERNET_
MIN_FRAME_SIZE_
VIOLATION_P
The size of an ethernet MAC

frame should be equal to or
greater than the minimum
allowed size of 64 octets.
The data field contains a sequence of n

octets. A minimum frame size (of 64 octets)
is required for correct CSMA/CD protocol
operation. This check fires when this
minimum frame size requirement is
violated.
The destination address in a

PAUSE control frame on the
transmit interface should be
globally assigned multicast
address 01-80-C2-00-00-01.
The globally assigned 48-bit multicast

address 01-80-C2-00-00-01 has been
reserved for use in MAC Control PAUSE
frames for inhibiting transmission of data
frames from a DTE. A transmitting station
sending out a Pause frame must use this
global address. This check fires when this
The reserved field in a

PAUSE control frame
should have a value of 8'h00
in all the octets.
The Reserved field is used when the MAC

Control parameters do not fill the fixed
length MAC Control frame. The size of the
Reserved field is determined by the size of
the MAC Control Parameters. In the case of
Pause frames, only two octets of pause
quantum parameter is defined and all the
remaining reserved fields must be 0. This
check fires when this requirement is
violated. This check is active only if
is set to 1.
All octets of the preamble

field should have a value of
8'b10101010 (8'hAA).
The preamble field is a 7-octet field that is

used to allow the PLS circuitry to reach its
steady-state synchronization with the
received frames timing. The preamble
pattern is a continuous stream of 8 bit
sequences of 10101010. The nature of the
pattern is such that, for Manchester
encoding, it appears as a periodic waveform
on the medium that enables bit
synchronization. This check fires when this
preamble pattern is violated.
The control opcode should

not be reserved.
The Length/Type field of a MAC Control

frame contains the hexadecimal value of
88-08. The next two octets define the
control opcode. Currently, the only defined
opcode is 00_01 to denote Pause control
frames. This check fires whenever a
reserved opcode is detected.
GIGABIT_ETHERNET_
MIN_FRAME_SIZE_
VIOLATION_N
GIGABIT_ETHERNET_
PAUSE_DEST_ADDR_
VIOLATION_P
GIGABIT_ETHERNET_
PAUSE_DEST_ADDR_
VIOLATION_N
GIGABIT_ETHERNET_
PAUSE_RESERVED_
VIOLATION_P
GIGABIT_ETHERNET_
PAUSE_RESERVED_
VIOLATION_N
GIGABIT_ETHERNET_
PREAMBLE_VIOLATION_P
GIGABIT_ETHERNET_
PREAMBLE_VIOLATION_N
GIGABIT_ETHERNET_
RESERVED_CONTROL_
OPCODE_P
GIGABIT_ETHERNET_
RESERVED_CONTROL_
OPCODE_N
259
Gigabit Ethernet
Monitor Checks
Table 8-25. MAC Checks (cont.)

Check ID
Violation
Description
GIGABIT_ETHERNET_
RX_MIN_IFG_VIOLATION_P
The spacing between two

packets on the receive
interface should be greater
than the minimum of 8 BT,
40 BT and 64 BT in
100/40G, 10G, and 1G
implementations,
respectively.
In the case of 1 Gb/s implementations, the

spacing between two non-colliding packets,
from the last bit of the FCS field of the first
packet to the first bit of the preamble of the
second packet, should be a minimum of 64
BT (bit times), as measured at the GMII
receive signals at the DTE. For 10G/s
implementation, a minimum gap of 40 bit
times and for 100/40G/s implementation, a
minimum gap of 8 bit times must be
maintained. This check fires when the gap
between two frames violates this
requirement.
This check not valid for XLAUI and CAUI
interfaces.
The start frame delimiter

(SFD) should have a value
of 8'b10101011 (8'hAB).
The SFD field has the sequence 10101011.

It immediately follows the preamble pattern
and indicates the start of a frame. Upon
reception of this sequence, further bits are
sent to the MAC client for processing. This
check fires when this pattern is violated.
The source address should

be an individual address.
A multi-destination address associated with

one or more stations on a given network are
called multicast addresses. A source address
cannot be a group (multicast) address. This
check fires when a multicast source address
is detected.
The spacing between two

packets on the transmit
interface should be a
minimum of 96 BTs.
On the transmit interface, both 1G/s and

10G/s implementations must ensure a
minimum interframe spacing of 96 bit times.
violated.
This check is not valid for XLAUI and
CAUI interfaces.
When the LEN/TYPE field

indicates a TYPE, this value
should indicate one of
CONTROL, TAGGED, or
JUMBO frames.
If the value of this field is greater than or

equal to 1536 (decimal), then this field
indicates the nature of the MAC client
protocol (Type interpretation). However, the
only defined types are Control frames,
Tagged frames, and Jumbo frames. This
check fires when the LEN/TYPE field
indicates a type other than these defined
values.
GIGABIT_ETHERNET_
RX_MIN_IFG_VIOLATION_N
GIGABIT_ETHERNET_
SFD_VIOLATION_P
GIGABIT_ETHERNET_
SFD_VIOLATION_N
GIGABIT_ETHERNET_
SOURCE_ADDR_VIOLATION_P
GIGABIT_ETHERNET_
SOURCE_ADDR_VIOLATION_N
GIGABIT_ETHERNET_
TX_MIN_IFG_VIOLATION_P
GIGABIT_ETHERNET_
TX_MIN_IFG_VIOLATION_N
GIGABIT_ETHERNET_
TYPE_VIOLATION_P
GIGABIT_ETHERNET_
TYPE_VIOLATION_N
260
Gigabit Ethernet
Monitor Checks
Table 8-26. GMII Checks

Check ID
Violation
Description
GIGABIT_ETHERNET_GMII_
CAR_EXTN_ON_RX_
WITHOUT_FRAME
Carrier extension detected

on receive interface without
a preceding frame.
Carrier extension is performed to maintain

the minimum carrier event. This can only
follow a frame. This check fires if a carrier
extension is detected on the receive
interface without a preceding frame.
CAR_EXTN_ON_TX_
WITHOUT_FRAME
Carrier extension detected

Carrier extension is performed to maintain
on transmit interface without the minimum carrier event. This can only
a preceding frame.
follow a frame. This check fires if a carrier
extension is detected on the transmit
interface without a preceding frame.
CAR_EXTN_FULL_DUPLEX_
VIOLATION
Carrier extension should not

be there in Full Duplex
mode.
Carrier extension is not a part of Full

Duplex mode. This assertion gets fired
when it detected carrier extension in Full
Duplex.
COLLISION_DETECTED_
WITHOUT_CAR
In Half Duplex mode, a

collision is detected even
when there is no carrier
sense.
In Half Duplex mode, the collision detect

signal is driven by the PHY upon detection
of a collision on the medium. A collision
cannot be detected when there is no carrier
sensed in the medium. This check fires if
the CRS signal is low, indicating that both
transmit and receive interfaces are idle and
COL is asserted, indicating a collision.
CRS_DEASSERTED_DURING_
COLLISION
In Half Duplex mode, carrier

sense should be held high
throughout the collision
period.
In the event of a collision, the COL is

asserted by the PHY and is held high until
the collision persists, after which it is deasserted. The carrier sense should also be
driven high until the collision persists. This
check fires when CRS is de-asserted while
COL is high.
RESERVED_VALUES_ON_RX_
INTERFACE
Reserved values detected on

receive interface when the
RX_DV was not asserted
and RX_ER is asserted.
Reserved values should not be used on the

receive interface when RX_DV is deasserted and RX_ER is asserted. This check
fires when RX_DV is de-asserted and
RX_ER is asserted with a reserved value on
RXD. This check is active only if
is set to 1.
RESERVED_VALUES_ON_TX_
INTERFACE

the transmit interface when
TX_EN was not asserted and
TX_ER is asserted.

transmit interface when TX_EN is asserted
and TX_ER is asserted. This check fires
when TX_EN is de-asserted and TX_ER is
asserted with a reserved value on TXD.
This check is active only if
is set to 1.
RX_INTERFACE_ACTIVE_
WHEN_TX_ACTIVE
In Half Duplex mode, the

receive interface is non-idle
when the transmit interface
is already active.
In Half Duplex mode, either the transmit or

the receive interface can be active at any
given time and the other interface should be
idle. This check fires when the receive
interface is detected active when the
transmit interface is already active.
261
Gigabit Ethernet
Monitor Checks
Table 8-26. GMII Checks (cont.)

Check ID
Violation
Description
RX_START_WITH_
NON_PREAMBLE_OR_SFD
When RX_DV is asserted, it

indicates that a frame
reception has started. A
frame reception must always
begin with a preamble or
SFD.
When RX_DV is asserted, the value on the

RXD can only start with preamble or SFD.
This check fires when this is violated.
TX_ASSERTED_WHEN_
CAR_SENSED
In Half Duplex mode,

TX_EN should not be
asserted when the carrier
sense is high.
In Half Duplex mode, the carrier sense

signal is driven by the PHY when either the
transmit or the receive interface is non-idle.
If the transmit interface is idle and the
carrier sense is asserted, then it means that
the receive interface is non-idle and the
TX_EN should not be asserted until CRS is
sampled low. This check fires if TX_EN is
asserted when CRS is high.
TX_ASSERTED_WHEN_
COLLISION_DETECTED
In Half Duplex mode,

TX_EN should not be
asserted when a collision is
detected.
In Half Duplex mode, the collision detect

signal is driven by the PHY upon detection
of a collision on the medium, and shall
remain asserted while the collision
condition persists. The transmit interface
should not make an attempt to transmit a
frame (assert TX_EN) during a collision
period and must wait until COL is low. This
check fires if TX_EN is asserted when COL
is high.
TX_INTERFACE_ACTIVE_
WHEN_RX_ACTIVE

transmit interface is non-idle
when the receive interface is
already active.
In Half Duplex mode, either the receive or

the transmit interface can be active at any
idle. This check fires when the transmit
interface is detected active when the receive
interface is already active.
TX_START_WITH_
NON_PREAMBLE
When TX_EN is asserted, it This check fires whenever TX_EN is

asserted, indicating a new frame and the
transmission has started. The data is other than preamble (8'h55).
frame transmission should
always begin with a
preamble.
TX_ER_ASSERTED_DURING_
FRAME_TRANSMISSION
TX_ER is asserted while

frame is being transmitted.
During the frame transmission, TX_EN is

asserted. Assertion of TX_ER at this
moment indicates a Transmit error
propagation.
RX_ER_ASSERTED_DURING_
FRAME_TRANSMISSION
RX_ER is asserted while

During the frame transmission, RX_DV is

asserted. Assertion of RX_ER at this
moment indicates a Data Reception error.
TX_EXTN_ERR
TX_ER is asserted with

This check is fired when an error is
TXD carrying 0x1F while
encountered within carrier extension
extension bits are being sent. indicated by 0x1F on TXD while keeping
TX_EN de-asserted.
RX_EXTN_ERR
RX_ER is asserted with

RXD carrying 0x1F while
extension bits are being sent. indicated by 0x1F on RXD while keeping
RX_EN de-asserted.
262
Gigabit Ethernet
Monitor Checks
Table 8-26. GMII Checks (cont.)

Check ID
Violation
Description
GIGABIT_ETHERNET_FALSE_
CAR_INDICATION

0x0E on RXD.
While RX_DV is de-asserted, the PHY may

provide a False carrier indication by
asserting the RX_ER signal while driving
0x0E on RXD.
BURST_LIMIT_EXCEEDED
Burst limit is exceeded
The transmitting station is allowed to

initiate frame transmission until a specified
limit specified as burstLimit. This check is
fired when this limit is exceeded.
INCORRECT_EXTN_LENGTH
Extension length is not

correct.
If frame (or first frame in a burst) has length

less than slot time, then it should be
extended with the extension length as
(slotTime-FrameSize).
This check is fired when the number of
extension bits are not correct.
GIGABIT_ETHERNET_PAUSE_
FRAME_DETECTED
In Half Duplex mode, pause

frame is detected.
Pause frames are sent by DTEs configured

for Full Duplex operation. This check fires
when pause frame is sent in Half Duplex
mode.
GIGABIT_ETHERNET_LATE_
COLLISION_DETECTED
Late collision is detected.
MAC treats any collision that occurs after

the first frame of a burst, or that occurs after
the slotTime has been reached in the first
frame of a burst, as a late collision. This
check is fired when late collision is
detected.
GIGABIT_ETHERNET_JAM_
SIZE_NOT_CORRECT
Jam size is not equal to the

specified JAM_SIZE
parameter bit times.
When a collision is detected during a frame

transmission, the transmission continues for
additional bits corresponding to jam
sequence. This check fires when jam size is
not correct.
Table 8-27. RGMII Checks

Check ID
Violation
Description
GIGABIT_ETHERNET_RGMII_
RESERVED_VALUES_ON_RX_
INTERFACE

RX_DV was not asserted
and RX_ER is asserted.

receive interface when RX_DV is deasserted and RX_ER is asserted. This check
fires when RX_DV is de-asserted and
RX_ER is asserted with a reserved value on
RXD. This check is active only if
is set to 1.
RESERVED_VALUES_ON_TX_
INTERFACE

TX_EN was not asserted and
TX_ER is asserted.

transmit interface when TX_EN is asserted
and TX_ER is asserted. This check fires
when TX_EN is de-asserted and TX_ER is
asserted with a reserved value on TXD.
This check is active only if
is set to 1.
263
Gigabit Ethernet
Monitor Checks
Table 8-27. RGMII Checks (cont.)

Check ID
Violation
Description
RX_INTERFACE_ACTIVE_
WHEN_TX_ACTIVE

when the transmit interface
is already active.
In Half Duplex mode, either the transmit or

the receive interface can be active at any
idle. This check fires when the receive
interface is detected active when the
transmit interface is already active.
RX_START_WITH_
NON_PREAMBLE_OR_SFD

reception has started. A
frame reception must always
begin with a preamble or
SFD.
When RX_DV is asserted, the value on the

RXD can only start with preamble or SFD.
This check fires when this is violated.
TX_INTERFACE_ACTIVE_
WHEN_RX_ACTIVE

already active.
In Half Duplex mode, either the receive or

the transmit interface can be active at any
idle. This check fires when the transmit
interface is detected active when the receive
TX_START_WITH_
NON_PREAMBLE
When TX_EN is asserted, it This check fires whenever TX_EN is

asserted, indicating a new frame and the
transmission has started. The data is other than preamble (8'h55).
always begin with a
preamble.
FRAME_TRANSMISSION
TX_ER is asserted while

During the frame transmission, TX_EN is

asserted. Assertion of TX_ER at this
moment indicates a Transmit error
propagation.
FRAME_TRANSMISSION
RX_ER is asserted while

During the frame transmission, RX_DV is

asserted. Assertion of RX_ER at this
moment indicates a Data Reception error.
TX_EXTN_ERR
TX_ER is asserted with

TXD carrying 0x1F while
extension bits are being sent. indicated by 0x1F on TXD while keeping
TX_EN de-asserted.
RX_EXTN_ERR

RXD carrying 0x1F while
extension bits are being sent. indicated by 0x1F on RXD while keeping
RX_EN de-asserted.
INVALID_DUPLEX_STATUS
RX_CTL 0, 0 then rxd

shows duplex indication.
This check is fired when normal interframe

RXD value does not show proper Duplex
indication configured.
INVALID_CLK_SPEED_STATUS

should be x10x for 125
MHz.

RXD value is not equal to x10x for 125
MHz speed.
RESERVED_CLK_SPEED_
STATUS

should not be x11x which
indicates reserved status
value.

RXD value is equal to x11x.
264
Gigabit Ethernet
Monitor Checks
Table 8-27. RGMII Checks (cont.)

Check ID
Violation
Description
INVALID_NIBBLES_ON_
NEGEDGE_INTERFRAME
During interframe if optional

status is enabled, then data
on negedge should be the
same as data on posedge.
This check is fired during normal

interframe if optional status indictions are
enabled and RXD on negedge is not the
same as RXD on posedge.
CAR_INDICATION

0x0E on RXD.
While RX_DV is de-asserted, the PHY may

provide a False carrier indication by
asserting the RX_ER signal while driving
0x0E on RXD.
BURST_LIMIT_EXCEEDED
Burst limit is exceeded
The transmitting station is allowed to

initiate frame transmission until a specified
limit specified as burstLimit. This check is
fired when this limit is exceeded.
INCORRECT_EXTN_LENGTH
Extension length is not

correct.
If frame (or first frame in a burst) has length

less than slot time, then it should be
extended with the extension length as
(slotTime-FrameSize).
This check is fired when the number of
extension bits are not correct.
FRAME_DETECTED

frame is detected.
Pause frames are sent by DTEs configured

for Full Duplex operation. This check fires
when pause frame is sent in Half Duplex
mode.
COLLISION_DETECTED
MAC treats any collision that occurs after

the first frame of a burst, or that occurs after
the slotTime has been reached in the first
frame of a burst, as a late collision. This
check is fired when late collision is
detected.
SIZE_NOT_CORRECT

specified JAM_SIZE
parameter bit times.
When a collision is detected during a frame

transmission, the transmission continues for
additional bits corresponding to jam
sequence. This check fires when jam size is
not correct.
Table 8-28. MII Checks

Check ID
Violation
Description
ETHERNET_MII_COLLISION_
DETECTED_WITHOUT_CAR
In Half Duplex mode, a collision

is detected even when there is no
carrier sense.
In Half Duplex mode, the collision

detect signal is driven by the PHY
upon detection of a collision on the
medium. A collision cannot be
detected when there is no carrier
sensed in the medium. This check fires
if the CRS signal is low, indicating
that both transmit and receive
interfaces are idle and COL is asserted,
indicating a collision.
265
Gigabit Ethernet
Monitor Checks
Table 8-28. MII Checks (cont.)

Check ID
Violation
Description
ETHERNET_MII_CRS_
DEASSERTED_
DURING_COLLISION
In Half Duplex mode, carrier

sense should be held high
throughout the collision period.
In the event of a collision, the COL is

asserted by the PHY and is held high
until the collision persists, after which
it is de-asserted. The carrier sense
should also be driven high until the
collision persists. This check fires
when CRS is de-asserted while COL is
high.
ETHERNET_MII_RESERVED_
VALUES_ON_RX_
INTERFACE
Reserved values detected on the

RX_DV is not asserted and
RX_ER is asserted.
Reserved values should not be used on

the receive interface when rx_dv is deasserted and rx_er is asserted. This
check fires when rx_dv is de-asserted
and rx_er is asserted with a reserved
value on rxd. This check is active only
if RESERVED_VALUE_CHECK_
ENABLE is set to 1.
ETHERNET_MII_RESERVED_
VALUES_ON_TX_
INTERFACE
Reserved values detected on the

transmit interface when TX_EN
was not asserted and TX_ER was
asserted.

the transmit interface when TX_EN is
de-asserted and TX_ER is asserted.
This check fires when TX_EN is deasserted and TX_ER is asserted with a
reserved value on txd. This check is
active only if RESERVED_VALUE_
CHECK_ENABLE is set to 1.
ETHERNET_MII_RX_
EXTRA_NIBBLE_
DETECTED
An extra nibble is detected on the

RX interface.
When the frame ends, there should not

be any extra nibble, which cannot be
packed as 8-bit data. The frame should
always contain an even number of
nibbles so that the data is byte aligned.
ETHERNET_MII_RX_
INTERFACE_ACTIVE_
WHEN_TX_ACTIVE
In Half Duplex mode, the receive

interface is non-idle when the
transmit interface is already
active.
In Half Duplex mode, either the

transmit or the receive interface can be
active at any given time and the other
interface should be idle. This check
fires when transmit interface is
detected active when the receive
ETHERNET_MII_RX_
START_WITH_NON_
PREAMBLE_OR_SFD

indicates that a frame reception
has started. A frame reception
must always begin with a
preamble or SFD.
When rx_dv is asserted, the value on

the rxd can only start with preamble or
SFD. This check fires when this is
violated.
ETHERNET_MII_TX_EN_
ASSERTED_WHEN_
CAR_SENSED
In Half Duplex mode, TX_EN

should not be asserted when
carrier sense is high.
In Half Duplex mode, the carrier sense

signal is driven by the PHY when
either the transmit or the receive
interface is non-idle. If the transmit
interface is idle and the carrier sense is
asserted, then it means that the receive
interface is non-idle and the tx_en
should not be asserted until CRS is
sampled low. This check fires if tx_en
is asserted when CRS is high.
266
Gigabit Ethernet
Monitor Checks

Check ID
Violation
Description
ETHERNET_MII_TX_EN_
ASSERTED_WHEN_
COLLISION_DETECTED
In Half Duplex mode, TX_EN

should not be asserted when a
collision is detected.
In Half Duplex mode, the collision

detect signal is driven by the PHY
upon detection of a collision on the
medium, and shall remain asserted
while the collision condition persists.
The transmit interface should not make
an attempt to transmit a frame (assert
TX_EN) during a collision period and
must wait until COL is low. This
check fires if tx_en is asserted when
COL is high.
ETHERNET_MII_TX_
EXTRA_NIBBLE_
DETECTED
An extra nibble is detected on the

TX interface.
When the frame ends, there should not

be any extra nibble, which cannot be
packed as 8-bit data. The frame should
always contain an even number of
nibbles so that the data is byte aligned.
ETHERNET_MII_TX_
INTERFACE_ACTIVE_
WHEN_RX_ACTIVE

already active.

receive or the transmit interface can be
fires when transmit interface is
detected active when the receive
ETHERNET_MII_TX_
START_WITH_NON_
PREAMBLE
When TX_EN is asserted, it

transmission has started. The
frame transmission should always
begin with a preamble.
This check fires whenever tx_en is

asserted, indicating a new frame and
the data is other than preamble
(8'hAA).
ETHERNET_MII_
FRAME
TX_ER is asserted while frame is

being transmitted.
During the frame transmission,

TX_EN is asserted. Assertion of
TX_ER at this moment indicates a
Transmit error propagation.
ETHERNET_MII_
FRAME
RX_ER is asserted while frame is

being transmitted.
During the frame transmission,

RX_DV is asserted. Assertion of
RX_ER at this moment indicates a
Data Reception error.
CAR_INDICATION
RX_ER is asserted with 0x0E on

RXD.
While RX_DV is de-asserted, the PHY

may provide a False carrier indication
by asserting the RX_ER signal while
driving 0x0E on RXD.
FRAME_DETECTED

frame is detected.
Pause frames are sent by DTEs

configured for Full Duplex operation.
This check fires when pause frame is
sent in Half Duplex mode.
COLLISION_DETECTED
MAC treats any collision that occurs

after the first frame of a burst, or that
occurs after the slotTime has been
reached in the first frame of a burst, as
a late collision. This check is fired
when late collision is detected.
267
Gigabit Ethernet
Monitor Checks

Check ID
Violation
Description
SIZE_NOT_CORRECT

specified JAM_SIZE parameter
bit times.
When a collision is detected during a

frame transmission, the transmission
continues for additional bits
corresponding to jam sequence. This
check fires when jam size is not
correct.
Table 8-29. RMII Checks

Check ID
Violation
Description
ETHERNET_RMII_RESERVED_
VALUES_ON_RX_INTERFACE:

the receive interface when the
CRS_DV is not asserted and
RX_ER is asserted.

the receive interface when crs_dv is deasserted and rx_er is asserted. This
check fires when crs_dv is de-asserted
and rx_er is asserted with a reserved
value on rxd. This check is active only
ENABLE is set to 1.
ETHERNET_RMII_RESERVED_
VALUES_ON_TX_INTERFACE

TX_EN was not asserted.

the transmit interface when TX_EN is
not asserted. This check fires when
TX_EN is de-asserted with a reserved
value on txd. This check is active only
ENABLE is set to 1.
ETHERNET_RMII_RX_INTERFACE_
ACTIVE_WHEN_TX_ACTIVE

when the transmit interface is
already active.

transmit or the receive interface can be
fires when transmit interface is detected
active when the receive interface is
already active.
ETHERNET_RMII_RX_START_
WITH_NON_PREAMBLE_OR_SFD
When CRS_DV is asserted, it

indicates that a frame reception
has started. A frame reception
must always begin with a
preamble or SFD.
When crs_dv is asserted, the value on

the rxd can only start with preamble or
SFD. This check fires when this is
violated.
ETHERNET_RMII_TX_INTERFACE_
ACTIVE_WHEN_RX_ACTIVE

already active.
In Half Duplex mode, either the receive

or the transmit interface can be active at
any given time and the other interface
should be idle. This check fires when
transmit interface is detected active
when the receive interface is already
active.
ETHERNET_RMII_TX_START_
WITH_NON_PREAMBLE
When TX_EN is asserted, it

transmission has started. The
always begin with a preamble.
This check fires whenever tx_en is

asserted, indicating a new frame and
the data is other than preamble
(8'hAA).
268
Gigabit Ethernet
Monitor Checks
Table 8-29. RMII Checks (cont.)

Check ID
Violation
Description
ETHERNET_RMII_RX_ER_
ASSERTED_DURING_FRAME
RX_ER is asserted while frame During the frame transmission,

is being transmitted.
CRS_DV is asserted. Assertion of
RX_ER at this moment indicates a Data
Reception error.
ETHERNET_RMII_FALSE_
CAR_INDICATION
RX_ER is asserted with 2'b10

on RXD.
PHY may provide a False carrier

indication at the beginning of a packet
where preamble is decoded (i.e.,
RXD[1:0]=01) while driving 2'b10 on
RXD.
FRAME_DETECTED

frame is detected.
Pause frames are sent by DTEs

configured for Full Duplex operation.
This check fires when pause frame is
sent in Half Duplex mode.
Table 8-30. XGMII Checks

Check ID
Violation
Description
GIGABIT_ETHERNET_XGMII_
IDLE_BEFORE_TERM_
VIOLATION_P
Idle is detected while the

frame is in progress.
Once a frame has started with a Start control

character, it must be terminated with a
Terminate character before sending Idle
characters. This check fires when Idle
characters are detected even before the
frame is terminated.
When the bus is idle, Idle

control characters should
be detected on all lanes.
Idle columns are transmitted in full columns,

except when a Terminate is detected,
wherein only the remaining lanes are Idles.
This check fires when an Idle column is
detected with a non-Idle character.
The column prior to the

column containing start
control character should
have all Idle characters or
a sequence ordered set.
In XGMII, a frame is considered valid only

when it begins with a start control character
aligned to lane 0 with the previous column
being all-idles or a sequence ordered set.
This check fires when a frame violates this
requirement.
IDLE_BEFORE_TERM_
VIOLATION_N
IDLE_COLUMN_VIOLATION_P
IDLE_COLUMN_VIOLATION_N
NON_IDLE_OR_SEQ_PRIOR_TO_
START_P
NON_IDLE_OR_SEQ_PRIOR_TO_
START_N
269
Gigabit Ethernet
Monitor Checks
Table 8-30. XGMII Checks (cont.)

Check ID
Violation
Description
RSVD_CONTROL_CHAR_
VIOLATION_P
Reserved control
characters should not be
used.
TXC/RXC indicate whether data or control

characters are being transmitted/received.
The TXC signal for a lane is asserted when a
control character is being sent. In XGMII,
only 5 characters are defined: Idle, Start,
Terminate, Error, and Sequence. All other
encodings are reserved. This check fires
when a reserved encoding is detected.
When Error Control

character is detected on Rx
lanes.
An Error Control Character should not be

present on Rx lanes while a frame is in
progress. This check fires when this
The sequence control

character should be
aligned to lane 0.
Status is signaled through a four byte

Sequence ordered set, with the sequence
control character on lane 0 and data on the
remaining three lanes. The sequence control
character must be aligned to lane 0. This
check fires if this requirement is violated.
The sequence ordered set

should not contain
reserved values.
The PHY indicates Local Fault with a

Sequence control character in lane 0, data
characters of 0x00 in lanes 1 and 2, and a
data character of 0x01 in lane 3.
The RS indicates a Remote Fault with a
characters of 0x00 in lanes 1 and 2, and a
data character of 0x02 in lane 3.
All other values are reserved for future use
and are not to be used. This check fires when
a Sequence ordered set contains a reserved
value.

should be aligned to lane
3.
The preamble and SFD are transmitted

through the XGMII as octets sequentially
ordered on the lanes of the XGMII. If a start
control character is detected on lane 0 in the
previous clock edge, then the start frame
delimiter should be detected on lane 3. This
check fires if SFD is detected on any lane
other than lane 3.
RSVD_CONTROL_CHAR_
VIOLATION_N
RX_ERROR_CONTROL_
CHARACTER_DETECTED_P
RX_ERROR_CONTROL_
CHARACTER_DETECTED_N
SEQUENCE_ALIGNMENT_
VIOLATION_P
SEQUENCE_ALIGNMENT_
VIOLATION_N
SEQUENCE_OS_
VIOLATION_P
SEQUENCE_OS_
VIOLATION_N
SFD_ALIGNMENT_
VIOLATION_P
SFD_ALIGNMENT_
VIOLATION_N
270
Gigabit Ethernet
Monitor Checks
Table 8-30. XGMII Checks (cont.)

Check ID
Violation
Description
START_ALIGNMENT_
VIOLATION_P
The start control character

0.
The Start control character indicates the

beginning of MAC data on the XGMII. The
start control character must be aligned to
lane 0 of the XGMII by the RS on transmit
and by the PHY on receive. This check fires
if a Start control character is detected on any
lane other than lane 0.
A start control character

for a new frame should not
be issued before
terminating previous
frame.
A new frame can begin only after the end of

current frame. Since the end of frame is
indicated by a Terminate character, a start
character for a new frame should follow a
terminate for the current frame. This check
fires when successive starts are detected
without an intervening terminate.
The terminate control

character should follow a
start control character.
Terminate control character on any lane

constitutes an end of frame delimiter for the
data stream. A terminate should not be
issued before a frame and should always
follow a start control character. This check
fires when a terminate control character is
detected before the start control character.
When Terminate is
detected, all lanes
following the terminate
character should carry idle
control character.
A terminate should be followed by idle

characters. If terminate is not in lane 3, then
all the lanes following the terminate should
be idle characters. This check fires when this
When Error Control

character is detected on Tx
lanes.

present on Tx lanes while a frame is in
START_ALIGNMENT_
VIOLATION_N
START_BEFORE_TERM_
VIOLATION_P
START_BEFORE_TERM_
VIOLATION_N
TERM_BEFORE_START_
VIOLATION_P
TERM_BEFORE_START_
VIOLATION_N
TERMINATE_COLUMN_
VIOLATION_P
TERMINATE_COLUMN_
VIOLATION_N
TX_ERROR_CONTROL_
CHARACTER_DETECTED_P
TX_ERROR_CONTROL_
CHARACTER_DETECTED_N
271
Gigabit Ethernet
Monitor Checks
Table 8-31. XLGMII/CGMII Checks

Check ID
Violation
Description
GIGABIT_ETHERNET_
XLGMII_CGMII_START_
ALIGNMENT_VIOLATION
The start control

character should be
aligned to lane 0.
The Start control character indicates the

beginning of MAC data on the
XLGMII/CGMII. The start control character
must be aligned to lane 0 of the
XLGMII/CGMII by the RS on transmit and by
the PHY on receive. This check fires if a Start
control character is detected on any lane other
than lane 0.
GIGABIT_ETHERNET_
XLGMII_CGMII_SFD_
ALIGNMENT_VIOLATION

7.
The preamble and SFD are transmitted through

the XLGMII/CGMII as octets sequentially
ordered on the lanes of the XLGMII/CGMII. If
a start control character is detected on lane 0,
then the start frame delimiter should be
detected on lane 7. This check fires if SFD is
detected on any lane other than lane 7 or no
SFD detected on lane 7.
GIGABIT_ETHERNET_
XLGMII_CGMII_SEQUENCE_
ALIGNMENT_VIOLATION
The sequence control

character should be
aligned to lane 0.
Status is signaled through an eight byte

Sequence ordered set, with the sequence
control character on lane 0 and data on the
remaining 7 lanes. The sequence control
character must be aligned to lane 0. This check
fires if this requirement is violated.
GIGABIT_ETHERNET_
XLGMII_CGMII_SEQUENCE_
OS_VIOLATION
The sequence ordered set The PHY indicates Local Fault with a
should not contain
reserved values.
characters of 0x00 in lanes 1 and 2, a data
character of 0x01 in lane 3, and a 0x00 on
lanes 4 to 7.
The RS indicates a Remote Fault with a
characters of 0x00 in lanes 1 and 2, a data
character of 0x02 in lane 3, and a 0x00 on
lanes 4 to 7.
All other values are reserved for future use and
are not to be used. This check fires when a
Sequence ordered set contains a reserved
value.
GIGABIT_ETHERNET_
XLGMII_CGMII_TERM_
BEFORE_START_VIOLATION
The terminate control

Terminate control character on any lane
character should follow a constitutes an end of frame delimiter for the
start control character.
data stream. A terminate should not be issued
before a frame and should always follow a start
control character. This check fires when a
terminate control character is detected before
the start control character.
GIGABIT_ETHERNET_
XLGMII_CGMII_START_
BEFORE_TERM_VIOLATION

for a new frame should
not be issued before
terminating previous
frame.
272
A new frame can begin only after the end of

the current frame. Since the end of frame is
indicated by a Terminate character, a start
character for a new frame should follow a
terminate for the current frame. This check
fires when successive starts are detected
without an intervening terminate.
Gigabit Ethernet
Monitor Checks
Table 8-31. XLGMII/CGMII Checks (cont.)

Check ID
Violation
Description
GIGABIT_ETHERNET_
XLGMII_CGMII_IDLE_
BEFORE_TERM_VIOLATION
Idle was detected while

the frame is in progress.
Once a frame has started with a Start control

character, it must be terminated with a
Terminate character before sending Idle
characters. This check fires when Idle
characters are detected even before the frame is
terminated.
GIGABIT_ETHERNET_
XLGMII_CGMII_RSVD_
CONTROL_CHAR_
VIOLATION
Reserved control
used.
TXC/RXC indicate whether data or control

characters are being transmitted/received. The
TXC signal for a lane is asserted when a
control character is being sent.
In XLGMII/CGMII, only 5 characters are
defined: Idle, Start, Terminate, Error, and
Sequence. All other encodings are reserved.
This check fires when a reserved encoding is
detected.
GIGABIT_ETHERNET_
XLGMII_CGMII_IDLE_
COLUMN_VIOLATION
When the bus is idle, Idle Idle columns are transmitted in full columns,
control characters should except when a Terminate is detected, wherein
be detected on all lanes. only the remaining lanes are Idles.
This check fires when an Idle column is
detected with a non-Idle character.
GIGABIT_ETHERNET_
XLGMII_CGMII_TERMINATE_
COLUMN_VIOLATION
When Terminate is
detected, all lanes
following the terminate
character should carry
idle control character.
GIGABIT_ETHERNET_
XLGMII_CGMII_TX_ERROR_
CONTROL_CHARACTER_
DETECTED
Error control character is An Error Control Character should not be

detected on Tx interface. present on Tx lanes while a frame is in
GIGABIT_ETHERNET_
XLGMII_CGMII_RX_ERROR_
CONTROL_CHARACTER_
DETECTED
Error control character is An Error Control Character should not be

detected on Rx interface. present on Rx lanes while a frame is in
A terminate should be followed by idle

characters. If terminate is not in lane 7, then all
the lanes following the terminate should be
idle characters. This check fires when this
Table 8-32. TBI Checks

Check ID
Violations
GIGABIT_ETHERNET_TBI_
INVALID_10B_CG
Detected an invalid 10B code- Invalid 10B code-group that cannot be

group.
decoded into 8b.
DISPARITY_ERROR_IN_K_CG
Disparity error in /K/ codegroup detected.
/K/code detected has wrong disparity.
DISPARITY_ERROR_IN_D_CG
Disparity error in /D/ codegroup detected.
/D/ code detected has wrong disparity.
Descriptions
273
Gigabit Ethernet
Monitor Checks
Table 8-32. TBI Checks (cont.)

Check ID
Violations
Descriptions
LOSS_OF_SYNC
Synchronization lost on lane.
After achieving synchronization, it has

been lost on bus.
T_NOT_FOLLOWED_BY_R_
VIOLATION
The terminate code-group /T/

should be followed by /R/
code-group.
Terminate code group /T/ sequence /T/R/ is

not correct.
MULTI_OS_FIRST_CG_
VIOLATION
First code-group of
multigroup ordered set should
be transmitted on even
position.
First Code group of multigroup ordered set

must be on even position.
EPD_OS_VIOLATION
In End of Packet (EPD), /T/

EPD rule violation. It should be either
must be followed by /R/R/ if
/T/R/ or /T/R/R/ if first /R/ is on even
first /R/ ends on even position. position.
R_CG_VIOLATION
Code-group /R/ should follow

either /R/ or /T/ code-group.
Code-group /R/ occurrence violation. It

should be present either in carrier extension
or EPD.
INVALID_CG_AFTER_K28_5
Code-group other than /D5.6/,

/D16.2/, /D21.5/, and /D2.2/
detected after /K28.5/.
Invalid code-group i.e., non-idle nonconfiguration code-group.
FIRST /I/ followed the packet

INVALID_IDLE_OS_AFTER_PKT should restore negative
running disparity.
/I1/ and /I2/ occurrence violation. /I1/

should be there if running disparity at end
is positive, else /I2/ to maintain running
disparity negative.
INVALID_IDLE_OS_AFTER_
CONFIGURATION_OS
FIRST /I/ followed the

configuration ordered set
should restore negative
running disparity.
/I1/ and /I2/ occurrence violation after

configuration. /I1/ should be there if
running disparity at end is positive, else /I2/
to maintain running disparity negative.
T_BEFORE_S_VIOLATION
/T/ code-group should not

come before /S/ code-group.
Terminate code-group /T/ should be there

only when frame ends.
MISALIGNED_D_CG
/D/ code-group is found at

invalid location.
/D/ code-group not a part of frame, IDLE,

or Configuration.
ERROR_OS_DETECTED_
DURING_FRAME
Error /V/ code-group detected

while frame in progress.
/V/ code-group found in frame.
ERROR_OS_DETECTED_
DURING_IDLE
Error /V/ code-group detected

during idle.
/V/ code-group found in IDLE.
INVALID_I_OS
Subsequent /I/ should be /I2/

to ensure negative running
disparity.
When /I/ is in progress then if running

disparity is negative, then /I/ should be /I2/
to maintain negative running disparity.
SPD_NOT_BEFORE_I_OR_R_OS
SPD /S/ should follow either

/I/ or /R/ ordered set.
Start of packet delimiter /S/ should come

only after IDLE or in Burst frame.
Invalid configuration ordered

INVALID_CONFIGURATION_OS set detected.
Configuration Ordered set not transferred

with /D/ code group defined.
274
Gigabit Ethernet
Monitor Checks
Table 8-32. TBI Checks (cont.)

Check ID
Violations
Descriptions
RESERVED_K_CG_DURING_
FRAME
Reserved /K/ code-group

detected during frame.
Reserved value of /K/ codes detected in

frame.
RESERVED_K_CG_DURING_
IDLE
Reserved /K/ code-group

detected during idle.
Reserved value of /K/ codes detected

during IDLE.
DISPARITY_NEUTRAL_000111_
ERROR
Sub-blocks encoded as
000111 should be generated
only when the running
disparity at the beginning of
the sub-block is positive.
The 8B/10B transmission code rules

specify that the sub-blocks encoded as
000111b or 0011b are generated only when
the running disparity at the beginning of the
sub-block is positive. The monitor fires
when this is violated.
ERROR
the sub-block is negative.

sub-block is negative. The monitor fires
ERROR
Sub-blocks encoded as 0011

should be generated only
when the running disparity at
the beginning of the sub-block
is positive.

sub-block is positive. The monitor fires
ERROR
Sub-blocks encoded as 1100

should be generated only
when the running disparity at
the beginning of the sub-block
is negative.

sub-block is negative. The monitor fires
Table 8-33. XAUI Checks

Check ID
Violation
Description
GIGABIT_ETHERNET_XAUI_
10B_CODE_VIOLATION_P
Detected an invalid 10B

code group.
Valid 10B symbols should be detected on the

lanes. If the detected 10B code group does not
correspond to either (+ve or -ve running
disparity) column, then the symbol is
considered to be invalid. This check fires if an
invalid 10B code group is detected on the lane.
10B_CODE_VIOLATION_N
275
Gigabit Ethernet
Monitor Checks
Table 8-33. XAUI Checks (cont.)

Check ID
Violation
Description
ALIGN_COL_VIOLATION_P
In an Align column, all

the code-groups should
be K28.3.
Idle ordered sets (||I||) are transmitted in full

columns continuously and repetitively
whenever the XGMII is idle. If one of the lanes
carries a Align character, then all the lanes in
that column must carry Align characters. This
check fires when an Align character is detected
on at least one lane but not on all lanes.
The first ||I|| following

||T|| should not be ||A||
and should alternate
between ||A|| and ||K||.
The first ||I|| following ||T|| alternates between

||A|| or ||K||. This check fires when an ||A||
column is detected when ||K|| was expected.
Data character(s)
detected during idle
period between frames.
Once a frame has been terminated, the inter

frame gap until the start of next fame should be
filled with Idle. This check fires when a data
character is detected between two frames.
Disparity error detected.
The incoming 10B symbol may not be found in

the column being searched (as indicated by the
disparity). However, this would result in
disparity errors. This check fires for legal codes
that violate disparity.
Subblocks encoded as
000111 should be
generated only when the
running disparity at the
beginning of the subblock
is positive.
The 8B/10B transmission code rules specify

that the subblocks encoded as 000111b or
0011b are generated only when the running
disparity at the beginning of the subblock is
positive. The monitor fires when this is
violated.
disparity at the beginning
of the subblock is
positive.

violated.
ALIGN_COL_VIOLATION_N
ALIGNS_AFTER_SUCCESSIVE_
TERM_P
ALIGNS_AFTER_SUCCESSIVE_
TERM_N
DATA_CHAR_DURING_IDLE_P
DATA_CHAR_DURING_IDLE_N
DISPARITY_ERROR_P
DISPARITY_ERROR_N
ERROR_P
ERROR_N
ERROR_P
ERROR_N
276
Gigabit Ethernet
Monitor Checks

Check ID
Violation
Description
ERROR_P
disparity at the beginning
of the subblock is
negative.

negative. The monitor fires when this is
violated.
111000 should be
beginning of the subblock
is negative.

violated.
When error control

character is present on
bus while frame is in
progress.

present on bus while a frame is in progress.
violated.
When error control

character is present on
bus while interframe in
progress.

present on bus while a interframe gap is in
Control character other

than Terminate,
Sequence, or Error
detected during a frame.
The defined control characters are Start,

Terminate, Idle, Error, Sequence (used for fault
signalling). Of these, once a frame has
commenced, then the only legal control
characters are Terminate, Sequence, and Error.
This check fires when a control character other
than these is detected during frame reception.
Reserved control
detected during idle.
When no frame is in progress (during idle

period), the legal control characters are Start,
Terminate, Idle, Error, and Sequence. This
check fires when a control character other than
these is detected during idle.
ERROR_N
ERROR_P
ERROR_N
ERROR_CTRL_CHAR_DURING_
FRAME_P
FRAME_N
IDLE_P
IDLE_P
INVALID_CTRL_CHAR_DURING_
FRAME_P
FRAME_N
IDLE_P
IDLE_N
277
Gigabit Ethernet
Monitor Checks

Check ID
Violation
Description
LOSS_OF_ALIGNMENT_P
When Alignment is lost

on bus.
||A|| column should be received on all lanes in

parallel. If any /A/ is received but not on all
lanes consecutively for 4 times, then this check
is fired.
When Synchronization is
lost on bus.
Four continuos invalid symbol should not be

received for proper synchronization. This check
No more than a
maximum of 31 non-||A||
columns should be
detected between two
||A|| columns.
The Align or ||A|| ordered_set consists of a

unique special code-group, also known as Align
or /A/ in each lane. /A/ is not used in any other
ordered_set. Each ||A|| is sent after r non-||A||
columns where r is a uniform randomly
distributed number between 16 and 31,
inclusive. This check fires when the two ||A||
violate the maximum |A|| interval requirements.
A minimum of 16 non||A|| columns should be

detected between two
||A|| columns.
The Align or ||A|| ordered set consists of a

unique special code-group, also known as Align
or /A/ in each lane. /A/ is not used in any other
ordered_set. Each ||A|| is sent after r non-||A||
columns where r is a uniform randomly
distributed number between 16 and 31,
inclusive. This check fires when two ||A|| did
not meet the minimum interval requirements.
The ||T|| should be

followed by an ||A|| or
||K|| in the next column.
The first ||I|| following the terminate column is

always an ||A|| or ||K||. This check fires when
the column that immediately follows a
terminate is neither an ||A|| nor a ||K||.
The second ||I|| following

a ||T|| should be an ||R|| or
||Q||.
The ||R|| (Skip ordered set) is included in the

PCS Idle sequence to allow for clock rate
compensation in the case of multiple clock
domains. ||R|| can be inserted anywhere in the
Idle stream starting with the second column
following the terminate column ||T||. Given that
an ||A|| can come on the first clock after ||T||, the
second clock after a ||T|| can be a ||Q|| since a
||Q|| has to follow an ||A||. This check fires when
the second column that follows a terminate is
neither an ||R|| nor a ||Q||.
LOSS_OF_ALIGNMENT_N
LOSS_OF_SYNC_P
LOSS_OF_SYNC_N
MAX_ALIGN_SPACING_
VIOLATION_P
MAX_ALIGN_SPACING_
VIOLATION_N
MIN_ALIGN_SPACING_
VIOLATION_P
MIN_ALIGN_SPACING_
VIOLATION_N
NON_ALIGN_OR_SYNC_AFTER_
TERM_P
NON_ALIGN_OR_SYNC_AFTER_
TERM_N
SECOND_COL_FROM_TERM_
NOT_SKP_OR_SEQ_P
SECOND_COL_FROM_TERM_
NOT_SKP_OR_SEQ_N
278
Gigabit Ethernet
Monitor Checks

Check ID
Violation
Description
SEQUENCE_ALIGNMENT_
VIOLATION_P
A sequence control
character should not be
placed on any lane other
than lane zero.
The Sequence or ||Q|| ordered set directly maps

to the XGMII Sequence control character on
lane 0 followed by three data characters in
XGMII lanes 1 through 3. ||Q|| indicates to the
PCS that a link status message has been
initiated. This check fires whenever a Sequence
control character is detected on a lane other
than 0.
A ||Q|| should always

follow an ||A||.
Sequence ordered-sets are always sent over the

PMA service interface in the column that
follows an ||A|| ordered set. The Sequence
ordered-sets do not otherwise interfere with the
randomized ||I|| sequence. This check fires
when a ||Q|| follows a non-||A|| column.
Lane to lane skew should

not be greater than the
maximum limit of 41BT.
The definition of a 10GBASE-X ordered set

guarantees that align code groups are
simultaneously initiated on all lanes at the
transmitter and the maximum allowable lane to
lane skew at the receive interface is 41 BTs.
This check fires when the skew at the receive
interface exceeds this maximum limit.
In a Skip column, all the

code-groups should be
K28.0.

carries a Skip character, then all the lanes in
that column must carry Skip characters. This
check fires when a Skip character is detected on
at least one lane but not on all lanes.

should not be placed on
any lane other than lane
zero.
The Start or ||S|| ordered set directly maps to the

XGMII Start control character in lane 0
followed by any three data characters in XGMII
lanes 1 through 3. This check fires when a start
control character is detected on a lane other
than lane 0.
In a Sync column, all the

code-groups should be
K28.5.

carries a Sync character, then all the lanes in
that column must carry Sync characters, except
for the column in which a terminate is detected
(here it is a partial column of Sync characters).
This check fires when a Sync character is
detected on at least one lane but not on all
lanes.
SEQUENCE_ALIGNMENT_
VIOLATION_N
SEQUENCE_NOT_FOLLOWING_
ALIGN_P
SEQUENCE_NOT_FOLLOWING_
ALIGN_N
SKEW_LIMIT_VIOLATION_P
SKEW_LIMIT_VIOLATION_N
SKIP_COL_VIOLATION_P
SKIP_COL_VIOLATION_N
START_ALIGNMENT_
VIOLATION_P
START_ALIGNMENT_
VIOLATION_N
SYNC_COL_VIOLATION_P
SYNC_COL_VIOLATION_N
279
Gigabit Ethernet
Monitor Checks

Check ID
Violation
Description
SYNCS_AFTER_SUCCESSIVE_
TERM_P
The first ||I|| following

||T|| should not be ||K||
and should alternate
between ||A|| and ||K||.
The first ||I|| following ||T|| alternates between

||A|| or ||K||, except if an ||A|| is to be sent and
the ||A|| spacing counter has not expired, then a
||K|| is sent instead. This check fires when a ||K||
column is detected when ||A|| was expected.
The terminate code-group

should be followed by
sync code-groups in that
column.
The Terminate or ||T|| ordered set directly maps

to the XGMII Terminate control character
located in any lane, preceded by data characters
and followed by Idle characters if Terminate is
not in lane 3. These Idle characters must be
Sync characters. This check fires when the
terminate character is followed by a non-Sync
character in that column.
SYNCS_AFTER_SUCCESSIVE_
TERM_N
TERMINATE_OS_ERROR_P
TERMINATE_OS_ERROR_N
Table 8-34. BASER Checks

Check ID
Violation
Description
GIGABIT_ETHERNET_BASER_ Block type field should be

defined.
INVALID_BLOCK_TYPE
The control blocks begin with an 8-bit

block type field that indicates the format
of the remainder of the block. The block
type is a standard defined value,
depending on the contents of the block.
This check fires when an undefined value
is detected on the block type field.
GIGABIT_ETHERNET_BASER_ Control blocks of type 0x1E

should contain codes of either
INVALID_CTRL_CODE_
Idle or Error control characters.
TYPE_1E
The 10GBASE-R family of PHYs use the

64B/66B encoding scheme where every
64 bits of data is converted to either a
data block or a control block. A control
block with block type of 8'h1E should
have all 8 control characters and must be
used only for encoding idle or error
control characters. This check fires when
other control codes are tagged with this
block type.
GIGABIT_ETHERNET_BASER_
INVALID_O_CODE_
VIOLATION
280
The O-Code that encodes the /Q/

control character should be
encoded with all zeros or all
ones.
In 64B/66B encoding scheme, ordered

sets are encoded using a 4-bit O code.
The ||Q|| (sequence ordered set) is
encoded using an O-code of 4'b0. This
check fires when a ||Q|| is encoded with a
nonzero O-code value.
Gigabit Ethernet
Monitor Checks
Table 8-34. BASER Checks (cont.)

Check ID
Violation
Description
GIGABIT_ETHERNET_BASER_ Synchronization header should

be either 2'b01 or 2'b10.
INVALID_SYNC_HEADER
In 64B/66B encoding scheme, 64-bits of

data is converted into one 66B block. The
lowest order two bits, called the
synchronization header, indicates
whether what follows is a data or a
control block. In addition, the
synchronization headers of the code
enable the receiver to achieve block
alignment on the incoming PHY bit
stream. The allowed values for sync
header are 2'b01 and 2'b10. This check
fires when a sync header contains 2'b00
or 2'b11.
GIGABIT_ETHERNET_BASER_ The null fields in a 66b block

should be encoded with zero on
NULL_VALUE_VIOLATION
transmit.
In the case of control blocks containing a

Start or Terminate character, that
character is implied by the block type
field. In these blocks, some bits are
unused and are null fields. These are sent
as zero and ignored upon receipt. This
check fires if these are nonzero on a
transmit interface.
GIGABIT_ETHERNET_BASER_ The control codes following a

TERMINATE_BLOCK_ERROR terminate character in a 66b
block should be zeros, indicating
Idles.
A terminate character must be followed

by idle control characters in all the lanes
in that column. This check fires when a
Terminate block has non-Idle control
codes on any of the lanes following the
terminate character.
GIGABIT_ETHERNET_BASER_ Block contains error control

character.
BLOCK_CONTAINS_ERROR_
CONTROL_CHARACTER
This check is fired whenever error code

for /E/ is found on the bus.
GIGABIT_ETHERNET_BASER_ Block contains reserved control

character.
BLOCK_CONTAINS_
RESERVED_CONTROL_
CHARACTER
This check is fired whenever control

character reserved0, reserved1,
reserved2, reserved3, reserved4, or
reserved5 is found on the bus.
This check is not valid for XLAUI/CAUI
interfaces.
START_OR_IDLE_BLOCK_
EXPECTED
Block after an idle control block

reception is not a start control
block, Idle block and ordered set
control block.
While idle control blocks are being

received, only start control block, Idle
block, and ordered set control block
should follow. This check is fired when
this requirement is violated.
TERMINATE_OR_CONTROL_
BLOCK_EXPECTED
Control block other than

terminate block or Error is
received during transmission of
data blocks.
While data blocks are being received,

only terminate block and Error Control
Blocks would be possible valid blocks.
This check fires when some other control
block is received.
INVALID_CONTROL_
CHARACTER
Control character contains a

value other than 0x00, 0x1e,
0x2d, 0x33, 0x4b, 0x55, 0x66, or
0x78 (Section 49.2.4.6).
Control character should be among one of

the values: 0x00, 0x1e, 0x2d, 0x33, 0x4b,
0x55, 0x66,or 0x78 else the block is
invalid. This check is fired whenever
block contains a control character with
some other value.
281
Gigabit Ethernet
Monitor Checks
Table 8-34. BASER Checks (cont.)

Check ID
Violation
Description
GIGABIT_ETHERNET_BASER_ Sequence OS should not be

reserved values.
SEQUENCE_OS_VIOLATION
A sequence should have valid values.

This check is fired when this requirement
is not met.
GIGABIT_ETHERNET_BASER_ Bits 65:38 of ordered set block

should contain all zeros.
NON_ZERO_BITS_IN_O_
ORDERED_SET_P
This check is fired when bits 65 to 38 of

ordered set block is non-zero. This check
is only valid for XLAUI/ CAUI interface.
Table 8-35. XLAUI/CAUI Checks

Check ID
Violation
Description
AM_INVLD_CNT_4
Four consecutive invalid

alignment marker received.
This check fires when am_invld_cnt

reaches 4 value and transitions from
INVALID_AM to SLIP state. This
represents the loss of AM lock.
AM_COUNTER_EXPIRED
Alignment marker not received This check fires when alignment marker
after am_counter reached
not received after am_counter expires.
maximum value.
This check not valid for first alignment
marker after AM_RESET_CNT state.
AM_BIP_ERROR
BIP error in received

alignment marker.
This check fires when expected BIP is

not present in received alignment
marker. This check is not valid for first
alignment marker after
AM_RESET_CNT state.
AM_NOT_MATCHING
Alignment marker not

matching previous alignment
marker value on lane.
This check fires when dynamic lane

reorder happens. For example, if AM0
received on physical lane 0 first time and
then on physical lane 2 next time, this
check fires.
AM_BIP_ON_M3_NOT_
MATCHING_BIP_ON_M7
BIP on position M3 is not

inversion of BIP on M7 in a
received alignment marker.
BIP7 is simply bit-wise inversion of

BIP3. This check fires if above rule is
violated.
SH_INVLD_CNT_MAX
Sync header invalid count

reached maximum value.
This check fires when sh_invld_cnt

reaches 65 value and transitions from
INVALID_SH to SLIP state. This
represents the loss of lane lock.
LANE_LOCK_FAIL_AFTER_
MAX_SLIP
Block lock not achieved after

maximum number of slip (64).
A receiving device should synchronize

to proper boundary within first 64 slips.
This check fires when lane lock is not
achieved within the first 64 slips.
SKEW_MORE_THAN_MAX
Skew among lanes reached

maximum configured skew.
This check fires when skew among lanes

crosses a value of 1856 bits (29
symbols) in case of XLAUI and 928 (15
symbols) in case of CAUI.
282
Gigabit Ethernet
Monitor Checks
Table 8-35. XLAUI/CAUI Checks (cont.)

Check ID
Violation
Description
AM_ON_FEWER_LANES_
AFTER_DSKEW_DONE
Alignment marker not received This check fires when there are
on all lanes after deskew done. alignment marker on at least one lane but
not on all lane. This check is not valid
for first alignment marker after
AM_RESET_CNT state.
PARAM_PHYSICAL_LANE_
COUNT_ERR
Illegal value specified for

physical lane count parameter.
This is parameter check. Valid values

are:
XLAUI: 1, 2, and 4.
CAUI: 1, 2, 4, 5, 10, and 20.
This check fires if different value is set
for PHYSICAL_LANE_COUNT
parameter.
Table 8-36. 40/100G Auto-Negotiation Checks

Check ID
Violation
Description
GIGABIT_ETHERNET_AN_
MANCHESTER_DELIMITER_
VIOLATION
Manchester delimiter duration in

DME data should be valid.
Once the synchronization for DME

pages is achieved, Manchester
violation delimiter should be valid.
CLOCK_TRANSITION_
VIOLATION
Clock to clock transition in DME

data should be in prescribed
limits.
Clock transition not received within

maximum specified duration.
DATA_TRANSITION_
VIOLATION
Data to data transition in DME

data should be in prescribed
limits.
After a clock transition, data transition

should happen within the specified
duration range.
RSVD_OR_UNSUPPORTED_
ELECTOR_FIELD
Reserved or unsupported selector

field transmitted.
The selector field in link codeword

S[4:0] should be 00001 corresponding
to IEEE Std 802.3. Any other field
value shall be treated as a violation.
GIGABIT_ETHERENT_AN_
NON_ZERO_ECHOED_
NONCE_FIELD_WITH_ZERO_
ACK
Echoed nonce field transmitted is

non-zero while Acknowledge bit
is set to logical zero.
When Acknowledge is set to zero in

base link codeword, the bits in Echoed
nonce field should contain logical
zeros.
ECHOED_NONCE_DOES_
NOT_MATCH_TX_NONCE_
FROM_LP
Echoed nonce does not match

When Acknowledge is set to one in
nonce transmitted by link partner. base link codeword, the bits in Echoed
nonce field should contain the value
received from link partner.
NON_ZERO_RSVD_TECH_
ABILITY_FIELD
Reserved technology ability field

bits transmitted are non-zero.
Reserved Technology ability field bits

should be transmitted as zero.
283
Gigabit Ethernet
Monitor Checks

Check ID
Violation
Description
FEC_REQUESTED_WITH_
NO_ABILITY
FEC request sent by local device

without ability field set to one.
The FEC requested bit may be set to

logical one only if FEC ability bit is
set to logical one.
NULL_MESSAGE_CODE_
NOT_TRANSMITTED
Next page transmitted without

NULL message code even with
NP bit set to logical zero in
previous link codeword.
If a device has no next pages to send

and its link partner has set the NP bit
to logical one, it should transmit next
pages with NULL message code.
MP_BIT_UNSET_DURING_
NULL_MESSAGE_CODE
MP bit is set to logical zero in

next page transmitted with NULL
message code.
If a device has no next pages send and

its link partner has set the NP bit to
logical one, it should transmit message
next pages with MP bit set.
NULL_HCD_RESOLVED
On Auto-Negotiation completion, On entering AN GOOD CHECK state,

resolved HCD has value NULL. the resolved HCD technology happens
to be NULL. Although this is not a
protocol violation, this check is kept
for integrity.
NON_NULL_MESSAGE_
CODE_TRANSMITTED_
AFTER_NULL_MESSAGE_
CODE
Next page transmitted has non

NULL message code while
previous codeword has NULL
message code.
If a device has no next pages to send

and its link partner has set the NP bit
to logical one, it should transmit next
pages with NULL message code. All
following message codes should
contain NULL message code.
NP_BIT_SET_AFTER_NP_
BIT_UNSET
Next page transmitted with NP

set to logical one while previous
codeword has NP bit set to logical
zero.
If a device has no next pages to send,

it shall set NP bit to logical zero. This
check is fired if any subsequent page
contains NP bit set to logical one.
Toggle bit inverted even when

TOGGLE_BIT_TRANSMITTED_ NEXT PAGE WAIT has not
reached.
INVERSED
The toggle bit is inverted only during

a transition from COMPLETE
ACKNOWLEDGE state to NEXT
PAGE WAIT state. This check is fired
if toggle bit is inverted in any other
state.
NUMBER_OF_ACK_PAGES_
OUT_OF_RANGE
Number of codewords
transmitted in COMPLETE
ACKNOWLEDGE state is out of
range.
While in COMPLETE
ACKNOWLEDGE state, number of
frames transmitted should be from 6 to
8. This check is fired if the number of
frames fall out of this range
DISSIMILAR_PAGE_
TRANSMITTED
Current link codeword

transmitted should be the same as
previous link codeword.
The transmitted frame changes its

value only when either Acknowledge
bit is set during ACKNOWLEDGE
DETECT state or in the first
transmitted frame during NEXT
PAGE WAIT state. This check is fired
if transmitted frame changes in cases
excluding the mentioned ones.
284
Gigabit Ethernet

Check ID
Violation
Description
INVALID_ACK_BIT_
TRANSMISSION
Acknowledge bit transmitted has

an invalid value in current
transmitted codeword.
Acknowledge bit value transmitted

should be 1'b1 in ACKNOWLEDGE
DETECT and COMPLETE
ACKNOWLEDGE state only. It
should be switched to 1'b0 (when
toggle bit also toggles) when
switching to NEXT PAGE WAIT
state.
PAGE_DETECTED_AFTER_
AUTONEG_COMPLETION
Page detected after auto

negotiation completion.
On entering AN GOOD CHECK state,

AN frame should not be detected until
the break_link_timer is done.

Table 8-37 shows the corner cases maintained by the Gigabit Ethernet monitor.
Table 8-37. Gigabit Ethernet Corner Cases
Corner Case
Description
66-bit blocks with terminate on octet 0
Number of 66-bit blocks with terminate on octet 0. This is

collected only by the BASER monitor.







Align ordered sets
Number of align ordered sets. This is collected only by the

XAUI monitor.
Blocks starting on octet 4 with an ordered set

on the first four octets
Number of blocks starting on octet 4 with an ordered set on the

first four octets. This is collected only by the BASER monitor.
This is not valid for XLAUI/CAUI interfaces.
285
Gigabit Ethernet
Table 8-37. Gigabit Ethernet Corner Cases (cont.)

Corner Case
Description
Blocks starting on octet 4 with idle on the first

four octets
Number of blocks starting on octet 4 with idle on the first four

octets. This is collected only by the BASER monitor.
This is not valid for XLAUI/CAUI interfaces.
Alignment marker blocks
Number of alignment marker received. This is only valid for

40/100G.
Blocks with start on octet 0
Number of blocks with start on octet 0. This is collected only

by the BASER monitor.
Carrier extensions
Number of carrier extensions. This is collected only by the

GMII monitor.
Collisions
Number of collisions. This is collected only by the GMII and

MII monitors.
Control frames
Number of control frames.
Data frames
Number of data frames.
Error blocks
Number of error blocks. This is collected only by the BASER

monitor.
False carriers
Number of false carriers. This is collected only by the GMII

and MII monitors.
Frame bursts
Number of back-to-back frames without idle in between. This

is collected only by the GMII monitor.
Frames with globally administered addresses
Number of frames with globally administered addresses.
Frames with individual addresses
Number of frames with individual addresses.
Frames with locally administered addresses
Number of frames with locally administered addresses.
Frames with multicast/group addresses
Number of frames with multicast/group addresses.
Frames with terminate on lane 0
Number of frames with terminate on lane 0. This is collected

only by the XLGMII/CGMII and XGMII monitors.




only by the XLGMII/CGMII monitors.



Idle blocks
Number of idle blocks. This is collected only by the BASER

monitor.
286
Gigabit Ethernet
Monitor Statistics
Table 8-37. Gigabit Ethernet Corner Cases (cont.)

Corner Case
Description
Jumbo data frames
Number of jumbo data frames.
Local faults
Number of local faults. This is collected only by the XGMII

monitor.
Packets of max_frame_size
Number of packets of max_frame_size.
Packets of min_frame_size
Number of packets of min_frame_size.
Packets with padding
Number of packets with padding.
Priority tagged data frames
Number of priority tagged data frames.
Priority tagged jumbo frames
Number of priority tagged jumbo frames.
Priority tagged pause control frames
Number of priority tagged pause control frames.
Remote faults
Number of remote faults. This is collected only by the XGMII

monitor.
Skip ordered set
Number of skip ordered sets. This is collected only by the

XAUI monitor.
Sync ordered sets
Number of sync ordered sets. This is collected only by the

XAUI monitor.
Untagged data frames
Number of untagged data frames.
Untagged jumbo frames
Number of untagged jumbo frames.
Untagged pause control frames
Number of untagged pause control frames.
Valid 66-bit control blocks
Number of valid 66-bit control blocks. This is collected only

by the BASER monitor.
Valid 66-bit data blocks
Number of valid 66-bit data blocks. This is collected only by

the BASER monitor.
VLAN tagged data frames
Number of VLAN tagged data frames.
VLAN tagged jumbo frames
Number of VLAN tagged jumbo frames.
VLAN tagged pause control frames
Number of VLAN tagged pause control frames.
Monitor Statistics
Table 8-38 shows the statistics maintained by the Gigabit Ethernet monitor.
Table 8-38. Gigabit Ethernet Protocol Statistics
Statistic
Description
Total frames
Total number of frames.
Valid 66-bit blocks
Number of valid 66-bit blocks.
Frames with length between 1518 and 1536
Number of frames with length between 1518 and 1536.
287
Gigabit Ethernet
Monitor Statistics
Table 8-38. Gigabit Ethernet Protocol Statistics (cont.)
288
Statistic
Description
Total base pages
Number of base pages.
Total next pages
Number of next pages.
Message next pages
Number of message next pages.
Unformatted next pages
Number of unformatted next pages.
Null Message codes
Number of pages with Null message codes.
Chapter 9
High-Definition Multimedia Interface (HDMI)
Introduction
This monitor checks the HDMI TMDS interface for compliance with HDMI 1.3a specification
and protocol.
HDMI 1.3a is designed to provide transmitting digital television audiovisual signals for DVD
players, set-top boxes and other audiovisual sources to television sets, projectors, and other
video displays.
This QVL HDMI monitor is modeled from the requirements provided in the following
documents:
High-Definition Multimedia Interface (HDMI), Specification Version 1.3a, November

10, 2006.
Supported Features
HDMI supports the following features:
HDMI is compatible with Digital Visual Interface (DVI), Revision 1.0, April 2, 1999.
HDMI link includes three Transition Minimized Differential Signaling (TMDS) Data
channels and a single TMDS Clock channel.
User configurable interfaces are as follows:

o
8-bits native interface per TMDS Data channel.
10-bits TMDS encoded interface per TMDS Data channel.
Serial interface per each TMDS Data channel.
User configurable TMDS Clock channel.
10-bits TMDS encoding and decoding.

o
Control Period Coding: 2 bits converted to 10 bits.
TMDS Error Reduction Coding (TERC4) Coding: 4 bits converted to 10 bits.
289

o
Video Data Coding: 8 bits converted to 10 bits.
HDMI link operates in three modes: Video Data Period, Data Island Period, and Control
Period.
Preamble, near the end of every Control Period, indicates whether the next Data Period
is a Video Data Period or a Data Island Period.
Maximum 18 packets per Data Island and 16 packet types.
Data Island improves reliability by adding Error Correction Code (ECC) parity to each
packet: BCH(64,56) and BCH(32,24).
Video pixels carried across the link are in one of three different pixel encoding: RGB
4:4:4, YCBCR 4:4:4, or YCBCR 4:2:2.
Video Format Timing (number of pixels per line and number of lines per video field)
codes are supported.
Color Depth Modes 24-bit, 30-bit, 36-bit, and 48-bit are supported.

The HMDI monitor is instantiated in the interface between an HDMI source and HDMI sink. A
typical HDMI setup is shown in Figure 9-1.
Figure 9-1. HDMI Monitor Implementation
Option 1
QVL
Monitor
HDMI
Source
TMDS Channel [0-2]

TMDS Clock Channel
HDMI
Sink
Option 2
TMDS Channel [0-2]
HDMI
Source
290
TMDS Clock Channel
QVL
Monitor
HDMI
Sink

Connect the HDMI monitor pins to internal signals as specified in the pin-out Table 9-1 and
Figure 9-2. HDMI Monitor Pins Diagram
clock
reset
areset
parallel_data_ch0
parallel_data_ch1
parallel_data_ch2
serial_data_ch0
serial_data_ch1
serial_data_ch2
HDMI Monitor
Table 9-1. HDMI Monitor Pins Description

Pins
Description
clock
Clock (TMDS clock) or serial data sample clock (10x TMDS clock).
reset
Synchronous reset, active high.
areset
Asynchronous reset, active high.
parallel_data_ch0
10-bit parallel channel 0 data.
parallel_data_ch1
parallel_data_ch2
serial_data_ch0
1-bit serial channel 0 data.
serial_data_ch1
serial_data_ch2
291

Monitor Parameters
The parameters shown in Table 9-2 should be passed with appropriate values to configure the
HDMI monitor.
Table 9-2. HDMII Monitor Parameters
Order Parameters
Default
Description
1.
Constraints_Mode
This parameter configures the checks in the monitor

as constraints during formal analysis.
2.
NUMBER_DATA_CHANNELS
Number of TMDS data channels.
3.
DATA_CHANNEL_ENCODED_
WIDTH
10
Width of encoded character per TMDS clock cycle.
4.
DATA_CHANNEL_UNENCODED_
WIDTH
Width of unencoded character per TMDS clock

cycle.
5.
BYPASS_SERIAL_TO_PARALLEL
This parameter can be used to bypass the monitor

module that converts TMDS serial data to parallel.
Instead, the monitors clock input and
parallel_data_ch[2:0] are used as the TMDS clock
and encoded data channels, respectively. To enable
this bypass, just set this parameter != 0.
6.
USE_CLOCK_INPUT_TO_SAMPLE_
SERIAL_DATA
The monitors serial-to-parallel module can sample

the TMDS serial data either using the monitors
clock input or via an internally generated clock.
This parameter is "dont care" when
BYPASS_SERIAL_TO_PARALLEL != 0. To
enable using the monitors clock input to sample
the serial data, set this parameter != 0.
7.
CLOCK_10X_PERIOD
This parameter can be used to generate an internal

clock for TMDS serial data sampling. This
parameter is "dont care" when
BYPASS_SERIAL_TO_PARALLEL != 0. The
number specifies an internal clock period. For
example, setting this parameter to 2 would generate
an internal clock with period 2 timeunits.
8.
INVERT_CLOCK10X_OUT
When using an internally generated clock to sample

the TMDS serial channel data, you can invert that
clock if you set this parameter to a non-zero
number. This might be useful in avoiding a race
condition between the data and the active edge of
the clock.
292

Table 9-2. HDMII Monitor Parameters (cont.)

Order Parameters
Default
Description
9.
This parameter can be used to bypass all 8-to-10 bit

encoding in the CTL, Data Island (TERC4) and
Video Data phase of TMDS channel data.
BYPASS_ENCODING
Setting parameter BYPASS_ENCODING to a

non-zero value causes the following assertions to
not be generated in the monitor:
HDMI_DATA_CHANNEL_DATA_ISLAND_
PERIOD_ILLEGAL_TERC4_ENCODING
HDMI_DATA_CHANNEL_VIDEO_DATA_
PERIOD_GT5_TRANSITIONS_PER_PIXEL_
CLK_ERR
HDMI_DATA_ISLAND_PERIOD_PACKET_
NOT_32_PIXEL_CLKS_MULTIPLE_ERR
These assertions do not exist in the monitor if the

BYPASS_ENCODING parameter is set to
non-zero since these do not make sense and are not
necessary with that parameter setting.
10.
ENABLE_SAFE_HIZ_RESET_
HANDLING
This parameter can be used when the reset signals

(reset and areset) are unconnected. This will set the
internal reset and areset signal to an inactive value.
11.
SET_VIDEO_FORMAT_16x8
This parameter can be used to over-ride the

programmed video format from what is commonly
720x480 to 16x8. This is useful for simulation and
formal verification as the time required to see
complete video fields is much smaller.
12.
PROGRAMMING_CHECK_OFF_
GENERAL_CONTROL_CD
This parameter is used when the parameter,

PROGRAMMING_CHECK_ENABLE, is reset to
0, which means that the programming of Data
Island Packet Types may not be following the rules,
and that the stimulus may not match what is
programmed. If that is the case, then you can use
this parameter as the color depth instead of what is
programmed by General Control data packets.
The default color depth is 24-bit mode.
The valid color depth modes are as follows:
24-bits per pixel

30-bits per pixel
36-bits per pixel
48-bits per pixel
Refer to the Color Depth Values table in

the HDMI Specification 1.3a for details.
293


Order Parameters
Default
Description
13.

this parameter as the RGB/YCbCr indicator instead
of what is programmed by AVI Infoframe data
packets.
AVI_INFOFRAME_Y
The default RGB/YCbCr indicator is RGB 444.
0 = RGB 444
1 = YCbCr 444
2 = YCbCr 422
14.
AVI_INFOFRAME_VI

this parameter as the video format ID code instead
of what is programmed by AVI Infoframe data
packets.
The default video format ID code is 720x480p @
59.94/60HZ.
The valid values are 1 to 59. Refer to the HDMI
Valid Pixel Repeat Values for Each Video Format
Timing table in the HDMI Specification 1.3a
for details.
15.
This parameter can be used to enable or disable

X / Z assertion checking on either the TMDS serial
or parallel data channel inputs (depending on
whether BYPASS_SERIAL_TO_PARALLEL ==
0 or not, respectively). Set this parameter to 1 to
enable checking or 0 to disable.
16.
PROGRAMMING_CHECK_
ENABLE

assertion checking on Data Island packets. Set this
parameter to 1 to enable checking or 0 to disable.
17.
PACKET_COVER_ENABLE

cover directive checking on Data Island Packet
Types. Setting this parameter to 1 would turn on
coverage for the 17 different packet types.
18.
PROGRAMMING_COVER_ENABLE

cover directive checking on various programming
modes: deep color modes, RGB and YCbCr video
format modes, and video format ID codes (for
example, 720x480p @ 59.94/60HZ). Set this
parameter to 1 to enable coverage and 0 to disable.
294


Order Parameters
Default
Description
19.
`QVL_COVER_
ALL (15)
This parameter can be used to filter cover

directives. The different coverage levels are as
follows:
COVERAGE_LEVEL_FILTER
`QVL_COVER_NONE == 0;
`QVL_COVER_SANITY == 1;
`QVL_COVER_BASIC == 2;
`QVL_COVER_CORNER == 4;
`QVL_COVER_STATISTIC == 8;
`QVL_COVER_ALL == 15.
Notice that `QVL_COVER_ALL is a bit-wise OR
of the other non-zero coverage levels.
20.
COVERAGE_LEVEL_MESSAGE_
FILTER
`QVL_COVER_
MESSAGE_ALL
(15)

cover directive messages. The cover directives are
unaffected. The different message filtering are as
follows:
`QVL_COVER_MESSAGE_NONE == 0;
`QVL_COVER_MESSAGE_SANITY == 1;
`QVL_COVER_MESSAGE_BASIC == 2;
`QVL_COVER_MESSAGE_CORNER == 4;
`QVL_COVER_MESSAGE_STATISTIC == 8;
`QVL_COVER_MESSAGE_ALL == 15.
Notice that `QVL_COVER_MESSAGE_ALL is a

bit-wise OR of the other non-zero cover message
filter levels.
If you explicitly assign parameters by name, then it is not required to specify the parameters in the above order.
HDMI Monitor Instantiation Example

Example 9-1 instantiates the HDMI monitor.
Example 9-1. HDMI Monitor Instantiation
qvl_hdmi_monitor #(
0,
3,
/* NUMBER_DATA_CHANNELS */
10,
/* DATA_CHANNEL_ENCODED_WIDTH */
8,
/* DATA_CHANNEL_UNENCODED_WIDTH */
0,
/* BYPASS_SERIAL_TO_PARALLEL */
0,
/* USE_CLOCK_INPUT_TO_SAMPLE_SERIAL_DATA */
0,
/* CLOCK_10X_PERIOD */
0,
/* INVERT_CLOCK10X_OUT */
0,
/* BYPASS_ENCODING */
0,
/* ENABLE_SAFE_HIZ_RESET_HANDLING */
0,
/* SET_VIDEO_FORMAT_16x8 */
295

Compiler Directives
4,
/* PROGRAMMING_CHECK_OFF_GENERAL_CONTROL_CD */
0,
/* PROGRAMMING_CHECK_OFF_AVI_INFOFRAME_Y */
2,
/* PROGRAMMING_CHECK_OFF_AVI_INFOFRAME_VI */
1,
/* DATA_X_Z_CHECK_ENABLE */ */
1,
/* PROGRAMMING_CHECK_ENABLE */
1,
/* PACKET_COVER_ENABLE */
1,
/* PROGRAMMING_COVER_ENABLE */
15,
/* COVERAGE_LEVEL_FILTER */
15
/* COVERAGE_LEVEL_MESSAGE_FILTER */
)
HDMI_MONITOR (
.clock
(clock),
.reset
(reset),
.areset
(areset),
.parallel_data_ch0
(parallel_data_ch0),
.parallel_data_ch1
.parallel_data_ch2
.serial_data_ch0
(serial_data_ch0),
.serial_data_ch1
(serial_data_ch1),
.serial_data_ch2
(serial_data_ch2)
);
Compiler Directives
Table 9-3 describes the available Verilog and SystemVerilog compiler directives.
Table 9-3. Verilog and SystemVerilog Compiler Directives
Compiler Directive
Dependent Compiler Directive
Description
QVL_VERSION_PRINT_OFF
none
Turns off a DPI C function that

prints the current QVL version.
QVL_ASSERT_ON
none
Enables assertions.
QVL_XCHECK_OFF
QVL_ASSERT_ON
Can selectively turn off assertions

related to X and Z data checking.
Within QVL_ASSERT_ON
(meaning this compiler directive
must be true first).
QVL_COVER_ON
none
Enables cover directives and final

coverage statistics summary.
QVL_SV_COVER_DIRECTIVES_OFF QVL_COVER_ON
Can turn off cover directives

selectively.
Within QVL_COVER_ON
296

Monitor Checks
Table 9-3. Verilog and SystemVerilog Compiler Directives (cont.)

Compiler Directive
Dependent Compiler Directive
Description
QVL_MW_FINAL_COVER_OFF
QVL_COVER_ON
Can turn off final coverage

statistics summary selectively.
Within QVL_COVER_ON
Monitor Checks
Table 9-4 shows the data channel serial and parallel X or Z (unknown) monitor checks
performed by the HDMI monitor.
The checks in Table 9-4 can be disabled if the parameter DATA_X_Z_CHECK_ENABLE is
set to 0.
Table 9-4. HDMI Data Channel Unknown Checks
Check ID
Violation
Description
HDMI_SERIAL_DATA_
CHANNEL_UNKNOWN_
OR_Z_DRIVEN
Data channel (serial mode) is not

driven to a valid level.
Checks that the TMDS Channel (0, 1,

or 2) serial data input is both known
HDMI_PARALLEL_DATA_
CHANNEL_UNKNOWN_
OR_Z_DRIVEN
Data channel (parallel mode) is not

Checks that the TMDS Channel (0, 1,

or 2) parallel data input is both known
Table 9-5 shows the data integrity monitor checks performed by the HDMI monitor.
Table 9-5. HDMI Data Integrity Checks
Check ID
Violation
HDMI_DATA_CHANNEL_CTL_
PERIOD_ILLEGAL_ENCODING
Illegal encoding value on data Checks that the TMDS Channel data
channel during a CTL Period. input is properly encoded from the
two-bit control signal to a 10-bit
encoding 00 -> 0x354, 01 -> 0x0AB,
10 -> 0x154, 11 -> 0x2AB.
HDMI_DATA_CHANNEL_CTL_
PREAMBLE_ILLEGAL_
ENCODING
Illegal encoding value on data

channel during a CTL Period
Preamble.
Checks that the TMDS Channel data

input is properly encoded from the
two-bit control signal to a 10-bit
encoding 00 -> 0x354, 01 -> 0x0AB,
10 -> 0x154, 11 -> 0x2AB which are all
valid combinations for HVSYNC.
HDMI_DATA_CHANNEL_
DATA_ISLAND_PERIOD_
ILLEGAL_TERC4_ENCODING
Illegal terc4 encoding value

on data channel during a Data
Island Period.
Checks that the TMDS Channel 0 data

input is properly encoded from the 4-bit
to a 10-bit TERC4 encoding (print list
from the specification).
Description
297

Monitor Checks
Table 9-5. HDMI Data Integrity Checks (cont.)

Check ID
Violation
Description
HDMI_DATA_CHANNEL_
DATA_ISLAND_PERIOD_
UNEXPECTED_BCH_ECC_
VALUE
Unexpected BCH ECC value

on data channel during a Data
Island Period.
Data Island Period data BCH0(64,56)

8-bit ECC actual value matches the
expected value.
HDMI_DATA_CHANNEL_
VIDEO_DATA_PERIOD_
GT5_TRANSITIONS_PER_
PIXEL_CLK_ERR
Too many transitions (greater TMDS characters <=5 transitions per

than 5) on data channel during pixel clock during VIDEO DATA
a Video Data Period.
Period.
Table 9-6 shows the protocol monitor checks performed by the HDMI monitor.
Table 9-6. HDMI Protocol Checks
Check ID
Violation
Description
HDMI_CTL_PERIOD_LT12_PIXEL_
CLKS_MINIMUM_ERR
Not enough pixel clocks (12

minimum) during a CTL
Period.
All TMDS Control Periods shall be at

least 12 pixel clocks long.
HDMI_CTL_PERIOD_PREAMBLE_
GT8_PIXEL_CLKS_ERR
CTL Period Preamble error

where the preamble lasted
longer than 8 pixel clocks.
All TMDS Control Period Preambles

shall be 8 pixel clocks long.
HDMI_CTL_PERIOD_PREAMBLE_
ILLEGAL_CHARACTERS
CTL Period Preamble contain

illegal characters; legal
characters are CTL[3:0] ===
4'b0001 or 4'b0101.
The TMDS Control Period Preamble

has only two legal characters:
CTL[3:0] === 0001 (Video Data
Period) and
CTL[3:0] === 0101 (Data Island
Period).
HDMI_CTL_PERIOD_
PREAMBLE_NOT_8_PIXEL_
CLKS_ERR
Number of pixel clocks during

a CTL Period Preamble was
not 8.
All TMDS Control Period Preambles

shall be 8 pixel clocks long.
HDMI_DATA_ISLAND_PERIOD_
CH0_D3_ONE_AFTER_FIRST_
CLK_TERC4_ENCODING_ERR
Invalid value found on data

channel 0 after first pixel clock
of Data Island Period TERC4
encoding.
The TMDS Data Island Period Channel

0 D[3] value one clock after a leading
guard band is D[3] === 1 after the first
pixel clock of the TERC4 encoding
period until the trailing guard band.
CH0_D3_ZERO_AFTER_LEADING_
GUARD_BAND_ERR

channel 0 at first pixel clock of
Data Island Period TERC4
encoding.

0 D[3] value one clock after a leading
guard band is D[3] === 0.
GUARD_BAND_INVALID_VALUE

channel during a Data Island
Period guard band.

leading or trailing guard band value is
0x133.
GUARD_BAND_NOT_2_PIXEL_
CLKS_ERR
Leading or trailing guard band The leading and trailing guard bands
during Data Island Period not 2 are 2 pixel clocks in length during a
pixel clocks error.
Data Island Period.
298

Monitor Checks
Table 9-6. HDMI Protocol Checks (cont.)

Check ID
Violation
Description
INVALID_PACKET_TYPE_
HEADER_ERR
During a Data Island Period,

an invalid packet type header
was detected.
Valid Packet Types include

0x00 -> 0x0A and 0x80 -> 0x85.
MAXIMUM_NUMBER_OF_
PACKETS_18_ERR
More than maximum (18)

number of data packets
transmitted during Data Island
Period.
The maximum number of packets

within a Data Island Period is 18.
MINIMUM_NUMBER_OF_
PACKETS_1_ERR
No data packet detected error

during Data Island Period.
The minimum number of packets

within a Data Island Period is 1.
PACKET_NOT_32_PIXEL_CLKS_
MULTIPLE_ERR
The length of packets within a

Data Island Period is not a
multiple of 32 pixel clocks.
A packet within a Data Island Period is

32 pixel clocks in length.
UNEXPECTED_DATA_AFTER_
TRAILING_GUARD_BAND_ERR
Unexpected data after a Data

Island Period trailing guard
band; expected CTL Period
encoded data.
Expected data after a Data Island

Period trailing guard band; expected
CTL Period encoded data.
HDMI_DATA_ISLAND_TO_
VIDEO_DATA_PERIOD_ERR
A Control Period is required

between any two non-Control
Periods; found a Data Island to
Video Data Period error.
A Control Period is required between

any two periods that are not Control
Periods; detected a Data Island Period
immediately followed by a Video Data
Period.
HDMI_INVALID_NUMBER_OF_
ACTIVE_PIXELS_PER_
PROGRAMMED_VALUE
The number of active video

pixels in a video data period
did not match the programmed
value.
The number of pixel clocks in one

active video transmission should match
the programmed value (for example,
720 active pixel clocks in a 720x480
video frame).
HDMI_MONITOR_STATE_
MACHINE_TO_RESET_
STATE_ERR
Unexpected data has caused

the HDMI Monitor to
transition into the reset state.
The HDMI Monitor state machine has

transitioned into the reset state due to
unexpected data.
HDMI_MONITOR_STATE_
MACHINE_UNKNOWN_STATE_
ERR
Unexpected data has caused

the HDMI Monitor to
transition into an unknown
state.
The HDMI Monitor state machine has

transitioned into an unknown state due
to unexpected data.
HDMI_ONE_DATA_ISLAND_
PERIOD_PER_TWO_VIDEO_
FIELDS_ERR
While transmitting video, at

least one Data Island shall be
transmitted during every two
video fields error.
While transmitting video, at least one

Data Island shall be transmitted during
every two video fields.
HDMI_VIDEO_DATA_PERIOD_
GUARD_BAND_INVALID_VALUE

channel during a Video Data
Period guard band.
The TMDS Video Data Period Channel

0, 1, and 2 leading guard band values
are as follows:
ch0 === 0x2CC
ch1 === 0x133
ch2 === 0x2CC
299

Monitor Checks
Table 9-6. HDMI Protocol Checks (cont.)

Check ID
Violation
Description
HDMI_VIDEO_DATA_PERIOD_
GUARD_BAND_NOT_2_PIXEL_
CLKS_ERR
Leading guard band during

Video Data Period not 2 pixel
clocks error.
The leading guard band is 2 pixel

clocks in length during a Video Data
Period.
HDMI_VIDEO_DATA_TO_DATA_
ISLAND_PERIOD_ERR

Periods; found a Video Data to
Data Island Period error.

Periods; detected a Video Data Period
immediately followed by a Data Island
Period.
HDMI_VIDEO_DATA_TO_VIDEO_
DATA_PERIOD_ERR

Periods; found a Video Data to
Video Data Period error.

Periods; detected a Video Data Period
immediately followed by a Video Data
Period.
Table 9-7 shows the programming monitor checks performed by the HDMI monitor.
The checks in Table 9-7 can be disabled if the PROGRAMMING_CHECK_ENABLE
Table 9-7. HDMI Programming Checks
Check ID
Violation
Description
HDMI_AUDIO_CLOCK_
REGENERATION_PACKET_ERR
Audio Clock Regeneration

packet contains undefined
programming data or non-zero
data that should be zero.
Audio Clock Regeneration (ACR)

packet contains either undefined
programming data for N or CTS, or it
contains non-zero data that should be
zero.
HDMI_AUDIO_CLOCK_
REGENERATION_SUBPACKET_
DIFF_ERR
Audio Clock Regeneration four Audio Clock Regeneration (ACR)

subpackets are not identical.
subpacket diff error; all four
subpackets should contain the same
data.
HDMI_AUDIO_SAMPLE_
PACKET_ERR
Audio Sample packet contains Audio Sample packet contains defined

undefined programming data or programming data or data that should
non-zero data that should be
be zero.
zero.
HDMI_GENERAL_CONTROL_
PACKET_ERR
General Control packet

contains undefined
General Control (GC) packet contains

either defined programming data, or it
contains data that should be zero.
SUBPACKET_DIFF_ERR
General Control four

subpackets are not identical.
General Control (GC) subpacket diff

error; all four subpackets should
contain the same data.
PACKET_AVMUTE_
PROGRAMMING_ERR
General Control packet sets

both Clear_AVMute and
Set_AVMute flags
simultaneously.
General Control (GC) packet does not

set Clear_AVMute and Set_AVMute
flags simultaneously.
300

Monitor Checks
Table 9-7. HDMI Programming Checks (cont.)

Check ID
Violation
Description
PACKET_CD_ZERO_PP_NOT_
ZERO_PROGRAMMING_ERR

programs CD[3:0] to zero but
PP[3:0] is not zero.
General Control (GC) packet programs

CD[3:0] to zero and PP[3:0] is zero.
PACKET_PP_RESERVED_
PROGRAMMING_ERR

programs PP[3:0] to a reserved
value.
The General Control (GC) Packet has

valid PP[3:0] values from 0x0 to 0x4;
values 0x5 to 0xF are reserved.
PACKET_CD_RESERVED_
PROGRAMMING_ERR

The General Control (GC) Packet has
programs CD[3:0] to a reserved valid CD[3:0] values from 0x4 to 0x7;
value.
values 0x1 to 0x3 and 0x8 to 0xF are
reserved; value 0x0 indicates Color
Depth not indicated.
HDMI_AUDIO_CONTENT_
PROTECTION_PACKET_ERR
Audio Content Protection

Audio Content Protection (ACP)

packet contains either defined
programming data or data that should
be zero.
HDMI_AUDIO_CONTENT_
PROTECTION_PACKET_ACP_
TYPE_RESERVED_
PROGRAMMING_ERR
Audio Content Protection

packet programs
ACP_Type[7:0] to a reserved
value.
The Audio Content Protection (ACP)

Packet has valid ACT_Type[7:0] from
0x00 to 0x03; values 0x04 to 0xFF are
reserved.
HDMI_ISRC1_PACKET_ERR
ISRC1 packet contains

ISRC1 packet contains either defined
undefined programming data or programming data, or data that should
be zero.
zero.
HDMI_ISRC2_PACKET_ERR
ISRC2 packet contains

ISRC2 packet contains either defined
undefined programming data or programming data, or data that should
be zero.
zero.
HDMI_ONE_BIT_AUDIO_
SAMPLE_PACKET_ERR
One Bit Audio Sample packet

contains undefined
One Bit Audio Sample (OBAS) packet

contains either defined programming
data, or data that should be zero.
DST Audio (DSTA) packet contains

HDMI_DST_AUDIO_PACKET_ERR DST Audio packet contains
undefined programming data or either defined programming data, or
zero.
HDMI_HIGH_BITRATE_AUDIO_
STREAM_PACKET_ERR
High-Bitrate Audio Stream

High-Bitrate Audio Stream (HBRAS)

packet contains either defined
programming data, or data that should
be zero.
HDMI_GAMUT_METADATA_
PACKET_ERR
Gamut Metadata packet

contains undefined
Gamut Metadata (GM) packet contains

either defined programming data, or
PACKET_GBD_PROFILE_
PROGRAMMING_ERR

programs GBD_profile[2:0] to
a reserved value.
GM GBD_profile reserved values.
301

Monitor Checks

Check ID
Violation
Description
PACKET_SEQ_NUM_
PROGRAMMING_ERR

programs
Affected_Gamut_Seq_Num to
a value that is not
Current_Gamut_Seq_Num nor
Current_Gamut_Seq_Num+1.
Affected_Gamut_Seq_Num ===
Current_Gamut_Seq_Num or
Current_Gamut_Seq_Num + 1 is
required if No_Current_GBD === 0.
HDMI_INFOFRAME_PACKET_
ERR
InfoFrame packet contains

InfoFrame packet contains either
undefined programming data or defined programming data, or data that
should be zero.
zero.
INFOFRAME_LENGTH_
PROGRAMMING_ERR
InfoFrame packet
InfoFrame_length
programming exceeds the
maximum value of 27.
SUBPACKET_CHECKSUM_ERR
InfoFrame subpacket checksum InfoFrame subpacket checksum

does not match expected
matches the expected checksum.
checksum.
HDMI_AVI_INFOFRAME_
PACKET_ERR
AVI InfoFrame packet contains AVI InfoFrame packet contains either

undefined programming data or defined programming data, or data that
should be zero.
zero.
HDMI_AVI_INFOFRAME_
PACKET_INFOFRAME_
VERSION_PROGRAMMING_ERR
AVI InfoFrame packet

InfoFrame_version
programming not 0x02.
AVI InfoFrame packet contains

InfoFrame_version programming that
is 0x02.
HDMI_AVI_INFOFRAME_
PACKET_INFOFRAME_LENGTH_
PROGRAMMING_ERR

InfoFrame_length
programming is not 0x0D.
AVI InfoFrame packet contains

InfoFrame_length programming that is
0x0D.
HDMI_AVI_INFOFRAME_
PACKET_SUBPACKET_
CHECKSUM_ERR
AVI InfoFrame subpacket

checksum does not match
expected checksum.
AVI InfoFrame subpacket checksum

matches expected checksum.
HDMI_AVI_INFOFRAME_
PACKET_Y_RESERVED_
PROGRAMMING_ERR

programs Y[1:0] to a reserved
value.
The AVI InfoFrame Packet has valid

Y[1:0] values from 0x0 to 0x2; value
0x3 is reserved.
HDMI_AVI_INFOFRAME_
PACKET_VI_RESERVED_
PROGRAMMING_ERR

programs VI[1:0] to a reserved
value.
The AVI InfoFrame Packet has valid

VI[1:0] values from 0x01 to 0x3B;
other values are reserved.
HDMI_AUDIO_INFOFRAME_
PACKET_ERR
Audio InfoFrame packet

contains undefined
Audio InfoFrame packet contains

either defined programming data, or

PACKET_INFOFRAME_VERSION_ InfoFrame_version
programming is not 0x01.
PROGRAMMING_ERR
302
InfoFrame packet contains

InfoFrame_length programming that
has a maximum value of 27.

InfoFrame_version programming that
is 0x01

Monitor Coverage

Check ID
Violation
Description
PACKET_INFOFRAME_LENGTH_
PROGRAMMING_ERR

InfoFrame_length
programming is not 0x0A.

InfoFrame_length programming that is
0x0A.
PACKET_SUBPACKET_
CHECKSUM_ERR
Audio InfoFrame subpacket

checksum does not match
expected checksum.
Audio InfoFrame subpacket checksum

matches the expected checksum.
Monitor Coverage
Table 9-8 shows the cover basic cases collected by the HDMI monitor.
Refer to the COVERAGE_LEVEL_FILTER and COVERAGE_LEVEL_MESSAGE_FILTER
parameters in Table 9-2 on page 292 for additional information.
Table 9-8. HDMI Cover Basic
Cover Basic
Description
HDMI_CONTROL_PERIOD
Covered a Control Period.
HDMI_CONTROL_PERIOD_DATA_ISLAND_PREAMBLE
Covered a Control Period Data Island Preamble.
HDMI_DATA_ISLAND_PERIOD
Covered a Data Island Period.
HDMI_DATA_ISLAND_PERIOD_PACKET
Covered a Data Island Period packet.
HDMI_CONTROL_PERIOD_VIDEO_DATA_PREAMBLE
Covered a Control Period Video Data Preamble.
HDMI_VIDEO_DATA_PERIOD
Covered a Video Data Period.
Table 9-9 shows the cover corner cases collected by the HDMI monitor.
Table 9-9. HDMI Cover Corner
Cover Corner
Description
HDMI_VIDEO_FRAME
Covered a Video Frame
303

Monitor Coverage
Table 9-10 shows the packet cover statistics cases collected by the HDMI monitor.
The cover directives in Table 9-10 can be disabled if the PACKET_COVER_ENABLE
Table 9-10. HDMI Packet Cover Statistics
Packet Cover
Description
HDMI_DATA_ISLAND_PERIOD_NULL_PACKET
Covered a Data Island Period Null packet.
HDMI_DATA_ISLAND_PERIOD_AUDIO_CLOCK_
REGENERATION_PACKET
Covered a Data Island Period Audio Clock

Regeneration packet.
HDMI_DATA_ISLAND_PERIOD_AUDIO_SAMPLE_ Covered a Data Island Period Audio Sample packet.

PACKET
HDMI_DATA_ISLAND_PERIOD_GENERAL_
CONTROL_PACKET
Covered a Data Island Period General Control

packet.
HDMI_DATA_ISLAND_PERIOD_AUDIO_
CONTENT_PROTECTION_PACKET
Covered a Data Island Period Audio Content

Protection packet
HDMI_DATA_ISLAND_PERIOD_ISRC1_PACKET
Covered a Data Island Period ISRC1 packet
HDMI_DATA_ISLAND_PERIOD_ISRC2_PACKET
Covered a Data Island Period ISRC2 packet
HDMI_DATA_ISLAND_PERIOD_ONE_BIT_
AUDIO_SAMPLE_PACKET
Covered a Data Island Period One Bit Audio Sample

packet
HDMI_DATA_ISLAND_PERIOD_DST_AUDIO_
PACKET
Covered a Data Island Period DST Audio packet
HDMI_DATA_ISLAND_PERIOD_HIGH_BITRATE_
AUDIO_STREAM_PACKET
Covered a Data Island Period HBR Audio Stream

packet
HDMI_DATA_ISLAND_PERIOD_GAMUT_
METADATA_PACKET
Covered a Data Island Period Gamut Metadata

packet
HDMI_DATA_ISLAND_PERIOD_INFOFRAME_
PACKET
Covered a Data Island Period InfoFrame packet
HDMI_DATA_ISLAND_PERIOD_VENDOR_
SPECIFIC_INFOFRAME_PACKET
Covered a Data Island Period Vendor Specific

InfoFrame packet
HDMI_DATA_ISLAND_PERIOD_AVI_
INFOFRAME_PACKET
Covered a Data Island Period AVI InfoFrame packet
HDMI_DATA_ISLAND_PERIOD_SOURCE_
PRODUCT_DESCRIPTOR_INFOFRAME_PACKET
Covered a Data Island Period Source Product

Descriptor InfoFrame packet
HDMI_DATA_ISLAND_PERIOD_AUDIO_
INFOFRAME_PACKET
Covered a Data Island Period Audio InfoFrame

packet
HDMI_DATA_ISLAND_PERIOD_MPEG_SOURCE_
INFOFRAME_PACKET
Covered a Data Island Period MPEG Source

InfoFrame packet
304

Monitor Coverage
Table 9-11 shows the programming cover statistics cases collected by the HDMI monitor.
The cover directives in Table 9-11 can be disabled if the parameter
PROGRAMMING_COVER_ENABLE is set to 0.
Table 9-11. HDMI Programming Cover Statistics
Programing Cover
Description
HDMI_VIDEO_DATA_PERIOD_24_BIT_COLOR_
DEPTH_MODE
Covered a Video Data Period that used a 24-bit

color depth mode
HDMI_VIDEO_DATA_PERIOD_30_BIT_DEEP_
COLOR_DEPTH_MODE

deep color depth mode
COLOR_DEPTH_MODE

COLOR_DEPTH_MODE

HDMI_VIDEO_DATA_PERIOD_RGB_444_VIDEO_
FORMAT_MODE
Covered a Video Data Period that used a RGB 444

video format mode
HDMI_VIDEO_DATA_PERIOD_YCbCr_444_VIDEO_
FORMAT_MODE
Covered a Video Data Period that used a YCbCr

444 video format mode
HDMI_VIDEO_DATA_PERIOD_CbCr_422_VIDEO_
FORMAT_MODE
Covered a Video Data Period that used a YCbCr

422 video format mode
HDMI_VIDEO_DATA_PERIOD_40x480p_60HZ_
VIDEO_FORMAT_ID_CODE
Covered a Video Data Period that used a 640x480p

@ 60HZ video format id code

@ 59.94/60HZ video format id code
Covered a Video Data Period that used a

1280x720p @ 59.94/60HZ video format id code
HDMI_VIDEO_DATA_PERIOD_1920x1080i_60HZ_

1920x1080i @ 59.94/60HZ video format id code
HDMI_VIDEO_DATA_PERIOD_720_1440x480i_60HZ_

720(1440)x480i @ 59.94/60HZ video format id
code
HDMI_VIDEO_DATA_PERIOD_720_1440x240p_60HZ_

720(1440)x240p @ 59.94/60HZ video format id
code
Covered a Video Data Period that used a 2880x480i


305

Monitor Coverage
Table 9-11. HDMI Programming Cover Statistics (cont.)

Programing Cover
Description




1280x720p @ 50HZ video format id code

1920x1080i @ 50HZ video format id code
HDMI_VIDEO_DATA_PERIOD_720_1440x288p_50HZ_

720(1440)x288p @ 50HZ video format id code

720(1440)x576i @ 50HZ video format id code
Covered a Video Data Period that used a 2880x576i

HDMI_VIDEO_DATA_PERIOD_2880x288_50HZ_
Covered a Video Data Period that used a 2880x288








HDMI_VIDEO_DATA_PERIOD_1920x1080i_1250_
TOTAL_50HZ_VIDEO_FORMAT_ID_CODE

1920x1080i (1250 total) @ 50HZ video format id
code

306

Monitor Coverage Count Totals
Table 9-11. HDMI Programming Cover Statistics (cont.)

Programing Cover
Description







code

VIDEO_FORMATID_CODE



code

Table 9-12 shows the coverage count totals collected by the HDMI monitor.
Table 9-12. Coverage Count Totals for HDMI 1.3a Monitor
Coverage
Description
Total CTL Periods
Total number of CTL Periods transmitted
Data preamble
Total Control Period Data Island Preambles
Video preamble
Total Control Period Video Data Preambles
Total Data Island Periods
Total number of Data Island Periods transmitted
Total Video Data Periods
Total number of Video Data Periods transmitted
307

Table 9-12. Coverage Count Totals for HDMI 1.3a Monitor (cont.)
Coverage
Description
Total Data Island Period Packets
Total number of packets transmitted within Data Island Periods
Total Video Frames
Total number of video frames transmitted
Table 9-13 shows the statistics count totals collected by the HDMI monitor.
Table 9-13. Statistics Count Totals for HDMI 1.3a Monitor
Statistic
Description
Total [Null to MPEG Source InfoFrame]

per Packet Type
Total number of packets transmitted according to a specific Packet

Type [Null to MPEG Source InfoFrame] (should total 17 unique
packet types).
Refer to the Packet Types table in the HDMI Specification 1.3a for
details.
Total [640x480p to 720(1440)x480i] Video Total number of video period transmissions using individual video
Codes
codes [640x480p to 720(1440)x480i] (should total 37 unique
totals).
Refer to the HDMI Valid Pixel Repeat Values for Each Video
Format Timing table in the HDMI Specification 1.3a for details.
Total RGB 4:4:4 Transactions
Total number of video period transmissions using RGB 4:4:4.
Total YCBCR 4:4:4 Transactions
Total number of video period transmissions using YCBCR 4:4:4.
Total YCBCR 4:2:2 Transactions
Total number of video period transmissions using YCBCR 4:2:2.
Total 24-bit mode Deep Color Pixel

Packing
Total number of video period transmissions using 24-bit mode

Deep Color Pixel Packing.

Packing


Packing


Packing

308
Chapter 10
I2C (Inter-IC) Monitor
Introduction
The I2C (Inter-IC) bus was originally developed by Philips Semiconductors to provide a simple
and uniform connectivity for a variety of peripheral and general-purpose devices such as
intelligent control, EEPROM, RAM, and LCD drivers.
The Mentor Graphics Corporation I2C QVL monitor is used to verify any I2C designs for
protocol correctness, and to measure the verification coverage through structural coverage
metrics. The I2C monitor contains assertion directives that track all I2C interface protocol rules.
The statistics block collects the occurrences of various protocol scenarios on the I2C bus.
This I2C Monitor can be simulated with Mentor Graphics Questa simulator and used with the
0-In Formal Verification tools (Search, Confirm, and Prove). With the 0-In Formal Verification
tools, the assertion directives in the I2C monitor can be used as Constraints and
Goals/Properties-to-prove-or-falsify, when used with the 0-In Formal Verification tools.
Figure 10-1 illustrates the I2C System Topology.
Figure 10-1. I2C System Topology
I2C Slave
I2C Master
I2C Bus
I2C Slave
I2C Master
309

This QVL I2C monitor is modeled from the requirements provided in the following documents:
The I2C-Bus Specification, Version 2.1, January 2000
I2C Monitor
I2C is a multiple master, multiple slave interface. Any I2C device can be of the following types:
Master only function
Slave only function
Master and Slave functions in a single package
The following top modules are provided:
qvl_i2c_master_monitor to track Master only I2C devices
qvl_i2c_slave_monitor to track Slave only I2C devices
qvl_i2c_master_slave_monitor to track Master/Slave I2C devices
Figure 10-2 illustrates the I2C Monitor Connectivity.

Figure 10-2. I2C Monitor Connectivity
I2C Master
I2C Slave
I2C Master Monitor
I2C Slave Monitor
I2C Bus
I2C Master/Slave Monitor

I2C Master
I2C Slave
As shown in Figure 10-2, if you want to track multiple I2C Master/Slave and Master-Slave
devices simultaneously, then multiple instances of the appropriate I2C Master, or Slave, or
Master/Slave top modules are needed.
310

I2C Monitor
Connect the I2C Master, or Slave, or Master/Slave monitor pins to internal signals as specified
in the pin-out Table 10-1 and illustrated in Figure 10-3, Figure 10-4, and Figure 10-5.
Figure 10-3. I2C Master Monitor Pins Diagram
clock
reset
areset
sda_out
sda_out_en_n
sda_in
scl_out
scl_out_en_n
scl_in
clock_prescale_count
I2C Master Monitor
Figure 10-4. I2C Slave Monitor Pins Diagram

clock
reset
areset
sda_out
sda_out_en_n
sda_in
scl_out
scl_out_en_n
scl_in
slave_addr
I2C Slave Monitor
Figure 10-5. I2C Master/Slave Monitor Pins Diagram

clock
reset
areset
sda_out
sda_out_en_n
sda_in
scl_out
scl_out_en_n
scl_in
slave_addr
I2C Master/Slave
Monitor
311

I2C Monitor
Table 10-1. I2C Monitor PINs Description

Pins
Description
areset
Asynchronous reset signal. Active HIGH.
clock
Clock signal. Positive edge active. This clock signal should be at least twice as
fast as scl_out/scl_in to be able to sample the scl_out/scl_in.
Clock prescaler value/sampling enable signal. 16-bit wide. When the

configurable parameter, CLOCK_PRESCALE_EN (see Table 10-3 on page 315)
is set to 1, pass a nonzero positive integer to this signal. If the configurable
parameter CLOCK_PRESCALE_EN is set to 0, then connect an external
sampling enable signal to 0th bit of this signal by appending a leading 15'b0.
When the CLOCK_PRESCALE_EN parameter is set to 1, this monitor internally
generates a slower sampling signal using this prescaler value.
Recommendation: If the clock signal speed is equal, or just twice the speed of
SCL, then it is recommended to connect 1'b1or an external sampling enable
signal to the 0th bit of this signal.
reset
Synchronous reset signal. Active HIGH.
scl_in
I2C clock signal. The serial clock (SCL) input signal to the DUT.
scl_out
I2C clock signal. Input to the tristate buffer. SCL output signal to the DUT.
scl_out_en_n
SCL clock enable signal. Active LOW. Enable to the tristate buffer.
sda_in
I2C data signal. The serial data (SDA) input signal to the DUT.
sda_out
I2C data signal. SDA output signal from the DUT. Input to the tristate buffer.
Control and data signal.
sda_out_en_n
SDA output enable signal. Active LOW. Enable to the tristate buffer.
slave_addr
Slave address input. 10-bits wide. Both 7-bit address or 10-bit address can be
connected. When a 7-bit address is passed, 3'b0 should be appended with the
actual 7-bit address.
Note that as per the protocol, an I2C device can be configured with an address
through the hardware general call address. Hence, this monitor takes this input as
a configured address until a hardware general call address is issued on the bus, or
there is no hardware general call address at all on the bus.
Note that this signal is not available with the Master only monitor (see
Example 10-1 on page 314).
312

I2C Monitor
Monitor Parameters
I2C monitor to track the I2C Master, I2C Slave, or I2C Master/Slave devices.
Table 10-2. I2C Monitor Parameters
Order Parameters
Default Description
0.
Constraints_Mode
Common enable/disable for all assertions as

constraints to the 0-In Formal tools (Search,
Confirm, and Prove).
To use a group of assertions of this monitor as
constraints with the 0-In Formal tools, pass the value
1 to this parameter.
1.
MAX_TXN_LENGTH
Maximum Transaction Length Limit.

A check fires if this monitor finds an I2C transaction
that is longer than the length specified to this
parameter.
This check is disabled if this parameter is passed
with 0. To activate this check, pass any nonzero
positive number.
2.
CLOCK_PRESCALE_EN
Clock Prescaler Enable.

If set to 1, then pass a nonzero positive value to the
clock_prescale_count signal.
If set to 0, then connect an external sampling enable
to the 0th bit of the clock_prescale_count signal by
appending 15'b0 at the leading position.
3.
OUTPUT_ENABLES_ON
Output Enables ON or OFF.

If the I2C design has tristate compatible signals, then
pass 1 to this parameter, and connect the
corresponding enable signals to sda_out_en_n and
scl_out_en_n.
If the I2C design does not have output enable signals,
then pass 0 to this parameter and connect 1'b0 to both
sda_out_en_n and scl_out_en_n signals.
I2C Monitor Instantiation Examples

I2C Master Monitor
Example 10-1 instantiates the I2C Master monitor with no output enables, clock prescaler value
as 16'd20.
313

I2C Monitor
Example 10-1. I2C Master Monitor Instantiation for a Master Only Design
qvl_i2c_master_monitor #(.Constraints_Mode (1),
.CLOCK_PRESCALE_EN (1) ) MAS_ONLY0
(.clock (CLOCK),
.reset (!RESETN),
.areset (!RESETN),
.sda_out (OSDA),
.sda_out_en_n (1'b0),
.sda_in (ISDA),
.scl_out (OSCL),
.scl_out_en_n (1'b0),
.scl_in (ISCL),
.clock_prescale_count (16'd20) ) ;
I2C Slave Monitor

Example 10-2 instantiates the I2C Slave monitor with no output enables, clock prescaler value
as 16'd20, and the Slave address as 10'h3a5.
Example 10-2. I2C Slave Monitor Instantiation for a Slave Only Design
qvl_i2c_slave_monitor #(.Constraints_Mode (1),
.CLOCK_PRESCALE_EN (1) ) SLV_ONLY0
(.clock (CLOCK),
.reset (!RESETN),
.areset (!RESETN),
.sda_out (OSDA),
.sda_out_en_n (1'b0),
.sda_in (ISDA),
.scl_out (OSCL),
.scl_out_en_n (1'b0),
.scl_in (ISCL),
.slave_addr (10'h3a5),
.clock_prescale_count (16'd20) ) ;
I2C Master/Slave Monitor

Example 10-3 instantiates the I2C Master/Slave monitor for an I2C design that has Master and
Slave functions, with output enables present, no clock prescaler value, external sampling
enable, and the Slave address as 10'h07f.
Note that Example 10-3 assumes that Fast-mode and High-speed mode (Hs-mode) have
separate external sampling enables in the design. You can bitwise OR them when you connect
them as an external sampling enable signal to the clock_prescale_count of the monitor.
Example 10-3. I2C Master/Slave Monitor Instantiation for a Master/Slave Design
qvl_i2c_master_slave_monitor #(.Constraints_Mode (1),
.CLOCK_PRESCALE_EN (0) ) MAS_SLV0
(.clock (CLOCK),
314

Master Checks
.reset (!RESETN),
.areset (!RESETN),
.sda_out (OSDA),
.sda_out_en_n (OSDA_en_n),
.sda_in (ISDA),
.scl_out (OSCL),
.scl_out_en_n (OSCL_en_n),
.scl_in (ISCL),
.slave_addr (10'h07f),
.clock_prescale_count ( {15'b0,
(FS_MODE_SAMPLING_ENABLE | HS_MODE_SAMPLING_ENABLE) } ) );
Master Checks
Table 10-3 shows the Master checks performed by the I2C monitor.
Table 10-3. I2C Master Checks
Check ID
Violation
Description
I2C_m_cbus_not_needed_
in_fast_or_hs_mode
CBUS is not allowed in

Fast-mode or Hs-mode.
This check will fire if the CBUS transaction

is issued when the Hs-mode transaction is
entered.
I2C_m_cbus_transaction_
ends_with_stop
CBUS transactions should

always end with STOP.
This check will fire if a CBUS transaction

ends with a restart.
I2C_m_during_address_
phase_master_should_drive_
sda_and_scl
During the address phase, the

Master should drive SDA and
SCL.
Once a Master issues the START, it should

continue to own the bus until the end of the
address phase.
I2C_m_during_arbitration_
if_own_address_master_to_
switch_role_as_slave
An I2C device that has Master

and Slave functions together.
During arbitration, if the
Slave address matches with
its own Slave address, then
the Master should abruptly
terminate the arbitration cycle
to provide sufficient time for
its Slave to respond to the
transaction.
This check is applicable for an I2C device

that has both Master and Slave as active
functions. When such a device starts a
transaction as a Master, and if there is
another Master on the bus that is also
initiating a transaction at the same time, then
the Masters should resolve the winner
through the arbitration process.
Note that Slaves are not

involved in the arbitration
procedure.
If a Master incorporates a Slave function and

it loses arbitration during the addressing
stage, then it is possible that the winning
Master is trying to address it. Therefore, the
losing Master must switch over immediately
to its Slave mode.
Note that this check is disabled when the
DUT is a Master only function.
315

Master Checks
Table 10-3. I2C Master Checks (cont.)

Check ID
Violation
Description
I2C_m_during_write_data_
master_should_drive_scl_
during_data_txn
During write transactions, the

Master should drive SCL
during data transfer.
In write transactions, the Master will be in

the data transmitting mode. During the data
phase of the write transaction, the active
Master should own the SDA and SCL bus. It
should drive the SDA with valid values, and
it should toggle the SCL line to transmit the
data.
This check will fire during the data phase of
the write transaction if the SCL line is not
toggled by the Master, which initiated the
write transaction.
I2C_m_during_write_data_
master_should_drive_sda_
during_data_txn
For write transactions, the

Master should drive SDA
during data transfer.
In write transactions, the Master will be in

the data transmitting mode. During the data
phase of the write transaction, the active
Master should own the SDA and SCL bus. It
should drive the SDA with valid values, and
it should toggle the SCL line to transmit the
data.
This check will fire during the data phase of
the write transaction if the SDA line is not
driven by the master, which initiated the
write transaction.
I2C_m_except_start_byte_
start_to_follow_at_least_
one_data_phase
Except for START byte

transfer, every START signal
should follow at least one data
phase.
This is more of a Warning. As per the I2C

protocol, only the START byte does not have
any data phase. This check monitors if all
other transactions have at least one data
phase before it stops or restarts.
I2C_m_for_read_txn_mas_
should_assert_ack_or_nack
For read data transactions, the

Master should assert ACK.
For all data phases during read transactions,

the Master should issue ACK/NACK.
I2C_m_for_write_txn_mas_
should_deassert_sda_out_
during_ack_or_nack

Master should de-assert the
sda_out_en signal during
ACK/NACK.
This check ensures that the bus is owned by

Slave during the read data phases, and Master
de-asserts SDA by either deactivating the
*_out_en_n signals or driving SDA to open
collector HIGH.
I2C_m_gcall_address_2nd_
byte_8b00_not_allowed
On the second byte of the

GCALL address, 8'h00 is not
allowed.
The second byte of general call address

should not have all bits zero.
I2C_m_mas_to_stop_or_
restart_if_slv_issues_slave_nack
Master to restart/stop the

transaction if the Slave issues
NACK.
If Slave responds with NACK, then the

Master should terminate the current
transaction by issuing STOP or restart.
I2C_m_master_to_issue_
gcall_address_first_before_
any_valid_txn
After reset, the Master should

issue the GCALL address
before any other transfer.
I2C protocol says that the general call address

should be issued before any valid transaction
is issued on the bus. This check will fire if,
after reset, the monitor observes a valid
read/write transaction before a general call
address transaction.
316

Master Checks

Check ID
Violation
Description
I2C_m_max_txn_len_to_
equal_length_parameter_value
Master should signal STOP or

restart if the read/write
transaction length reaches the
configured value of the
maximum transaction length
count parameter
MAX_TXN_LENGTH.
This is a custom check. Protocol does not

enforce this rule. This could be more useful
as constraints to the 0-In Formal tools.
Reserved addresses that

should not be issued.
The I2C protocol specification sets aside a

few addresses as reserved. This monitor
ensures that those reserved addresses are not
issued by the Master on the interface.
I2C_m_reserved_addresses_
not_allowed
This check is disabled if the

MAX_TXN_LENGTH parameter is assigned
with 0.
Ignore this firing if it is legal for your design

that allows an address that comes under the
addresses that are categorized as reserved
addresses in the I2C protocol specification.
I2C_m_reseved_addresses_
not_allowed_in_hs_mode
The reserved address,

8'b0000_1000, is not allowed
in Hs-mode.
Similar to the above check. When the device

enters into Hs-mode, the protocol
specification mentions a few more addresses
as reserved.
This check will fire when Hs-mode is entered
and the addresses that are marked as reserved
are seen on the I2C bus.
I2C_m_sda_to_be_stable_
as_long_as_slave_asserts_
scl_low_towards_slave_wait
SDA should be held stable as

long as SCL is LOW.
When Slave asserts SCL LOW on the

9-bits boundary towards a Slave wait state,
Master should hold the value on the SDA
stable.
I2C_m_serial_data_length_
always_8_bits_wide
Every data phase is only

8-bits wide.
This check ensures that every data phase that

is sent serially does not stop toggling before
transmitting all 8-bits of data.
I2C_m_start_byte_to_
follow_repeated_start
START byte transfer should

follow repeated START.
This check will fire if a START byte

transaction ends with a STOP.
I2C_m_why_same_address_
of_slave_which_is_part_
of_same_device
If the I2C device has Master

and Slave functions, then as a
Master, it should not issue the
address that addresses its own
Slave.
Custom Check. This is not enforced by the

protocol. Could be more useful as constraints
with the formal tools.
This check ensures that the Master of the I2C
DUT that contains both the Master and Slave
functions in a single package, does not
generate an address that addresses a Slave
that is part of the same DUT.
Note that this check is disabled when the
DUT is a Master only function.
317

Slave Checks

Check ID
Violation
Description
I2C_ms_after_clock_sync_
high_width_to_be_equal_
that_of_device_had_
shortest_high
Once clock synchronization is

over, the HIGH period of SCL
should be equal to that of the
shortest HIGH that was
observed during the clock
synchronization.
This check ensures that after the clock

synchronization, the SCL HIGH width of the
Master DUT is synchronized, and also the
HIGH period is equal to that of the I2C
device on the bus that had the shortest SCL
HIGH width.
I2C_ms_no_arb_and_clk_
sync_allowed_in_hs_mode
Arbitration and clock

synchronization are not
allowed in Hs-mode.
When the Master device enters into

Hs-mode, clock synchronization and
arbitration functions are not allowed.
I2C_ms_no_scl_low_when_
sda_high_bus_idle
When the bus is IDLE, SCL

and SDA should be high, and
SCL should not toggle.
This rule applies when the I2C bus is idle.

This check is applicable for the I2C Master
and Slave. It ensures that when the I2C bus is
idle and SDA is HIGH, then SCL should be
HIGH and it should not toggle.
Slave Checks
Table 10-4 shows the Slave checks performed by the I2C monitor.
Table 10-4. I2C Slave Checks
Check ID
Violation
Description
I2C_ms_no_scl_low_when_
sda_high_bus_idle
When the bus is IDLE, SCL

and SDA should be high, and
SCL should not toggle.
This rule applies when the I2C bus is idle.

This check is applicable for the I2C Master
and Slave. It ensures that when the I2C bus
is idle and SDA is HIGH, then SCL should
be HIGH and it should not toggle.
I2C_s_address_should_match_
when_the_slave_device_
responds_for_a_txn
When Slave claims the

transaction by signaling ACK
during the address phase, the
address seen on the bus should
match with its address.
This check ensures that the Slave asserts

ACK/NACK towards claiming/not claiming
the transaction when the address on the I2C
bus does/does not match the configured
address.
I2C_s_bit_level_hand_shake_
is_not_allowed_by_stretching_
scl_low
Slave interruption through

signaling SCL LOW can be
only at the 8-bits boundary; it
cannot be between the
data/address bits.
The I2C Slave devices can insert a wait state

by stretching the SCL signal LOW only at
the 8-bits of address/data boundary
(i.e., 8-bits + 1-bit of ACK/NACK), and not
on the middle of the address/data phases.
I2C_s_during_read_data_
slave_should_drive_sda_
during_data_txn
For read transactions, the Slave The check ensures that the SDA is driven by
should drive SDA during data the Slave during the read data phases.
transfer.
I2C_s_for_read_txn_slv_
should_deassert_sda_out_en_
n_during_ack_or_nack
For read transactions, the Slave This check ensures that for a read
should de-assert sda_out_en
transaction the ACK/NACK bit is driven by
during ACK/NACK.
the Master, and the Slave stops driving the
SDA bit to avoid contention.
318

Assertion Checks
Table 10-4. I2C Slave Checks (cont.)

Check ID
Violation
Description
I2C_s_for_write_txn_slv_
should_assert_ack_or_nack

Slave should assert
ACK/NACK.
For the address/data phases of the write

transactions, the Slave should assert the
ACK or NACK bits.
This check fires for the following
conditions:
If the Slave device does not own the
bus by asserting sda_out_en_n to 1'b0

(if the I/O contains a tristate buffer).
The SDA is LOW, and it is not driven
by the Slave that is addressed (I/O bus

has an open collector).
I2C_s_hs_mode_signaling_
should_be_followed_w_nack
Hs-mode signaling should

always be followed with
NACK.
The Hs-mode signaling is common for all

I2C devices that exist on the bus. Hence,
none of the devices should assert ACK.
I2C_s_no_ack_for_cbus_cycle
No ACK is issued for the

CBUS cycle.
The CBUS signaling is a special

transaction. Hence, regular I2C devices that
exist on the bus should not assert ACK.
I2C_s_start_byte_to_follow_
nack
START byte should always

follow NACK.
The START byte transaction is common for

all I2C devices that exist on the bus. Hence,
none of the devices should assert ACK.
Assertion Checks
Table 10-5 shows the Assertion checks performed by the I2C monitor.
Table 10-5. I2C Assertion Checks
Check ID
Violation
Description
I2C_KNOWN_sda_out
Control signal, sda_out, should

not be X or Z
Checks that control signal sda_out

is both known (not X) and driven
(not Z)
I2C_KNOWN_sda_in
Control signal, sda_in, should not

be X or Z
Checks that control signal sda_in is

both known (not X) and driven
(not Z)
I2C_KNOWN_sda_out_en_n
Control signal, sda_out_en_n,

should not be X or Z
Checks that control signal scl_out

(not Z)
I2C_KNOWN_scl_out
Control signal, scl_out, should

not be X or Z
Checks that control signal scl_out

(not Z).
I2C_KNOWN_scl_out_en_n
Control signal, scl_out_en_n,

should not be X or Z
Checks that control signal

scl_out_en_n is both known (not
319

Master Corner Cases
Table 10-5. I2C Assertion Checks (cont.)

Check ID
Violation
Description
I2C_KNOWN_scl_in
Control signal, scl_in, should not

be X or Z
Checks that control signal scl_in is

both known (not X) and driven
(not Z).
I2C_KNOWN_clock_prescale_count
Clock prescale value should not

be X or Z.
Checks that control signal

clock_prescale_count is both
Master Corner Cases

Table 10-6 shows the corner cases maintained by the I2C Master monitor.
Table 10-6. I2C Master Corner Cases
Name
Description
Total 7-Bit Addresses
Number of 7-bit addresses issued.
Number of 10-bit addresses issued.
Master Statistics
Table 10-7 shows the statistics maintained by the I2C Master monitor.
Table 10-7. I2C Master Statistics
320
Name
Description
Total Starts
Number of starts issued.
Total Reads
Number of read transactions performed.
Total Writes
Number of write transactions performed.
Total Stops
Number of stops issued.
Total Repeated Starts
Number of repeated starts issued.
Total Valid Transactions
Number of read and write transactions.
Total Valid Data Phases
Number of data phases with proper ACK.
Total Arbitration Losses
Number of times Master lost in arbitration.
Total Gcall Addresses
Number of general call address transactions.
Total Gcall Slave Resets
Number of general call addresses with Slave reset.
Total Gcall No Slave Resets
Number of general call addresses with no Slave reset.
Total Hardware Gcalls
Number of hardware general call address.
Total Hs-mode Entries
Number of Hs-mode entries.
Total Start Bytes
Number of start byte transactions.

Slave Corner Cases
Table 10-7. I2C Master Statistics (cont.)

Name
Description
Total ACKs
Number of positive acknowledgements (ACKs).
Total NACKs
Number of negative acknowledgements (NACKs).
Total CBUS Transactions
Number of CBUS transactions.
Slave Corner Cases

Table 10-8 shows the corner cases maintained by the I2C Slave monitor.
Table 10-8. I2C Slave Corner Cases
Name
Description
Number of 7-bit addresses received.
Number of 10-bit addresses received.
Slave Statistics
Table 10-9 shows the statistics maintained by the I2C Slave monitor.
Table 10-9. I2C Slave Statistics
Name
Description
Total Starts
Number of start signals issued.
Total Reads
Number of read transactions performed.
Total Writes
Number of write transactions performed.
Total Stops
Number of stop signals received.
Total Repeated Starts
Number of repeated starts received.
Total Valid Transactions
Number of read and write transactions.
Total Valid Data Phases
Number of data phases with proper ACK.
Total Gcall Addresses
Number of general call address transactions received.
Total Gcall Slave Resets
Number of general call addresses with Slave reset.
Total Gcall No Slave Resets
Number of general call addresses with no Slave reset.
Total Hardware Gcalls
Number of hardware general call address received.
Total Hs-mode Entries
Number of Hs-mode entries.
Total Start Bytes
Number of START byte transactions received.
321

Slave Statistics
Table 10-9. I2C Slave Statistics (cont.)
322
Name
Description
Total ACKs
Number of positive acknowledgements (ACKs).
Total NACKs
Number of negative acknowledgements (NACKs).
Total CBUS Transactions
Number of CBUS transactions.
Chapter 11
Low Pin Count (LPC)
Introduction
The Low Pin Count (LPC) bus interface is designed to enable a system without ISA or X-bus
interfaces. The LPC interface reduces the cost of traditional X-bus devices while meeting or
exceeding the data transfer rate of X-bus. LPC performs the same cycle types as the X-bus:
Memory, I/O, DMA, and Bus Master.
This LPC monitor is modeled from the requirements provided in the following document:
Low Pin Count (LPC) Interface Specification, Rev. 1.0, September 29, 1997.

To use the LPC monitor, place an instance of the monitor inside the host or peripheral device as
shown in the block diagram in Figure 11-1.
Figure 11-1. LPC Monitor Implementation
PCI
Host Bus
ISA
SuperIO
Host
LPC
Monitor
LPC
Monitor
LPC Local Bus
Connect the LPC monitor pins to internal signals as specified in the pin-out Table 11-1 and
323
Low Pin Count (LPC)

Figure 11-2. LPC Monitor Pin Diagram

lclk
lreset_n
lframe_n
lad
ldrq_n
serirq
clkrun_n
pme_n
lpcpd_n
lmsi_n
LPC Monitor
Table 11-1. LPC Monitor Pins

Pin
Description
clkrun_n
Clock Run. Stopping the clock is not supported by the monitor. The signal
is active low.
lad
The multiplexed command, address and data bus which is 4-bits wide.
lclk
The clock of the LPC interface.
ldrq_n
Encoded DMA / Bus Master request. The signal is active low.
lframe_n
Indicates the start of a cycle or the termination of a broken cycle. The

signal is active low.
lmsi_n
SMI on I/O instruction for retry is not supported by the monitor. The signal
is active low.
lpcpd_n
Power Down. This is not supported by the monitor. The signal is active
low.
lreset_n
The reset signal for the LPC interface. The signal is active low.
pme_n
Power Management Event. This is not supported by the monitor. The

signal is active low.
serirq
Serialized IRQ. Interrupt support is not supported by the monitor. The

signal is active high.
Monitor Parameters
The parameters shown in Table 11-2 configure the LPC monitor.
Table 11-2. LPC Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode

2.
LDRQ_WIDTH
Specifies the number of LDRQ# lines.
324
Low Pin Count (LPC)

Table 11-2. LPC Monitor Parameters (cont.)

Order Parameter
Default Description
3.
RETAIN_DMA_ON_
ABORT
on a particular channel when the device does not

respond within the time-out period and the host aborts
the cycle. The default value of 1 indicates that the
monitor retains DMA requests even after an abort
cycle.
4.
CHECK_RESERVED_VALUE
Set this parameter to 1 if the monitor should fire for

reserved SYNC values sent on the LAD bus. The
default value of 0 indicates that the monitor will not
fire for reserved values on the bus.
5.
ALLOW_LARGE_DMA_
TRANSFERS
Set this parameter to 0 if 16-bit/32-bit DMA on 8-bit

channels and 32-bit DMA on 16-bit channels are not
allowed. The default value of 1 indicates that these
transfers are allowed.
6.
ALLOW_DMA_AFTER_
DEACTIVATION
Set this parameter to 0 if the host is not allowed to

initiate DMA transfers on deactivated channels. The
default value of 1 allows the host to initiate DMA
transfers on channels deactivated using an LDRQ
message.
When the Constraints_Mode parameter is set to 0, the Constraints Mode feature is disabled, and
all the checks are used as targets when running formal analysis.
Instantiation Example
Example 11-1 instantiates the LPC monitor.
Example 11-1. LPC Monitor Instantiation
qvl_lpc_monitor #(
0,
2,
/* LDRQ_WIDTH */
1,
/* RETAIN_DMA_ON_ABORT */
0,
/* CHECK_RESERVED_VALUE */
1,
/* ALLOW_LARGE_DMA_TRANSFERS */
1
/* ALLOW_DMA_AFTER_DEACTIVATION */ )
lpc_mon (
.lclk
(lclk),
.lreset_n
(lreset_n),
.lframe_n
(lframe_n),
.lad
(lad),
.ldrq_n
(ldrq),
.serirq
(serirq),
.clkrun_n
(clkrun_n),
.pme_n
(pme_n),
.lpcpd_n
(lpcpd_n),
.lsmi_n
(lsmi_n) );
325
Low Pin Count (LPC)

Monitor Checks
Monitor Checks
Table 11-3 shows the checks performed by an LPC monitor.
Table 11-3. LPC Checks
Check ID
Violation
Description
LPC_lframe_n
lframe_n has a X or Z value.
lframe_n must always have a valid value.
LPC_ldrq_n
ldrq_n has a X or Z value.
ldrq_n must always have a valid value.
LPC_serirq
serirq has a X or Z value.
serirq must always have a valid value.
LPC_clkrun_n
clkrun_n has a X or Z value.
clkrun_n must always have a valid value.
LPC_pme_n
pme_n has a X or Z value.
pme_n must always have a valid value.
LPC_lpcpd_n
lpcpd_n has a X or Z value.
lpcpd_n must always have a valid value.
LPC_lsmi_n
lsmi_n has a X or Z value.
lsmi_n must always have a valid value
LPC_1
Invalid Cycle Type and Direction

detected (4.2.1.2).
The Cycle Type and Direction specified is

not valid.
LPC_2
Value on lad port is not 4'b1111

during the turnaround cycle
(4.2.1.4).
During a turnaround cycle, lad must be set

to 4'b1111.
LPC_3
CHANNEL cycles can only occur

in DMA operations (4.2.1.6).
A Channel cycle is detected in a non-DMA

operation.
LPC_4
ADDR cycles can only occur in

non-DMA operations (4.2.1.6).
An ADDR cycle is detected in a DMA

operation.
LPC_5
Value on lad port was not constant The lad port during a SYNC cycle indicates
across contiguous synchronization the type of synchronization. This value
cycles (4.2.1.8).
must remain constant across contiguous
SYNC cycles.
LPC_6
The host does synchronization

cycles only in bus master
operations (4.2.1.8).
The host can only perform SYNC cycles in

the bus master operations.
LPC_7
The lad port has an invalid SYNC

value (4.2.1.8).
An invalid SYNC is detected.
LPC_8
The lad port has a reserved SYNC

value (4.2.1.8).
A reserved value is detected on the lad port

during a SYNC cycle.
LPC_9
The peripheral should not be

synchronizing in a bus master
operation (4.2.1.8).
The peripheral can only perform SYNC

cycles in the non-bus master operations.
LPC_10
The lad port has an invalid SIZE

value (4.2.1.3).
An invalid value is detected on the lad port

during a SIZE cycle.
LPC_11
SIZE cycles can only happen in

non-host initiated operations
(4.2.1.3).
A SIZE cycle is detected in a host initiated

operation.
LPC_12
lad[3:2] must be 2'b00 in a SIZE

cycle (4.2.1.3).
lad[3:2] is not 2'b00 in a SIZE cycle.
326
Low Pin Count (LPC)

Monitor Checks
Table 11-3. LPC Checks (cont.)

Check ID
Violation
Description
LPC_14
The lad port has a reserved

START type (4.2.1.1).
The lad port has a reserved value during a

START cycle.
LPC_15
The lad port does not have value

4'b1111 when lframe_n asserts to
abort the transfer (4.2.2.2).
When an operation is aborted via lframe_n,

lad must be set to 4'b1111.
LPC_16
lframe_n must be asserted for 4

contiguous cycles when aborting
the transfer (4.2.2.2).
When an operation is aborted via lframe_n,

lframe_n must be asserted for 4 contiguous
cycles.
LPC_17
DMA is requested with the

reserved channel number 4 (6.4).
A DMA is requested on the reserved

channel number 4.
LPC_18
DMA operation is occurring on a

channel that did not send a request
for a DMA operation via the ldrq
port (6.4).
A DMA operation has been started on a

channel that did not have a DMA request
outstanding.
LPC_19
Peripheral Initiated Bus Master

operation is occurring on a
channel that did not send a request
for that via the ldrq port (7.3).
A Bus Master operation has been started on

a channel that did not have a Bus Master
operation request outstanding.
LPC_20
A Short Wait is indicated, but it

took more than 8 clocks to SYNC
(4.2.1.8).
A Short Wait is indicated on a SYNC

cycle. However, the device took more than
8 clocks to SYNC. A Long Wait should
have been indicated.
LPC_21
Cycle and Start type mismatch on

the bus master operation (7.2).
A Bus Master operation is indicated on a

CYCTYPE cycle, but a Bus Master
operation is not indicated on the START
cycle.
LPC_22
A request for a peripheral initiated

bus master operation is received
on ldrq port
[",8d48+s[WIDTH_OF_LDRQ_
WIDTH:0],"] when another bus
master request is outstanding
(7.3).
A bus master request is received when

another bus master request is still
outstanding. Only one bus master request
can be outstanding at any time.
LPC_23
The sequence of values on the

An illegal sequence of values is detected on
ldrq port
the ldrq port.
WIDTH:0],"] do not match a valid
DMA or Bus Master request (6.2).
LPC_24
A DMA deactivation request is

received on the ldrq port
WIDTH:0],"] for a channel that
does not have a DMA request
outstanding (6.3).
A DMA abort request is received via the

ldrq port for a channel that does not have a
DMA request outstanding.
LPC_25
Invalid start type.
An invalid start type encoding is detected

on the lad port.
LPC_26
Invalid size.
An invalid size encoding is detected on the

lad port.
327
Low Pin Count (LPC)

Monitor Checks
Table 11-3. LPC Checks (cont.)

Check ID
Violation
Description
LPC_27
A '0000b' (Ready) or '1010b'

(Ready with Error) encoding sent
on the SYNC field of an odd byte
during a read operation on a 16-bit
DMA channel (6.4.3).
Indicating a '0000b' or '1010b' (Ready or

Ready with Error) encoding on the SYNC
field of an odd byte of a 16-bit DMA
channel is an error condition. In case of
DMA read transfers, these encodings must
not be sent by the peripheral after the first
byte has been received. A violation of this
rule causes this check to fire.
LPC_28
A '0000b' (Ready) or '1010b'

(Ready with Error) encoding sent
on the SYNC field of an odd byte
during a write operation on a 16bit DMA channel (6.4.3).
Indicating a '0000b' or '1010b' (Ready or

Ready with Error) encoding on the SYNC
field of an odd byte of a 16-bit DMA
channel is an error condition. In case of
DMA write transfers, these encodings must
not be sent by the peripheral before the first
byte has been transferred. A violation
causes this check to fire.
LPC_29
Larger DMA transfer attempted

on a device which does not
support large transfer sizes (6.1).
If the peripheral is not capable of larger

transfers, then 16-bit/32-bit DMA must not
be performed on channels 0-3 and 32-bit
DMA must not be performed on channels
5-7. A violation causes this check to fire.
LPC_30
A DMA request sent on ldrq port

WIDTH:0],"] for a channel that
has already been requested by
another ldrq port.
No two devices can request DMA transfers

on the same channel number. The monitor
fires if it detects more than one LDRQ#
port requesting DMA transfers using the
same channel number (except channel
number 4).
LPC_31
A Bus Master request sent on ldrq

port
WIDTH:0],"] that is not allowed
to perform Bus Master cycles as
two other ports have already
registered Bus Master requests.
The LPC protocol allows 2 devices capable

of performing bus-master cycles. The
monitor fires if it detects more than 2
devices requesting bus-master cycles.
LPC_32
A message started on ldrq port

WIDTH:0],"] prior to 8 clocks
from de-assertion of a DMA
request using SYNC field (6.4.4).
Since DMA transfers on LPC are requested

through an LDRQ# assertion message and
are ended through a SYNC field during the
DMA transfer, the peripheral must not
assert another message for 8 LCLKs after a
de-assertion is indicated through the SYNC
field. A violation of this rule causes the
monitor to fire.
LPC_unsupported_serirq
Serialized IRQ mode is not

currently supported.
The LPC monitor does not support

serialized IRQ mode.
LPC_unsupported_clkrun_n
Clock Run is not currently

supported.
The LPC monitor does not support clock

run.
LPC_unsupported_pme_n
PME (power management) mode

is not currently supported.
The LPC monitor does not support power

management mode.
LPC_unsupported_lpcpd_n
Power Down mode is not

currently supported.
The LPC monitor does not support power

down mode.
LPC_unsupported_lsmi_n
SMI is not currently supported.
The LPC monitor does not support SMI.
328
Low Pin Count (LPC)


The corner cases captured by the LPC monitor are shown in Table 11-4. These corner cases are
collected separately on the master and target controllers.
Table 11-4. LPC Monitor Corner Cases
Corner Case
Description
Host Initiated I/O Read Transfers
Number of host initiated I/O read operations.
Host Initiated I/O Write Transfers
Number of host initiated I/O write operations.
Host Initiated Memory Read Transfers
Number of host initiated memory read operations.
Host Initiated Memory Write Transfers
Number of host initiated memory write operations.
DMA Read Transfers
Number of DMA read operations.
DMA Write Transfers
Number of DMA write operations.
Peripheral Initiated I/O Read Transfers
Number of peripheral initiated I/O read operations.
Peripheral Initiated I/O Write Transfer
Number of peripheral initiated I/O write operations.
Peripheral Initiated Memory Read Transfers
Number of peripheral initiated memory read operations.
Peripheral Initiated Memory Write Transfers
Number of peripheral initiated memory write operations.
Back to Back Transfers
Number of back to back operations.
Aborted Transfers
Number of operations that are aborted.
8-bit Data Transfers
Number of operations with 8-bit data.
DMA Transfers On Deactivated Channels
Number of times the host went ahead with the DMA

transfer even after the peripheral deactivated the channel.
Monitor Statistics
The statistics captured by the LPC monitor are shown in Table 11-5. These statistics are
Table 11-5. LPC Monitor Statistics
Statistic
Description
Total Transfers
329
Low Pin Count (LPC)

Monitor Statistics
330
Chapter 12
Open Core Protocol (OCP)
Introduction
The Open Core Protocol (OCP) is a core-centric protocol that comprehensively describes the
system level integration requirements of intellectual property (IP) cores. The OCP supports very
high performance data transfer models ranging from simple request-grants through pipelined
and multi-threaded objects. Higher complexity SOC communication models are supported
using thread identifiers to manage out-of-order completion of multiple concurrent transfer
sequences. The QVL OCP monitor is designed for checking the OCP interfaces.
This OCP monitor is modeled from the requirements provided in the following documents:
Open Core Protocol Specification 2.1, Document Revision 1.0, Part number: 161000125-0003.
Open Core Protocol Specification 2.2, Document Revision 1.1
Please refer to Instantiation Modification is Required for OCP 2.1 Users on page 333 for
additional information.
Supported Features
Commands
Basic Commands: Read, Write, Idle.
Five command extensions: WriteNonPost, Broadcast, ReadExclusive, ReadLinked, and

WriteConditional.
Data Transfers
Pipelined data transfers.
Non-Pipelined data transfers.
Bursts
Precise Bursts with single address.
331

Supported Features
Precise Bursts with successive command address.
Imprecise Bursts with successive command address.
Bursts with combined request and data.
Bursts with optional Last signals.
Supports WRAP, INCR, STRM, XOR, and BLCK (two-dimensional) type bursts.
Response Signaling
All types of responses: NULL, DVA, FAIL, and ERR.
Tags
Out-of-order return of responses.
Out-of-order commit of write data.
Threads and Connections
Out-of-order thread processing.
Supports exact ThreadBusy semantics.
Data buses
Partial word transfer using MByteEn and MDataByteEn.
Inband Signaling.
Data transfers with Data Handshake Phase.
Synchronization
Locked Synchronization.
Lazy Synchronization.
Sideband Signals
332
Reset Signals.
Control and Status Signals.

Supported Features
OCP Disconnect Proposal Revision 0.6
Three disconnect signals: mconnect, sconnect, and swait
Parameter CONNECTION and tie-off signal as per the OCP disconnect proposal.
Refer to Instantiation Modification is Required for OCP 2.1 and 2.2 Users on page 334 for
additional information.
Scan Interface, Clock Control Interface, Debug and Test Interface.
The monitor will assume the data as-is and will not perform endianness conversion.
Interleaving of transfers on any of the phases is not supported if the dataflow transfer
checks are enabled. Dataflow transfer checks are enabled by enabling the parameter
ENABLE_INTER_PHASE_TRANFER_CHECKS.
Instantiation Modification is Required for OCP 2.1 Users

The OCP monitor now supports Open Core Protocol Specification 2.2, Document Revision 1.1.
As a result, the monitor has more ports, more bits in some configuration ports, and more
parameters added in its interface.
A user supporting only Open Core Protocol Specification 2.1, Document Revision 1.0 does not
need to be concerned about the OCP 2.2 parameters (detailed in the subsection below) as these
parameters are located at the bottom of the parameter order in the monitor implementation and
they carry their own default values.
Ports Added for OCP 2.2 Compliance

Following are the new ports added for OCP 2.2 compliance (see Table 12-1 on page 341):
enableclk
mareset_n
sareset_n
mblockheight
mblockstride
mdatarowlast
mreqrowlast
sresprowlast
333

Supported Features
The two asynchronous reset ports should each be connected to 1'b1; the remainder of the ports
should be unconnected for a OCP 2.1 specification use model.
Configuration Port Changes for OCP 2.2 Compliance

Following are the configuration ports that have changes for OCP 2.2 compliance (see
Table 12-1 on page 341:
basic_group OCP 2.2 has 8-bits instead of 7-bits in width in OCP 2.1.
burst_ext_group OCP 2.2 has 23-bits instead of 17-bits in width in OCP 2.1.
thread_ext_group OCP 2.2 has 10-bits instead of 7-bits in width in OCP 2.1.
The new higher order bits are all set to 0 when connecting these configuration ports for a OCP
2.1 specification use model.
Parameters Added for OCP 2.2 Compliance

The following parameters are added to the end of the order of the existing parameters, and they
all have default values (see Table 12-2 on page 350):
BLOCKHEIGHT_WDTH
BLOCKSTRIDE_WDTH
These parameters can be ignored for a OCP 2.1 specification use model instance of the monitor.
Instantiation Modification is Required for OCP 2.1 and 2.2

Users
The following ports and parameters are part of OCP Disconnect Proposal (version 0.6) that
require special handling by the OCP 2.1 and OCP 2.2 users:
Parameter CONNECTION: Leave at default value 0.
Ports mconnect, sconnect, swait: Leave these ports unconnected.
Following is the configuration port change for OCP Disconnect Proposal compliance:
sideband_sig_group Port has support for 7-bit width instead of 6-bit width in OCP
2.1 and OCP 2.2 (see Table 12-1 on page 341).
The new higher order bits are all set to 0 when connecting these configuration ports for a OCP
2.1 or 2.2 specification use model.
Example Instance of the Monitor Using OCP 2.1 Specification

A typical example instance of the monitor for the OCP 2.1 specification use model is as follows:
qvl_ocp_monitor #(
334

Supported Features
0,
0,
8,
/* ADDR_WDTH */
16,
/* DATA_WDTH */
4,
/* BURSTLENGTH_WDTH */
3,
/* ATOMICLENGTH_WDTH */
3,
/* THREADS */
2,
/* THREADID_WDTH */
1,
/* CONNID_WDTH */
2,
/* ADDRSPACE_WDTH */
16,
/* MDATAINFO_WDTH */
4,
/* MDATAINFOBYTE_WDTH */
10,
/* REQINFO_WDTH */
10,
/* RESPINFO_WDTH */
16,
/* SDATAINFO_WDTH */
4,
/* SDATAINFOBYTE_WDTH */
4,
/* CONTROL_WDTH */
4,
/* STATUS_WDTH */
3,
/* TAGS */
2,
/* TAGID_WDTH */
1,
/* TAG_INTERLEAVE_SIZE */
1,
/* ENABLE_INTER_PHASE_TRANFER_CHECKS */
16
/* MAX_OUTSTANDING_REQ */
// Neglected OCP 2.2 and disconnect specification relevant
// parameters
)
OCP_MONITOR ( .clk(Clk),
.enableclk(), // Unconnected OCP 2.2 specific port
.areset_n(1'b1),
.mdata(MData),
.mdatavalid (MDatavalid),
.mrespaccept(MRespaccept),
.scmdaccept(SCmdaccept),
.sdata(SData),
.sdataaccept(SDataaccept),
.sresp(SResp),
.maddrspace(MAddrSpace),
.mbyteen(MByteen),
.mdatabyteen(MDatabyteen),
.mdatainfo(MDataInfo),
.mreqinfo(MReqInfo),
.sdatainfo(SDataInfo),
.srespinfo(SRespInfo),
.matomiclength(MAtomicLength),
.mburstlength(MBurstLength),
.mburstprecise(MBurstPrecise),
.mburstseq(MBurstSeq),
.mburstsinglereq(MBurstSingleReq),
.mdatalast(MDatalast),
.mreqlast(MReqLast),
.sresplast(SResplast),
.mdatatagid(MDataTagID),
.mtagid(MTagID),
.mtaginorder(MTagInOrder),
.stagid(STagID),
.staginorder(STagInOrder),
.mconnid(MConnID),
.mdatathreadid(MDataThreadID),
335

Supported Features
.mthreadbusy(MThreadBusy),
.mthreadid(MThreadID),
.sdatathreadbusy(SDataThreadBusy),
.sthreadbusy(SThreadBusy),
.sthreadid(SThreadID),
.mreset_n(MReset_n),
.sreset_n(SReset_n),
.mareset_n(1'b1), // OCP 2.2 specific async reset tied to 1'b1
.sareset_n(1'b1), // OCP 2.2 specific async reset tied to 1'b1
.control(4'd0),
.controlbusy(1'b0),
.controlwr(1'b0),
.status(4'd0),
.statusbusy(1'b0),
.statusrd(1'b0),
.base(8'b0),
.phase_options_group(3'b001),
.basic_group(8'b0111_1111), // The 8th bit position is set to 0.
.simple_ext_group(7'b001_0100),
.burst_ext_group(23'b000_0000_0110_1011_0000_0001), // 18th - 23rd
// bit positions are all set to 0s
.tag_ext_group(1b0),
.thread_ext_group(10b00_0111_1111), // 8th - 10th bit positions
// are all set to 0s.
.sideband_sig_group(7'b000_0000),
.cmd_enable_group(6'b00_0011)
.mblockheight(), // OCP 2.2 specific ports are left unconnected
.mblockstride(),
.mdatarowlast(),
.mreqrowlast(),
.sresprowlast(),
.mconnect(), // Disconnect specific ports are left unconnected
.sconnect(),
.swait()
);
Refer to Instantiation Examples on page 352 for OPC 2.2 typical examples.
Example Instance of the Monitor Using OCP 2.2 Specification

A typical example instance of the monitor for the OCP 2.2 specification use model is as follows:
qvl_ocp_monitor #(
0,
0,
8,
/* ADDR_WDTH */
16,
/* DATA_WDTH */
4,
3,
3,
/* THREADS */
2,
/* THREADID_WDTH */
1,
/* CONNID_WDTH */
2,
16,
4,
10,
/* REQINFO_WDTH */
10,
/* RESPINFO_WDTH */
16,
336

Supported Features
4,
4,
4,
3,
2,
1,
1,
16,
0,
/*
/*
/*
/*
/*
/*
/*
/*
/*
SDATAINFOBYTE_WDTH */
CONTROL_WDTH */
STATUS_WDTH */
TAGS */
TAGID_WDTH */
TAG_INTERLEAVE_SIZE */
ENABLE_INTER_PHASE_TRANFER_CHECKS */
MAX_OUTSTANDING_REQ */
BLOCKHEIGHT_WDTH; To ensure backward compatibility, this parameter must be 0
for 2.1 use model as this is disabled in the configuration for 2.1 */
4
/* BLOCKSTRIDE_WDTH */
// Neglected disconnect specification relevant parameters
)
OCP_MONITOR ( .clk(Clk),
.enableclk(), // Unconnected OCP 2.2 specific port
.areset_n(1'b1),
.mdata(MData),
.mdatavalid (MDatavalid),
.mrespaccept(MRespaccept),
.scmdaccept(SCmdaccept),
.sdata(SData),
.sdataaccept(SDataaccept),
.sresp(SResp),
.maddrspace(MAddrSpace),
.mbyteen(MByteen),
.mdatabyteen(MDatabyteen),
.mdatainfo(MDataInfo),
.mreqinfo(MReqInfo),
.sdatainfo(SDataInfo),
.srespinfo(SRespInfo),
.matomiclength(MAtomicLength),
.mburstlength(MBurstLength),
.mburstprecise(MBurstPrecise),
.mburstseq(MBurstSeq),
.mburstsinglereq(MBurstSingleReq),
.mdatalast(MDatalast),
.mreqlast(MReqLast),
.sresplast(SResplast),
.mdatatagid(MDataTagID),
.mtagid(MTagID),
.mtaginorder(MTagInOrder),
.stagid(STagID),
.staginorder(STagInOrder),
.mconnid(MConnID),
.mdatathreadid(MDataThreadID),
.mthreadbusy(MThreadBusy),
.mthreadid(MThreadID),
.sdatathreadbusy(SDataThreadBusy),
.sthreadbusy(SThreadBusy),
.sthreadid(SThreadID),
.mreset_n(MReset_n),
.sreset_n(SReset_n),
.mareset_n(1'b1), // OCP 2.2 specific async reset tied to 1'b1
.sareset_n(1'b1), // OCP 2.2 specific async reset tied to 1'b1
.control(4'd0),
.controlbusy(1'b0),
.controlwr(1'b0),
.status(4'd0),
337

.statusbusy(1'b0),
.statusrd(1'b0),
.base(8'b0),
.basic_group(8'b0111_1111), // The 8th bit position is set to 0.
.simple_ext_group(7'b001_0100),
.burst_ext_group(23'b000_0000_0110_1011_0000_0001), // 18th - 23rd
// bit positions are all set to 0s
.tag_ext_group(1b0),
.thread_ext_group(10b00_0111_1111), // 8th - 10th bit positions
// are all set to 0s.
.cmd_enable_group(6'b00_0011)
.mblockheight(), // OCP 2.2 specific ports are leftunconnected
.mblockstride(),
.mdatarowlast(),
.mreqrowlast(),
.sresprowlast(),
.sconnect(),
.swait()
);

The QVL OCP monitor can be placed on the master or slave side to provide interface checks.
The checks in the OCP monitor can also be used as search targets and check constraints while
running formal analysis on the OCP master or slave devices. A typical OCP setup is shown in
Figure 12-1.
Figure 12-1. OCP Monitor Implementation
OCP
Interface
OCP
Compliant
Device
(Master)
OCP
MW
System / Core
OCP
MW
OCP
Compliant
Device
(Slave)
Core / System
In Figure 12-1, the Core / System side means the IP block side. The System / Core side means
the interconnect side (if any), or simply the bus wrapper interface module.
The four parameter values for the INTERFACE_TYPE parameter (see Table 12-2 on page 350)
comes from the four possible locations of the OCP monitor instance in reference to the system
configuration diagram shown in Figure 12-2. The required INTERFACE_TYPE parameter values
at specific locations in the whole system as per monitor instances are as follows:
338

If the user connects the monitor to the OCP Master DUT, then set as follows:
INTERFACE_TYPE = 0
If the user connects the monitor to the OCP Slave DUT, then set as follows:
INTERFACE_TYPE = 1
If the user connects the monitor to the Master side of the interconnect/bus wrapper
module, then set as follows:
INTERFACE_TYPE = 2
If the user connects the monitor to the Slave side of the interconnect/bus wrapper
module, then set as follows:
INTERFACE_TYPE = 3
Note that these parameter values come into play only when the Constraints_Mode parameter
is set to 1 (see Table 12-2 on page 350).
The system configuration block diagram (Figure 12-2) depicts the configuration around three
possible DUTs: Master DUT, Slave DUT, and both the Master DUT and Slave DUT.
339

Figure 12-2. OCP Monitor

System Initiator
System Initiator / Target
Core
System Target
Core
Core
INTERFACE_TYPE=0
INTERFACE_TYPE=0
INTERFACE_TYPE=1
INTERFACE_TYPE=1
DUT Master
DUT Master
DUT Slave
DUT Slave
Response
OCP
Bus
wrapper
interface
module
Request
Slave
Slave
Master
Master
INTERFACE_TYPE=3
INTERFACE_TYPE=3
INTERFACE_TYPE=2
INTERFACE_TYPE=2
Bus Initiator
Bus Initiator / Target
Bus Target
On-Chip Bus
Note:
This figure illustrates the OPC system configuration showing the OPC monitor INTERFACE_TYPE
parameter value with regards to the monitor instance location.
Connect the OCP monitor pins as specified in the pin-out Table 12-1 and illustrated in
Figure 12-3.
340

mconnid
mdatathreadid
mthreadbusy
mthreadid
sdatathreadbusy
sthreadbusy
sthreadid
maddrspace
mbyteen
mdatabyteen
mdatainfo
mreqinfo
sdatainfo
srespinfo
OCP
Monitor
matomiclength
mblockheight
mblockstride
mburstlength
mburstprecise
mburstseq
mburstsinglereq
mdatalast
mdatarowlast
mreqlast
mreqrowlast
sresplast
sresprowlast
mreset_n
mareset_n
sreset_n
sareset_n
control
controlbusy
controlwr
status
statusbusy
statusrd
mconnect
sconnect
swait
phase_options_group
basic_group
simple_ext_group
burst_ext_group
tag_ext_group
thread_ext_group
sideband_sig_group
cmd_enable_group
areset_n
base
Tag
Extensions
Thread
Extensions
mdatatagid
mtagid
mtaginorder
stagid
staginorder
Sideband Signals
clk
enableclk
maddr
mcmd
mdata
mdatavalid
mrespaccept
scmdaccept
sdata
sdataaccept
sresp
Monitor Signals
Burst Extensions
Simple Extensions
Basic Signals
Figure 12-3. OCP Monitor Pin Diagram
Table 12-1. OCP Monitor Pin

Port
Width (bits)
Description
areset_n
Asynchronous reset signal (active low). This signal is not part of OCP
interface.
341

Table 12-1. OCP Monitor Pin (cont.)

Port
Width (bits)
Description
base
configurable
BASE address for the XOR (exclusive OR) bursts. Width of this signal
is same as the maddr signal. This signal is required only if XOR bursts
are enabled.
The parameter BASE_PORT_SPECIFIED determines if the value at
this port matters. This parameter specifies if the base address for XOR
bursts is calculated by the user and passed to the monitor, or the monitor
should self-calculate the base address value for a XOR burst type
transaction. See the description of the BASE_PORT_SPECIFIED
parameter for more information.
basic_group
Bit position
0
1
2
3
4
5
6
7
See Note 2.
burst_ext_group
23
Bit position
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
clk
Input clock to OCP.
cmd_enable_group
Bit position
0
1
2
3
4
5
control
configurable
Core control information
342
Parameter
ADDR
CMDACCEPT
DATAACCEPT
MDATA
SDATA
RESPACCEPT
RESP
ENABLECLK
Parameter
BURSTSEQ_INCR_ENABLE
BURSTSEQ_STRM_ENABLE
BURSTSEQ_WRAP_ENABLE
BURSTSEQ_XOR_ENABLE
BURSTSEQ_DFLT1_ENABLE
BURSTSEQ_DFLT2_ENABLE
BURSTSEQ_UNKN_ENABLE
ATOMICLENGTH
BURSTLENGTH
BURSTPRECISE
BURSTSEQ
BURSTSINGLEREQ
REQLAST
DATALAST
RESPLAST
BURST_ALIGNED
FORCE_ALIGNED
BURSTSEQ_BLCK_ENABLE
BLOCKHEIGHT
BLOCKSTRIDE
DATAROWLAST
REQROWLAST
RESPROWLAST
Parameter
READ_ENABLE
WRITE_ENABLE
WRITENONPOST_ENABLE
BROADCAST_ENABLE
RDLWRC_ENABLE
READEX_ENABLE


Port
Width (bits)
Description
controlbusy
Hold control information
controlwr
Control information has been written
enableclk
Gating signal for the input clock to derive the OCP clock. This signal is
effective when the OCP parameter enableclk is set to 1 (configured
under basic signal group, refer to Note 6 below).
maddr
configurable
Transfer address
maddrspace
configurable
Address space
mareset_n
Active low asynchronous master reset signal. If the OCP application

supports asynchronous reset, then this signal must be connected to
appropriate asynchronous master reset signal and the monitors
synchronous master reset signal input mreset_n should be tied HIGH
(always inactive synchronous reset). However, if the application
supports synchronous reset only, then this signal should be tied to HIGH
(always inactive asynchronous reset) and the monitors synchronous
master reset signal input mreset_n must be connected to appropriate
synchronous master reset signal.
matomiclength
configurable
Length of atomic burst
mblockheight
configurable
Number of rows in a block burst
mblockstride
configurable
Address difference between the first data word in each consecutive row
in a block burst.
mburstlength
configurable
Burst length
mburstprecise
Given burst length is precise
mburstseq
Address sequence of burst
mburstsinglereq
Burst uses single request / multiple data protocol
mbyteen
configurable
Request phase byte enables
mcmd
Transfer command
mconnect
Master signal for OCP disconnect/connect control
mconnid
configurable
Connection identifier
mdata
configurable
Write data
mdatabyteen
configurable
Datahandshake phase write byte enables
mdatainfo
configurable
Additional information transferred with the write data
mdatalast
Last write data in burst
mdatarowlast
Last dataphase in a row in a block burst
mdatatagid
configurable
Ordering tag for write data
mdatathreadid
configurable
Write data thread identifier
mdatavalid
Write data valid
mreqinfo
configurable
Additional information transferred with the request
mreqlast
Last request in burst
343


Port
Width (bits)
Description
mreqrowlast
Last request phase in a row in a block burst
mreset_n
Synchronous master reset (also see description for mareset_n)
mrespaccept
Master accepts response
mtagid
configurable
Ordering tag for request
mtaginorder
Do not reorder this request
mthreadbusy
configurable
Master thread busy
mthreadid
configurable
Request thread identifier
phase_options_group
Bit position
0
1
2
See Note 2.
sareset_n
Active low asynchronous slave reset signal. If the OCP application

supports asynchronous reset, then this signal must be connected to
appropriate asynchronous slave reset signal and the monitors
synchronous slave reset signal input sreset_n should be tied HIGH
(always inactive synchronous reset). However, if the application
supports synchronous reset only, then this signal should be tied to HIGH
(always inactive asynchronous reset) and the monitors synchronous
slave reset signal input sreset_n must be connected to appropriate
synchronous slave reset signal.
scmdaccept
Slave accepts command transfer
sconnect
Slave signal for OCP disconnect/connect request
sdata
configurable
Read data
sdataaccept
Slave accepts write data
sdatainfo
configurable
Additional information transferred with the read data
sdatathreadbusy
configurable
Slave write data thread busy
sideband_sig_group
Bit position
0
1
2
3
4
5
6
344
Parameter
DATAHANDSHAKE
REQDATA_TOGETHER
WRITERESP_ENABLE
Parameter
CONTROL
CONTROLBUSY
CONTROLWR
STATUS
STATUSBUSY
STATUSRD
CONNECTCAP


Port
Width (bits)
Description
simple_ext_group
Bit position
0
1
2
3
4
5
6
See Note 2.
sreset_n
Synchronous slave reset (also see description for sareset_n)
sresp
Transfer response
srespinfo
configurable
Additional information transferred with the response
sresplast
Last response in burst
sresprowlast
Last response phase in a row in a block burst
stagid
configurable
Ordering tag for response
staginorder
This response is not reordered
status
configurable
Core status information
statusbusy
Status information is not consistent
statusrd
Status information has been read
sthreadbusy
configurable
Slave request thread busy
sthreadid
configurable
Response thread identifier
swait
Slave signal for insert/bypass wait states for disconnect/connect events
tag_ext_group
Bit position
Parameter
0
TAGINORDER
thread_ext_group
10
Bit position
Parameter
0
MTHREADBUSY_EXACT
1
SDATATHREADBUSY_EXACT
2
STHREADBUSY_EXACT
3
CONNID
4
MTHREADBUSY
5
SDATATHREADBUSY
6
STHREADBUSY
7
MTHREADBUSY_PIPELINED
8
SDATATHREADBUSY_PIPELINED
9
STHREADBUSY_PIPELINED
tieoff_connectcap
This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON

is enabled while compiling the monitor. Custom tie-off value for the
OCP disconnect parameter ConnectCap.
tieoff_control
configurable

port control is configured through this port.
Parameter
ADDRSPACE
BYTEEN
MDATABYTEEN
MDATAINFO
REQINFO
RESPINFO
SDATAINFO
345


Port
Width (bits)
Description
tieoff_controlbusy

port controlbusy is configured through this port.
tieoff_controlwr

port controlwr is configured through this port.
tieoff_enableclk

port enableclk is configured through this port.
tieoff_maddr
configurable

port maddr is configured through this port.
tieoff_maddrspace
configurable

port maddrspace is configured through this port.
tieoff_matomiclength
configurable

port matomiclength is configured through this port.
tieoff_mblockheight
configurable

port mblockheight is configured through this port.
tieoff_mblockstride
configurable

port mblockstride is configured through this port.
tieoff_mburstlength
configurable

port mburstlength is configured through this port.
tieoff_mburstprecise

port mburstprecise is configured through this port.
tieoff_mburstseq

port mburstseq is configured through this port.
tieoff_mburstsinglereq 1

port mburstsinglereq is configured through this port.
tieoff_mbyteen
configurable

port mbyteen is configured through this port.
tieoff_mconnid
configurable

port mconnid is configured through this port.
tieoff_mdata
configurable

port mdata is configured through this port.
346


Port
Width (bits)
Description
tieoff_mdatabyteen
configurable

port mdatabyteen is configured through this port.
tieoff_mdatainfo
configurable

port mdatainfo is configured through this port.
tieoff_mdatalast

port mdatalast is configured through this port.
tieoff_mdatarowlast

port mdatarowlast is configured through this port.
tieoff_mdatatagid
configurable

port mdatatagid is configured through this port.
tieoff_mdatathreadid
configurable

port mdatathreadid is configured through this port.
tieoff_mdatavalid

port mdatavalid is configured through this port.
tieoff_mreqinfo
configurable

port mreqinfo is configured through this port.
tieoff_mreqlast

port mreqlast is configured through this port.
tieoff_mreqrowlast

port mreqrowlast is configured through this port.
tieoff_mrespaccept

port mrespaccept is configured through this port.
tieoff_mtagid
configurable

port mtagid is configured through this port.
tieoff_mtaginorder

port mtaginorder is configured through this port.
tieoff_mthreadbusy
configurable

port mthreadbusy is configured through this port.
tieoff_mthreadid
configurable

port mthreadid is configured through this port.
347


Port
Width (bits)
Description
tieoff_scmdaccept

port scmdaccept is configured through this port.
tieoff_sdata
configurable

port sdata is configured through this port.
tieoff_sdataaccept

port sdataaccept is configured through this port.
tieoff_sdatainfo
configurable

port sdatainfo is configured through this port.
tieoff_sdatathreadbusy configurable

port sdatathreadbusy is configured through this port.
tieoff_sresp

port sresp is configured through this port.
tieoff_srespinfo
configurable

port srespinfo is configured through this port.
tieoff_sresplast

port sresplast is configured through this port.
tieoff_sresprowlast

port sresprowlast is configured through this port.
tieoff_stagid
configurable

port stagid is configured through this port.
tieoff_staginorder

port staginorder is configured through this port.
tieoff_status
configurable

port status is configured through this port.
tieoff_statusbusy
configurable

port statusbusy is configured through this port.
tieoff_statusrd

port statusrd is configured through this port.
tieoff_sthreadbusy
configurable

port sthreadbusy is configured through this port.
348


Port
Width (bits)
Description
tieoff_sthreadid
configurable

port sthreadid is configured through this port.
Notes:
1. Refer to the parameters section for description of parameters that configure the width of
the ports.
2. Bit 0 is the Least Significant Bit. Device parameters are configured as shown in the
following examples.
Example (a): If the design under test (DUT) supports the DATAHANDSHAKE
feature, then bit 0 of the port phase_options_group is set to 1'b1.
Example (b): If the design under test (DUT) supports Status signal, then bit 3 of the
port sideband_sig_group is set to 1'b1.
Example (c): If the design under test (DUT) supports disconnect protocol of OCP,
then the highest order bit 6 of the port sideband_sig_group is set to 1'b1.
3. If a signal is not configured for an interface, then the corresponding monitor port can be
left unconnected. A default tie-off value (as specified by the specification) for that signal
is assumed by the monitor. In the case where the design uses a tie-off value other than
default tie-off, the signal should be configured and tied to the tie-off value used in the
design.
The monitor also supports configuring tie-off values through additional ports in the
monitor interface. For such mode of tie-off configuration, the user has to do the
following:
i. Add +define+QVL_OCP_TIEOFF_CONFIG_ON to the command line while
compiling the monitor.
ii. The respective signal to be tied off to a custom value should not be configured in
the configuration ports.
iii. Connect the custom tie-off values to the tie-off configuration specific ports listed
in Table 12-1 on page 341.
4. Reset signals (mreset_n, sreset_n) should be tied to the proper system reset or to the
inactive condition (1'b1).
5. OCP specifies that the reset signals (mreset_n and sreset_n) should be asserted for at
least 16 clock cycles. Monitor does not check for this and enters in to reset state in the
first clock cycle on which reset is sampled asserted.
349

6. If the signal enableclk is added to the OCP interface, then the 8th bit in the monitor
configuration port, basic_signal_group should be set to 1. Then the derived OCP
clock used by the monitor is controlled by the enableclk signal. However, if the
signal enableclk is not added to the OCP interface, then the 8th bit in the same
configuration port should be set to the OCP recommended default 0. Then the derived
OCP clock used by the monitor is the same as the input clock.
Monitor Parameters
The parameters shown in Table 12-2 configure the OCP monitor.
Table 12-2. OCP Monitor Parameters
Order Parameter
Default
Description
1.
Constraints_Mode

2.
INTERFACE_TYPE

0 => Master interface on core side
1 => Slave interface on core side
2 => Master interface on system side
3 => Slave interface on system side
3.
ADDR_WDTH
32
Configures the width of maddr signal.
4.
DATA_WDTH
32
Configures the width of mdata / sdata signal.
5.
BURSTLENGTH_WDTH
Configures the width of mburstlength signal.
6.
ATOMICLENGTH_WDTH
Configures the width of matomiclength signal.
7.
THREADS
Number of threads.
8.
THREADID_WDTH
Configures the width of mthreadid / mdatathreadid /

sthreadid signal.
9.
CONNID_WDTH
Configures the width of mconnid signal.
10.
ADDRSPACE_WDTH
Configures the width of maddrspace signal.
11.
MDATAINFO_WDTH
Configures the width of mdatainfo signal.
12.
MDATAINFOBYTE_WDTH
The number of bits in mdatainfo associated with

each data byte in mdata signal.
13.
REQINFO_WDTH
Configures the width of mreqinfo signal.
14.
RESPINFO_WDTH
Configures the width of srespinfo signal.
15.
SDATAINFO_WDTH
Configures the width of sdatainfo signal.
16.
SDATAINFOBYTE_WDTH
The number of bits in sdataInfo associated with

each data byte in sdata signal.
17.
CONTROL_WDTH
Configures the width of control signal.
350

Table 12-2. OCP Monitor Parameters (cont.)

Order Parameter
Default
Description
18.
STATUS_WDTH
Configures the width of status signal.
19.
TAGS
Number of tags.
20.
TAGID_WDTH
Configures the width of mtagid / mdatatagid / stagid

signal.
21.
TAG_INTERLEAVE_SIZE
Defines the interleaving granularity for the

responses.
22.
ENABLE_INTER_PHASE_
TRANFER_CHECKS
Set this parameter to 1 to enable inter phase

dataflow transfer checks.
23.
MAX_OUTSTANDING_REQ
16
Defines the maximum number of outstanding

requests. This parameter indicates the depth of the
outstanding requests memory in the monitor.
24.
BLOCKHEIGHT_WDTH
Defines the width of the port blockheight.

blockheight_wdth must be 0 if blockheight is
disabled.
blockheight_wdth must be greater than 1 if
blockheight is enabled.
To ensure backward compatibility, this parameter
must be 0 for 2.1 use model as this is disabled in the
configuration for 2.1.
25.
BLOCKSTRIDE_WDTH
Defines the width of the port blockstride.
26.
BASE_PORT_SPECIFIED
This parameter specifies if the base address for

XOR bursts is calculated by the user and passed to
the monitor. A value of 0 indicates that the base
address is calculated internally by the monitor. A
value of 1 (or other than 0) indicates that the base
address is supplied by the user through the port
base.
27.
CONNECTION
Parameter for disconnect support.

Default value 0 denotes that OCP disconnect is not
supported by default and both master and slave are
considered to be always connected.
Set this parameter to 1 to support OCP disconnect
proposal.
28.
This parameter can be used to enable / disable

checking X / Z on read and/or write data bus. By
default these checks are enabled.
Set this parameter to 0 to disable both write and read
data checks.
Set this parameter to 3 to enable both write and read
data checks.
Set this parameter to 1 to enable only write data
checks.
Set this parameter to 2 to enable only read data
checks.
Notes:
351

Example 1
Example 12-1 instantiates an OCP monitor on a master interface of the core side. The OCP
interface has an address width of 16 bits and data width of 64-bits. Datahandshake and response
phases are enabled. The interface supports all types of burst address sequences and all type of
commands. All tag extensions, thread extensions, control, and status related features are
disabled. The signals mrespaccept, scmdaccept, sdataaccept are all disabled. Therefore,
all phases are accepted on the same clock cycle.
Example 12-1. OCP Monitor Instantiation for Example 1
qvl_ocp_monitor #(
1,
0,
16,
/* ADDR_WDTH */
64,
/* DATA_WDTH */
5,
1,
1,
/* THREADS */
1,
/* THREADID_WDTH */
1,
/* CONNID_WDTH */
4,
8,
1,
1,
/* REQINFO_WDTH */
1,
/* RESPINFO_WDTH */
8,
1,
1,
/* CONTROL_WDTH */
1,
/* STATUS_WDTH */
1,
/* TAGS */
1,
/* TAGID_WDTH */
1,
1,
16,
4,
/* BLOCKHEIGHT_WDTH */
4,
0,
/* BASE_PORT_SPECIFIED */
0
/*.CONNECTION */ Disconnect parameter default at zero that
// means the device is always connected and is not
// disconnected capable.
)
OCP_MONITOR
(.clk(clk),
.areset_n(1'b1),
.maddr(maddr),
.mcmd(mcmd),
.mdata(mdata),
.mdatavalid(mdatavalid),
.mrespaccept(),
.scmdaccept(),
.sdata(sdata),
352

.sdataaccept(),
.sresp(sresp),
.maddrspace(maddrspace),
.mbyteen(mbyteen),
.mdatabyteen(mdatabyteen),
.mdatainfo(mdatainfo),
.mreqinfo(mreqinfo),
.sdatainfo(sdatainfo),
.srespinfo(srespinfo),
.matomiclength(),
.mburstlength(mburstlength),
.mburstprecise(mburstprecise),
.mburstseq(mburstseq),
.mburstsinglereq(),
.mdatalast(),
.mreqlast(),
.sresplast(),
.mdatatagid(),
.mtagid(),
.mtaginorder(),
.stagid(),
.staginorder(),
.mconnid(),
.mdatathreadid(),
.mthreadbusy(),
.mthreadid(),
.sdatathreadbusy(),
.sthreadbusy(),
.sthreadid(),
.mreset_n(mreset_n),
.sreset_n(sreset_n),
.control(),
.controlbusy(),
.controlwr(),
.status(),
.statusbusy(),
.statusrd(),
.base(),
.basic_group(8'b0101_1101)),
.simple_ext_group(7'b111_1111)),
.burst_ext_group(23'b000_0000_0000_0111_0111_1111),
.tag_ext_group(1'b0),
.thread_ext_group(7'b000_0000),
.cmd_enable_group(6'b11_1111),
.enableclk(),
.mareset_n(1'b1),
.sareset_n(1'b1),
.mblockheight(),
.mblockstride(),
.mdatarowlast(),
.mreqrowlast(),
.sresprowlast(),
.sconnect(),
.swait()
);
353

Note that the tie-off specific ports are not shown in the example instances. These ports are
available only under the specific macro QVL_OCP_TIEOFF_CONFIG_ON (see Table 12-1 on
page 341).
Example 2
Example 12-2 instantiates an OCP monitor on a slave interface of the system side. The OCP
interface has an address width of 16-bits and data width of 16-bits. Datahandshake and response
phases are enabled. The interface supports only INCR and WRAP type of burst address
sequences. All type of commands are supported. All tag extensions and thread extensions
related features are disabled. Control and status related features are enabled. The signals
mrespaccept, scmdaccept, sdataaccept are all disabled. Therefore, all phases are accepted
on the same clock cycle.
Example 12-2. OCP Monitor Instantiation for Example 2
qvl_ocp_monitor #(
1,
0,
16,
/* ADDR_WDTH */
16,
/* DATA_WDTH */
5,
1,
1,
/* THREADS */
1,
/* THREADID_WDTH */
1,
/* CONNID_WDTH */
2,
2,
1,
1,
/* REQINFO_WDTH */
1,
/* RESPINFO_WDTH */
2,
1,
2,
/* CONTROL_WDTH */
2,
/* STATUS_WDTH */
1,
/* TAGS */
1,
/* TAGID_WDTH */
1
1,
16,
4,
/* BLOCKHEIGHT_WDTH */
4,
0,
/* BASE_PORT_SPECIFIED */
0
/*.CONNECTION */ Disconnect parameter default at zero that
// means the device is always connected and is not
// disconnected capable.
)
OCP_MONITOR
(.clk(clk),
.areset_n(1'b1),
.maddr(maddr),
.mcmd(mcmd),
.mdata(mdata),
354

.mdatavalid(mdatavalid),
.mrespaccept(),
.scmdaccept(),
.sdata(sdata),
.sdataaccept(),
.sresp(sresp),
.maddrspace(maddrspace),
.mbyteen(mbyteen),
.mdatabyteen(mdatabyteen),
.mdatainfo(mdatainfo),
.mreqinfo(mreqinfo),
.sdatainfo(sdatainfo),
.srespinfo(srespinfo),
.matomiclength(),
.mburstlength(mburstlength),
.mburstprecise(mburstprecise),
.mburstseq(mburstseq),
.mburstsinglereq(),
.mdatalast(),
.mreqlast(),
.sresplast(),
.mdatatagid(),
.mtagid(),
.mtaginorder(),
.stagid(),
.staginorder(),
.mconnid(),
.mdatathreadid(),
.mthreadbusy(),
.mthreadid(),
.sdatathreadbusy(),
.sthreadbusy(),
.sthreadid(),
.mreset_n(mreset_n),
.sreset_n(sreset_n),
.control(),
.controlbusy(),
.controlwr(),
.status(),
.statusbusy(),
.statusrd(),
.base(),
.basic_group(8'b0101_1101)),
.simple_ext_group(7'b111_1111)),
.burst_ext_group(23'b000_0000_0000_0111_0000_0101),
.tag_ext_group(1'b0),
.thread_ext_group(7'b000_0000),
.cmd_enable_group(6'b11_1111),
.enableclk(),
.mareset_n(1'b1),
.sareset_n(1'b1),
.mblockheight(),
.mblockstride(),
.mdatarowlast(),
.mreqrowlast(),
.sresprowlast(),
355

Monitor Checks
.sconnect(),
.swait()
);
Note that the tie-off specific ports are not shown in the example instances. These ports are
available only under the specific macro QVL_OCP_TIEOFF_CONFIG_ON (see Table 12-1 on
page 341).
Monitor Checks
Table 12-3 lists the checks performed by the OCP monitor.
Table 12-3. OCP Monitor Check
Check ID
Violation
Description
FIRE_OCP_SRESPINFO_NOT_
CONSTANT_DURING_BURST
SRespInfo should be constant

throughout the burst.
Regardless of whether the response is for

precise or imprecise burst, the SRespInfo
signal should be constant during the response
burst. This check fires if this requirement is
violated. This check is active only if the
parameter RESP is set to 1 and parameter
ENABLE_INTER_PHASE_TRANFER_
CHECKS is set to 1.
OCP_ATOMICLENGTH_
WITHOUT_BURSTLENGTH
ATOMICLENGTH should be
enabled only if
BURSTLENGTH is enabled.
The bursts can be issued only if MBurstlength

signal is configured for an interface. Other
burst related signals make sense only when
bursts can be issued. This check fires if
parameter ATOMICLENGTH is enabled
without enabling parameter BURSTLENGTH.
OCP_BCST_CMD_WHILE_
BROADCAST_ENABLE_0
A master with
BROADCAST_ENABLE set
to 0 should not generate
Broadcast command.
A master can generate a Broadcast command

only if parameter BROADCAST_ENABLE is
set. This check fires if Broadcast command is
generated when parameter
BROADCAST_ENABLE is set to 0.
OCP_BLCK_ADDRSPACE_
BOUNDARY_CROSS
A BLCK burst can never cross

the address space boundary.
An address space boundary is the last address

according to ADDRESS_WIDTH parameter
in that address space.
This check fires if BLCK burst sequence
crosses this boundary.
This check is active only if the parameters
BLOCKHEIGHT, BLOCKSTRIDE, and
BURSTSEQ_BLCK_ENABLE are set to 1.
Starting address of each

subsequence of BLCK burst
should be the starting address
of the prior subsequence, plus
MBlockStride.
This check fires if the address for each row of

BLCK burst do not increment by
MBlockStride.
BURSTSEQ_BLCK_ENABLE are set to 1
through the monitor port burst_ext_group.
(OCP 2.2 check)
OCP_BLCK_BURST_
INCORRECT_ADDRESS_
SEQUENCE
(OCP 2.2 check)
356

Monitor Checks
Table 12-3. OCP Monitor Check (cont.)

Check ID
Violation
Description
OCP_BLCK_BURST_WHILE_
BURSTSEQ_BLCK_ENABLE_0
A master with BURSTSEQ_

BLCK_ENABLE set to 0
should not issue BLCK burst.
This check fires if a BLCK burst is presented

when the BURSTSEQ_BLCK_ENABLE
blockheight can only be

enabled if
burstseq_blck_enable is
enabled.
The parameters blockheight and blockstride

depend on the setting of the parameter
burstseq_black_enable.
This check fires if the parameter blockheight is
enabled without enabling the other parameter
burstseq_blck_enable.
blockstride can only be

enabled if
burstseq_blck_enable is
enabled.
The parameters blockheight and blockstride

depend on the setting of the parameter
This check fires if the parameter blockstride is
burstseq_blck_enable.
OCP_BURST_ALIGNED_INCR_
BURST_NOT_PRECISE
When BURST_ALIGNED is
enabled, INCR bursts should
be issued as precise bursts.
The BURST_ALIGNED parameter provides

information about length and alignment of
INCR bursts, and can be used to optimize the
system. INCR bursts should be issued as
precise bursts when BURST_ALIGNED
violated.
OCP_BURST_ALIGNED_
INCR_BURST_SIZE_NOT_
POWER_OF_TWO
enabled, the total burst size of
INCR bursts should be power
of two.

INCR bursts and can be used to optimize the
system. Total burst size of INCR burst must be
power of two when BURST_ALIGNED
parameter is set to 1. This check fires when
this requirement is violated.
OCP_BURST_ALIGNED_INCR_
BURST_UNALIGNED_START_
ADDR
enabled, INCR bursts should
have their starting address
aligned to total burst size.

INCR bursts and can be used to optimize the
system. Starting address of INCR bursts must
be aligned to total burst size when
BURST_ALIGNED parameter is set to 1. This
check fires when this requirement is violated.
OCP_BURSTLENGTH_WDTH_
VALUE_OF_1
The
BURSTLENGTH_WDTH
value should not be set to 1.
Bursts are enabled on an interface to enable

transfers of length more than 1. To express a
meaningful burst, BURSTLENGTH_WDTH
must be at least 2 bits wide. This check fires if
the value of the BURSTLENGTH_WDTH
parameter is configured to be equal to 1. This
check is active only if the BURSTLENGTH
OCP_BURSTPRECISE_
WITHOUT_BURSTLENGTH
BURSTPRECISE should be
enabled only if

parameter BURSTPRECISE is enabled
(OCP 2.2 check)

OCP_BLOCKHEIGHT_
WITHOUT_BURSTSEQ_BLCK_
ENABLE
(OCP 2.2 check)
OCP_BLOCKSTRIDE_
WITHOUT_BURSTSEQ_BLCK_
ENABLE
(OCP 2.2 check)
357

Monitor Checks

Check ID
Violation
Description
OCP_BURSTSEQ_WITHOUT_
BURSTLENGTH
BURSTSEQ should be
enabled only if

parameter BURSTSEQ is enabled without
enabling parameter BURSTLENGTH.
OCP_BURSTSINGLEREQ_
ENABLED_WHILE_ONLY_
UNKN_ADDR_SEQ_ENABLED
BURSTSINGLEREQ should
not be enabled if the only
enabled burst address sequence
is UNKN.
For single request / multiple data bursts, only

the start address is issued with the request by
master. The slave has to calculate address for
each data transfer from the type of address
sequence (MBurstSeq field value). By
definition, burst address sequence for UNKN
burst sequence type is not statically known.
Hence, these bursts should not be issued as
single request / multiple data bursts. This
check fires when parameter
BURSTSINGLEREQ is enabled and the only
enabled burst sequence on the interface is
UNKN.
OCP_BURSTSINGLEREQ_
ENABLED_WITHOUT_
BURSTPRECISE
not be enabled if
BURSTPRECISE is not
enabled.
Single request / multiple data burst are

possible if burst length is known statically at
the start of burst (precise burst). This check
fires if parameter BURSTSINGLEREQ is
enabled without enabling parameter
BURSTPRECISE.
OCP_BURSTSINGLEREQ_
ENABLED_WITHOUT_
DATAHANDSHAKE
If any write-type commands

are enabled,
not be enabled if
DATAHANDSHAKE is not
enabled.
Single request / multiple data write type

transactions are possible only if datahandshake
phase is enabled. Parameter
BURSTSINGLEREQ is used to indicate such
transactions. Hence, when write-type
commands are enabled for an interface,
parameter BURSTSINGLEREQ can be
enabled only if parameter
DATAHANDSHAKE is enabled. This check
fires if this restriction is violated.
OCP_BURSTSINGLEREQ_
WITHOUT_BURSTLENGTH
be enabled only if

parameter BURSTSINGLEREQ is enabled
OCP_BYTE_ENABLES_NOT_
FORCE_ALIGNED
A master with
FORCE_ALIGNED option
enabled should not generate
any byte enable patterns that
are not force aligned.
Byte enable field indicates which bytes within

the OCP word are part of the current transfer.
The FORCE_ALIGNED parameter limits byte
enable patterns to be power-of-two in size and
aligned to that size. The byte enable pattern of
all 0s is also a legal pattern. This check fires if
this requirement is violated. This check is
performed on the MByteEn field. This check is
active only if parameter BYTEEN is set to 1
and parameter BURSTSEQ is set to 1.
358

Monitor Checks

Check ID
Violation
Description
OCP_CMDACCEPT_WHILE_
STHREADBUSY_AND_
STHREADBUSY_ XACT
CMDACCEPT should not be

enabled when both
STHREADBUSY and
STHREADBUSY_EXACT
are enabled.
STHREADBUSY_EXACT parameter
requires strict semantics for SThreadbusy
signal to ensure that multithreaded OCP
interface never blocks. This check fires when
parameter CMDACCEPT is enabled when
both the parameters STHREADBUSY and
STHREADBUSY_EXACT are enabled.
OCP_CONNECTCAP_NOT_
TIED_OFF_TO_ZERO_WHILE_
CONNECTION_PARAMETER_
CONFIGURED_ZERO
Connectcap must be
configured as zero while
parameter CONNECTION is
set to zero.
This is an OCP configuration correctness

verification check. When the OCP disconnect
specific parameter CONNECTION is set to 0
in the OCP monitor instance, the only allowed
value for the ConnectCap configuration bit in
the configuration port sideband_signal_group
is 0. This is required by the protocol that if an
OCP device is not disconnection capable, then
it cannot be configured as disconnection
capable.
Control signal should not

change more than once every
other cycle.
If Control signal transitions in the previous

cycle, it should be held steady in the current
cycle. This check fires if transition is detected
on Control signal in the current cycle when it
has already transitioned in the previous cycle.
This check is active only if the parameter
CONTROL is set to 1.
(OCP Disconnect Check)
OCP_CONTROL_CHANGED_
MORE_THAN_ONCE
OCP_CONTROL_CHANGED_
If ControlBusy is sampled
WHILE_CONTROLBUSY_
asserted in the previous cycle,
ACTIVE_IN_PREVIOUS_CYCLE then the Control should not
transition in the current cycle.
ControlBusy signal from the core indicates to

the system that it should hold Control signal
constant in the next cycle. This check fires
when Control signal transitions in the current
cycle when ControlBusy signal is sampled
asserted in the previous cycle. This check is
active only if the parameters CONTROL and
CONTROLBUSY are set to 1.
OCP_CONTROL_NOT_
STEADY_AFTER_RESET
Control should be held steady

for the first two cycles after
reset is de-asserted.
After the de-assertion of reset, Control signal

should be held constant for two clock cycles.
This check fires if this requirement is not met.
CONTROL is set to 1.
OCP_CONTROL_UNKN
Control signal should not be X

or Z.
Checks that Control is both known (not X) and

driven (not Z).
OCP_CONTROLBUSY_ UNKN
ControlBusy signal should not

be X or Z.
Checks that ControlBusy is both known (not

OCP_CONTROLBUSY_
ASSERTED_INCORRECTLY
ControlBusy should only be

asserted immediately after
reset is de-asserted, or in the
cycle after ControlWr is
asserted.
ControlBusy signal is set to 1 by the core to

indicate that the control information should be
held constant by the system. Hence,
ControlBusy signal can be asserted in the
following cycle after reset de-assertion or
cycle after ControlWr assertion. This check is
active only if the parameters
CONTROLBUSY and CONTROLWR are set
to 1.
359

Monitor Checks

Check ID
Violation
Description
OCP_CONTROLBUSY_
ENABLED_WITHOUT_
CONTROLWR
CONTROLBUSY should be
enabled only if
CONTROLWR is enabled.
ControlBusy signal is applicable only if

ControlWr signal is configured for an
interface. This check fires if parameter
CONTROLBUSY is enabled without enabling
parameter CONTROLWR.
OCP_CONTROLWR_
ASSERTED_FOR_MORE_
THAN_ ONE_CYCLE
ControlWr should not be

active for more than one clock
cycle.
ControlWr signal is set to 1 by the system to

indicate that the control information is written
by the system. Control information may not be
written to core continuously. This check fires
if the ControlWr signal is detected to be active
for more than one clock cycle. This check is
active only if the parameter CONTROLWR is
set to 1.
OCP_CONTROLWR_
ASSERTED_IN_FIRST_CYCLE_
AFTER_RESET
ControlWr signal should not

be asserted in the cycle
following a reset.
In the first clock cycle after reset de-assertion,

ControlWr signal should be held de-asserted.
This check fires if this requirement is not met.
CONTROLWR is set to 1.
OCP_CONTROLWR_
ASSERTED_WHILE_
CONTROLBUSY_ACTIVE

be asserted if ControlBusy is
asserted.

by the system. ControlBusy signal from the
core indicates to the system that it should hold
Control signal constant in the next cycle. This
check fires when ControlWr signal is sampled
asserted when ControlBusy signal is asserted.
CONTROLBUSY and CONTROLWR are set
to 1.
OCP_CONTROLWR_
DEASSERTED_WHILE_
CONTROL_ CHANGED
Control signal can toggle only

when ControlWr is sampled
asserted.

by the system. This check fires whenever a
transition is detected on the Control signal and
ControlWr signal is not asserted. This check is
active only if the parameters CONTROL and
CONTROLWR are set to 1.
OCP_CONTROLWR_ENABLED_ CONTROLWR should not be

WITHOUT_CONTROL
enabled if CONTROL is not
enabled.
ControlWr signal is asserted whenever there is

change in the value of Control field.
ControlWr signal without Control signal on an
interface is meaningless. This check fires if
parameter CONTROLWR is enabled without
enabling parameter CONTROL.
OCP_CONTROLWR_UNKN

be X or Z.
Checks that ControlWr is both known (not X)

and driven (not Z).
OCP_DATAACCEPT_
ENABLED_WITHOUT_
DATAHANDSHAKE
DATAACCEPT should not be

enabled if
enabled.
Slave asserts SDataAccept signal to indicate

acceptance of write data (on datahandshake
phase) from master. If datahandshake phase is
not enabled, SDataAccept is not necessary on
a interface. This check fires when parameter
DATAACCEPT is enabled while parameter
DATAHANDSHAKE is not enabled.
360

Monitor Checks

Check ID
Violation
Description
OCP_DATAACCEPT_WHILE_
SDATATHREADBUSY_AND_
DATAACCEPT should not be

enabled when both
SDATATHREADBUSY and
SDATATHREADBUSY_
EXACT are enabled.
SDATATHREADBUSY_EXACT parameter
parameter DATAACCEPT is enabled and both
the parameters SDATATHREADBUSY and
SDATATHREADBUSY_EXACT are
enabled.
OCP_DATAHANDSHAKE_
BEGINNING_BEFORE_
REQUEST
A datahandshake phase should

not begin before the associated
request phase begins.
A master can present the associated

datahandshake phase in the same clock in
which it presents a request phase or in the
subsequent clocks. A master should never
present a datahandshake phase for which no
request phase is presented. This check fires if
active only if the parameter
DATAHANDSHAKE is enabled and the
parameter
CHECKS is set to 1.
OCP_DATAHANDSHAKE_
BLOCKING_WHILE_REQ_
ON_BLOCKING_FLOW_
CONTROL
When request phase is

configured for non-blocking
flow control, datahandshake
phase should not be configured
for blocking flow control.
When request phase is configured for nonblocking flow control (CMDACCEPT = 0 &&
STHREADBUSY = 1 &&
STHREADBUSY_EXACT = 1),
datahandshake phase should not be configured
for blocking flow control (DATAACCEPT =
1, SDATATHREADBUSY = 0,
SDATATHREADBUSY_EXACT = 0). This
check fires if this requirement is violated.
OCP_DATAHANDSHAKE_
ENDING_BEFORE_REQUEST
A datahandshake phase should

not end before the associated
request phase ends.
A master can end the associated

datahandshake phase in the same clock in
which it ends a request phase or in the
subsequent clocks. A master should never end
a datahandshake phase before the
corresponding request phase. This check fires
if this requirement is violated. This check is
DATAHANDSHAKE is enabled and the
parameter
CHECKS is set to 1.
OCP_DATAHANDSHAKE_
WITHOUT_WRITE_TYPE_CMD
DATAHANDSHAKE should
be enabled only if at least one
of the write-type command is
enabled.
Datahandshake phase is optionally used to

send data for write-type commands. Hence,
enabling of the datahandshake phase is valid
only if a write-type command is configured for
an interface. This check fires if parameter
DATAHANDSHAKE is enabled without
enabling any of the write type commands.
OCP_DATALAST_ENABLED_
WITHOUT_DATAHANDSHAKE
DATALAST should not be

enabled if
enabled.
MDataLast signal is part of datahandshake

phase. If datahandshake phase is not enabled,
MDataLast signal should not be configured for
a core. This check fires if parameter
DATALAST is enabled when parameter
DATAHANDSHAKE is not enabled.
361

Monitor Checks

Check ID
Violation
Description
OCP_DATAROWLAST_
WITHOUT_BURSTLENGTH
datarowlast can only be

enabled if burstlength is also
enabled.
The parameter datarowlast depends on the

setting of the parameters datahandshake,
burstlength, datalast, and
This check fires if the parameter datarowlast is
burstlength.

enabled if datahandshake is
also enabled.

This check fires if the parameter datalowlast is
datahandshake.

enabled if both datalast and
burstseq_blck_enable are
enabled.

This check fires if the parameter datarowlast is
enabled without enabling the other parameters
datalast and burstseq_blck_enable.
OCP_DFLT1_BURST_WHILE_
BURSTSEQ_DFLT1_ENABLE_0
A master with
BURSTSEQ_DFLT1_
ENABLE set to 0 should not
issue DFLT1 burst.
This check fires if a DFLT1 burst is presented

when the BURSTSEQ_DFLT1_ENABLE
OCP_DFLT2_BURST_WHILE_
BURSTSEQ_DFLT2_ENABLE_0
A master with
BURSTSEQ_DFLT2_
issue DFLT2 burst.
This check fires if a DFLT2 burst is presented

when the BURSTSEQ_DFLT2_ENABLE
OCP_DFLT2_SEQUENCE_
WITHOUT_ANY_BYTE_
ENABLE_ASSERTED
Burst address sequence

DFLT2 should have at least
one byte enable asserted for
each transfer in the burst.

This check fires if none of the byte enables are
asserted for a transfer in the DFLT2 burst
address sequences. This check is performed on
the MByteEn field. This check is active only if
parameter BYTEEN is set to 1 and parameter
BURSTSEQ is set to 1.
OCP_DFLT2_SEQUENCE_
WITHOUT_ANY_
MDATABYTE_ENABLE_
ASSERTED
Burst address sequence

DFLT2 should have at least
one mdatabyte enable asserted
for each transfer in the burst.

asserted for a transfer in the DFLT2 burst
address sequences. This check is performed on
the MDataByteEn field. This check is active
only if parameter MDATABYTEEN is set to
1, parameter BURSTSEQ is set to 1, parameter
DATAHANDSHAKE is enabled and
parameter
CHECKS is set to 1.
(OCP 2.2 check)
OCP_DATAROWLAST_
WITHOUT_DATAHANDSHAKE
(OCP 2.2 check)
OCP_DATAROWLAST_
WITHOUT_DATLAST_AND_
(OCP 2.2 check)
362

Monitor Checks

Check ID
Violation
Description
OCP_FAIL_RESPONSE_
VIOLATION
The FAIL response should be

presented only for the
WriteConditional commands.
Lazy synchronization uses the ReadLinked

and WriteConditional commands. The FAIL
response is meaningful for the
WriteConditional commands, and indicates
whether the write part of the lazy
synchronization has failed. This response
should not be issued in response to any other
command. This check fires if this condition is
parameter RESP is set to 1, and the parameter
CHECKS is set to 1.
OCP_FORCE_ALIGNED_
ENABLED_WHEN_DATA_
WDTH_IS_NON_POWER_OF_
TWO
FORCE_ALIGNED should be
enabled only when
DATA_WDTH is set to a
power-of-two value.
FORCE_ALIGNED option for byte enables

can only be enabled if DATA_WDTH is set to
a power-of-two value. This check fires if this
restriction is violated.
OCP_ILLEGAL_
BLOCKHEIGHT_WIDTH
BLOCKHEIGHT_WIDTH
must be set to 0 if the
parameter blockheight is
disabled.
BLOCKHEIGHT_WIDTH
must be set to greater than 1 if
blockheight is enabled.
This check fires under any one of the

following two conditions:
(OCP 2.2 check)
If the parameter
BLOCKHEIGHT_WIDTH representing
port width of the signal blockheight is not
set to 0 when the other parameter
blockheight is set to 0.
If the parameter
BLOCKHEIGHT_WIDTH is not set to
greater than 1 when the other parameter
blockheight is set to 1.
OCP_ILLEGAL_
MATOMICLENGTH_
ENCODING
MAtomicLength should not

have a encoding of 0.
MAtomicLength field indicates the minimum

number of transfers within a burst that are to
be kept together as an atomic unit. A binary
encoding of the number of transfers is used.
Value N on MAtomicLength field indicates
that minimum N (and not N+1) number of
transfers are to be kept together as atomic unit.
Hence a value of 0 does not carry any meaning
and is not a legal encoding for
MAtomicLength field. This check fires if
MAtomicLength violates this restriction. This
ATOMICLENGTH is set to 1.
OCP_ILLEGAL_
MBLOCKHEIGHT_ENCODING
MblockHeight must be greater

than 0 for the BLCK burst
sequence.
MBlockHeight indicates the number of row

transfers in a burst for BLCK burst sequence.
A binary encoding of the number of row
transfers is used.
Value N on MBlockHeight field indicates that
N (and not N+1) number of row transfers for
BLCK sequence. Hence, a value of 0 does not
carry any meaning and is not a legal encoding
for the MBlockHeight field in the case of
BLCK sequence.
This check fires if MBlockHeight violates this
restriction.
BLOCKHEIGHT and
(OCP 2.2 check)
363

Monitor Checks

Check ID
Violation
Description
OCP_ILLEGAL_
MBLOCKSTRIDE_ENCODING
MblockStride must be greater

than 0 for BLCK burst
sequence and MblockHeight >
1.
MblockStride must be greater than 0 for the

BLCK burst sequence and MblockHeight > 1.
MBlockStride indicates the address offset
between the starting address of two
consecutive rows in a burst for BLCK
sequence.
If the first row address in a burst with BLCK
sequence is M, then a Value N on
MBlockStride field indicates that M + N will
be the address of next row. Hence, a value of 0
does not carry any meaning and is not a legal
encoding for MBlockStride field in the case of
BLCK sequence with MblockHeight > 1.
This check fires if MBlockStride violates this
restriction.
BLOCKHEIGHT, MBLOCKSTRIDE, and
(OCP 2.2 check)
OCP_ILLEGAL_
MBURSTLENGTH_ENCODING
MBurstLength should not have MBurstLength indicates the number of

a encoding of 0.
transfers in a burst. A binary encoding of the
number of transfers is used. Value N on
MBurstLength field indicates that N (and not
N+1) number of transfers. Hence, a value of 0
does not carry any meaning and is not a legal
encoding for MBurstLength field.
This check fires if MBurstLength violates this
restriction.
BURSTLENGTH is set to 1.
OCP_ILLEGAL_SETTING_OF_
MTHREADBUSY_PIPELINED
mthreadbusy_pipelined can
This check fires if the parameter
only be enabled if
mthreadbusy_pipelined is enabled without
mthreadbusy_exact is enabled. having the other parameter mthreadbusy_exact
enabled.
(OCP 2.2 check)

SDATATHREADBUSY_
PIPELINED
sdatathreadbusy_pipelined can
only be enabled if
sdatathreadbusy_exact is
enabled.

sdatathreadbusy_pipelined is enabled without
having the other parameter
sdatathreadbusy_exact enabled.
sthreadbusy_pipelined can
only be enabled if
sthreadbusy_exact is enabled.

sthreadbusy_pipelined is enabled without
having the other parameter sthreadbusy_exact
enabled.
BYTEEN should be enabled

only if MDATA or SDATA is
enabled and DATA_WDTH is
an integer multiple of 8.
There is one bit in MByteEn for each byte in

OCP data word. Byte enables are applicable
only if MData or Sdata signals are configured
and DATA_WDTH is an integer number of
bytes. This check fires if parameter BYTEEN
is enabled when parameters MDATA and
SDATA are not enabled or DATA_WDTH is
not an integer multiple of 8.
(OCP 2.2 check)

STHREADBUSY_PIPELINED
(OCP 2.2 check)
OCP_IMPROPER_BYTEEN_
ENABLING
364

Monitor Checks

Check ID
Violation
Description
OCP_IMPROPER_
MDATABYTEEN_ENABLING
MDATABYTEEN should be
enabled only if MDATA is
enabled,
DATAHANDSHAKE is
enabled, and DATA_WDTH is
an integer multiple of 8.
There is one bit in MDataByteEn for each byte

in OCP write data word. Byte enables as in
MDataByteEn are applicable only if
Datahandshake phase is enabled, MData signal
is configured and DATA_WDTH is an integer
number of bytes. This check fires if parameter
MDATABYTEEN is enabled when parameter
MDATA is not enabled or DATA_WDTH is
OCP_IMPROPER_MDATAINFO_ MDATAINFO should not be

ENABLING
enabled if DATA_WDTH is
MDataInfo signal is used to send additional

information sequenced with write data in a
core specific manner. This field is divided in
two parts: the lower order bits associated with
each data byte, while higher order bits are
associated with the entire write data transfer.
This check fires if parameter MDATAINFO is
enabled when DATA_
WDTH is not an integer multiple of bytes.
OCP_IMPROPER_SDATAINFO_
ENABLING
SDATAINFO should not be

enabled if DATA_WDTH is
SDataInfo signal is used to send additional

information sequenced with read data in a core
specific manner. This field is divided in two
parts: the lower order bits associated with each
data byte, while higher order bits are
associated with the entire read data transfer.
This check fires if parameter SDATAINFO is
enabled when DATA_
WDTH is not an integer multiple of bytes.
OCP_INCORRECT_
MDATAINFO_WDTH
MDATAINFO_WDTH should
be greater than or equal to
MDATAINFOBYTE_
WDTH*DATA_WDTH/8.
MDATAINFOBYTE_WDTH indicates the

number of bits to associate with each data byte
in the MDataInfo field, whereas
MDATAINFO_WDTH indicates the total
width of the MDataInfo field. Hence,
(MDATAINFOBYTE_WDTH*DATA_
WDTH/8) should not exceed the value of
parameter MDATAINFO_WDTH. This check
OCP_INCORRECT_
SDATAINFO_WDTH
SDATAINFO_WDTH should
be greater than or equal to
SDATAINFOBYTE_
WDTH*DATA_WDTH/8.
SDATAINFOBYTE_WDTH indicates the

number of bits to associate with each data byte
in the SDataInfo field, whereas
SDATAINFO_WDTH indicates the total
width of the MDataInfo field. Hence,
(SDATAINFOBYTE_WDTH*DATA_
WDTH/8) should not exceed the value of
parameter SDATAINFO_WDTH. This check
365

Monitor Checks

Check ID
Violation
Description
OCP_INCR_BURST_
INCORRECT_ADDRESS_
SEQUENCE
Each transfer of an INCR burst

should increment MAddr by
the OCP word size.
MAddr is a byte address that must be aligned

to the OCP word size (DATA_WDTH). If the
OCP word size is not a power-of- 2, the
address is the same as it would be for an OCP
interface with a word size equal to the next
larger power-of-2. This check fires if address
for each transfer of INCR burst do not
increment by OCP word size. This check is
active only if the parameter ADDR is set to 1
through monitor port basic_group and
OCP_INCR_BURST_WHILE_
BURSTSEQ_INCR_ENABLE_0
A master with
BURSTSEQ_INCR_
issue INCR burst.
This check fires if an INCR burst is presented

when the BURSTSEQ_INCR_ENABLE
OCP_LEAVING_CONNECTED_
STATE_DURING_ONGOING_
TRANSACTION
Master must not initiate

disconnect before reaching the
current transaction boundary.
Until the current transaction boundary is

reached by the proper control signal from
OCP, the master must maintains its connected
state with the slave. This check fires when this
condition is violated.
OCP_MADDR_NOT_ STEADY
MAddr should be steady from

the beginning of the request
phase until the end of the
request phase.
A request phase begins whenever a command

other than Idle is presented on the MCmd
field. It ends when the SCmdAccept signal is
sampled asserted. If the request phase spans
over multiple clocks, then the MAddr signal
should remain steady throughout the request
phase. This check fires if MAddr does not
remain steady during request phase. This
check is active only if the parameter ADDR is
set to 1.
OCP_MADDR_UNALIGNED_
TO_OCP_WORD_SIZE
MAddr should be aligned to

OCP word size

larger power-of-2. This check fires if MAddr
is not aligned to OCP word size. This check is
active only if the parameter ADDR is set to 1.
OCP_MADDR_UNKN
MAddr signal should not be X

or Z.
Checks that MAddr is both known (not X) and

driven (not Z).
OCP_MADDRSPACE_NOT_
CONSTANT_DURING_ BURST
MAddrSpace should be
constant throughout the burst.
Regardless of whether the burst is precise or

imprecise, MAddrSpace signal should be
constant during the burst. This check fires if
active only if the parameter BURSTLENGTH
is set to 1 and parameter ADDRSPACE is set
to 1.
366

Monitor Checks

Check ID
Violation
Description
OCP_MADDRSPACE_NOT_
STEADY
MAddrSpace should be steady

from the beginning of the
request phase until the end of
the request phase.

over multiple clocks, then the MAddrSpace
signal should remain steady throughout the
request phase. This check fires if MAddrSpace
does not remain steady during request phase.
ADDRSPACE is set to 1.
OCP_MADDRSPACE_UNKN
MAddrSpace signal should not Checks that MAddrSpace is both known (not
be X or Z.
OCP_MATOMICLENGTH_NOT_ MAtomicLength should be


imprecise, MAtomicLength signal should be
ATOMICLENGTH is set to 1.
OCP_MATOMICLENGTH_NOT_ MAtomicLength should be

STEADY
steady from the beginning of
the request phase until the end
of the request phase.

over multiple clocks, then the MAtomicLength
request phase. This check fires if
MAtomicLength does not remain steady
during request phase. This check is active only
if the parameter ATOMICLENGTH is set to 1.
OCP_MATOMICLENGTH_
UNKN
MAtomicLength signal should

not be X or Z.
Checks that MAtomicLength is both known

OCP_MBLOCKHEIGHT_NOT_
The value of MBlockHeight

should be constant throughout
the burst.
MBlockHeight indicates the total number of

row transfers in a burst with BLCK sequence.
Total number of row transfers are known at the
start of the burst, and the value of
MBlockHeight is held constant throughout the
burst.
This check fires if MBlockHeight does not
remain constant throughout the burst.
BLOCKHEIGHT and
MBlockHeight should be

over multiple clocks, then the MBlockHeight
request phase.
This check fires if MBlockHeight does not
remain steady during the request phase.
MBLOCKHEIGHT is set to 1.
(OCP 2.2 check)
OCP_MBLOCKHEIGHT_NOT_
STEADY
(OCP 2.2 check)
367

Monitor Checks

Check ID
Violation
Description
OCP_MBLOCKHEIGHT_
UNKN
MBlockHeight signal should

not be X or Z.
Checks that MBlockHeight is both known (not

The value of MBlockStride

should be constant throughout
the burst.
MBlockStride indicates the address offset

between rows in a burst with BLCK sequence.
Address offset between rows transfers are
known at the start of the burst, and the value of
MBlockStride is held constant throughout the
burst.
This check fires if MBlockStride does not
remain constant throughout the burst.
MBlockStride should be

over multiple clocks, then the MBlockStride
request phase.
This check fires if MBlockStride does not
MBLOCKSTRIDE is set to 1.
MBlockStride should be
aligned to OCP word size.
MBlockStride is a byte offset address that

must be aligned to the OCP word size
(DATA_WDTH).
If the OCP word size is not a power-of- 2, then
the stride is the same as it would be for an OCP
larger power-of-2.
This check fires if MBlockStride is not aligned
to OCP word size.
MBlockStride signal should

not be X or Z.
Checks that MBlockStride is both known (not

For precise bursts, the value of

MBurstLength should be
For precise bursts, MBurstLength indicates the

total number of transfers in a burst. Total
number of transfers are known at the start of
the burst and value of MBurstLength is held
constant throughout the burst. This check fires
if MBurstLength does not remain constant
throughout the precise burst. This check is
is set to 1.
(OCP 2.2 check)

OCP_MBLOCKSTRIDE_NOT_
(OCP 2.2 check)
OCP_MBLOCKSTRIDE_NOT_
STEADY
(OCP 2.2 check)
OCP_MBLOCKSTRIDE_
UNALIGNED_TO_OCP_WORD_
SIZE
(OCP 2.2 check)
OCP_MBLOCKSTRIDE_UNKN
(OCP 2.2 check)
OCP_MBURSTLENGTH_NOT_
CONSTANT_DURING_
PRECISE_BURST
368

Monitor Checks

Check ID
Violation
Description
OCP_MBURSTLENGTH_NOT_
STEADY
MBurstLength should be

over multiple clocks, then the MBurstLength
MBurstLength does not remain steady during
request phase. This check is active only if the
parameter BURSTLENGTH is set to 1.
OCP_MBURSTLENGTH_UNKN
MBurstLength signal should

not be X or Z.
Checks that MBurstLength is both known (not

OCP_MBURSTPRECISE_NOT_
MBurstPrecise should be

imprecise, MBurstPrecise signal should be
active only if the parameter BURSTPRECISE
is set to 1.
OCP_MBURSTPRECISE_NOT_
STEADY
MBurstPrecise should be

over multiple clocks, then the MBurstPrecise
MBurstPrecise does not remain steady during
request phase. This check is active only if the
parameter BURSTPRECISE is set to 1.
OCP_MBURSTPRECISE_UNKN
MBurstPrecise signal should

not be X or Z.
Checks that MBurstPrecise is both known (not

OCP_MBURSTSEQ_NOT_
MBurstSeq should be constant


imprecise, the MBurstSeq signal should be
active only if the parameter BURSTSEQ is set
to 1.
OCP_MBURSTSEQ_NOT_
STEADY
MBurstSeq should be steady

the request phase.

over multiple clocks, then the MBurstSeq
request phase. This check fires if MBurstSeq
does not remain steady during request phase.
OCP_MBURSTSEQ_UNKN
MBurstSeq signal should not

be X or Z.
Checks that MBurstSeq is both known (not X)

and driven (not Z).
369

Monitor Checks

Check ID
Violation
Description
OCP_MBURSTSINGLEREQ_
ASSERTED_WHEN_
MBURSTPRECISE_
DEASSERTED
MBurstSingleReq should not

be asserted when
MBurstPrecise is not asserted.
Single request / multiple data transfers are

possible only if the burst length is known at the
start of the burst. Hence, MBurstSingleReq
signal can be asserted only if MBurstPrecise
signal is asserted. This check fires if this
requirement is violated. This check is active
only if the parameter BURSTPRECISE and
BURSTSINGLEREQ is set to 1.
NOT_CONSTANT_DURING_
BURST
MBurstSingleReq should be

imprecise, MBurstSingleReq signal should be
BURSTSINGLEREQ is set to 1.
NOT_STEADY
MBurstSingleReq should be

over multiple clocks, then the
MBurstSingleReq signal should remain steady
throughout the request phase. This check fires
if MBurstSingleReq does not remain steady
if the parameter BURSTSINGLEREQ is set to
1.
UNKN
MBurstSingleReq signal
should not be X or Z.
Checks that MBurstSingleReq is both known

OCP_MBYTEEN_NOT_STEADY MByteEn should be steady

the request phase.

over multiple clocks, then the MByteEn signal
phase. This check fires if MByteEn does not
check is active only if the parameter BYTEEN
is set to 1.
OCP_MBYTEEN_UNKN
MByteEn signal should not be

X or Z.
Checks that MByteEn is both known (not X)

and driven (not Z).
OCP_MCMD_NOT_
MCmd should be constant


imprecise, MCmd signal should be constant
during the burst. This check fires if this
only if the parameter BURSTLENGTH is set
to 1.
OCP_MCMD_NOT_IDLE_
WHILE_OCP_NOT_
CONNECTED
Master must drive idle

commands when OCP is not
connected.
The OCP master is responsible for driving the

idle commands when OCP is not in connected
state. This check fires when the master drives
any valid OCP commands other than idle when
the master and slave are not in connected state.
370

Monitor Checks

Check ID
Violation
Description
OCP_MCMD_NOT_STEADY
MCmd should be steady from

request phase.

sampled asserted. If request phase spans over
multiple clocks, MCmd signal should remain
steady throughout the request phase. This
check fires if MCmd does not remain steady
during request phase.
OCP_MCMD_UNKN
MCmd signal should not be X

or Z.
Checks that MCmd is both known (not X) and

driven (not Z).
OCP_MCONNID_NOT_
MConnID should be constant


imprecise, MConnID signal should be constant
during the burst. This check fires if this
only if the parameter BURSTLENGTH is set
to 1 and parameter CONNID is set to 1.
OCP_MCONNID_NOT_STEADY
MConnID should be steady

the request phase.

multiple clocks, MConnID signal should
remain steady throughout the request phase.
This check fires if MConnID does not remain
steady during request phase. This check is
active only if the parameter CONNID is set to
1.
OCP_MCONNID_UNKN
MConnID signal should not be

X or Z.
Checks that MConnID is both known (not X)

and driven (not Z).
OCP_MDATA_NOT_STEADY_
FOR_DATAHANDSHAKE_
PHASE
MData should be steady from

the beginning of the
datahandshake phase until the
end of the datahandshake
phase.
A datahandshake phase begins whenever a1 is

presented on the MDataValid field. It ends
when the SDataAccept signal is sampled
asserted. If datahandshake phase spans over
multiple clocks, MData signal should remain
steady throughout the datahandshake phase.
This check fires if MData does not remain
steady during datahandshake phase. This
check is active only if the parameter MDATA
is set to 1 and parameter
DATAHANDSHAKE is enabled.
OCP_MDATA_NOT_STEADY_
FOR_REQ_PHASE
MData should be steady from

request phase.

multiple clocks, MData signal should remain
steady throughout the request phase. This
check fires if MData does not remain steady
if the parameter MDATA is set to 1 and
parameter DATAHANDSHAKE is not
enabled.
371

Monitor Checks

Check ID
Violation
Description
OCP_MDATA_UNKN
MData signal should not be X

or Z.
Checks that MData is both known (not X) and

driven (not Z). The parameter
disabling of the check. By default, this check is
ON.
OCP_MDATABYTE_ENABLES_
NOT_FORCE_ALIGNED
A master with
FORCE_ALIGNED option
enabled should not generate
any mdatabyte enable patterns
that are not force aligned.

The FORCE_ALIGNED parameter limits byte
enable patterns to be power-of-two in size and
aligned to that size. The byte enable pattern of
all 0s is also a legal pattern. This check fires if
performed on the MDataByteEn field. This
check is active only if parameter
MDATABYTEEN is set to 1, parameter
BURSTSEQ is set to 1, parameter
parameter
CHECKS is set to 1.
OCP_MDATABYTEEN_NOT_
STEADY
MDataByteEn should be
the datahandshake phase until
the end of the datahandshake
phase.

multiple clocks, MDataByteEn signal should
remain steady throughout the datahandshake
phase. This check fires if MDataByteEn does
not remain steady during datahandshake phase.
MDATABYTEEN is set to 1.
OCP_MDATABYTEEN_UNKN
MDataByteEn signal should

not be X or Z.
Checks that MDataByteEn is both known (not

OCP_MDATAINFO_NOT_
STEADY_FOR_
DATAHANDSHAKE_PHASE
MDataInfo should be steady

phase.

multiple clocks, MDataInfo signal should
phase. This check fires if MDataInfo does not
remain steady during datahandshake phase.
MDATAINFO is set to 1.
OCP_MDATAINFO_NOT_
STEADY_FOR_REQ_PHASE
MDataInfo should be steady

the request phase.

multiple clocks, MDataInfo signal should
remain throughout the request phase. This
check fires if MDataInfo does not remain
active only if the parameter MDATAINFO is
set to 1 and parameter DATAHANDSHAKE
is not enabled.
372

Monitor Checks

Check ID
Violation
Description
OCP_MDATAINFO_UNKN
MDataInfo signal should not

be X or Z.
Checks that MDataInfo is both known (not X)

and driven (not Z).
OCP_MDATALAST_NOT_
STEADY
MDataLast should be steady

phase.

multiple clocks, MDataLast signal should
phase. This check fires if MDataLast does not
DATALAST is set to 1.
OCP_MDATALAST_UNKN
MDataLast signal should not

be X or Z.
Checks that MDataLast is both known (not X)

and driven (not Z).
OCP_MDATALAST_
VIOLATION
MDataLast should be asserted

only for last data phase of the
burst.
MDataLast signal indicates the last data in the

write type burst. This check fires when
MDataLast signal is not asserted along with
the last transfer of the write data burst or
MDataLast signal is asserted in a transfer
which is not a last transfer in write data burst.
DATALAST is set to 1, parameter
parameter
CHECKS is set to 1.
OCP_MDATALAST_WITHOUT_ MDATALAST should be

BURSTLENGTH
enabled only if the
The bursts can be issued only if the

MBurstlength signal is configured for an
interface. Other burst related signals make
sense only when bursts can be issued. This
check fires if the parameter MDATALAST is
enabled without enabling the parameter
BURSTLENGTH.
OCP_MDATAROWLAST_NOT_
STEADY

multiple clocks, then MDataRowLast signal
should remain steady throughout the
datahandshake phase.
This check fires if MdataRowLast does not
DATAROWLAST is set to 1.
(OCP 2.2 check)
MDataRowLast should be
phase.
OCP_MDATAROWLAST_UNKN MDataRowLast signal should

not be X or Z.
(OCP 2.2 check)
Checks that MDataRowLast is both known

373

Monitor Checks

Check ID
Violation
Description
OCP_MDATATAGID_NOT_
STEADY
For tagged transactions,

MDataTagID should be steady
phase.
A datahandshake phase begins whenever a 1 is

multiple clocks, then the MDataTagID signal
should remain steady throughout the
datahandshake phase. This check fires if
MDataTagID does not remain steady during
the datahandshake phase. This check is active
only if the parameter TAGS is set to a value
greater than 1, parameter
DATAHANDSHAKE is enabled, and the
parameter
CHECKS is set to 1.
OCP_MDATATAGID_UNKN
MDataTagID signal should not Checks that MDataTagID is both known (not
be X or Z.
OCP_MDATATAGID_VALUE_
NOT_LESS_THAN_TAGS
For tagged transactions, the

value of the MDataTagID field
should be less than the number
of tags.
The value presented on the MDataTagID field

should be less than the number of tags
supported. This check fires if this requirement
is violated. This check is active only if the
parameter TAGS is set to a value greater than
1 and the parameter
CHECKS is set to 1.
OCP_MDATATHREADID_NOT_ MDataThreadID should be

STEADY
phase.

multiple clocks, MDataThreadID signal should
phase. This check fires if MDataThreadID
does not remain steady during datahandshake
phase. This check is active only if the
parameter THREADS is set to a value greater
than 1.
OCP_MDATATHREADID_
UNKN
MDataThreadID signal should

not be X or Z.
Checks that MDataThreadID is both known

OCP_MDATATHREADID_
VALUE_NOT_LESS_THAN_
THREADS
The value of the

MDataThreadID field should
be less than the number of
threads.
The value presented on the MDataThreadID

field should be less than the number of threads
than 1.
OCP_MDATAVALID_NOT_
STEADY
MDataValid should be steady

phase.

multiple clocks, MDataValid signal should
phase. This check fires if MDataValid does not
DATAHANDSHAKE is set to 1.
374

Monitor Checks

Check ID
Violation
Description
OCP_MDATAVALID_UNKN
MDataValid signal should not

be X or Z.
Checks that MDataValid is both known (not

OCP_MREQINFO_NOT_
MReqInfo should be constant


imprecise, the MReqInfo signal should be
is set to 1.
OCP_MREQINFO_NOT_
STEADY
MReqInfo should be steady

the request phase.

multiple clocks, MReqInfo signal should
This check fires if MReqInfo does not remain
active only if the parameter REQINFO is set to
1.
OCP_MREQINFO_UNKN
MReqInfo signal should not be

X or Z.
Checks that MReqInfo is both known (not X)

and driven (not Z).
OCP_MREQLAST_NOT_
STEADY
MReqLast should be steady

the request phase.

multiple clocks, MReqLast signal should
This check fires if MReqLast does not remain
active only if the parameter REQLAST is set
to 1.
OCP_MREQLAST_UNKN
MReqLast signal should not be Checks that MReqLast is both known (not X)
X or Z.
and driven (not Z).
OCP_MREQLAST_VIOLATION
MReqLast should be asserted

only for last request phase of
the burst.
The MReqLast signal indicates the last request

in the burst. This check fires when the
MReqLast signal is not asserted along with the
last transfer of the request burst or the
MReqLast signal is asserted in a transfer
which is not a last transfer in the request burst.
REQLAST is set to 1.
OCP_MREQLAST_WITHOUT_
BURSTLENGTH
MREQLAST should be
enabled only if

check fires if the parameter MREQLAST is
BURSTLENGTH.
375

Monitor Checks

Check ID
Violation
Description
OCP_MREQROWLAST_NOT_
STEADY
MReqRowLast should be

multiple clocks, then MReqRowLast signal
phase.
This check fires if MReqRowLast does not
REQROWLAST is set to 1.
MReqRowLast signal should

not be X or Z.
Checks that MReqRowLast is both known (not

OCP_MRESPACCEPT_ UNKN
MRespAccept signal should

not be X or Z.
Checks that MRespAccept is both known (not

OCP_MRESPLAST_WITHOUT_
BURSTLENGTH
MRESPLAST should be
enabled only if

check fires if the parameter MRESPLAST is
BURSTLENGTH.
(OCP 2.2 check)
OCP_MREQROWLAST_UNKN
(OCP 2.2 check)
OCP_RESPONSE_REORDERED_ For tagged requests, responses

BEYOND_INTERLEAVE_SIZE_ for burst sequences must stay
VIOLATION
together up to tag interleave
size.
This check fires when responses to the burst

transactions are out of bound beyond the
configured tag interleave size of OCP with
reference to the received requests.
This check fires when tagged requests

OCP_RESPONSE_REORDERED_ For tagged requests with
FOR_OVERLAPPING_
overlapping addresses,
addressing to overlapped region of memory
ADDRESSES_VIOLATION
response may not be reordered. are responded out of order with reference to
the order of requests.
OCP_MTAGID_NOT_
MTagID should be constant


imprecise, the MTagID signal should be
active only if the parameter TAGS is set to a
value greater than 1.
OCP_MTAGID_NOT_STEADY

MTagID should be steady
the request phase.

over multiple clocks, then the MTagID signal
phase. This check fires if MTagID does not
check is active only if the parameter TAGS is
set to a value greater than 1.
OCP_MTAGID_UNKN
MTagID signal should not be

X or Z.
Checks that MTagID is both known (not X)

and driven (not Z).
376

Monitor Checks

Check ID
Violation
Description
OCP_MTAGID_VALUE_NOT_
LESS_THAN_TAGS

value of MTagID field should
be less than the number of
tags.
The value presented on the MTagID field

1.
OCP_MTAGINORDER_NOT_
MTagInOrder should be

imprecise, the MTagInOrder signal should be
active only if the parameter TAGS is set to a
OCP_MTAGINORDER_NOT_
STEADY
MTagInOrder should be steady

the request phase.

over multiple clocks, then the MTagInOrder
MTagInOrder does not remain steady during
the request phase. This check is active only if
the parameter TAGS is set to a value greater
than 1 and the parameter TAGINORDER is set
to 1.
OCP_MTAGINORDER_UNKN
MTagInOrder signal should

not be X or Z.
Checks that MTagInOrder is both known (not

OCP_MTHREADBUSY_
ENABLED_WITHOUT_RESP
MTHREADBUSY should not

be enabled if RESP is not
enabled.
MThreadbusy signal is valid only if response

phase is enabled. This check fires when
parameter MTHREADBUSY is enabled while
parameter RESP is not enabled.
OCP_MTHREADBUSY_EXACT_ MTHREADBUSY_
ENABLED_WITHOUT_
EXACT should be enabled
MTHREADBUSY
only if MTHREADBUSY is
enabled.
MTHREADBUSY_EXACT has no meaning if

the MTHREADBUSY signal is not configured
for an interface in the first place. This check
fires when parameter
MTHREADBUSY_EXACT is enabled when
parameter MTHREADBUSY is not enabled.
OCP_MTHREADBUSY_EXACT_ Response presented on a

RESPONSE_ACCEPTANCE_
thread for which
VIOLATION
MThreadBusy is de-asserted in
the current cycle should be
accepted by the master in that
cycle.
The master notifies the slave that it cannot

accept any responses associated with certain
thread by asserting MThreadBusy signal for
that thread. MTHREADBUSY_EXACT
parameter. If the MTHREADBUSY_
EXACT parameter is enabled for a master and
a response is presented on a thread for which
MThreadBusy is de-asserted in the current
cycle, it should be accepted by the master in
that cycle. This check fires if this restriction is
violated.
MTHREADBUSY_EXACT must be enabled
and MTHREADBUSY_PIPELINED
must be disabled to activate this check.
377

Monitor Checks

Check ID
Violation
Description
OCP_MTHREADBUSY_EXACT_ Slave should not present a

RESPONSE_PRESENTATION_
response on a thread for which
VIOLATION
the corresponding
MThreadBusy bit is asserted in
that cycle.

that thread. If the MTHREADBUSY_
EXACT parameter is enabled for a slave, it
should not present a response on a thread for
which the corresponding MThreadBusy bit is
asserted in the cycle. This check fires if this
MTHREADBUSY_EXACT must be enabled
and MTHREADBUSY_PIPELINED must be
disabled to activate this check.
OCP_MTHREADBUSY_
PIPELINED_RESPONSE_
PRESENTATION_VIOLATION
If MTHREADBUSY_
PIPELINED is enabled, slave
should not present a response
on a thread for which the
corresponding MThreadBusy
bit is asserted in the previous
cycle.

that thread. If the MTHREADBUSY_EXACT
and MTHREADBUSY_PIPELINED
parameter is enabled for a slave, it should not
present a response on a thread for which the
corresponding MThreadBusy bit is asserted in
the previous cycle. This check fires if this
restriction is violated. Both
STHREADBUSY_EXACT and
STHREADBUSY_PIPELINED must be
enabled to activate this check.
mthreadbusy can only be

enabled if exactly one of
mthreadbusy_exact and
respaccept is enabled.
Mthreadbusy can only be enabled if

EXACTLY one of mthreadbusy_exact and
respaccept is enabled.
(OCP 2.2 check)
OCP_MTHREADBUSY_
WITHOUT_EXACTLY_ONE_
OF_MTHREADBUSY_EXACT_
AND_RESPACCEPT
(OCP 2.2 check)
OCP_MTHREADBUSY_
MTHREADBUSY should not
WITHOUT_RESPACCEPT_
be enabled when
AND_MTHREADBUSY_ EXACT RESPACCEPT and
MTHREADBUSY_
EXACT are not enabled.
MTHREADBUSY_EXACT parameter
requires strict semantics for MThreadbusy
parameter MTHREADBUSY is enabled
without enabling RESPACCEPT and
MTHREADBUSY_EXACT.
OCP_MTHREADID_NOT_
MThreadID should be constant Regardless of whether the burst is precise or

imprecise, MThreadID signal should be
is set to 1 and parameter THREADS is set to a
OCP_MTHREADID_NOT_
STEADY
MThreadID should be steady

the request phase.
378

multiple clocks, MThreadID signal should
This check fires if MThreadID does not remain
active only if the parameter THREADS is set
to a value greater than 1.

Monitor Checks

Check ID
Violation
Description
OCP_MTHREADID_UNKN
MThreadID signal should not

be X or Z.
Checks that MThreadID is both known (not X)

and driven (not Z).
OCP_MTHREADID_VALUE_
NOT_LESS_THAN_THREADS
The value of the MThreadID

field should be less than the
number of threads.
The value presented on the MThreadID field

should be less than the number of threads
than 1.
OCP_NONE_OF_THE_BURST_
SEQUENCE_ENABLED
If BURSTSEQ is enabled, at
least one of the burst sequence
parameters should be enabled.
If the MBurstSeq signal is configured for an

interface, at least one of the burst sequence
parameter should be configured. This check
fires if the parameter BURSTSEQ is enabled
when none of the burst sequence parameters is
enabled.
OCP_NONE_OF_THE_
COMMANDS_ENABLED
At least one of the

COMMAND_ENABLEs
should be set to 1.
At least one of the command must be enabled

for an OCP interface. This check fires if none
of the COMMAND_ENABLEs is set to 1.
OCP_RD_CMD_WHILE_READ_
ENABLE_0
A master with
READ_ENABLE set to 0
should not generate Read
command.
A master can generate a Read command only

if parameter READ_ENABLE is set. This
check fires if Read command is generated
when parameter READ_ENABLE is set to 0.
OCP_RDEX_CMD_AS_ BURST
The ReadEx command should

not be used as part of burst.
ReadEx command assumes a single

transaction model and cannot be used in a
burst. This check fires if the ReadEx command
is used as part of the burst.
OCP_RDEX_CMD_WHILE_
READEX_ENABLE_0
A master with
READEX_ENABLE set to 0
should not generate ReadEx
command.
A master can generate a ReadEx command

only if parameter READEX_ENABLE is set.
This check fires if ReadEx command is
READEX_ENABLE is set to 0.
OCP_RDL_CMD_AS_ BURST
The ReadLinked command

should not be used as part of
burst.
ReadLinked command assumes a single

burst. This check fires if the ReadLinked
command is detected as part of the burst.
OCP_RDL_CMD_WHILE_
RDLWRC_ENABLE_0
A master with
RDLWRC_ENABLE set to 0
should not generate
ReadLinked command.
A master can generate a ReadLinked

command only if parameter
RDLWRC_ENABLE is set. This check fires if
ReadLinked command is generated when
parameter RDLWRC_ENABLE is set to 0.
OCP_RDL_CMD_WHILE_
WRITERESP_ENABLE_0
A master with
WRITERESP_ENABLE is set
ReadLinked command.
When WRITERESP_ENABLE is set to 0,

posted write model is assumed and all write
commands complete on command acceptance
(no responses). Since responses are must for
synchronization commands, these commands
should not be issued when responses are
disabled. This check fires when a ReadLinked
command is issued while
WRITERESP_ENABLE is set to 0.
379

Monitor Checks

Check ID
Violation
Description
OCP_RDLWRC_ENABLE_
SET_WITHOUT_WRITERESP_
ENABLE
RDLWRC_ENABLE should
be set to 1 only if
to 1.
ReadLinked / WriteCondtional commands are

used for synchronization operation and
responses are necessary for proper
synchronization. This check fires if parameter
RDLWRC_ENABLE is enabled without
enabling parameter WRITERESP_ENABLE.
OCP_READEX_CMD_NOT_
FOLLOWED_BY_WR_WRNP_
CMD
When ReadEx command is

issued, the next request on the
thread that issued a ReadEx
should be a Write or
WriteNonPost to the matching
address.
Locked synchronization mechanism consists

of a ReadEx command followed by a Write or
WriteNonPost command. ReadEx command
sets a lock for a initiating thread on the
addressed location. Write/WriteNonPost
command unlocks the access to the matched
address. When a master issues a ReadEx
command on a thread, the next command
issued by master on that thread must be a
Write or WriteNonPost command to the
matching address. This check fires if this
OCP_READEX_ENABLE_SET_
WITHOUT_WRITE_ENABLE_
OR_WRITENONPOST_ENABLE
READEX_ENABLE should
not be enabled if
WRITE_ENABLE or
WRITENONPOST_
ENABLE is not set to 1.
For locked synchronization operations ReadEx

commands needs to be followed on a thread by
a Write or WriteNonPost command to
matching address. Hence,
READEX_ENABLE should not be enabled if
none of the parameters WRITE_ENABLE or
WRITENONPOST_ENABLE is not enabled.
This check fires if this restriction is violated.
OCP_REQ_BLOCKING_WHILE_ When datahandshake phase is

DATAHANDSHAKE_NON_
configured for non-blocking
BLOCKING_FLOW_CONTROL
flow control, request phase
should not be configured for
blocking flow control.
When datahandshake phase is configured for

non-blocking flow control (DATAACCEPT =
0, SDATATHREADBUSY = 1,
SDATATHREADBUSY_EXACT = 1),
request phase should not be configured for
blocking flow control (CMDACCEPT = 1 &&
STHREADBUSY = 0 &&
STHREADBUSY_EXACT = 0). This check
fires if this requirement is violated.
OCP_REQDATA_TOGETHER_
MULTI_REQ_ACCEPTANCE_
VIOLATION
The REQDATA_TOGETHER parameter

indicates interfaces where datahandshake is
enabled only to support the write data phases
of single request / multiple data transactions. If
such an interface also supports multiple
request / multiple data transfers (e.g., to
support burst sequences such as UNKN that
cannot be single request / multiple data), the
request and datahandshake phases should
begin and end together. This check fires when
slave with both REQDATA_TOGETHER and
BURSTSINGLEREQ enabled does not accept
the request and the associated datahandshake
phase together for each transfer in any multiple
request / multiple data write-type burst.
380
Slave with both

REQDATA_TOGETHER and
BURSTSINGLEREQ enabled
should accept the request and
the associated datahandshake
phase together for each
transfer in any multiple request
/ multiple data write-type
burst.

Monitor Checks

Check ID
Violation
Description
MULTI_REQ_PRESENTATION_
VIOLATION
Master with both

REQDATA_TOGETHER and
BURSTSINGLEREQ enabled
should present the request and
the associated datahandshake
phase together for each
transfer in any multiple
request/ multiple data writetype burst.
The REQDATA_TOGETHER parameter

indicates interfaces where datahandshake is
enabled only to support the write data phases
of single request / multiple data transactions. If
such an interface also supports multiple
request / multiple data transfers (e.g., to
support burst sequences such as UNKN that
cannot be single request / multiple data), the
request and datahandshake phases should
begin and end together. This check fires when
master with both REQDATA_TOGETHER
and BURSTSINGLEREQ enabled does not
present the request and the associated
datahandshake phase together for each transfer
in any multiple request / multiple data writetype burst.
SINGLE_REQ_ACCEPTANCE_
VIOLATION
In a single request / multiple

data write-type burst, slave
should accept request and
datahandshake phases of the
first transfer in the same cycle.
When parameter REQDATA_TOGETHER is

enabled, the request and datahandshake phases
of the first transfer in a single request /
multiple data write-type burst should begin
and end together. This check fires if
REQDATA_TOGETHER parameter is
enabled and request and datahandshake phases
multiple data write-type burst are not accepted
in the same cycle.
SINGLE_REQ_
In a single request / multiple

data write-type burst, master
should present request and
datahandshake phases of the
first transfer in the same cycle.
When parameter REQDATA_TOGETHER is

enabled, the request and datahandshake phases
multiple data write-type burst should begin
and end together. This check fires if
REQDATA_TOGETHER parameter is
enabled and request and datahandshake phases
multiple data write-type burst are not
presented in the same cycle.
OCP_REQROWLAST_
WITHOUT_BURSTLENGTH
reqlowlast can only be enabled

if burstlength is also enabled.
The parameter reqlowlast depends on the

setting of the parameters burstlength, reqlast,
and burstseq_black_enable.
This check fires if the parameter reqlowlast is
burstlength.
reqlowlast can only be enabled

if both reqlast and
enabled.
The parameter reqlowlast depends on the

setting of the parameters burstlength, reqlast,
and burstseq_black_enable.
This check fires if the parameter reqlowlast is
enabled without enabling both the parameters
reqlast and burstseq_blck_enable.
RESP should be enabled if any

read-type command is enabled
or WRITERESP_ENABLE is
set to 1.
Response phase needs to be configured if readtype commands are configured or write

commands with responses are configured for
an interface. This check fires if parameter
RESP is not enabled when any read-type
command is enabled or parameter
WRITERESP_ENABLE is enabled.
(OCP 2.2 check)
OCP_REQROWLAST_
WITHOUT_REQLAST_AND_
(OCP 2.2 check)
OCP_RESP_NOT_ENABLED
381

Monitor Checks

Check ID
Violation
Description
OCP_RESPACCEPT_ENABLED_ RESPACCEPT should not be

WITHOUT_RESP
enabled if RESP is not
enabled.
Master asserts MRespAccept signal to

indicates acceptance of response from slave. If
responses are not enabled, MRespAccept is
not necessary on a interface. This check fires
when parameter RESPACCEPT is enabled
while parameter RESP is not enabled.
OCP_RESPACCEPT_WHILE_
MTHREADBUSY_AND_
MTHREADBUSY_EXACT
RESPACCEPT should not be

enabled when both
MTHREADBUSY and
MTHREADBUSY_
EXACT are enabled.
MHREADBUSY_EXACT parameter requires

strict semantics for MThreadbusy signal to
ensure that multithreaded OCP interface never
blocks. This check fires when parameter
RESPACCEPT is enabled and both the
parameters MTHREADBUSY and
MTHREADBUSY_EXACT are enabled.
OCP_RESPACCEPT_WITH_
MTHREADBUSY_EXACT_
ENABLED
respaccept can only be enabled

when mthreadbusy_exact is
not enabled.
Respaccept can only be enabled when

mthreadbusy_exact is NOT enabled.
OCP_RESPINFO_ENABLED_
WITHOUT_RESP
RESPINFO should not be

enabled.
SRespInfo signal is part of response phase. If

response phase is not enabled, SRespInfo
signal should not be configured for a core.
This check fires if parameter RESPINFO is
enabled when parameter RESP is not enabled.
OCP_RESPLAST_ENABLED_
WITHOUT_RESP
RESPLAST should not be

enabled.
SRespLast signal is part of response phase. If

response phase is not enabled, SRespLast
This check fires if parameter RESPLAST is
OCP_RESPONSE_BEGINNING_
BEFORE_DATAHANDSHAKE
A response phase should not

begin before the associated
datahandshake phase begins.
A slave can present the associated write

response phase in the same clock in which the
master presents a write data or in the
subsequent clocks. A slave should never
present a response phase for which no write
data is presented by the master. This check
fires if this requirement is violated. This check
is active only if the parameter
DATAHANDSHAKE is enabled, the
parameter RESP is enabled, and the parameter
CHECKS is set to 1.
OCP_RESPONSE_BEGINNING_
BEFORE_REQUEST

begin before the associated
request phase begins.
A slave can present the associated response

phase in the same clock in which master
presents a request phase or in the subsequent
clocks. A slave should never present a
response phase before the master presents the
request phase. This check fires if this
only if the parameter RESP is enabled, and the
parameter
CHECKS is set to 1.
(OCP 2.2 check)
382

Monitor Checks

Check ID
Violation
Description
OCP_RESPONSE_ENDING_
BEFORE_DATAHANDSHAKE

end before the associated
datahandshake phase ends.
A slave can end the associated write response

phase in the same clock in which the master
ends a write data or in the subsequent clocks.
A slave should never end a response phase
before the master ends the the write data. This
check fires if this requirement is violated. This
DATAHANDSHAKE is enabled, the
parameter RESP is enabled, and the parameter
CHECKS is set to 1.
OCP_RESPONSE_ENDING_
BEFORE_REQUEST

end before the associated
request phase ends.
A slave can end the associated response phase

in the same clock in which the master ends a
request phase or in the subsequent clocks. A
slave should never end a response phase before
the master ends the request phase. This check
fires if this requirement is violated. This check
is active only if the parameter RESP is
enabled, and the parameter
CHECKS is set to 1.
OCP_RESPROWLAST_
WITHOUT_BURSTLENGTH
resprowlast can only be

enabled if burstlength is also
enabled.
The parameter resprowlast depends on the

setting of the parameters resp, burstlength,
resplast, and burstseq_black_enable.
This check fires if the parameter resprowlast is
burstlength.

enabled if both resplast and
enabled.

enabled without enabling both the parameters
resplast and burstseq_blck_enable.

enabled if response is also
enabled.

datahandshake.
(OCP 2.2 check)
OCP_RESPROWLAST_
WITHOUT_DATLAST_AND_
(OCP 2.2 check)
OCP_RESPROWLAST_
WITHOUT_RESP
(OCP 2.2 check)
OCP_SCMDACCEPT_UNKN
SCmdAccept signal should not Checks that SCmdAccept is both known (not
be X or Z.
OCP_SDATA_ENABLED_
WITHOUT_RESP
SDATA should not be enabled

if RESP is not enabled.
SData signal is part of response phase. If

response phase is not enabled, SData signal
should not be configured for a core. This check
fires if parameter SDATA is enabled when
parameter RESP is not enabled.
383

Monitor Checks

Check ID
Violation
Description
OCP_SDATA_NOT_STEADY
SData should be steady from

the beginning of the response
response phase.
A response phase begins whenever a response

other than Null is presented on the SResp field.
It ends when the SRespAccept signal is
sampled asserted. If response phase spans over
multiple clocks, SData signal should remain
steady throughout the response phase. This
check fires if SData does not remain steady
during response phase. This check is active
only if the parameter SDATA is set to 1.
OCP_SDATA_UNKN
SData signal should not be X

or Z.
Checks that SData is both known (not X) and

driven (not Z). The parameter
disabling of the check. By default, this check is
ON.
OCP_SDATAACCEPT_UNKN
SDataAccept signal should not

be X or Z.
Checks that SDataAccept is both known (not

OCP_SDATAINFO_ENABLED_
WITHOUT_RESP
SDATAINFO should not be

enabled.
SDataInfo signal is part of response phase. If

response phase is not enabled, SDataInfo
This check fires if parameter SDATAINFO is
OCP_SDATAINFO_NOT_
STEADY
SDataInfo should be steady

response phase until the end of
the response phase.

multiple clocks, SDataInfo signal should
remain steady throughout the response phase.
This check fires if SDataInfo does not remain
steady during response phase. This check is
active only if the parameter SDATAINFO is
set to 1.
OCP_SDATAINFO_UNKN
SDataInfo signal should not be

X or Z.
Checks that SDataInfo is both known (not X)

and driven (not Z).
OCP_SDATATHREADBUSY_
EXACT_DATAHANDSHAKE_
ACCEPTANCE_VIOLATION
Datahandshake phase
presented on a thread for
which SDataThreadBusy is deasserted in the current cycle
should be accepted by the
slave in that cycle.
The slave notifies the master that it cannot

accept any datahandshake phases associated
with certain thread by asserting
SDataThreadBusy signal for that thread. If the
is enabled for a slave and a datahandshake
phase is presented on a thread for which
SDataThreadBusy is de-asserted in the current
cycle, it should be accepted by the slave in that
cycle. This check fires if this restriction is
violated.
SDATATHREADBUSY_EXACT must be
enabled and
SDATATHREADBUSY_PIPELINED must
be disabled to activate this check.
384

Monitor Checks

Check ID
Violation
Description
EXACT_DATAHANDSHAKE_
Master should not present a

datahandshake phase on a
thread for which the
corresponding
SDataThreadBusy bit is
asserted in that cycle.

with certain thread by asserting
SDataThreadBusy signal for that thread. If
is enabled for a master, it should not present a
datahandshake phase on a thread for which the
corresponding SDataThreadBusy bit is
asserted in this cycle. This check fires if this
SDATATHREADBUSY_EXACT must be
enabled and
SDATATHREADBUSY_PIPELINED must
be disabled to activate this check.
EXACT_ENABLED_WITHOUT_
SDATATHREADBUSY
SDATATHREADBUSY_
EXACT should be enabled
only if
SDATATHREADBUSY is
enabled.
SDATATHREADBUSY_EXACT has no
meaning if the SDATATHREADBUSY signal
is not configured for an interface in the first
place. This check fires when the parameter
SDATATHREADBUSY_EXACT is enabled
when the parameter SDATATHREADBUSY
is not enabled.
PIPELINED_
DATAHANDSHAKE_
If SDATATHREADBUSY_
PIPELINED is enabled, then a
datahandshake phase should
not be presented on a thread
for which the corresponding
SDataThreadBusy bit is
asserted in the previous cycle.

with a certain thread by asserting
SDataThreadBusy signal for that thread. If
SDATATHREADBUSY_EXACT and
SDATATHREADBUSY_PIPELINED
parameter are enabled for a master, then it
should not present a datahandshake phase on a
thread for which the corresponding
SDataThreadBusy bit is asserted in the
previous cycle. This check fires if this
SDATATHREADBUSY
should not be enabled when
DATAACCEPT and
SDATATHREADBUSY_
EXACT are not enabled.
requires strict semantics for SDataThreadbusy
parameter SDATATHREADBUSY is enabled
without enabling DATAACCEPT and
SDATATHREADBUSY_EXACT, as there is
no real flow control.
(OCP 2.2 check)
WITHOUT_DATAACCEPT_
AND_
OCP_SINGLE_REQ_MULTIPLE_ Single request / multiple data

DATA_REQ_WITH_UNKN_
bursts should not be issued
ADDR_SEQ
with the address sequence
UNKN.
For single request / multiple data bursts, only

the start address is issued with the request by
master. The slave has to calculate address for
each data transfer from the type of address
sequence (MBurstSeq field value). By
definition, burst address sequence for UNKN
burst sequence type is not statically known.
Hence, these bursts should not be issued as
single request / multiple data bursts. This
check fires such violation. This check is active
only if the parameter BURSTSEQ and
BURSTSINGLEREQ are set to 1.
385

Monitor Checks

Check ID
Violation
Description
OCP_SRESP_NOT_STEADY
SResp should be steady from

response phase.

sampled asserted. If the response phase spans
over multiple clocks, then the SResp signal
should remain steady throughout the response
phase. This check fires if SResp does not
remain steady during response phase. This
check is active only if the parameter RESP is
set to 1.
OCP_SRESP_UNKN
SResp signal should not be X

or Z.
Checks that SResp is both known (not X) and

driven (not Z).
OCP_SRESPINFO_NOT_
STEADY
SRespInfo should be steady

the response phase.

multiple clocks, SRespInfo signal should
This check fires if SRespInfo does not remain
active only if the parameter RESPINFO is set
to 1.
OCP_SRESPINFO_UNKN
SRespInfo signal should not be Checks that SRespInfo is both known (not X)
X or Z.
and driven (not Z).
OCP_SRESPLAST_NOT_
STEADY
SRespLast should be steady

the response phase.
OCP_SRESPLAST_UNKN
SRespLast signal should not be Checks that SRespLast is both known (not X)
X or Z.
and driven (not Z).
OCP_SRESPLAST_VIOLATION
SRespLast should be asserted

only for last response phase of
the burst.
386

multiple clocks, SRespLast signal should
This check fires if SRespLast does not remain
active only if the parameter RESPLAST is set
to 1.
SRespLast signal indicates the last response in

the burst. This check fires when the SRespLast
signal is not asserted along with the last
transfer of the response burst, or the
SRespLast signal is asserted in a transfer
that is not a last transfer in response burst. This
RESPLAST is set to 1, parameter RESP is set
to 1, and parameter
CHECKS is set to 1.

Monitor Checks

Check ID
Violation
Description
OCP_SRESPROWLAST_NOT_
STEADY
SRespRowLast should be
the response phase until the
end of the response phase.

multiple clocks, then SRespRowLast signal
phase.
This check fires if SRespRowLast does not
remain steady during the response phase.
RESPROWLAST is set to 1.
SRespRowLast signal should

not be X or Z.
Checks that SRespRowLast is both known (not

OCP_SRMD_WR_RESP_
BEGINNING_BEFORE_LAST_
WR_DATA
For SRMD writes, a response

phase should not begin before
the associated last
datahandshake phase begins.
For SRMD write requests, a master presents

only a single request phase, one or more
datahandshake phases, and expects only a
single response phase. A slave can present the
associated write response phase in the same
clock in which the master presents the last
write data or in the subsequent clocks. A slave
should never present a response for a request
before the last write data is presented by the
master. This check fires if this requirement is
parameter DATAHANDSHAKE is enabled,
the parameter RESP is enabled, and the
parameter
CHECKS is set to 1.
OCP_SRMD_WR_RESP_
ENDING_BEFORE_LAST_WR_
DATA
For SRMD writes, a response

phase should not end before
the associated last
datahandshake phase ends.
For SRMD write requests, a master presents

only a single request phase, one or more
datahandshake phases, and expects only a
single response. A slave can end the associated
write response in the same clock in which the
master presents the last write data or in the
subsequent clocks. A slave should never end a
response for a request before the last write data
ends. This check fires if this requirement is
the parameter RESP is enabled, and the
parameter
CHECKS is set to 1.
OCP_STAGID_NOT_STEADY

STagID should be steady from
response phase.

over multiple clocks, then the STagID signal
phase. This check fires if STagID does not
remain steady during response phase. This
check is active only if the parameter TAGS is
set to a value greater than 1.
(OCP 2.2 check)
OCP_SRESPROWLAST_UNKN
(OCP 2.2 check)
387

Monitor Checks

Check ID
Violation
Description
OCP_STAGID_UNKN
STagID signal should not be X

or Z.
Checks that STagID is both known (not X) and

driven (not Z).
OCP_STAGID_VALUE_NOT_
LESS_THAN_TAGS

value of the STagID field
should be less than the number
of tags.
The value presented on the STagID field

1.
OCP_STAGINORDER_NOT_
STEADY
STagInOrder should be steady

the response phase.

over multiple clocks, then the STagInOrder
response phase. This check fires if
STagInOrder does not remain steady during
the response phase. This check is active only if
the parameter TAGINORDER is set to 1.
OCP_STAGINORDER_UNKN
STagInOrder signal should not

be X or Z.
Checks that STagInOrder is both known (not

OCP_STATUS_UNKN
Status signal should not be X

or Z.
Checks that Status is both known (not X) and

driven (not Z).
OCP_STATUSBUSY_
ENABLED_WITHOUT_STATUS
STATUSBUSY should not be

enabled if STATUS is not
enabled.
Statusbusy signal indicates the consistency of

information on the Status field. If Status signal
is not configured for an interface, Statusbusy
signal does not have any meaning. This check
fires if parameter STATUSBUSY is enabled
without enabling parameter STATUS.
OCP_STATUSBUSY_UNKN
StatusBusy signal should not

be X or Z.
Checks that StatusBusy is both known (not X)

and driven (not Z).
OCP_STATUSRD_ASSERTED_
FOR_MORE_THAN_ONE_
CYCLE
StatusRd should be asserted

for only one clock cycle.
StatusRd signal is set to 1 by the system to

indicate that the status information is read by
the system. This check fires if the StatusRd
signal is asserted for more than one clock
cycle. This check is active only if the
parameter STATUSRD is set to 1.
OCP_STATUSRD_ASSERTED_
StatusRd signal should not be
WHILE_STATUSBUSY_ACTIVE asserted if StatusBusy is
asserted.

the system. StatusBusy signal from the core
tells the system to disregard the status field
because it may be inconsistent. This check
fires when StatusRd signal is sampled asserted
when StatusBusy signal is asserted. This check
is active only if the parameters
STATUSBUSY and STATUSRD are set to 1.
OCP_STATUSRD_ENABLED_
WITHOUT_STATUS

the system. If Status field in not configured for
an interface, nothing can be read by asserting
StatusRd signal. This check fires if parameter
STATUSRD is enabled without enabling
parameter STATUS.
388
STATUSRD should not be

enabled if STATUS is not
enabled.

Monitor Checks

Check ID
Violation
Description
OCP_STATUSRD_UNKN
StatusRd signal should not be

X or Z.
Checks that StatusRd is both known (not X)

and driven (not Z).
OCP_STHREADBUSY_EXACT_
COMMAND_ACCEPTANCE_
VIOLATION
Command presented on a
thread for which SThreadBusy
is de-asserted in the current
cycle should be accepted by
the slave in that cycle.

accept any requests associated with certain
thread by asserting SThreadBusy signal for
that thread. If STHREADBUSY_EXACT
parameter is enabled for a slave and a
command is presented on a thread for which
SThreadBusy is de-asserted in the current
cycle, it should be accepted by the slave in that
cycle. This check fires if this restriction is
violated.
STHREADBUSY_EXACT must be enabled
and STHREADBUSY_PIPELINED must be
COMMAND_PESENTATION_
VIOLATION
If STHREADBUSY_EXACT
is enabled for a master, it
should not present a command
on a thread for which the
corresponding SThreadBusy
bit asserted in this cycle.

accept any requests associated with certain
that thread. If STHREADBUSY_EXACT is
enabled for a master, it should not present a
command on a thread for which the
corresponding SThreadBusy bit is asserted in
this cycle. This check fires if this restriction is
violated.
STHREADBUSY_EXACT must be enabled
and STHREADBUSY_PIPELINED must be
ENABLED_WITHOUT_
STHREADBUSY
STHREADBUSY_EXACT
should be enabled only if
STHREADBUSY is enabled.
STHREADBUSY_EXACT has no meaning if

the STHREADBUSY signal is not configured
for an interface in the first place. This check
fires when parameter
STHREADBUSY_EXACT is enabled when
parameter STHREADBUSY is not enabled.
OCP_STHREADBUSY_
PIPELINED_COMMAND_
If STHREADBUSY_EXACT
is enabled, then a command
should not be presented on a
thread for which the
corresponding SThreadBusy
bit asserted in this cycle.

accept any requests associated with a certain
that thread. If STHREADBUSY_EXACT and
STHREADBUSY_PIPELINED are enabled
for a master, then it should not present a
command on a thread for which the
corresponding SThreadBusy bit is asserted in
the previous cycle. This check fires if this
STHREADBUSY should not

be enabled when
CMDACCEPT and
STHREADBUSY_EXACT
are not enabled.
STHREADBUSY_EXACT parameter
parameter STHREADBUSY is enabled
without enabling CMDACCEPT and
STHREADBUSY_EXACT, as there is no real
flow control.
(OCP 2.2 check)
OCP_STHREADBUSY_
WITHOUT_CMDACCEPT_
ANDSTHREADBUSY_EXACT
389

Monitor Checks

Check ID
Violation
Description
OCP_STHREADID_NOT_
STEADY
SThreadID should be steady

the response phase.

over multiple clocks, then the SThreadID
response phase. This check fires if SThreadID
does not remain steady during response phase.
THREADS is set to a value greater than 1.
OCP_STHREADID_UNKN
SThreadID signal should not

be X or Z.
Checks that SThreadID is both known (not X)

and driven (not Z).
OCP_STHREADID_VALUE_
NOT_LESS_THAN_THREADS
The value of the SThreadID

field should be less than the
number of threads.
The value presented on the SThreadID field

should be less than the number of threads
than 1.
OCP_STRM_BURST_MADDR_
NOT_CONSTANT
STRM bursts should have the

same MAddr across all
transfers of the burst.

larger power-of-2. The STRM address burst
sequences are used for FIFO oriented targets.
For STRM bursts address should remain
constant for all transfers. This check fires if
active only if the parameter ADDR is set to 1
through monitor port basic_group and
OCP_STRM_BURST_WHILE_
BURSTSEQ_STRM_ENABLE_0
A master with
BURSTSEQ_STRM_
issue STRM burst.
This check fires if a STRM burst is presented

when BURSTSEQ_STRM_ENABLE
OCP_STRM_SEQUENCE_NOT_
HAVING_SAME_BYTE_
ENABLES
Bursts with the STRM address

sequence should have the same
byte enable pattern for each

For STRM address sequence, the byte enables
should have the same pattern for all the
transfers in the burst. This check fires if this
performed on the MByteEn field. This check is
active only if the parameter BYTEEN is set to
1 and the parameter BURSTSEQ is set to 1.
390

Monitor Checks

Check ID
Violation
Description
OCP_STRM_SEQUENCE_NOT_
HAVING_SAME_
MDATABYTE_ENABLES
Bursts with the STRM address

sequence should have the same
mdatabyte enable pattern for

For STRM address sequence, the byte enables
should have the same pattern for all the
transfers in the burst. This check fires if this
performed on the MDataByteEn field. This
check is active only if parameter
MDATABYTEEN is set to 1, parameter
BURSTSEQ is set to 1, parameter
DATAHANDSHAKE is enabled, and
parameter
CHECKS is set to 1.
OCP_STRM_SEQUENCE_
WITHOUT_ANY_BYTE_
ENABLE_ASSERTED
Burst address sequence STRM

should have at least one byte
enable asserted for each

asserted for a transfer in the STRM burst
address sequence. This check is performed on
the MByteEn field. This check is active only if
parameter BYTEEN is set to 1 and parameter
OCP_STRM_SEQUENCE_
WITHOUT_ANY_
MDATABYTE_ENABLE_
ASSERTED
Burst address sequence STRM

should have at least one
mdatabyte enable asserted for

asserted for a transfer in the STRM burst
address sequence. This check is performed on
the MDataByteEn field. This check is active
only if the parameter MDATABYTEEN is set
to 1, parameter BURSTSEQ is set to 1,
and the parameter
CHECKS is set to 1.
OCP_TAGGED_WRITE_DATA_
OUT_OF_ORDER
For tagged write transactions,

the datahandshake phase must
observe the same order as the
request phase.
For tagged write transactions, the master must

present the datahandshake phases in the same
order in which it presents request phases. This
check fires if the master presents the
datahandshake phases out of order with
request phases. This check is active only if the
1, parameter DATAHANDSHAKE is enabled,
and the parameter
CHECKS is set to 1.
OCP_TAGID_WDTH_NOT_
LOG2_OF_TAGS
The value of the

TAGID_WDTH parameter
should be equal to the next
whole integer of log2 of
TAGS.
The TAGID_WDTH parameter defines the

width of MTagID, MDataTagID, and STagID
fields. To present all possible values of tags on
MTagID, MDataTagID, and STagID fields,
the width of these fields must be set to a value
that is the next whole integer of log2 of TAGS
parameter. This check fires if the value of the
TAGID_WDTH parameter is not equal to the
next whole integer of log2 of TAGS.
391

Monitor Checks

Check ID
Violation
Description
OCP_TAGINORDER_WHEN_
TAGS_NOT_GREATER_THAN_
1
TAGINORDER should not be

set when tagged transactions
are not enabled.
When the TAGINORDER parameter is set to

1, it enables the MTagInOrder and
STagInOrder signals. These signals do not
have a meaning when tagged transactions are
not enabled. This check fires when the
TAGINORDER parameter is set to 1 when
tagged transactions are not enabled.
OCP_THREADID_WDTH_NOT_
LOG2_OF_THREADS
The value of the

THREADID_WDTH
parameter should be equal to
the next whole integer of log2
of THREADS.
The THREADID_WDTH parameter defines

the width of MThreadID, MDataThreadID,
and SThreadID fields. To present all possible
values of threads on MThreadID,
MDataThreadID, and SThreadID fields, the
width of these fields must be set to a value that
is the next whole integer of log2 of the
THREADS parameter. This check fires if the
value of the THREADID_WDTH parameter is
not equal to the next whole integer of log2 of
THREADS.
OCP_TRANSITS2MCON_
WITHOUT_SLAVE_GRANT
Master must not change state

The OCP interface can transition to M_CON
to M_CON before slave allows state only if the slave allows it (SConnect=1
to connect.
and SWait=0). This check fires when this

OCP_TRANSITS2MDISC_
WITHOUT_SLAVE_REQUEST

to M_DISC before slave
requests to disconnect.
The MConnect signal can transition to

M_DISC state only if the slave has requested it
(SConnect =0 and SWait=0). This check fires
when this condition is violated.

to M_OFF before slave allows
this transition.
The OCP interface can transition to M_OFF

state only if the slave allows it (SWait=0). This
check fires when this condition is violated.

to M_WAIT before slave
requests to wait.
The OCP interface can transition to M_WAIT

state only if the slave allows it (Swait =1). This
check fires when this condition is violated.
A master with
BURSTSEQ_UNKN_
issue UNKN burst.
This check fires if a UNKN burst is presented

when BURSTSEQ_UNKN_ENABLE
OCP_UNLOCKING_WR_WRNP_ The unlocking Write or

CMD_AS_BURST
WriteNonPost command
associated with a ReadEx
command should not be used
as part of a burst.
Locked synchronization mechanism consists

of a ReadEx command followed by a Write or
WriteNonPost command. ReadEx command
sets a lock for a initiating thread on the
addressed location. Write/WriteNonPost
command unlocks the access to the matched
address. The unlocking Write or
WriteNonPost command cannot be used in a
burst. This check fires if unlocking Write or
WriteNonPost command associated with a
ReadEx command is used as part of the burst.
OCP_WR_CMD_WHILE_
WRITE_ENABLE_0
A master can generate a Write command only

if parameter WRITE_ENABLE is set. This
check fires if Write command is generated
when parameter WRITE_ENABLE is set to 0.

OCP_TRANSITS2MOFF_
WITHOUT_SLAVE_GRANT
OCP_TRANSITS2MWAIT_
WITHOUT_SLAVE_REQUEST
OCP_UNKN_BURST_WHILE_
BURSTSEQ_UNKN_ENABLE_0
392
A master with
WRITE_ENABLE set to 0
should not generate Write
command.

Monitor Checks

Check ID
Violation
Description
OCP_WRAP_BURST_
INCORRECT_ADDRESS_
SEQUENCE
For WRAP bursts, MAddr

sequence should be as defined
by the specification.

to the OCP word size (DATA_WDTH). For
WRAP bursts address sequence wraps across a
wrap boundary. Wrap boundary is aligned to
the MBurstLength times the OCP word size in
bytes, where both MBurstLength and OCP
word size are power of two values. This check
fires if for WRAP bursts address sequence do
not follow this scheme. This check is active
only if the parameter ADDR is set to 1 through
monitor port basic_group and BURSTSEQ is
set to 1.
OCP_WRAP_BURST_WHILE_
BURSTSEQ_WRAP_ENABLE_0
A master with
BURSTSEQ_WRAP_
issue WRAP burst.
This check fires if a WRAP burst is presented

when BURSTSEQ_WRAP_ENABLE
OCP_WRAP_SEQUENCE_FOR_
IMPRECISE_BURST
Burst address sequence WRAP To calculate the proper address sequence for
should be used only for precise WRAP burst, length of the burst must be
bursts.
known at the start of the burst. For this reason,
burst address sequence WRAP should be
issued as a precise burst. This check fires if
active only if the parameter BURSTSEQ is set
to 1.
OCP_WRAP_SEQUENCE_NON_
POWER_OF_TWO_BURST_
LENGTH
Burst length of WRAP address

sequence should be power-oftwo value.
WRAP burst address sequence cannot be

calculated properly for non-power-of-two
burst lengths. Hence, burst address sequence
WRAP should have power-of-two burst
length. This check fires if burst length for
XOR burst sequence is detected as non-powerof-two value. This check is active only if the
parameter BURSTSEQ is set to 1.
OCP_WRAP_SEQUENCE_NON_
POWER_OF_TWO_DATA_
WDTH
Burst address sequence WRAP

DATA_WDTH is a power-oftwo number of bytes.
WRAP burst address sequence cannot be

calculated properly for DATA_WDTH which
is non-power-of-two bytes in size. Hence,
burst address sequence WRAP should be
enabled only if DATA_WDTH is a power-oftwo number of bytes. This check fires if this
OCP_WRC_CMD_AS_ BURST
The WriteConditional
command should not be used
as part of burst.
WriteConditional command assumes a single

burst. This check fires if the WriteConditional
command is used as part of the burst.
OCP_WRC_CMD_WHILE_
RDLWRC_ENABLE_0
A master with
RDLWRC_ENABLE set to 0
should not generate
WriteConditional command.
A master can generate a WriteConditional

RDLWRC_ENABLE is set. This check fires if
WriteConditional command is generated when
parameter RDLWRC_ENABLE is set to 0.
393

Monitor Checks

Check ID
Violation
Description
OCP_WRC_CMD_WHILE_
WRITERESP_ENABLE_0
A master with
WriteConditional command.

disabled. This check fires when a
WriteConditional command is issued while
OCP_WRITENONPOST_
ENABLE_SET_WITHOUT_
WRITERESP_ENABLE
WRITENONPOST_
ENABLE should be set to 1
only if
to 1.
A WriteNonpost command is completed on the

receipt of a response. If responses are not
enabled for write-type commands, then
WriteNonpost should not be issued. This
check fires if parameter
WRITENONPOST_ENABLE is enabled
without enabling parameter
WRITERESP_ENABLE.
OCP_WRNP_CMD_WHILE_
WRITENONPOST_ENABLE_0
A master with
WRITENONPOST_ENABLE
set to 0 should not generate
WriteNonPost command.
A master can generate a WriteNonPost

WRITENONPOST_ENABLE is set. This
check fires if WriteNonPost command is
WRITENONPOST_ENABLE is set to 0.
OCP_WRNP_CMD_WHILE_
WRITERESP_ENABLE_0
A master with
WriteNonPost command.

disabled. This check fires when a
WriteNonPost command is issued while
OCP_XOR_BURST_
INCORRECT_ADDRESS_
SEQUENCE
For XOR bursts, MAddr

sequence should be as defined
by the specification.

to the OCP word size (DATA_WDTH). The
Exclusive OR address sequence bursts are
used typically for processor cache line fill. The
address sequence for XOR bursts is as follows.
Let BASE be the lowest byte address in the
burst, which must be aligned with the total
burst size. Let FIRST_OFFSET be the byte
offset (from BASE) of the first transfer in the
burst. Let CURRENT_COUNT be the count
of the current transfer in the burst, starting at 0.
Let WORD_SHIFT be the log2 of the OCP
word size in bytes. Then the current address of
the transfer is BASE | (FIRST_OFFSET ^
(CURRENT_COUNT << WORD_SHIFT)).
This check fires when address for each transfer
in XOR burst do not follow this sequence. This
check is active only if the parameter ADDR is
set to 1 through monitor port basic_group and
394


Check ID
Violation
Description
OCP_XOR_BURST_WHILE_
BURSTSEQ_XOR_ENABLE_0
A master with
BURSTSEQ_XOR_
issue XOR burst.
This check fires if a XOR burst is presented

when BURSTSEQ_XOR_ENABLE
OCP_XOR_SEQUENCE_FOR_
IMPRECISE_BURST
Burst address sequence XOR

should be used only for precise
bursts.
To calculate the proper address sequence for

XOR burst, length of the burst must be known
at the start of the burst. For this reason, burst
address sequence XOR should be issued as a
precise burst. This check fires if this
only if the parameter BURSTSEQ is set to 1.
OCP_XOR_SEQUENCE_NON_
POWER_OF_TWO_BURST_
LENGTH
Burst length of XOR address

sequence should be power-oftwo value.
XOR burst address sequence cannot be

calculated properly for non-power-of-two
burst lengths. Hence, burst address sequence
XOR should have power-of-two burst length.
This check fires if burst length for XOR burst
sequence is detected as non-power-of-two
value. This check is active only if the
parameter BURSTSEQ is set to 1.
OCP_XOR_SEQUENCE_NON_
POWER_OF_TWO_DATA_
WDTH
Burst address sequence XOR

DATA_WDTH is a power-oftwo number of bytes.
XOR burst address sequence cannot be

calculated properly for DATA_WDTH which
is non-power-of-two bytes in size. Hence,
burst address sequence XOR should be
enabled only if DATA_WDTH is a power-oftwo number of bytes. This check fires if this

Table 12-4 lists the checks performed by the OCP monitor.
Table 12-4. OCP Corner Cases
Corner Cases
Description
Read requests
Number of Read requests
Write requests
Number of Write requests
Broadcast requests
Number of Broadcast requests
WriteNonPost requests
Number of WriteNonPost requests
WriteConditional requests
Number of WriteConditional requests
ReadLinked requests
Number of ReadLinked requests
ReadEx requests
Number of ReadEx requests
DFLT1 burst sequences
Number of DFLT1 burst sequences
DFLT2 burst sequences
Number of DFLT2 burst sequences
INCR burst sequences
Number of INCR burst sequences
395

Table 12-4. OCP Corner Cases (cont.)

Corner Cases
Description
STRM burst sequences
Number of STRM burst sequences
UNKN burst sequences
Number of UNKN burst sequences
WRAP burst sequences
Number of WRAP burst sequences
XOR burst sequences
Number of XOR burst sequences
Imprecise bursts
Number of Imprecise bursts
Precise bursts with multiple requests
Number of Precise bursts with multiple requests
Precise bursts with single request
Number of Precise bursts with single request
DVA responses
Number of DVA responses
ERR responses
Number of ERR responses
FAIL responses
Number of FAIL responses
Sconnect signal state toggles from S_CON to

S_DISC
Number of Sconnect signal state toggles from S_CON to

S_DISC
Sconnect signal state toggles from S_DISC to

S_CON
Number of Sconnect signal state toggles from S_DISC to

S_CON
Swait signal state toggles from S_WAIT to

S_OK
Number of Swait signal state toggles from S_WAIT to

S_OK
Swait signal state toggles from S_OK to

S_WAIT
Number of Swait signal state toggles from S_OK to

S_WAIT
Mconnect signal state toggles from M_CON to

M_DISC
Number of Mconnect signal state toggles from M_CON to

M_DISC

M_WAIT

M_WAIT

M_OFF

M_OFF
Mconnect signal state toggles from M_DISC to

M_CON
Number of Mconnect signal state toggles from M_DISC to

M_CON

M_WAIT

M_WAIT

M_OFF

M_OFF
Mconnect signal state toggles from M_WAIT to

M_CON
Number of Mconnect signal state toggles from M_WAIT to

M_CON

M_DISC

M_DISC

M_OFF

M_OFF
Mconnect signal state toggles from M_OFF to

M_WAIT
Number of Mconnect signal state toggles from M_OFF to

M_WAIT

M_CON

M_CON
396

Monitor Statistics
Table 12-4. OCP Corner Cases (cont.)

Corner Cases
Description

M_DISC

M_DISC
Note that the corner cases are applicable only if the corresponding features (parameters) are
enabled.
Monitor Statistics
Table 12-5 lists the corner cases maintained by the OCP monitor.
Table 12-5. OCP Protocol Statistics
Statistic
Description
Total requests
Total number of requests
Back to back Read requests
Number of Back to back Read requests
Back to back Write requests
Number of Back to back Write requests
Back to back WriteNonPost requests
Number of Back to back WriteNonPost requests
Back to back Broadcast requests
Number of Back to back Broadcast requests
Request phases with all data masked
Number of Request phases with all data masked
Datahandshake phases with all data masked
Number of Datahandshake phases with all data masked
Note that the statistics are applicable only if the corresponding features (parameters) are
enabled.
397

Monitor Statistics
398
Chapter 13
Peripheral Component Interconnect (PCI)
Introduction
The Peripheral Component Interconnect (PCI) local bus is an industry standard, highperformance local bus architecture. The Mentor Graphic QVL PCI Monitor verifies the
operation of a PCI compliant device under simulation. When running the Assertion in
Simulation tool, the checkers defined by the monitor validate various restrictions and
requirements of the PCI specification. With formal analysis, the monitors checks can be targets
for search or they can be used to constrain the interface to provide legal stimulus.
The Mentor Graphic QVL PCI Monitor supports PCI compliant devices that use the 32-bit
standard data bus configuration and those that use the 64-bit extension.
This PCI monitor is modeled from the requirements provided in the following document:
PCI Local Bus Specification Rev. 2.2, Dec. 18, 1998
PCI Local Bus Specification Rev 2.3, Mar. 29, 2002

To use the QVL PCI monitor, place an instance of the monitor inside the PCI compliant device
as shown in the block diagram in Figure 13-1.
Figure 13-1. PCI Monitor Implementation
PCI Compliant Device
PCI Monitor
PCI Local Bus
399

Connect the PCI monitor pins to internal signals as specified in the pin-out Table 13-1 and
The PCI monitor enable signals (*_en_n) are active low signals. When asserted (low), the PCI
monitor samples the corresponding out signal (for example, pci_frame_out_n). When deasserted (high), the PCI monitor samples the corresponding in signal (for example,
pci_frame_in_n).
Figure 13-2. PCI Monitor Pin Diagram
From PCI Bus
From PCI Compliant Device
pci_rst_in_n
pci_clk_in
pci_gnt_in_n
pci_idsel_in
pci_ad_in
pci_cbe_in_n
pci_frame_in_n
pci_irdy_in_n
pci_trdy_in_n
pci_devsel_in_n
pci_stop_in_n
pci_lock_in_n
pci_perr_in_n
PCI Monitor
pci_par_in
pci_par64_in
pci_req64_in_n
pci_ack64_in_n
pci_ad_en_n
pci_cbe_en_n
pci_frame_en_n
pci_irdy_en_n
pci_trdy_en_n
pci_devsel_en_n
pci_stop_en_n
pci_perr_en_n
pci_par_en_n
pci_par64_en_n
pci_req64_en_n
pci_ack64_en_n
pci_req_out_n
pci_ad_out
pci_cbe_out_n
pci_frame_out_n
pci_irdy_out_n
pci_trdy_out_n
pci_devsel_out_n
pci_stop_out_n
pci_perr_out_n
pci_serr_out_n
pci_par_out
pci_par64_out
pci_req64_out_n
pci_ack64_out_n
Table 13-1. PCI Monitor Pins

Pin
Description
pci_ack64_en_n
Enable signal from the PCI compliant device to the ACK64# buffer.
pci_ack64_in_n
PCI Acknowledge 64-bit Transfer (ACK64#) input to the PCI compliant device.
pci_ack64_out_n
PCI Acknowledge 64-bit Transfer (ACK64#) output from the PCI Compliant Device.
pci_ad_en_n
Enable signal from the PCI compliant device to the AD buffers.
400

Table 13-1. PCI Monitor Pins (cont.)

Pin
Description
pci_ad_in
PCI multiplexed Address and Data (AD) bus input to the PCI compliant device,
minimum 32-bits wide (default), maximum 64-bits wide.
pci_ad_out
PCI multiplexed Address and Data (AD) bus output from the PCI compliant device,
minimum 32-bits wide (default), maximum 64-bits wide.
pci_cbe_en_n
Enable signal from the PCI compliant device to the C/BE# buffers.
pci_cbe_in_n
PCI multiplexed Bus Command and Byte Enables (C/BE#) bus input to the PCI
compliant device, minimum 4-bits wide (default), maximum 8-bits wide.
pci_cbe_out_n
PCI multiplexed Bus Command and Byte Enables (C/BE#) bus output from the PCI
compliant device, minimum 4-bits wide (default), maximum 8-bits wide.
pci_clk_in
PCI Clock (CLK) input to the PCI compliant device.
pci_devsel_en_n
Enable signal from the PCI compliant device to the DEVSEL# buffer.
pci_devsel_in_n
PCI Device Select (DEVSEL#) input to the PCI compliant device.
pci_devsel_out_n
PCI Device Select (DEVSEL#) output from the PCI compliant device.
pci_frame_en_n
Enable signal from the PCI compliant device to the FRAME# buffer.
pci_frame_in_n
PCI Cycle Frame (FRAME#) input to the PCI compliant device.
pci_frame_out_n
PCI Cycle Frame (FRAME#) input to the PCI compliant device.
pci_gnt_in_n
PCI Grant (GNT#) input to the PCI compliant device.
pci_idsel_in
PCI Initialization Device Select (IDSEL) input to the PCI compliant device.
pci_irdy_en_n
Enable signal from the PCI compliant device to the IRDY# buffer.
pci_irdy_in_n
Initiator Ready (IRDY#) input to the PCI compliant device.
pci_irdy_out_n
PCI Initiator Ready (IRDY#) output from the PCI compliant device.
pci_lock_in_n
PCI lock (LOCK#) input to the PCI compliant device.
pci_par64_en_n
Enable signal from the PCI compliant device to the PAR64 buffer.
pci_par64_in
PCI Parity Upper DWORD (PAR64) input for pci_ad_in[63:32] and pci_cbe_in_n[7:4]
to the PCI compliant device.
pci_par64_out
PCI Parity Upper DWORD (PAR64) output for pci_ad_out[63:32] and

pci_cbe_out_n[7:4] from the PCI compliant device.
pci_par_en_n
Enable signal from the PCI compliant device to the PAR buffer.
pci_par_in
PCI parity (PAR) input for pci_ad_in[31:0] and pci_cbe_in_n[3:0] to the PCI
compliant device.
pci_par_out
PCI parity (PAR) output for pci_ad_out[31:0] and pci_cbe_out_n[3:0] from the PCI
compliant device.
pci_perr_en_n
Enable signal from the PCI compliant device to the PERR# buffer.
pci_perr_in_n
PCI Parity Error (PERR#) input to the PCI compliant device.
pci_perr_out_n
PCI Parity Error (PERR#) output from the PCI compliant device.
pci_req64_en_n
Enable signal from the PCI compliant device to the REQ64# buffer.
pci_req64_in_n
PCI Request 64-bit Transfer (REQ64#) input to the PCI compliant device.
401

Table 13-1. PCI Monitor Pins (cont.)

Pin
Description
pci_req64_out_n
PCI Request 64-bit Transfer (REQ64#) output from the PCI compliant device.
pci_req_out_n
PCI Request (REQ#) output from the PCI compliant device.
pci_rst_in_n
PCI Reset (RST#) input to the PCI compliant device.
pci_serr_out_n
PCI System Error (SERR#) output from the PCI compliant device
pci_stop_en_n
Enable signal from the PCI compliant device to the STOP# buffer.
pci_stop_in_n
PCI Stop (STOP#) input to the PCI compliant device.
pci_stop_out_n
PCI Stop (STOP#) output from the PCI compliant device.
pci_trdy_en_n
Enable signal from the PCI compliant device to the TRDY# buffer.
pci_trdy_in_n
PCI Target Ready (TRDY#) input to the PCI compliant device.
pci_trdy_out_n
PCI Target Ready (TRDY#) output from the PCI compliant device.
Monitor Parameters
The parameters shown in Table 13-2 configure the PCI monitor.
Table 13-2. PCI Monitor Parameters
Order
Parameter
Default
Description
1.
Bit64Mode
Set to 1 if the target design is a 64-bit capable device.
2.
Constraints_Mode
Parameter to configure the checks in the monitor as

constraints or targets for the formal analysis. By
default, the Constraints_Mode is disabled. That is, all
the checks in the monitor are configured as targets for
formal analysis.
Set this parameter to 1 to configure the checks in the
monitor as constraints for formal analysis.
3.
Parity_Error_Response
Set to 0 if PERR# is disabled in the design. By default,

PERR# tracking is set.
4.
Self_Config
Set to 1 if the design supports self-configuration from

the PCI interface. By default, self-configuration is not
supported.
Instantiation Example
Example 13-1 instantiates the PCI monitor inside a 64-bit capable PCI compliant device.
Constraints mode is not enabled.
402

Monitor Checks
Example 13-1. PCI Monitor Instantiation

qvl_pci_monitor
#( /* Bit64Mode */
.pci_ad_en_n
.pci_cbe_en_n
.pci_frame_en_n
.pci_irdy_en_n
.pci_trdy_en_n
.pci_devsel_en_n
.pci_stop_en_n
.pci_perr_en_n
.pci_par_en_n
.pci_par64_en_n
.pci_req64_en_n
.pci_ack64_en_n
.pci_rst_in_n
.pci_clk_in
.pci_gnt_in_n
.pci_idsel_in
.pci_ad_in
.pci_cbe_in_n
.pci_frame_in_n
.pci_irdy_in_n
.pci_trdy_in_n
.pci_devsel_in_n
.pci_stop_in_n
.pci_lock_in_n
.pci_perr_in_n
.pci_par_in
.pci_par64_in
.pci_req64_in_n
.pci_ack64_in_n
.pci_req_out_n
.pci_ad_out
.pci_cbe_out_n
.pci_frame_out_n
.pci_irdy_out_n
.pci_trdy_out_n
.pci_devsel_out_n
.pci_stop_out_n
.pci_perr_out_n
.pci_serr_out_n
.pci_par_out
.pci_par64_out
.pci_req64_out_n
.pci_ack64_out_n
1,
0) pci_mon
(pci_aden_n),
(pci_cbe_en_n),
(pci_frame_en_n),
(pci_irdy_en_n),
(pci_trdy_en_n),
(pci_devsel_en_n),
(pci_stop_en_n),
(pci_perr_en_n),
(pci_par_en_n),
(pci_par64_en_n),
(pci_req64_en_n),
(pci_ack64_en_n),
(pci_rst_in_n),
(pci_clk_in),
(pci_gnt_in_n),
(pci_idsel_in),
(pci_adin),
(pci_cbein_n),
(pci_frame_in_n),
(pci_irdy_in_n),
(pci_trdy_in_n),
(pci_devsel_in_n),
(pci_stop_in_n),
(pci_lock_in_n),
(pci_perr_in_n),
(pci_par_in),
(pci_par64_in),
(pci_req64_in_n),
(pci_ack64_in_n),
(pci_req_out_n),
(pci_adout),
(pci_cbeout_n),
(pci_frame_out_n),
(pci_irdy_out_n),
(pci_trdy_out_n),
(pci_devsel_out_n),
(pci_stop_out_n),
(pci_perr_out_n),
(pci_serr_out_n),
(pci_par_out),
(pci_par64_out),
(pci_req64_out_n),
(pci_ack64_out_n)
);
Monitor Checks
The checks defined for the PCI monitor are separated into the following classes:
Initiator (master) checks
403

Initiator (Master) Checks
Target checks
Top-level monitor checks
These classes correspond to the two submodules and the top-level module defined for the PCI
monitor.

Table 13-3 lists the checks performed by the monitor submodule that verifies the operation of
the initiator. Note that IUT is the Initiator Under Test.
Table 13-3. PCI Initiator Checks
404
Check ID and
Section Number
Violation
Description
MZ01
(*)
IUT never uses C/BE# reserved

bus command.
Constrains formal analysis to exercise the pins in

accordance with the PCI protocol. Failure to do
so can cause the core to malfunction when formal
analysis controls the pins.
MZ02
(*)
IUT asserts FRAME# only to

indicate the start of a
transaction.

MZ03
(*)
IUT asserts FRAME# when the

bus is idle.

MZ04
(*)
IRDY# is never asserted when

the master is not in transaction.

MZ05
(*)
Whenever STOP# is asserted,

the master must de-assert
FRAME# as soon as IRDY# can
be asserted.

MZ06
(*)
PCI master monitor should not

be in an Unknown State.
Internal monitor state machine check.
MZ07_1, MZ07_2
(*)
The IUTs C/BE# output buffers

should remain enabled from the
first clock of the data phase
through the end of the
transaction.

MZ08
(3.2.2)
Valid Combination of AD and

BE during I/O cycle.
The check fires if an invalid combination of AD

and C_BE# is issued during I/O Space decoding.
Refer to table 3-1 under section 3.2.2.1 for more
details.
MZ09
(2.2.8 and 3.8)
FRAME# and REQ64# should

be identical during 64-bit
memory transactions
REQ64#, when asserted by the initiator, indicates

its desire to transfer data using 64-bits. REQ64#
has the same timing as FRAME# (i.e., REQ64#
mirrors FRAME# once asserted).

Table 13-3. PCI Initiator Checks (cont.)

Check ID and
Section Number
Violation
Description
MZ10
(*)
REQ64# should not be asserted

if it is not asserted during
address phase.
REQ64# has the same timing as FRAME#. It

should be asserted along with FRAM# and not
after FRAME# has already been asserted.
MZ11
(3.8)
IUT always drives REQ64# only A master has to assert REQ64# only during
during memory transactions.
memory transactions. Interrupt Acknowledge and
Special Cycle commands are basically 32-bit
transactions and must not be used with REQ64#.
The bandwidth requirements for I/O and
Configuration Cycles cannot justify the added
complexity, and therefore, only memory
transactions support 64-bit data transfers.
MP02_1, MP02_2
(3.1.1)
IUT always asserts byte enables

during each data phase of a
Memory Write Invalidate cycle.
Memory Write and Invalidate command

guarantees a minimum transfer of one complete
cacheline; that is, the master intends to write all
bytes within the addressed cacheline in a single
PCI transaction, unless interrupted by the target.
All byte enables must be asserted during each
data phase for this command.
MP03
(3.1.1)
IUT always uses Linear Burst

Ordering for Memory Write
Invalidate cycles.
In linear burst order mode, the address is assumed

to increment by one DWORD (four bytes) for 32bit transactions and two DWORDs (eight bytes)
for 64-bit transactions after each data phase until
the transaction is terminated. Transactions using
Memory Write and Invalidate command can only
use the linear incrementing burst mode.
MP06
(3.2.1)
Once IUT asserts IRDY# it

never changes FRAME# until
the current data phase
completes.
Once an initiator (master) has asserted IRDY#, it

cannot change IRDY# or FRAME# until the
current data phase completes, regardless of the
state of TRDY#.
MP07
(3.2.1)
Once IUT asserts IRDY# it

never changes IRDY# until the
current data phase completes.
Once an initiator (master) has asserted IRDY#, it

cannot change IRDY# or FRAME# until the
current data phase completes, regardless of the
state of TRDY#.
MP08
(3.2.2)
IUT never uses reserved burst

ordering AD[1:0]=01.
AD[1:0]=01 encoded value is reserved. Masters

cannot use this encoding.
MP09
(3.2.2)
IUT never uses reserved burst

ordering AD[1:0]=11.
AD[1:0]=11 encoded value is reserved. Masters

cannot use this encoding.
MP11_1, MP11_2
(3.2.4)
The IUTs AD lines are driven

to stable values during every
address and data phase.
All AD lines (including AD[63:32], when the

master supports a 64-bit data path) must be driven
to stable values during every address and data
phase. Even byte lane not involved in the current
data transfers must physically drive stable data
onto the bus.
405

406
Check ID and
Section Number
Violation
Description
MP12_1, MP12_2
(3.3.1)
The IUTs C/BE# output buffers

remain enabled from the first
clock of the data phase through
the end of the transaction.
During the data phase, the C/BE# indicate which

byte lanes are involved in the current data phase.
A data phase can consist of wait cycles and a data
transfer. The C/BE# output buffers must remain
enabled for both read and write from the first
clock of the data phase through the end of the
transaction. This ensures C/BE# are not left
floating for long intervals.
MP14
(3.3.3.1)
IUT never de-asserts the

FRAME# unless IRDY# is
asserted or will be asserted.
The master must support the FRAME#IRDY#

relationship on all transactions. FRAME# cannot
be de-asserted before IRDY# is asserted, and
IRDY# must remain asserted for at least one
clock after FRAME# is de-asserted.
MP15
(3.3.3.1)
IUT never de-asserts the IRDY#

until at least one clock after
FRAME# is de-asserted.
The master must support the FRAME#IRDY#

relationship on all transactions. FRAME# cannot
be de-asserted before IRDY# is asserted, and
IRDY# must remain asserted for at least one
clock after FRAME# is de-asserted.
MP16
(3.3.3.1)
Once the IUT de-asserts the

FRAME#, it never reasserts
FRAME# during the same
transaction.
Once FRAME# has been de-asserted, it cannot be

reasserted during the same transaction.
MP17
(3.3.3.1)
IUT never terminates with

master abort once the target has
asserted DEVSEL#.
Master-Abort termination is a case of master

initiated termination. A master determines that
there will be no response to a transaction if
DEVSEL# remains de-asserted on clock 6. If
DEVSEL# had been asserted on clocks 3, 4, 5, or
6, then it indicates the request has been
acknowledged by an agent and Master-Abort
termination is not permissible.
MP18
(3.3.3.1)
IUT never signals master abort

earlier than 5 clocks after the
FRAME# is first sampled
asserted.
The earliest a master can terminate a transaction

with Master-Abort is five clocks after FRAME#
is first sampled asserted, which occurs when the
master attempts a single data transfer. If a burst is
attempted, then the transaction is longer than five
clocks.
MP20
(3.4.1)
IUT never starts a cycle unless

GNT# is asserted.
Each master is required to ensure its GNT# is

asserted on the rising clock edge it wants to start a
transaction. A master is allowed to start a
transaction when its GNT# is asserted and the bus
is in idle state.
MP23
(3.5.2)
IUT always asserts IRDY#

within eight clocks on all data
phases.
All masters are required to assert IRDY# within

eight clocks of the assertion of the FRAME# on
the initial data phase and within eight clocks on
all subsequent data phases.
MP27
(3.2.2.3.4)
IUT always uses Linear Burst

Ordering for Configuration
Cycles.
Devices respond to Configuration Cycles, by

asserting DEVSEL#, if the devices IDSEL is
asserted and AD[1:0] is 00 (Linear Burst
Ordering) during the Address phase. Otherwise,
the device ignores the transaction.


Check ID and
Section Number
Violation
Description
MP28_1, MP28_2
(3.7.1)
IUT always drives PAR within

one clock of C/BE# and AD
being driven.
On any given bus phase, PAR and PAR64 are

driven by the agent that drives AD and "lag" the
corresponding address or data by one clock.
MP29_1
(3.7.1)
IUT always drives PAR such

that the number of 1s on
AD[31:0], C/BE[3:0], and PAR
equals an even number.
Parity is calculated the same on all PCI

transactions regardless of type or form. The total
number of 1s on AD[31:0], C/BE[3:0], and PAR
is an even number. Parity generation is not
optional, it must be done by all PCI compliant
devices.
MP29_2
(3.7.1)
IUT always drives PAR64 such

that the number of 1s on
AD[63:32], C/BE[7:4], and
PAR64 equals an even number.

devices.
MP30
(3.7.4.1)
IUT always drives PERR#

(when enabled) active two
clocks after data when data
parity error is detected.
A device asserting PERR# must do so two clocks

after the completion of each data phase in which
an error occurs. This check is enabled if the
parameter Parity_Error_Response is 1.
MP32
(3.9)
IUT always holds FRAME#

asserted for cycle following
DUAL command.
In a DAC transaction, an additional address phase

is inserted. FRAME# must be asserted during
both address phases. To adhere to the
FRAME#IRDY# relationship, FRAME#
cannot be de-asserted until IRDY# is asserted.
MP33
(3.9)
IUT never generates DUAL

cycle when the upper 32-bits of
address are zero.
A master that supports 64-bit addressing must

generate a SAC, instead of a DAC, when the
upper 32-bits of the address are zero. This allows
masters that generate 64-bit addresses to
communicate with 32-bit addressable targets via
SAC. The type of addressing (SAC or DAC)
depends on whether the address is in the low 4GB address range or not.
(*) Indicates check is not part of the Rev. 2.2 compliance list.
Target Checks
Table 13-4 lists the checks performed by the monitor submodule that verifies the operation of
the target.
Table 13-4. PCI Target Checks
Check ID and
Section Number
Violation
Description
TZ01
(*)
DEVSEL#, TRDY#, and

STOP# are never changed
when IUT is not involved
in the transaction.

407

Table 13-4. PCI Target Checks (cont.)
408
Check ID and
Section Number
Violation
Description
TZ02_1
IUT should not assert

DEVSEL# more than 5
clocks after FRAME# is
first sampled asserted.

analysis controls the pins. This check is active
when a Dual address cycle is being performed.
TZ02_2
IUT should not assert

DEVSEL# more than 4
clocks after FRAME# is
first sampled asserted.

when non-Dual address cycles are performed.
TZ03
(*)
FRAME# should not be

driven low if GNT# is not
sampled asserted at the
previous clock edge.

when non-Dual address cycles are performed.
TZ04
(*)
STOP# or TRDY# should

not be asserted by the target
before claiming the
transaction.

TZ05
(*)
STOP#, DEVSEL#, and

TRDY# should be deasserted at the same time.

TZ06
(*)
Bus protocol should not be

in an Unknown state.
Internal monitor state machine check.
TZ07
(2.2.8 and 3.8)
Timing and duration of

DEVSEL# and ACK64#
are identical if the target is
64-bit capable.
ACK64#, when asserted by the target, indicates

that the target is ready for 64-bit transactions.
ACK64# has the same timing as DEVSEL# when
asserted.
TZ08
(3.8)
ACK64# should not be

asserted if REQ64# is not
asserted during the address
phase.
ACK64#, when asserted by the target, indicates

that the target is ready for 64-bit transactions. The
master indicates its willingness to perform a 64bit transaction by asserting REQ64#. The target
should not assert ACK64# if REQ64# is not
asserted by the master.
TZ09
(*)
ACK64# should not be

asserted if it is not asserted
along with DEVSEL#.

TP02
IUT never reports PERR#

until it has claimed the
cycle and completed a data
phase.
PERR# is used to report Parity errors during all

transactions except Special cycles. The PERR#
must be driven active by the agent receiving data
(when enabled) two clocks following the data
when a parity error is detected, and for a
minimum duration of one clock for each data
phase that a parity error is detected, which means
PERR# cannot be asserted before the device
actually claims the transaction and completes a
data phase. This check is enabled if parameter
Parity_Error_Response is 1.


Check ID and
Section Number
Violation
Description
TP03
(3.1.1)
IUT never responds to

reserved commands.
"Reserved" command encodings are reserved for

future use. PCI targets must not alias reserved
commands to other commands, and targets must
not respond to reserved encodings.
TP05
(3.2.1)
Once IUT has asserted

TRDY#, it never changes
TRDY# until the data
phase completes.
Once a target has asserted TRDY# or STOP#, it

cannot change DEVSEL#, TRDY#, or STOP#
until the current data phase completes.
TP06
(3.2.1)

DEVSEL# until the data
phase completes.

TP07
(3.2.1)

STOP# until the data phase
completes.

TP08
(3.2.1)

STOP#, it never changes
STOP# until the data phase
completes.

TP09
(3.2.1)

TRDY# until the data
phase completes.

TP10
(3.2.1)

DEVSEL# until the data
phase completes.

TP14
(3.2.2)

reserved encodings.
All targets are required to check AD[1:0] during a

memory transaction. The reserved encodings
cannot be assigned any "new" meaning.
Therefore, IUTs should not respond to these
encodings.
TP15
(3.2.2.3.4)
IUT should ignore the

configuration command
unless IDSEL is asserted
and AD[1:0]=00.
Each device should assert DEVSEL# when a

configuration command is decoded; the devices
IDSEL is asserted and AD[1:0] is 00. Otherwise,
it should ignore the configuration command.
TP16
(3.2.2)
IUT always disconnects

after the first data phase
when the reserved burst
mode is detected.
All targets are required to check AD[1:0] during

memory command transactions and either
provide the requested burst order or terminate the
transaction with disconnect. The target is not
allowed to terminate the transaction with Retry.
TP17_1, TP17_2
(3.2.4)
The IUTs AD lines are

driven to stable values
during every address and
data phase.
All AD lines (including AD[63:32] when the

master supports a 64-bit data path) must be
driven to stable values during the 64-bit transfer
every address and data phase. Even byte lanes not
involved in the current data transfers must
physically drive stable data onto the bus.
409

410
Check ID and
Section Number
Violation
Description
TP19
(3.3.1)
IUT never asserts TRDY# A turnaround cycle is required to avoid

during the turnaround cycle contention. The first data phase on a read
on a read.
transaction requires a turnaround cycle, enforced
by the target by de-asserting TRDY#. Therefore,
TRDY# should not be asserted during turnaround
cycle, even if the target has asserted DEVSEL#.
TP20
(3.3.3.2.1)
IUT always de-asserts

TRDY#, STOP#, and
DEVSEL# the clock
following the completion
of the last data phase.
If not already de-asserted, TRDY#, STOP#, and

DEVSEL# must be de-asserted on the clock
following the completion of the last data phase
and must be tri-stated on the next clock. The
target must release control of all target signals.
TP22
(3.3.3.2.1)

STOP# the cycle
immediately following the
FRAME# being deasserted.
The last data phase of a transaction completes

when FRAME# is de-asserted, IRDY# is
asserted, and STOP (or TRDY#) is asserted. The
target must not assume any timing relationship
between the assertion of STOP# and the deassertion of FRAME#, but must keep STOP#
asserted until FRAME# is de-asserted and the last
data phase completes. STOP# must be deasserted on the clock following the completion
for the last data phase.
TP23
(3.3.3.2.1)
Once the IUT has asserted

STOP#, it never de-asserts
STOP# until the FRAME#
is negated.
The last data phase of a transaction completes

when FRAME# is de-asserted, IRDY# is
asserted, and STOP (or TRDY#) is asserted. The
target must not assume any timing relationship
between the assertion of STOP# and the deassertion of FRAME#, but must keep STOP#
asserted until FRAME# is de-asserted and the last
data phase completes. STOP# must be deasserted on the clock following the completion
for the last data phase.
TP24
(3.3.3.2.1)

TRDY# before signaling
target-abort.
To signal Target-Abort, TRDY# must be deasserted when DEVSEL# is de-asserted and

STOP# is asserted.
TP25
(3.3.3.2.1)
IUT never de-asserts

STOP# and continues the
transaction.
Once the target has asserted STOP#, it must keep

STOP# asserted until FRAME# is de-asserted,
whereupon it must de-assert STOP#.
TP26
IUT always completes

initial data phase within 16
clocks.
If a target is accessed during run-time (RST# has

been de-asserted greater then 2**25 clocks), it
must complete the initial data phase of a
transaction (read or write) within 16 clocks from
assertion of the FRAME#. The target completes
the initial data phase by asserting TRDY# (to
accept or provide the requested data) or by
terminating the request by asserting STOP#
within the target initial latency requirement.


Check ID and
Section Number
Violation
Description
TP28_1, TP28_2, TP28_3

(3.7.1)
IUT always issues

DEVSEL# is driven by the target of the current
DEVSEL# before any other transaction to indicate that it is responding to the
response.
transaction. DEVSEL# must be asserted with or
prior to the edge at which that target enables its
TRDY# and STOP#. DEVSEL# must be asserted
before or coincident with signaling any other
target response.
TP29
(3.6.1 and 3.3.3.2)

DEVSEL#, it never deasserts DEVSEL# until the
last data phase has
completed except to signal
target-abort.
Once DEVSEL# is asserted, it cannot be deasserted until the last data phase has completed,
except to signal Target-Abort. Target abort can
be signaled on any clock subsequent to the
assertion of DEVSEL#. Target-Abort is signaled
by de-asserting DEVSEL# and asserting STOP#
at the same time.
TP30
(3.6.2)

special cycles.
A Special Cycle command is like any other bus

command where there is an address phase and a
data phase. The command starts with the
assertion of FRAME# and completes like all
other commands when FRAME# and IRDY# are
de-asserted. The uniqueness of this command is
that no agent responds with the assertion of
DEVSEL#, and the transaction concludes with a
Master-Abort termination.
TP31_1, TP31_2
(3.7.1)
IUT always drives PAR

within one clock of
C/BE# and AD being
driven.
On any given bus phase, PAR (and PAR64) is

driven by the agent that drives AD and "lags" the
corresponding address or data by one clock.
TP32_1
(3.7.1)
IUT always drives PAR

such that the number of 1s
on AD[31:0], C/BE[3:0],
and PAR equals an even
number.

devices.
TP32_2
IUT always drives PAR64

such that the number of 1s
on AD[63:32], C/BE[7:4],
and PAR64 equals an even
number.

devices.
(*) Indicates check is supplemental to the Rev. 2.2 compliance list.
411

Top-level Monitor Checks

Table 13-5 lists the checks performed by the top-level monitor.
Table 13-5. PCI Top-Level Monitor Checks
Check ID and
Section Number
Violation
Description
IO10
(*)
PCI monitor in both Master and

Target mode.
Constrains formal analysis to exercise the

pins in accordance with the PCI protocol.
Failure to do so can cause the core to
malfunction when formal analysis controls
the pins. For simulation, this check can be
disabled by setting parameter Self_Config
to 1.
IO11
(*)
Master or Target transaction is

interrupted by reset.

to 1.
IO12
(*)
Input FRAME#, IRDY#, and

REQ64# signals should not be
toggled when DUT is in the
master mode.

to 1.
IO21
(*)
Outputs STOP# and TRDY# are

not enabled together.

to 1.
IO22
(*)
Outputs STOP# and DEVSEL#

are not enabled together.

to 1.
IO23
(3.4.1)
FRAME# should not be driven

low if GNT# is not asserted and
the bus is idle.
A PCI master is allowed to start a

transaction when its GNT# is asserted and
the bus is in Idle. Please refer to section
3.4.1 of the specification for details.
MP22
(3.4.3)
IUT always drives C/BE# and

AD within eight clocks of GNT#
assertion when the bus is idle.
When the arbiter asserts a masters GNT#

and the bus is in the Idle state, then that
master must enable its AD and C/BE#
output buffers within eight clocks. PCI
specifies this requirement for arbitration
parking. Please refer to section 3.4.3 of the
specification for details.
412

Table 13-5. PCI Top-Level Monitor Checks (cont.)

Check ID and
Section Number
Violation
Description
TP01_devsel,
TP01_trdy,
TP01_stop,
TP01_ack64MP01_frame,
MP01_irdy,
MP01_perr,
MP01_req64
(2.1)
All Sustained Tri-State signals

are driven high for one clock
before being tri-stated. (2.1)
Sustained Tri-State (s/t/s) is an active low

tri-state signal owned and driven by one and
only one agent at a time. The agent that
drives an s/t/s pin low must drive it high for
at least one clock before letting it float.
IO_pci_ack64_en_n
pci_ack64_en_n is undriven.
Checks that pci_ack64_en_n is both known

IO_pci_ad_en_n
pci_ad_en_n is undriven.
Checks that pci_ad_en_n is both known (not

IO_pci_cbe_en_n
pci_cbe_en_n is undriven.
Checks that pci_cbe_en_n is both known

IO_pci_devsel_en_n
pci_devsel_en_n is undriven.
Checks that pci_devsel_en_n is both known

IO_pci_frame_en_n
pci_frame_en_n is undriven.
Checks that pci_frame_en_n is both known

IO_pci_irdy_en_n
pci_irdy_en_n is undriven.
Checks that pci_irdy_en_n is both known

IO_pci_par64_en_n
pci_par64_en_n is undriven.
Checks that pci_par64_en_n is both known

IO_pci_par_en_n
pci_par_en_n is undriven.
Checks that pci_par_en_n is both known

IO_pci_perr_en_n
pci_perr_en_n is undriven.
Checks that pci_perr_en_n is both known

enabled only if Parity_Error_Response is 1.
IO_pci_req64_en_n
pci_req64_en_n is undriven.
Checks that pci_req64_en_n is both known

IO_pci_stop_en_n
pci_stop_en_n is undriven.
Checks that pci_stop_en_n is both known

IO_pci_trdy_en_n
pci_trdy_en_n is undriven.
Checks that pci_trdy_en_n is both known

(*) Indicates check is supplemental to the Rev. 2.2 compliance list.
413


The corner cases maintained by the PCI monitor are shown in Table 13-6. These corner cases
are collected separately on the master and target controllers.
Table 13-6. PCI Monitor Corner Cases
Corner Case
Description
Read Transfers
Write Transfers
Interrupt Acknowledge Cycles
Number of interrupt acknowledge cycles.
Special Cycles
Number of special cycles.
Reserved Cycles
Number of reserved cycles.
Dual Address Cycles
Number of dual address cycles.
Address States
Number of address states.
Dual Address States
Number of dual address states.
Address Fast Decodes
Number of address fast decodes.
Address Medium Decodes
Number of address medium decodes.
Address Slow Decodes
Number of address slow decodes.
Address Bridge Decodes
Number of address bridge decodes.
Retry States
Number of retry states.
Disconnect A/B States
Number of disconnect A/B states.
Disconnect C States
Number of disconnect C states.
Target Aborts
Number of target aborts.
Master Aborts
Number of master aborts.
Monitor Statistics
The statistics maintained by the PCI monitor are shown in Table 13-7. These statistics are
Table 13-7. PCI Monitor Statistics
414
Statistic
Description
Total Transfers
Total number of transfers.
Unknown Commands
Number of unknown commands.
Chapter 14
PCI Express
Introduction
PCI Express is a high-performance, general purpose I/O interconnect defined for a wide variety
of future computing and communication platforms. It is a high-speed point-to-point, highly
scalable, serial interconnect. The PCI Express link consists of two signal groups, a transmit and
a receive.
The PHY Interface for the PCI Express architecture (PIPE) is an extension to the PCI Express
protocol, which defines the interface between the MAC Layer and PHY Layer of a PCI Express
compatible device.
The QVL PCI Express monitor can be instantiated in a standard configuration for checking PCI
Express implementations. It also can be instantiated in a PIPE configuration for checking PHY
Interface for PCI Express implementations. The monitor works in both Gen1 and Gen2 mode
and can be instantiated separately in both mode.
This PCI Express monitor is modeled from the requirements provided in the following
document:
PCI Express Base Specification, Revision 1.1, March 28, 2005.
PCI Express Base Specification, Revision 2.0, December 20, 2006.
PHY Interface for the PCI Express Architecture, Version 1.0, June 19, 2003.
PHY Interface for the PCI Express Architecture, Draft Version 1.87, September 28,
2006.
Supported Features
Lane Widths
Monitor supports lane widths of x1, x2, x4, x8, x12, x16, x32.
Packet Types
Monitor tracks transaction layer packet (TLP), data link layer packet (DLLP) and
physical layer packet (PLP) for proper encoding of various fields of the packets.
415
PCI Express
Supported Features
Monitor tracks the sequence number generated by the data link layer.
Monitor tracks address translation (AT) field of TLP packet in Gen2 mode.
Transaction Types
Monitor tracks all types of transactions, namely Memory, I/O, Configuration, and
Message.
The monitor tracks configuration transaction rules.
The monitor treats trusted configuration request as deprecated request in Gen2 mode.
The monitor tracks ACS violation rule for memory request.
Data Integrity
Monitor supports data integrity checking for DLL packets (16-bit CRC).
Monitor supports data integrity checking for TL packets (32-bit LCRC).
Monitor supports end to end data integrity checking for TL packets (32-bit ECRC).
Flow Control
Monitor tracks the flow control initialization mechanism.
Monitor tracks receive buffer flow control.
Monitor supports multiple Virtual Channels (VCs).
Link Training and Initialization
416
Monitor supports Link training and Initialization sequence in both Gen1 and Gen2
mode.
Monitor tracks the Training sequence ordered sets (TS1 and TS2).
Monitor tracks the Fast training sequences.
Monitor tracks the Electrical Idle Exit sequences in Gen2 mode.
Monitor tracks EIE symbol before FTS in L0s.
Monitor tracks the Compliance pattern.
Monitor tracks modified compliance pattern in Gen2 mode.
Monitor supports Lane polarity inversion.
Monitor supports Lane reversal.
Monitor supports speed change in Polling Compliance in Gen2 mode.
PCI Express
Supported Features
Monitor tracks data rate and upconfigurabilty record in configuration complete state in
Gen2 mode.
Monitor tracks all scenarios of speed change in recovery in Gen2 mode.
Monitor supports speed change through L1 in Gen2 mode.
Monitor supports link width change in Gen2 mode.
Power Management
Monitor tracks power management protocol.
Lane-to-Lane Deskew
Monitor supports multilane deskew on the receive interface. The deskew must be in the order of
multiple of symbol times.
Skew on Transmit Lanes

Monitor supports skew on transmit lanes.
Clock Tolerance Compensation

Monitor tracks the skip ordered sets, which must be transmitted or received at regular intervals.
Implementations
Monitor can be instantiated in any of the following implementations:
Root complex.
Device or the component that is the root of an I/O hierarchy.
Switch.
Device or component that is a logical assembly of multiple virtual PCI-to-PCI bridge
device.
End points.
Device that can be a requestor or completer of PCI Express transaction. End points are
classified as either legacy or PCI Express end points.
PCI Express PCI bridge.

Device that has one PCI Express port and one or multiple PCI/PCI-X bus interfaces.
PIPE
The monitor supports 8-bit and 16-bit PIPE.
417
PCI Express
This monitor does not track transaction ordering rules.
The monitor does not support FLR in Gen2 mode.
The monitor does not support all ACS violation scenarios.

Standard Monitor
To use the QVL PCI Express monitor, place an instance of the monitor inside the Root complex
(RC) device, PCI Express end point, Legacy end point, Upstream port of the PCI Express
switch, or Downstream port of the PCI Express switch as shown in Figure 14-1 on page 419.
The PCI Express monitor can be instantiated in either serial mode or parallel mode. If the
implementation under test does not include a serializer/deserializer block, then the PCI Express
monitor has to be configured to parallel mode (symbol mode) while instantiating. If the
implementation under test does include a serializer/deserializer block, then the monitor has to
be configured to serial mode while instantiating. In either of the modes, the input to the monitor
should be 10B encoded values. The user can include the instances of PCI Express monitor in a
checker control file. The term transmitter refers to the PCI Express interface signals that are
outputs from the implementation. The term receiver refers to the PCI Express interface signals
that are inputs to the implementation. The term upstream refers to the interface which is nearest
to the Root complex (RC). The term downstream refers to the interface that is farthest from the
Root complex (RC).
The PCI Express monitor can be instantiated in either Gen1 mode or Gen2 mode. In Gen1 mode
monitor is compatible with PCI Express Base Specification 1.1. In this mode all Gen2 features
are disabled. In Gen2 mode monitor is compatible with PCI Express Base Specification 2.0. In
this mode, all Gen1 features which are not part of 2.0 specification are disabled. The monitor is
having two separate top file for Gen1 and Gen2. This allows two monitors to be instantiated in
an environment where both Gen1 and Gen2 buses are present.
418
PCI Express
Figure 14-1. PCI Express Gen1 Monitor Implementation

PCI Express Device
PCI Express Monitor
reset
areset
Rx_interface
Tx_interface
rx_symbols_plus
rx_symbols_minus
rx_clk
tx_symbols_plus
tx_symbols_minus
tx_clk
skip_link_training
extended_sync_enable
device_control_register
device_capabilities_register
phy_layer_checks_disable
link_layer_checks_disable
transaction_layer_checks_disable
L0s_entry_supported
enable_vc_id
tc_mapped_to_vc_id_0
419
PCI Express
Figure 14-2. PCI Express Gen2 Monitor Implementation

PCI Express Device
PCI Express Monitor
reset
areset
Rx_interface
Tx_interface
420
rx_symbols_plus
rx_symbols_minus
rx_clk
tx_symbols_plus
tx_symbols_minus
tx_clk
skip_link_training
L0s_entry_supported
acs_translation_blocking_enable
disable_cpl_timeout
enable_vc_id
PCI Express
Connect the PCI Express monitor pins as specified in the pin-out Table 14-1 and illustrated in
Figure 14-3.
Figure 14-3. PCI Express Monitor Pin Diagram
PCI Express Monitor
reset
areset
rx_symbols_plus
rx_symbols_minus
rx_clk
Receiver
tx_symbols_plus
tx_symbols_minus
tx_clk
Transmitter
skip_link_training
L0s_entry_supported
disable_cpl_timeout
enable_vc_id
Table 14-1. PCI Express Monitor Pins

Pin
Description
areset
Asynchronous reset, active high. This is not a part of the PCI Express interface.
(32 bits)
Device capabilities register offset 04h. If this configuration data is not

available, then wire 32'h5 to this port in which case the monitor can be
configured for all possible values of Max_Payload_Size (configured through
device_control_register) (Connectivity Note 6).
(16 bits)
Device control register offset 08h. If this configuration data is not available,
then wire 16'b0 to this port in which case the monitor is configured for a 5-bit
tag field and maximum payload size of 128-bytes (Connectivity Note 1).
enable_vc_id [7:0]
Bit positions of this input correspond to virtual channel numbers. Set the bit
corresponding to the virtual channel number supported in the design, along
with the VC_SUPPORT parameter and the tc_mapped_to_vc_id_n inputs.
This input can be left unconnected if the parameter VC_SUPPORT is 0 or 1.
Extended sync bit of Link Control Register offset 10h. When set, configures
the monitor to track maximum of 4096 FTS sequences. By default, the monitor
tracks 255 FTS sequences.
L0s_entry_supported
When set, indicates that the entry in to L0s ASPM state is supported.
421
PCI Express
Table 14-1. PCI Express Monitor Pins (cont.)

Pin
Description
When set, disables all the data link layer checks performed by the monitor.
When set, disables all the physical layer checks performed by the monitor.
reset
Synchronous reset, active high. This is not a part of the PCI Express interface.
rx_clk
Receive clock. This clock is used by the receiver to sample the symbols on the
lane. The clock is active on the posedge or on both edges based on the mode of
operation.
rx_symbols_minus
Inputs to the PCI Express device. In serial mode of operation, this should be
connected to the D- inputs of the device.
rx_symbols_plus
Inputs to the PCI Express device. In serial mode of operation, this should be
connected to D+ inputs of the device. In symbol mode of operation, this should
be connected to 10B encoded symbols.
skip_link_training
When set, link width negotiation is not tracked and the operating link width is
set to maximum link width for which the monitor is configured. Wire this port
to 1'b0 if link width negotiation needs to be tracked. The default link training
state of the monitor is POLLING. Monitor does not perform any receiver
detection. When link training and width negotiation is not tracked, the monitor
expects few TS1/TS2 ordered sets to be in sync and to register the n_fts values.
tc_mapped_to_vc_id_0 [7:0]
Configures the TCs mapped to VC0. Bit locations within this field corresponds
to TC values.
to TC values.
to TC values.
to TC values.
to TC values.
to TC values.
to TC values.
to TC values.
transaction_layer_checks_
disable
When set, disables all the transaction layer checks performed by the monitor.
tx_clk
Transmit clock. This clock is used by the transmitter to drive the symbols on
the lane. The clock is active on the posedge or on both edges based on the
mode of operation.
tx_symbols_minus
Outputs from the PCI Express device. In serial mode of operation, this should
be connected to the D- outputs of the device.
422
PCI Express
Table 14-1. PCI Express Monitor Pins (cont.)

Pin
Description
tx_symbols_plus
Outputs from the PCI Express device. In serial mode of operation, this should
be connected to D+ outputs of the device. In symbol mode of operation, this
should be connected to the 10B encoded symbols.
When set, enables the acs translation blocking enable bit in configuration
space. This bit is applicable for Gen2 mode.
disable_cpl_timeout
When set, disables the completion timeout mechanism of monitor. this bit is
applicable for Gen2 mode.
Connectivity Notes
1. Implementation under tests device control configuration register must be connected to
the monitor. The monitor is reconfigured depending on the value in
device_control_register. If this configuration data is not available, then pass 16'b0
to this port. The monitor requires Max_Payload_Size
(device_control_register[7:5]), Max_Read_Request_Size
(device_control_register[14:12]), and Extended_Tag_Field_Enable
(device_control_register[8]) fields of this register.
The encoding for the Max_Payload_Size and Max_Read_Request_Size fields is as
follows:
000b
001b
010b
011b
100b
101b
110b
111b
128 Bytes
256 Bytes
512 Bytes
1024 Bytes
2048 Bytes
4096 Bytes
Reserved
Reserved
When the Extended_Tag_Field_Enable bit is set, an 8-bit tag field is used. If the bit
is cleared, then a 5-bit tag field is used.
2. In symbol mode of operation, the encoded 10B symbols should be connected to the
monitor as shown below.
tx_symbols_plus [9:0] = {j,h,g,f,i,e,d,c,b,a}
where bit a is the LSB of the symbol and bit j is the MSB of the symbol.
3. The reset and areset inputs are not part of the PCI Express interface. Connect
reset/areset of the implementation under test (IUT) to the monitor. The
reset/areset must be asserted for at least one clock during initial time before the link
training starts.
4. When the skip_link_training option is set, the monitor expects a few TS-ordered
sets to be transmitted and received to be in sync and to register the n_FTS values.
423
PCI Express
5. The tc_mapped_to_vc_id_n ports can be left unconnected if the configuration

parameter VC_SUPPORT is 0 or 1.
6. Implementation under tests device capabilities register must be connected to the
monitor. The device capabilities register indicates the permissible values allowed for
Max_Payload_Size in the device control register. If this configuration data is not
available, then pass 32'h5 to this port. This allows all possible values for
Max_Payload_Size in the device control register.
Monitor Parameters
The parameters shown in Table 14-2 configure the PCI Express monitor.
Table 14-2. PCI Express Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode

2.
PCI_EXPRESS_DEVICE_
TYPE
Configures the monitor to track various types of

devices. Set this parameter as follows:
0 to track PCI Express end point
1 to track legacy end point
4 to track root complex
5 to track upstream port of a switch
6 to track downstream port of a switch
7 to track PCI Express / PCI-X bridge
By default, the monitor is instantiated in a PCI
Express end point.
3.
INTERFACE_TYPE
Configures the monitor to either serial or parallel

mode. Set this parameter to 1 if the monitor is
instantiated on a parallel (symbol) interface. By
default, the monitor is instantiated on a serial
interface.
4.
MAX_LINK_WIDTH
Set this parameter equal to the maximum lane width

of the device in which the monitor is instantiated. The
link widths supported are x1, x2, x4, x8, x12, x16, and
x32. By default, this is set to 1.
5.
DOUBLE_DATA_RATE
Specifies the active edge of the tx_clk/rx_clk clocks.

Set this parameter to 1 if both edges of tx_clk/rx_clk
clocks are active. Set this parameter to 0 if
tx_clk/rx_clk is active on only rising edge. By default,
tx_clk/rx_clk is active on only the rising edge.
6.
MAX_REQUESTS_ADDR_
WIDTH
Configures the maximum number of outstanding

requests that the monitor should handle. The
maximum number of outstanding requests is
2^(MAX_REQUESTS_ADDR_WIDTH). By default,
maximum of 32 outstanding requests are allowed.
424
PCI Express
Table 14-2. PCI Express Monitor Parameters (cont.)

Order Parameter
Default Description
7.
ELECTRICAL_IDLE_VAL
Specifies the value of the encoded 10B symbol during

electrical idle conditions. This parameter is applicable
only when INTERFACE_TYPE is set to 1 (symbol
mode of operation). In serial mode of operation, the
monitor detects electrical idle when both D+ and Dinputs are driven to the same level.
8.
RESERVED_FIELD_
CHECK_ENABLE
Configures the monitor to track the reserved field of

the transaction layer packets (TLPs), Data link layer
packets, and other reserved fields. Set this parameter
to 1 if the monitor has to track for any nonzero value
in the reserved fields. By default, the monitor tracks
for nonzero value in the reserved field.
9.
VENDOR_SPECIFIC_
ENCODING_ENABLE
Configures the monitor to track for vendor specific

codes in the TLP or DLLP packets. Set this parameter
to 1 if vendor specific codes are allowed in TLP and
DLLP packets. By default, vendor specific codes are
not allowed in DLLP and TLP packets.
10.
OVERRIDE_TIMER_VALUE
Allows to override the timer values. Set this

parameter to 1 to override the timer values. By
default, the monitor computes the timer values based
on maximum payload size and operating link width.
11.
REPLAY_TIMER_VALUE
711
Configures the counts time since the last Ack or Nak

DLL packet is received. By default, the monitor
computes the REPLY TIMER value based on the
maximum pay load size and link operating width.
This parameter is active if parameter
OVERRIDE_TIMER_VALUE is set.
12.
ACKNAK_TIMER_VALUE
237
Configures the ACKNAK_TIMER. By default, the

monitor computes the ACKNAK_TIMER value
based on maximum pay load size and link operating
width. This parameter is active if the parameter
OVERRIDE_TIMER_VALUE is set.
13.
MIN_TS1_COUNT
1024
Configures the minimum number of TS1 ordered sets

that must be transmitted by the device before
transitioning in to Polling.Configuration state from
Polling.Active state. By default, at least 1024 TS1
ordered sets must be transmitted.
14.
DESKEW_SUPPORT
Configures the monitor for lane-to-lane deskew

support on the receive interface. Set this parameter to
1 to enable multilane deskew. By default, multilane
deskew is not supported. Maximum allowed skew
across all lanes is 5 symbols.
425
PCI Express
Table 14-2. PCI Express Monitor Parameters (cont.)

Order Parameter
Default Description
15.
VC_SUPPORT
Configures the monitor to support multiple VCs. By

default, the monitor supports only VC0 and all the
TCs are mapped to VC0. Set this parameter to 1 when
all the VCs are supported and 1-to-1 TC/VC mapping
(TC0/VC0, TC1/VC1) is required. Set this parameter
to 2 when any other mapping is required. When set to
2, TC/VC mapping should be configured through the
monitor input ports. When this parameter is set to 0 or
1, input ports enable_vc_id and
tc_mapped_to_vc_id_n can be left unconnected.
16.
HOT_PLUG_MESSAGE_
ENABLE
Configures the monitor to support Hot plug signaling

messages. By default, Hot plug signaling messages
are not allowed.
For Gen2, this parameter has no effect.
17.
TX_SKEW_SUPPORT
Configures the monitor for supporting skew on the

transmit lanes. Set this parameter to 1 to allow skew
on transmit lanes. By default, skew on transmit lanes
is not supported.
18.
ENABLE_DATA_PLUS_
MINUS_CHECK
Configures the monitor to check the logic levels on

D+ and D- inputs of the monitor when the monitor is
configured for the serial mode of operation. By
default, the monitor does not perform this check.
19
CPL_TIMEOUT_CLK
30000
Configures the completion timeout value. The value

indicates in terms of the number of clocks.This
parameter is applicable for Gen2 mode.
20
UPDATE_FC_30US_TIMER_
CLK
75000
/7500
Configures the update FC frequency in terms of the

number of clocks. Default value is 75000 for
INTERFACE_TYPE=0(Serial mode) and 7500 for
INTERFACE_TYPE=1(Parallel mode). If
extended_sync_enable is set, then this parameter is
multiplied by 4 internally to make 30 us to 120 us.
Following are the notes:

2. The width of ports tx_symbols_plus, tx_symbols_minus, rx_symbols_plus, and
rx_symbols_minus is N bits (N is the number of lanes on the link, MAX_LINK_WIDTH) if
the monitor is configured to track the serial interface of a multiple lane link. The width is
10 x N bits if the monitor is configured to track the symbol interface of a multiple lane
link. The allowed values of N are 1, 2, 4, 8, 12, 16, and 32.
Example: The link width is 8-bits if the monitor is configured to track the serial interface
and 80-bits if the monitor is configured to track the symbol interface for N=8 (i.e., x8
link). When the monitor is configured to track a symbol interface, 10b symbols of all
lanes should be concatenated and then connected to these ports as follows:
tx_symbols_plus = {lane7,lane6,lane5,lane4,lane3,lane2,lane1,lane0}
426
PCI Express
3. Parameter ELECTRICAL_IDLE_VAL is applicable in symbol mode of operation only.

This parameter specifies the value on the symbols when electrical idle condition exists
on the bus.
4. TC/VC mapping information is available in the VC resource control register of the
design under test. For example, if the design supports VC IDs 0, 1, 2, 3 (TC0 and TC1
are mapped to VC0; TC2 and TC3 are mapped to VC1; TC4 and TC5 are mapped to
VC2; and TC6 and TC7 are mapped to VC3), then the monitor can be configured with
the following:
set VC_SUPPORT parameter to 2
enable_vc_id = 8'b 0000_1111;
tc_mapped_to_vc_id_0 = 8'b 0000_0011;
Example 1
Example 14-1 instantiates a PCI Express monitor within a PCI Express end point device. The
input to the device is serial 10B symbols. The maximum link width is set to 1. Reserved-bit
field checking is disabled. The maximum number of requests that can be outstanding is 32. The
device uses a 5-bit tag field. The maximum pay load size and maximum read request size are set
to 128 bytes. The example supports only VC0.
Example 14-1. PCI Express Monitor Instantiation Example 1
qvl_pci_express_monitor
0,
/* PCI_EXPRESS_DEVICE_TYPE */
0,
0,
/* MAX_LINK_WIDTH */
1,
/* DOUBLE_DATA_RATE */
0,
/* MAX_REQUESTS_ADDR_WIDTH */
5,
/* ELECTRICAL_IDLE_VAL */
0,
/* RESERVED_FIELD_CHECK_ENABLE */
0,
/* VENDOR_SPECIFIC_ENCOING_ENABLE */0)
MONITOR_END_POINT(
.areset
(areset),
.reset
(reset),
.tx_clk
(tx_clk),
.tx_symbols_plus
(tx_data_plus),
.tx_symbols_minus
(tx_data_minus),
.rx_clk
(rx_clk),
.rx_symbols_plus
(rx_data_plus),
.rx_symbols_minus
(rx_data_minus),
.skip_link_training
(1'b0),
.extended_sync_enable
(1'b0),
.device_control_register
(16'b0),
427
PCI Express
.device_capabilities_register
.phy_layer_checks_disable
.link_layer_checks_disable
.transaction_layer_checks_disable
(32'h5),
(1'b0),
(1'b0),
(1'b0) );
Example 2
Example 14-2 instantiates a PCI Express monitor within a Legacy end point device. The input
to the device is parallel 10B symbols. The maximum link width is set to 8. The clocks are active
on both the edges. Reserved-bit field checking is disabled. The maximum number of requests
that can be outstanding is 32. The device uses a 5-bit tag field. The maximum pay load size and
maximum read request size are set to 128 bytes. The maximum number of FTS sequences is set
to 4096. This example supports only VC0.
Example 14-2. PCI Express Monitor Instantiation Example 2
qvl_pci_express_monitor
0,
1,
1,
8,
1,
5,
0,
/* RESRVED_FIELD_CHECK_ENABLE */
0,
MONITOR_END_POINT(
.areset
(areset),
.reset
(reset),
.tx_clk
(tx_clk),
.tx_symbols_plus
(tx_data),
.tx_symbols_minus
(tx_data),
.rx_clk
(rx_clk),
.rx_symbols_plus
(rx_data),
.rx_symbols_minus
(rx_data),
.skip_link_training
(1'b0),
(1'b1),
(16'b0),
(32'h5),
(1'b0),
(1'b0),
.transaction_layer_checks_disable(1'b0));
Example 3
Example 14-3 instantiates a PCI Express Gen2 monitor within a Root Complex device. The
input to the device is parallel 10B symbols. The maximum link width is set to 16. The clocks are
active on both the edges. Reserved-bit field checking is enabled. The maximum number of
requests that can be outstanding is 32. The device uses a 5-bit tag field. The maximum pay load
size and maximum read request size are set to 128 bytes. The maximum number of FTS
428
PCI Express
sequences is set to 4096. This example supports only VC0. Completion timeout value is 40000
clk.
Example 14-3. PCI Express Gen2 Monitor Instantiation Example 3
qvl_pci_express_gen2_monitor
0,
4,
1,
16,
1,
5,
0,
/* RESRVED_FIELD_CHECK_ENABLE */
1,
/* VENDOR_SPECIFIC_ENCOING_ENABLE */0,
/* OVERRIDE_TIMER_VALUE */
0,
/* REPLAY_TIMER_VALUE */
711,
/* ACK_NAK_TIMER_VALUE */
237,
/* MIN_TS1_COUNT */
16,
/* DESKEW_SUPPORT */
0,
/* VC_SUPPORT */
0,
/* HOT_PLUG_MESSAGE_ENABLE */
0,
/* TX_SKEW_SUPPORT */
0,
/* ENABLE_DATA_PLUS_MINUS_CHECK */ 0,
/* CPL_TIMEOUT_CLK */
40000)
MONITOR_ROOT_COMPLEX(
.areset
(areset),
.reset
(reset),
.tx_clk
(tx_clk),
.tx_symbols_plus
(tx_data),
.tx_symbols_minus
(tx_data),
.rx_clk
(rx_clk),
.rx_symbols_plus
(rx_data),
.rx_symbols_minus
(rx_data),
.acs_translation_blocking_enable (1b0),
.disable_cpl_timeout
(1b0),
.skip_link_training
(1'b0),
(1'b1),
(16'b0),
(32'h5),
(1'b0),
(1'b0),
.transaction_layer_checks_disable(1'b0));
PIPE Configuration
To use the QVL PIPE monitor, place an instance of the monitor inside the PHY Layer or MAC
Layer of a root complex (RC) device, a PCI Express end point, a legacy end point, an upstream
port of the PCI Express switch or a downstream port of the PCI Express switch as shown in
Figure 14-4 on page 430.
The PIPE monitor can be instantiated in either 8-bit mode or 16-bit mode. You can include
instances of a PIPE monitor in a checker control file. The term upstream refers to an interface
429
PCI Express
nearer to the root complex (RC). The term downstream refers to an interface farther from the
root complex (RC).
The PIPE monitor can be instantiated in either Gen1 mode or Gen2 mode. In Gen1 mode
monitor is compatible with PCI Express Base Specification 1.1. In this mode all Gen2 features
are disabled. In Gen2 mode monitor is compatible with PCI Express Base Specification 2.0. In
this mode, all Gen1 features which are not part of 2.0 specification are disabled. The monitor is
having two separate top file for Gen1 and Gen2. This allows two PIPE monitors to be
instantiated in an environment where both Gen1 and Gen2 buses are present.
Figure 14-4. Gen1 PIPE Monitor Implementation
PHY/MAC Interface
TxData 16 or 8 bits
PHY Layer Device
MAC Layer Device

TxDataK 2 or 1 bit
Command 7 bits
PIPE
Monitor
16 or 8 bits RxData
PIPE
Monitor
2 or 1 bit RxDataK
6 Bits Status
PCLK
Figure 14-5. Gen2 PIPE Monitor Implementation

PHY/MAC Interface
TxData 16 or 8 bits
PHY Layer Device
MAC Layer Device

TxDataK 2 or 1 bit
Command 7 bits
PIPE
Monitor
16 or 8 bits RxData
PIPE
Monitor
2 or 1 bit RxDataK
12 Bits Status
PCLK
430
PCI Express
Monitor Connectivity (PIPE)

Connect the PIPE monitor pins as specified in the pin-out Table 14-3 and illustrated in
Figure 14-6.
Figure 14-6. PIPE Monitor Pin Diagram
pclk
reset_n
areset_n
tx_data
tx_data_k
tx_detect_rx_looopback
tx_elecidle
tx_compliance
rx_polarity
power_down
rate
tx_margin
tx_deemph
tx_swing
rx_data
rx_data_k
rx_valid
rx_elecidle
rx_status
phystatus
PIPE
Monitor
disable_descrambler
skip_link_training
L0s_entry_supported
disable_cpl_timeout
enable_vc_id
Table 14-3. PIPE Monitor Pins

Pin
Description
areset_n
Asynchronous reset. Active low.
(32 bits)
Device capabilities register offset 04h. If this configuration data is not

available, then wire 32'h5 to this port in which case the monitor can be
configured for all possible values of Max_Payload_Size (configured through
device_control_register) (Connectivity Note 6).
(16 bits)
Device control register - offset 08h. If this configuration data is not available,
then wire 16'b0 to this port in which case the monitor is configured for a 5-bit
tag field and maximum pay load and maximum read request size of 128 bytes
(Connectivity Note 1).
disable_descrambler
When set, the monitor does not descramble the data.
enable_vc_id [7:0]
Bit positions of this input corresponds to virtual channel numbers. Set the bit
corresponding to the virtual channel number supported in the design along
with the VC_SUPPORT parameter and tc_mapped_to_vc_id_x inputs. This
input can be left unconnected if parameter VC_SUPPORT = 0 or 1.
431
PCI Express
Table 14-3. PIPE Monitor Pins (cont.)

Pin
Description
Extended sync bit of Link Control Register - offset 10h. When set, configures
the monitor to track maximum of 4096 FTS sequences. By default, the monitor
tracks 255 FTS sequences.
L0s_entry_supported
When set, indicates that the entry in to L0s ASPM state is supported.
When set, disables all the data link layer checks performed by the monitor.
pclk
Clock output from the PHY layer device. The data on the PIPE interface is
synchronous to this clock. The clock operates at 125 Mhz for the 16-bit
interface and 250 Mhz for the 8-bit interface.
When set, disables all the physical layer checks performed by the monitor.
phystatus
Output from the PHY Layer device. Indicates the completion of several PHY
functions such as power management state transition, receiver detection, etc.
power_down
Input to the PHY Layer device. Indicates when to power down or power up the
transceiver.
reset_n
Synchronous reset. Active low.
rx_data
Parallel PCI Express data output from the PHY layer device. The data bus
width can be 8-bits or 16-bits based on the mode of operation.
rx_data_k
Data/Control output for the symbols on rx_data bus. The width of this output is
1-bit if rx_data is 8-bits wide and 2-bits if rx_data output is 16-bits wide.
rx_elecidle
Output from the PHY Layer device. Indicates that the receiver has detected
electrical idle.
rx_polarity
Input to the PHY Layer device. Indicates when to do a polarity inversion on

the received data.
rx_status
Output from the PHY Layer device. Encodes the receiver status and error.
rx_valid
Output from the PHY Layer device. Indicates symbol_lock and valid data on
rx_data and rx_data_k.
skip_link_training
When set, link width negotiation is not tracked and the operating link width is
set to the maximum link width for which the monitor is configured. Wire this
port to 1'b0 if the link width negotiation needs to be tracked. The default link
training state of the monitor is POLLING. Monitor does not perform any
receiver detection. When link training and width negotiation is not tracked, the
monitor expects few TS1/TS2 ordered sets to be in sync and to register n_FTS.
to TC values.
to TC values.
to TC values.
to TC values.
to TC values.
432
PCI Express
Table 14-3. PIPE Monitor Pins (cont.)

Pin
Description
to TC values.
to TC values.
to TC values.
When set, enables the acs translation blocking enable bit in the configuration
space. This bit is applicable for Gen2 mode.
disable_cpl_timeout
When set, disables the completion timeout mechanism of monitor. This bit is
transaction_layer_checks_
disable
When set, disables all the transaction layer checks performed by the monitor.
tx_compliance
Input to the PHY Layer device. Indicates when to drive compliance pattern.
tx_data
Parallel PCI Express data input to the PHY layer device. The data bus width
can be 8-bits or 16-bits based on the mode of operation.
tx_data_k
Data/Control input for the symbols on tx_data bus. The width of this input is
1-bit if tx_data input is 8-bits wide and 2-bits if tx_data input is 16-bits wide.
tx_detect_rx_loopback
Input to the PHY Layer device that indicates when to start receiver detection or
loopback.
tx_elecidle
Input to the PHY Layer device. Indicates when to drive electrical idle.
rate
Input to PHY Layer device indicates current speed of operation. This bit is
tx_margin
Input to PHY Layer device. Indicates transmitter voltage level. This bit is
tx_deemph
Input to PHY Layer device. Indicates transmitter de-emphasis. This bit is

tx_swing
Input to PHY Layer device. Indicates transmitter voltage swing level. This bit
is applicable for Gen2 mode.
Connectivity Notes (PIPE)

1. Implementation under the tests device control configuration register must be connected
to the monitor. The monitor is reconfigured depending on the value in
device_control_register. If this configuration data is not available, then pass 16'b0
to this port. The monitor requires Max_Payload_Size
(device_control_register[7:5]), Max_Read_Request_Size
(device_control_register[14:12]), and Extended_Tag_Field_Enable
(device_control_register[8]) fields of this register.
433
PCI Express
The encoding for the Max_Payload_Size and Max_Read_Request_Size fields is as

follows:
000b
001b
010b
011b
100b
101b
110b
111b
128 Bytes
256 Bytes
512 Bytes
1024 Bytes
2048 Bytes
4096 Bytes
Reserved
Reserved
When the Extended_Tag_Field_Enable bit is set, an 8-bit tag field is used. If the bit
is cleared, then a 5-bit tag field is used.
2. The reset_n and areset_n inputs are not part of the PCI Express interface. Connect
reset_n/areset_n or RESET# of the implementation under test (IUT) to the monitor.
The reset_n/areset_n must be asserted for at least one clock during initial time
before the link training starts.
3. When the skip_link_training option is set, the monitor expects a few TS-ordered
sets to be transmitted and received to be in sync and to register the n_FTS values.
4. The tc_mapped_to_vc_id_n ports can be left unconnected if the configuration
parameter VC_SUPPORT is 0 or 1.
5. 9-Bit Interface Mode:
The widths of ports tx_elecidle, tx_compliance, rx_polarity, rx_valid,

rx_elecidle, and rx_status depend on the number of lanes in a multilane PIPE
(set by MAX_LINK_WIDTH).
If 8b data are not scrambled, then connect port disable_descrambler to 1'b1.
Connect tx_elecidle and rx_elecidle so that port bits are asserted when
electrical idle is detected on Tx/Rx.
Connect tx_data and rx_data ports as follows:

{lane_n,..., lane_1, lane_0}
Connect tx_data_k and rx_data_k ports as follows:

{lane_n_control,..., lane_1_control, lane_0_control}
You can assert rx_valid port bits whenever valid 8b data are received.
6. Implementation under tests device capabilities register must be connected to the

monitor. The device capabilities register indicates the permissible values allowed for
Max_Payload_Size in the device control register. If this configuration data is not
available, then pass 32'h5 to this port. This allows all possible values for
Max_Payload_Size in the device control register.
434
PCI Express
Monitor Parameters (PIPE)

The parameters shown in Table 14-6 configure the PIPE monitor.
Table 14-4. PIPE Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode

2.
PCI_EXPRESS_DEVICE_
TYPE
Configures the monitor to track various types of

devices. Set this parameter as follows:
0 to track PCI Express end point
1 to track legacy end point
4 to track root complex
5 to track upstream port of a switch
6 to track downstream port of a switch
7 to track PCI Express / PCI-X bridge
By default, monitor is instantiated in a PCI Express
end point.
3.
MAC_LAYER_SIDE

the PHY Layer side of the PIPE interface. By default,
the monitor is instantiated on the MAC Layer side of
the PIPE interface.
4.
INTERFACE_TYPE
Configures the monitor to either 8-bit or 16-bit mode.

a 16-bit PIPE interface. By default, the monitor is
instantiated on a 8-bit PIPE interface.
5.
MAX_LINK_WIDTH
Set this parameter equal to the maximum number of

lanes supported by the device in which the monitor is
instantiated. The number of lanes supported are x1,
x2, x4, x8, x12, x16, and x32. By default, this
6.
MAX_REQUESTS_ADDR_
WIDTH
Configures the maximum number of outstanding

requests that the monitor should handle. The
maximum number of outstanding requests is
2^(MAX_REQUESTS_ADDR_WIDTH). By default,
a maximum of 32 outstanding requests are allowed.
7.
RESERVED_FIELD_
CHECK_ENABLE
Configures the monitor to track the reserved field of

the transaction layer packets (TLPs), Data link layer
packets, and other reserved fields. Set this parameter
to 1 if the monitor has to track for any nonzero value
in the reserved fields. By default, the monitor tracks
for nonzero value in the reserved field.
8.
VENDOR_SPECIFIC_
ENCODING_ENABLE
Configures the monitor to track for vendor specific

codes in the TLP or DLLP packets. Set this parameter
to 1 if the vendor specific codes are allowed in TLP
and DLLP packets. By default, vendor specific codes
are not allowed in DLLP and TLP packets.
435
PCI Express
Table 14-4. PIPE Monitor Parameters (cont.)
436
Order Parameter
Default Description
9.
OVERRIDE_TIMER_VALUE
Allows to override the timer values. Set this

parameter to 1 to override the timer values. By
default, the monitor computes the timer values based
on maximum payload size and operating link width.
10.
REPLAY_TIMER_VALUE
711
Configures the counts time since last the Ack or Nak

DLL packet is received. By default, the monitor
computes the REPLY TIMER value based on the
maximum pay load size and link operating width.
This parameter is active if the
OVERRIDE_TIMER_VALUE parameter is set.
11.
ACKNAK_TIMER_VALUE
237
Configures the ACKNAK_TIMER. By default, the

monitor computes the ACKNAK_TIMER value
based on the maximum pay load size and link
operating width. This parameter is active if the
OVERRIDE_TIMER_VALUE parameter is set.
12.
MIN_TS1_COUNT
1024
Configures the minimum number of TS1 ordered sets

that must be transmitted by the device before
transitioning in to Polling.Configuration state from
Polling.Active state. By default, at least 1024 TS1
ordered sets must be transmitted.
13.
DESKEW_SUPPORT
Configures the monitor for lane-to-lane deskew

support on the receive interface. Set this parameter to
1 to enable multilane deskew. By default, multilane
deskew is not supported. Maximum allowed skew
across all lanes is 5 symbols.
14.
VC_SUPPORT
Configures the monitor to support multiple VCs. By

default, the monitor supports only VC0 and all the
TCs are mapped to VC0. Set this parameter to 1 when
all the VCs are supported and 1-to-1 TC/VC mapping
(TC0/VC0, TC1/VC1) is required. Set this parameter
to 2 when any other mapping is required. When set to
2, TC/VC mapping should be configured through the
monitor input ports. When this parameter is set to 0 or
1, input ports enable_vc_id and
tc_mapped_to_vc_id_n can be left unconnected.
15.
HOT_PLUG_MESSAGE_
ENABLE
Configures the monitor to support Hot plug signaling

messages. By default, Hot plug signaling messages
are not allowed.
For Gen2, this parameter has no effect.
16.
TX_SKEW_SUPPORT
Configures the monitor for supporting skew on

transmit lanes. Set this parameter to 1 to allow skew
on transmit lanes. By default, skew on transmit lanes
is not supported.
17
CPL_TIMEOUT_CLK
30000
Configures the completion timeout value. The value

indicates in terms of the number of clocks.This
parameter is applicable for Gen2 mode.
PCI Express
Table 14-4. PIPE Monitor Parameters (cont.)

Order Parameter
Default Description
18
7500
/3750
UPDATE_FC_30US_TIMER_
CLK
Configures the update FC frequency in terms of the

number of clocks. Default value is 7500 for
INTERFACE_TYPE=0(8-bit PIPE) and 3750 for
INTERFACE_TYPE=1(16-bit PIPE). If
extended_sync_enable is set, then this parameter is
multiplied by 4 internally to make 30 us to 120 us.
Notes:
2. The width of ports tx_data and rx_data is n*8-bits (n is the number of lanes on the
link, MAX_LINK_WIDTH) if the monitor is configured to track the 8-bit PIPE interface of
a multiple lane link. The width is n*16-bits if the monitor is configured to track the 16bit PIPE interface of a multilane PIPE. The allowed values of n are 1, 2, 4, 8, 12, 16, and
32.
Example: The width is 64-bits if the monitor is configured to track the 8-bit PIPE
interface and 128-bits if the monitor is configured to track the 16-bit PIPE interface for
n=8 (i.e., x8 link).
3. The width of ports tx_data_k and rx_data_k is n bits (n is the maximum number of
lanes supported by the device, MAX_LINK_WIDTH) if the monitor is configured to track
the 8-bit PIPE interface. The width is 2*n bits if the monitor is configured to track the
16-bit PIPE interface of a multilane PIPE.
4. The width of ports tx_elecidle, tx_compliance, rx_polarity, rx_valid, and
rx_elecidle is n bits (n is the maximum number of lanes supported by the device,
MAX_LINK_WIDTH) if the monitor is configured to track a multilane PIPE.
5. The width of ports rate, tx_deemph, and tx_swing is 1-bit in Gen2 mode.
6. The width of port tx_margin is 3 bits in Gen2 mode.
7. The width of port rx_status is 3*n bits (n is the maximum number of lanes supported
by the device, MAX_LINK_WIDTH) if the monitor is configured to track a multilane PIPE.
8. If the monitor is configured to track a multilane PIPE, then the per-lane signals should
be concatenated and connected to the respective monitor ports (see the following
classification of signals).
Shared signals
pclk
tx_detect_rx_ loopback
power_down [1:0]
phystatus
rate(Gen2 only)
tx_margin(Gen2 only)
tx_deemph(Gen2 only)
tx_swing(Gen2 only)
Per-lane Signals
(tx_data, tx_data_k)
(rx_data, rx_data_k)
(tx_elecidle)
(tx_compliance, rx_polarity, rx_valid,
rx_elecidle, rx_status[2:0])
437
PCI Express
9. TC/VC mapping information is available in the VC resource control register of the

design under test. For example, if the design supports VC IDs 0, 1, 2, 3 (TC0 and TC1
are mapped to VC0; TC2 and TC3 are mapped to VC1; TC4 and TC5 are mapped to
VC2; and TC6 and TC7 are mapped to VC3) then the monitor can be configured with
the following:
set VC_SUPPORT parameter to 2
enable_vc_id = 8'b 0000_1111;
Instantiation Examples (PIPE)

Example 1
Example 14-4 instantiates a PIPE monitor within a end point device. The monitor is instantiated
on the MAC Layer side of the PIPE interface. The input to the device is parallel 8-bit symbols.
The maximum link width is set to 1. Reserved-bit field checking is disabled. The maximum
number of requests that can be outstanding is 32. The device uses a 5-bit tag field. The
maximum pay load size and maximum read request size are set to 128 bytes. The example
supports only VC0.
Example 14-4. PIPE Monitor Instantiation
qvl_pci_express_pipe_monitor
0,
0,
/* MAC_LAYER_SIDE */
1,
0,
1,
5,
0,
MONITOR_PIPE(
.areset_n
(RESET#),
.reset_n
(1'b1),
.pclk
(PCLK),
.tx_data
(TxData[7:0]),
.tx_data_k
(TxDataK),
.tx_detect_rx_loopback
(TxDetectRx/Loopback),
.tx_elecidle
(TxElecidle),
.tx_compliance
(TxCompliance),
.rx_polarity
(RxPolarity),
.power_down
(Power_Down[1:0]),
.rx_data
(RxData[7:0]),
.rx_data_k
(RxDataK),
.rx_valid
(RxValid),
.rx_elecidle
(RxElecidle),
.rx_status
(RxStatus[2:0]),
438
PCI Express
.phystatus
(PhyStatus),
.disable_descrambler
(1'b0),
.skip_link_training
(1'b0),
(1'b0),
(16'b0),
(32'h5),
(1'b0),
(1'b0),
.transaction_layer_checks_disable (1'b0) );
Example 2
Example 14-5 instantiates the PIPE monitor within an end point component. The monitor is
instantiated on the PHY Layer side of the multilane PIPE interface. The input to the device is
parallel 8-bit symbols. The maximum link width is set to 2. Reserved-bit field checking is
disabled. The maximum number of requests that can be outstanding is 32. The device uses 5-bit
tag field. The maximum pay load size and maximum read request size are set to 128 bytes.
Supports only VC0.
0,
0,
0,
0,
2,
5,
0,
/* VENDOR_SPECIFIC_ENCOING_ENABLE * 0)
MONITOR_PIPE(
.areset_n
(RESET#),
.reset_n
(1'b1),
.pclk
(PCLK),
.tx_data
({TxData_ln1, TxData_ln0}),
.tx_data_k
({TxDataK_ln1, TxDataK_ln0}),
.tx_elecidle
({TxElecidle_ln1,
TxElecidle_ln0}),
.tx_compliance
({TxCompliance_ln1,
TxCompliance_ln0}),
.rx_polarity
({RxPolarity_ln1,
RxPolarity_ln0}),
.power_down
(Power_Down[1:0]),
.rx_data
({RxData_ln1, RxData_ln0}),
.rx_data_k
({RxDataK_ln1, RxDataK_ln0}),
.rx_valid
({RxValid_ln1, RxValid_ln0}),
.rx_elecidle
({RxElecidle_ln1,
RxElecidle_ln0}),
.rx_status
({RxStatus_ln1,
RxStatus_ln0}),
.phystatus
(PhyStatus),
(1'b0),
.skip_link_training
(1'b0),
439
PCI Express
(1'b0),
(16'b0),
(32'h5),
(1'b0),
(1'b0),
Note that when instantiating the monitor in a multilane PIPE interface, the per-lane signals
should be concatenated and connected to the monitor as shown in the example.
Example 3 (9-Bit Mode)

Example 14-6 instantiates the PIPE monitor in a 9-bit mode system.
Example 14-6. PIPE Monitor Instantiation Example 3 (9Bit Mode)
0,
7,
1,
0,
4,
5,
0,
/* VENDOR_SPECIFIC_ENCOING_ENABLE */ 0,
/* OVERRIDE_TIMER_VALUE*/
0,
/* REPLAY_TIMER_VALUE*/
711,
/* ACKNAK_TIMER_VALUE*/
237,
/* MIN_TS1_COUNT*/
1024,
/* DESKEW_SUPPORT*/
1,
/* VC_SUPPORT*/
0)
MONITOR_PIPE(
.areset_n
(RESET#),
.reset_n
(1'b1),
.pclk
(PCLK), // Clock from PHY
.tx_data
(tx_data_pipe),
.tx_data_k
(tx_data_k_pipe),
(1'b0),
.tx_elecidle
(4'b0),
.tx_compliance
(4'b0),
.rx_polarity
(4'b0),
.power_down
(2'b0),
.rx_data
(rx_data_pipe),
.rx_data_k
(rx_data_k_pipe),
.rx_valid
(4'b1111),
.rx_elecidle
(4'b0),
.rx_status
(12'b0),
.phystatus
(1'b0),
(1'b0),
.skip_link_training
(1'b0),
(1'b0),
(device_control_register),
(32'h5),
(1'b0),
(1'b0),
440
PCI Express
Example 3
Example 14-7 instantiates the Gen2 PIPE monitor within an end point component. The monitor
is instantiated on the PHY Layer side of the multilane PIPE interface. The input to the device is
parallel 8-bit symbols. The maximum link width is set to 2. Reserved-bit field checking is
disabled. The maximum number of requests that can be outstanding is 32. The device uses 5-bit
tag field. The maximum pay load size and maximum read request size are set to 128 bytes.
Supports only VC0.
qvl_pci_express_gen2_pipe_monitor
0,
0,
0,
0,
2,
5,
0,
/* VENDOR_SPECIFIC_ENCOING_ENABLE * 0)
MONITOR_PIPE(
.areset_n
(RESET#),
.reset_n
(1'b1),
.pclk
(PCLK),
.tx_data
({TxData_ln1, TxData_ln0}),
.tx_data_k
({TxDataK_ln1, TxDataK_ln0}),
.tx_elecidle
({TxElecidle_ln1,
TxElecidle_ln0}),
.tx_compliance
({TxCompliance_ln1,
TxCompliance_ln0}),
.rx_polarity
({RxPolarity_ln1,
RxPolarity_ln0}),
.power_down
(Power_Down[1:0]),
.rate
(rate),
.tx_margin
(tx_margin),
.tx_deemph
(tx_deemph),
.tx_swing
(tx_swing),
.rx_data
({RxData_ln1, RxData_ln0}),
.rx_data_k
({RxDataK_ln1, RxDataK_ln0}),
.rx_valid
({RxValid_ln1, RxValid_ln0}),
.rx_elecidle
({RxElecidle_ln1,
RxElecidle_ln0}),
.rx_status
({RxStatus_ln1,
RxStatus_ln0}),
.phystatus
(PhyStatus),
(1'b0),
.skip_link_training
(1'b0),
(1'b0),
(16'b0),
(32'h5),
(1'b0),
(1'b0),
441
PCI Express
Monitor Checks
Note that when instantiating the monitor in a multilane PIPE interface, the per-lane signals
should be concatenated and connected to the monitor as shown in the example.
Monitor Checks
The checks performed by the PCI Express monitor are classified as follows:
Physical layer checks.

Validate encoded 10B values, link training and initialization, TS1/TS2 ordered sets,
SKIP ordered sets, Electrical Idle ordered sets, Electrical Idle Exit Sequence (In Gen2
mode only), and Fast training sequences.
Data link layer checks.

Validate the TLP packet integrity, DLLP packet integrity, Flow control initialization,
Sequence number generation and reception, DLLP packets, and ACK/NAK sequencing.
Transaction layer checks.

Validate the TLP packets, Requests/Completions, TLP packet size, ECRC, and receive
buffer flow control.
PIPE Interface checks (if configured).
Note that all checks are performed in both transmit and receive directions.
Physical Layer Checks

Table 14-5 shows the physical layer checks performed by the PCI Express monitor.
Table 14-5. PCI Express Monitor Physical Layer Checks
Check ID
Violation
Description
PCI_EXPRESS_10B_CODING_
VIOLATION_P
Invalid 10b code on this lane

of the TX/RX interface.
Valid 10B symbols should be detected on

the lanes. If the detected 10B symbol does
not correspond to either column, then the
symbol is considered to be invalid. This
check fires if an invalid 10B symbol is
detected on the lane.
COM symbol should not be

part of DLL or TL packet.
COM symbols should not be a part of the

TL or DLL packet. This check fires if a
COM symbol is detected in a TL or DLL
packet.
PCI_EXPRESS_10B_CODING_
VIOLATION_N
PCI_EXPRESS_COM_IN_
DLLP_TLP_P
PCI_EXPRESS_COM_IN_
DLLP_TLP_N
442
PCI Express
Monitor Checks
Table 14-5. PCI Express Monitor Physical Layer Checks (cont.)

Check ID
Violation
Description
PCI_EXPRESS_COMPLIANCE_ Compliance pattern error on

PATTERN_ERROR_P
this lane of the TX/RX
interface.
PCI_EXPRESS_COMPLIANCE_
PATTERN_ERROR_N
Compliance pattern consists of K28.5,

D21.5, K28.5, and D10.2 symbols. This
check fires if the above mentioned sequence
is not detected.
PCI_EXPRESS_DATA_PLUS_
MINUS_ERROR_P
D+ and D- pins of the transmit/receive lanes

must follow the following rules:
a. During electrical idle conditions, the
logic levels on these pins must be the
same.
b. During nonelectrical idle conditions,
the logic level on these pins must be
inverted.
This check fires if the above rules are not
followed. This check is applicable only
when the parameter INTERFACE_TYPE is
set to 0 (Serial Interface). This check is not
applicable for the PIPE interface.
Invalid logic levels on 'D+'

and 'D-' pins of this lane of
the TX/RX interface.
PCI_EXPRESS_DATA_PLUS_
MINUS_ERROR_N
Example: This check fires if the D- input is

not connected to the monitor and the
ENABLE_DATA_PLUS_MINUS_
CHECK parameter is set to 1.
PCI_EXPRESS_DISPARITY_
NEUTRAL_000111_ERROR_P
NEUTRAL_000111_ERROR_N
6'b000111 should be
beginning of the sub-block is
positive.

that the sub-blocks encoded as 000111b or
disparity at the beginning of the sub-block is
violated.
4'b0011 should be generated

violated.

violated.
6'b111000 should be
beginning of the sub-block is
negative.

violated.
443
PCI Express
Monitor Checks

Check ID
Violation
Description
PCI_EXPRESS_EDB_
WITHOUT_STP_P
Every EDB symbol should

be preceded by a STP
symbol.
Every EDB symbol should be associated

with a STP symbol. This check fires if an
EDB symbol is detected without an
associated STP symbol.
Electrical idle is not detected

on the bus within the
specified maximum time
interval after detecting
EIOS.
Electrical idle condition should be detected

on the bus within the specified maximum
time interval after detecting an electrical
idle ordered set. This check fires if electrical
idle is not detected within the specified
maximum time interval.
Total length of the packet

should always be an integral
multiple of 4.
Total length of the packet should always be

an integral multiple of 4. This check fires if
a packet length is not an integral multiple of
4.
Every END symbol should

be preceded by a STP /SDP
symbol.
Every END symbol should be associated

with a STP or SDP symbol. This check fires
if an END symbol is detected without an
associated STP or SDP symbol.
PCI_EXPRESS_FTS_COUNT_
ERROR_N
The number of FTS ordered

sets detected should be equal
to the specified number of
FTS in TS OS during
training.
N_FTS defines the number of FTS ordered

sets that must be transmitted when
transitioning from the L0s state to L0 state.
If extended sync enable is set, then the
maximum number of FTS ordered sets that a
device can transmit is 4096. This check fires
if the number of FTS ordered sets detected
is more than the specified N_FTS number of
ordered sets. If skip_link_training is set,
then this check is disabled.
PCI_EXPRESS_FTS_IN_
DLLP_TLP_P
FTS symbol should not be

FTS symbols should not be a part of the TL

or DLL packet. They should be a part of the
fast training sequence only. This check fires
if a FTS ordered set is detected in a TL or
DLL packet.
FTS symbol should be a part

of fast training sequence
only.
FTS symbols should always be part of FTS

ordered sets. This check fires if a FTS
symbol is detected when a FTS ordered set
is not in progress.
FTS ordered set error on this

lane of the TX/RX interface.
FTS ordered set should consist of one COM

symbol followed by three K 28.1 symbols.
This check fires if above mentioned rule is
violated.
PCI_EXPRESS_EDB_
WITHOUT_STP_N
PCI_EXPRESS_EIDLE_NOT_
DETECTED_P
PCI_EXPRESS_EIDLE_NOT_
DETECTED_N
PCI_EXPRESS_END_OF_PKT_
ERROR_P
PCI_EXPRESS_END_OF_PKT_
ERROR_N
PCI_EXPRESS_END_
WITHOUT_STP_SDP_P
PCI_EXPRESS_END_
WITHOUT_STP_SDP_N
PCI_EXPRESS_FTS_COUNT_
ERROR_P
PCI_EXPRESS_FTS_IN_
DLLP_TLP_N
PCI_EXPRESS_FTS_NOT_
PART_OF_FTS_OS_P
PART_OF_FTS_OS_N
PCI_EXPRESS_FTS_
ORDERED_SET_ERROR_P
PCI_EXPRESS_FTS_
ORDERED_SET_ERROR_N
444
PCI Express
Monitor Checks

Check ID
Violation
Description
PCI_EXPRESS_IDL_IN_
DLLP_TLP_P
IDL symbol should not be a

IDL symbols should not be part of the TL or

DLL packet. IDL symbols should always be
part of the electrical idle ordered set. This
check fires if an IDL symbol is detected in a
TL or DLL packet.
IDL symbol should be a part

of electrical idle ordered set
only.
IDL symbols should always be part of

electrical idle ordered sets. This check fires
if an IDL symbol is detected when a IDL
ordered set is not in progress.
ELECTRICAL IDLE
ordered set error on this lane
The transmitted electrical idle ordered set

should consist of one COM symbol
followed by three K28.3 symbols. Received
electrical idle ordered set can consist of one
COM symbol followed by two to three
K28.3 symbols. This check fires if above
mentioned rule is violated.
Illegal lane number is

assigned to this physical
lane.
Physical lanes must be assigned with proper

lane numbers during link width negotiation.
For example:
PCI_EXPRESS_IDL_IN_
DLLP_TLP_N
PCI_EXPRESS_IDL_NOT_
PART_OF_EIDL_OS_P
PART_OF_EIDL_OS_N
PCI_EXPRESS_IDLE_
ORDERED_SET_ERROR_P
PCI_EXPRESS_IDLE_
ORDERED_SET_ERROR_N
PCI_EXPRESS_ILLEGAL_
ASSIGNED_LANE_NUMBER_
P
Physical lane 1 must be assigned with a
ASSIGNED_LANE_NUMBER_
N
lane number 1 or lane number 0 if the

lane numbers are assigned to only two
lanes.
Physical lane 3 must be assigned with a
lane number 3 when link width is 8 and
lane reversal is not supported, or 4
when link width is 8 and lane reversal is
supported.
This check fires if the above rule is violated.

DATA_RATE_IDENTIFIER_P
DATA_RATE_IDENTIFIER_N
LANE_NUM_IDENTIFIER_P
LANE_NUM_IDENTIFIER_N
LINK_CONTROL_FIELD_P
LINK_CONTROL_FIELD_N
Illegal data rate identifier in

the TS1/TS2 ordered set on
interface.
Data rate identifier field of the TS1/TS2

ordered set should consist of D2.0 symbol.
This check fires if the monitor detects a data
rate identifier value other than D2.0.
Illegal lane number identifier

in the TS1/TS2 ordered set
on this lane of the TX/RX
interface.
Lane number field of TS1 / TS2 ordered sets

should not contain any symbol other than
D0.0 to D31.0, K23.7. This check fires if the
lane number field of the TS1/TS2 ordered
set contains any other value.
Illegal link control field in

the TS1/TS2 ordered set on
interface.
Link control field of the TS1 and TS2

should contain any of the following
symbols. D0.0, D1.0, D2.0, D4.0, D8.0.
This check fires if the link control field of
the TS1/TS2 ordered set contains any other
value.
445
PCI Express
Monitor Checks

Check ID
Violation
Description
SYMBOL_FOLLOWING_
COM_SYMBOL_P
COM symbol is followed by

an illegal special symbol on
interface.
The COM symbol should always be part of

TS1, TS2, FTS, SKP, or electrical idle
ordered sets. Only FTS, SKP, or IDL special
symbols can follow a COM symbol. This
check fires if any other special symbol
follows the COM symbol.
Illegal TS identifier in the

TS1/TS2 ordered set on this
The TS identifier field of the TS1/TS2

ordered set should consist of D10.2 or D5.2
symbols. If the lane polarity is inverted, then
these fields contain a value of D21.5 or
D26.5 symbols. This check fires if the TS
identifier field does not detect any of the
above values.
SYMBOL_FOLLOWING_
COM_SYMBOL_N
PCI_EXPRESS_ILLEGAL_TS_
IDENTIFIER_P
PCI_EXPRESS_ILLEGAL_TS_
IDENTIFIER_N
PCI_EXPRESS_INVALID_
CODE_IN_DLLP_TLP_P
CODE_IN_DLLP_TLP_N
PCI_EXPRESS_MORE_
THAN_ONE_SDP_P
Invalid 10B codes should not Invalid 10B codes should not be detected in
be part of the DLL or TL
a TL or DLL packet. This check fires if an
packet.
invalid 10B code is detected in a TL or DLL
packet.
There should not be more
than one SDP symbol in a
symbol time.
The SDP symbol must not be placed on the

link more frequently than once per symbol
time. This check fires if more than one SDP
symbol is detected in a symbol time.
There should not be more

than one STP symbol in a
symbol time.
The STP symbol must not be placed on the

link more frequently than once per symbol
time. This check fires if more than one STP
symbol is detected in a symbol time.
Idle data should be

transmitted when no DLLP,
TLP, or special symbols are
transmitted.
Idle data should be detected on the lane

when no DLLP,TLP, or any type of special
symbol is being transmitted/received. Idle
data is detected on the lane when the
physical link is up. This check fires if Idle
data is not detected on the lane.
SDP and STP symbols

should be placed on lane 0.
When initiating a packet transfer from

logical idle state, the SDP and STP symbols
should be placed on lane 0. This check fires
if a STP or SDP symbol is not detected on
lane 0.
PAD symbol should not be

PAD symbols should not be a part of the TL

or DLL packet. This check fires if a PAD
symbol is detected in a TL or DLL packet.
PCI_EXPRESS_MORE_
THAN_ONE_SDP_N
PCI_EXPRESS_MORE_
THAN_ONE_STP_P
PCI_EXPRESS_MORE_
THAN_ONE_STP_N
PCI_EXPRESS_NO_IDLE_
DATA_P
DATA_N
PCI_EXPRESS_NO_STP_
SDP_LANE0_P
PCI_EXPRESS_NO_STP_
SDP_LANE0_N
PCI_EXPRESS_PAD_IN_
DLLP_TLP_P
PCI_EXPRESS_PAD_IN_
DLLP_TLP_N
446
PCI Express
Monitor Checks

Check ID
Violation
Description
PCI_EXPRESS_PAD_WHEN_
LINK_WIDTH_1_2_4_P
PAD symbols should not be

transmitted after an end of
TL or DL packet when link
is <X8.
When the link width is 1, 2, or 4, then the

PAD symbols should not follow the END or
EDB symbols. This check fires if PAD
symbols follow END or EDB symbols when
the link width is 1, 2, or 4.
Padding error detected when

link is X8 or wider.
In a x8 and wider links, if an END/EDB

symbol is not followed by a STP or SDP
symbol, then PAD symbols must be driven
throughout the width of the link for that
symbol time. This check fires if PAD
symbols are not detected.
Reserved K code on this lane

Only defined special symbols should be

detected on the lanes. Special symbols are
used for framing and link management. This
check fires if reserved special symbols are
detected on the lane.
PCI_EXPRESS_PAD_WHEN_
LINK_WIDTH_1_2_4_N
PCI_EXPRESS_PADDING_
ERROR_P
ERROR_N
PCI_EXPRESS_RESERVED_
K_CODE_P
K_CODE_N
PCI_EXPRESS_SDP_NOT_
FOLLOWED_BY_END_P
Every SDP symbol should be Every SDP should be followed by an END

followed by an END symbol. symbol. This check fires if a SDP symbol is
detected without a preceding END symbol.
PCI_EXPRESS_SDP_NOT_
FOLLOWED_BY_END_N
PCI_EXPRESS_SDP_STP_ON_
INCORRECT_LANES_P
PCI_EXPRESS_SDP_STP_ON_
INCORRECT_LANES_N
STP and SDP symbols

should always be placed on
lanes that are multiples of
four.
In a x8 or wider links, the SDP and STP

symbols should always be sampled on lanes
that are multiples of 4. This check fires if
symbols are placed on lanes that are not
multiples of 4.
PCI_EXPRESS_SKP_IN_DLLP_ SKP symbol should not be

TLP_P
PCI_EXPRESS_SKP_IN_DLLP_
TLP_N
SKP symbols should not be part of the TL or

DLL packet. They should be a part of skip
ordered sets only. This check fires if a SKP
symbol is detected in a TL or DLL packet.
PCI_EXPRESS_SKP_NOT_
PART_OF_SKP_OS_P
SKP symbols should always be part of skip

ordered sets. This check fires if a SKP
symbol is detected when a SKIP ordered set
is not in progress.
SKP symbol should be a part

of SKP ordered set only.
PART_OF_SKP_OS_N
PCI_EXPRESS_SKP_OS_NOT_
RECEIVED_P
RECEIVED_N
XMTD_P
SKP ordered sets should be The maximum interval between two skip
received within 5664 symbol ordered sets can be 5664 symbols. This
times.
check fires if the interval between two skip
ordered sets exceeds the above specified
number of symbol times.
SKP ordered sets should be
scheduled once every 1180
to 1538 symbol times.
XMTD_N
The Skip ordered sets should be transmitted

once in every 1180 to 1538 symbol times. If
a packet transmission is in progress, then the
scheduled skip ordered sets should be
transmitted at the next packet boundary or
ordered set boundary. This check fires if an
idle data is detected after the maximum skip
interval count is exceeded.
447
PCI Express
Monitor Checks

Check ID
Violation
Description
PCI_EXPRESS_SKP_
ORDERED_SET_ERROR_P
SKP ordered set error on this

The transmitted skip ordered set should

consist of one COM symbol followed by
three SKP symbols. The received skip
ordered sets should consist of one COM
symbol followed by one to five SKP
symbols. This check fires if above
mentioned rule is violated.
SKP ordered set should not

be transmitted within first
rx_n_fts number of FTS
ordered sets.
No SKP ordered sets should be scheduled

during the first N_FTS number of FTS
ordered sets. A single SKP ordered set is
always sent after the last FTS ordered set.
This check fires if a SKP ordered set is
detected before N_FTS number of FTS
ordered sets.
Special reserved symbols

should not be part of the
DLL or TL packet.
Reserved K codes should not be a part of the

TL or DLL packet. This check fires if a
reserved K code is detected in a TL or DLL
packet.
Every STP symbol should be

followed by an END/EDB
symbol.
Every STP should be followed by an END

or EDB symbol. This check fires if a STP
symbol is detected without a preceding
END symbol or an EDB symbol.
TLP should not be

transmitted when data link
layer is down.
When the data link layer is down, the device

should not initiate transmission of the
transaction layer packet. The data link layer
is considered to be down when the physical
layer is not up or the physical layer is up and
flow control initialization is not complete.
TS1 ordered set error on this

A TS1 ordered set should consist of 10 TS1

ID symbols. This check fires if a TS1
ordered set contains more or less than the
specified number of TS1 ID symbols.
TS2 ordered set error on this

A TS2 ordered set should consist of 10 TS2

ID symbols. This check fires if a TS2
ordered set contains more or less than the
specified number of TS2 ID symbols.
Bus should be in the

electrical idle state for the
specified minimum time
interval.
Once the bus enters into electrical idle state

after detecting an electrical idle ordered set,
the bus should be in that state for the
specified minimum time interval. This
check fires if the bus exits the electrical idle
state before the specified minimum time
interval.
PCI_EXPRESS_SKP_
ORDERED_SET_ERROR_N
PCI_EXPRESS_SKP_
WITHIN_N_FTS_P
PCI_EXPRESS_SKP_
WITHIN_N_FTS_N
PCI_EXPRESS_SPL_
RESERVED_SYMBOLS_IN_
DLLP_TLP_P
PCI_EXPRESS_SPL_
RESERVED_SYMBOLS_IN_
DLLP_TLP_N
PCI_EXPRESS_STP_NOT_
FOLLOWED_BY_END_EDB_P
FOLLOWED_BY_END_EDB_N
PCI_EXPRESS_TLP_WHEN_
LINK_DOWN_P
PCI_EXPRESS_TLP_WHEN_
LINK_DOWN_
PCI_EXPRESS_TS1_
ORDERED_SET_ERROR_P
PCI_EXPRESS_TS1_
ORDERED_SET_ERROR_N
PCI_EXPRESS_TS2_
ORDERED_SET_ERROR_P
PCI_EXPRESS_TS2_
ORDERED_SET_ERROR_N
PCI_EXPRESS_TTX_IDLE_
MIN_VIOLATION_P
PCI_EXPRESS_TTX_IDLE_
MIN_VIOLATION_N
448
PCI Express
Monitor Checks
Notes:
1. Checkers with a _P suffix are active on the rising edge of the clock. Those with an _N
suffix are active on the falling edge of the clock.
2. Checkers with a _TX_P or _TX_N suffix are performed in the transmit direction and
checkers with a _RX_P or _RX_N suffix are performed in the receive direction. All
other checks are performed in both directions.
Table 14-6. Link Training and Width Negotiation Checks

Check ID
Violation
Description
PCI_EXPRESS_CHANGE_IN_
LINK_WIDTH_TX_P
The number of lanes on

which valid lane numbers
are detected should not
change.
The downstream port starts transmitting TS2

ordered sets only after accepting the link
width counter proposed by the upstream
port. Once TS2 ordered sets are detected, no
change in link width is allowed. This check
fires if the number of lanes on which valid D
codes are detected (lane number field of TS2
ordered sets) changes once TS2 ordered sets
are transmitted. This check does not fire
during the Recovery state of the device. As
there is a chance that the link width can
change due to which negotiation starts
afresh. This check is enabled only when the
skip link training option is not set.
Code violations detected in

loopback mode.
A loopback master is the component

requesting loopback and a loopback slave is
the component looping back the data. For a
master component, code violations should
not be transmitted. This check fires if code
violations are detected.
TS2 ordered set can only be

transmitted in the
Configuration Complete
state.
This check fires if TS2 is detected in the

Configuration state other than Configuration
Complete. This check is enabled only when
the skip link training option is not set.
Counter proposed width

should not be greater than
the proposed width.
During link width negotiation, the counter

proposed width should be either equal to
proposed width or less than the proposed
width. This check fires if counter proposed
width is greater than the proposed width.
This check is enabled only when the skip
link training option is not set.
LINK_WIDTH_TX_N
LINK_WIDTH_RX_P
LINK_WIDTH_RX_N
PCI_EXPRESS_CODE_
VIOLATION_LOOPBACK_P
PCI_EXPRESS_CODE_
VIOLATION_LOOPBACK_N
PCI_EXPRESS_CONFIG_
ILLEGAL_TS2_P
PCI_EXPRESS_CONFIG_
ILLEGAL_TS2_N
PCI_EXPRESS_COUNTER_
PROPOSED_GREATER_TX_P
PROPOSED_GREATER_TX_N
PROPOSED_GREATER_RX_P
PROPOSED_GREATER_RX_N
Example: Monitor is instantiated in the

downstream port. Downstream port assigns
valid lane numbers to TS1/TS2 ordered sets
transmitted on 8 lanes. This check fires if
valid lane numbers are detected on 12 lanes
of the received TS1/TS2 ordered sets.
449
PCI Express
Monitor Checks
Table 14-6. Link Training and Width Negotiation Checks (cont.)

Check ID
Violation
Description
PROPOSED_WIDTH_ERROR_
TX_P
Illegal counter proposed

link width.
PCI Express links must consist of 1, 2, 4, 8,

12, 16, or 32 lanes in parallel. Valid D codes
should be detected in the link/lane number
field of the TS1/TS2 ordered sets only on 1,
2, 4, 8, 12, 16, or 32 lanes. This check fires if
valid D codes are detected on illegal number
of lanes. This check is enabled only when the
TX_N
RX_P
Example 1: Monitor is instantiated in the

downstream port (proposer). This check fires
if D codes are detected in 3 lanes of the
receive interface.
RX_N
PCI_EXPRESS_DESKEW_
LIMIT_EXCEEDED_P
PCI_EXPRESS_DESKEW_
LIMIT_EXCEEDED_N
PCI_EXPRESS_DISABLE_NOT_
ENTERED_P
PCI_EXPRESS_DISABLE_NOT_
ENTERED_N
PCI_EXPRESS_DISABLE_OS_
ERROR_P
PCI_EXPRESS_DISABLE_OS_
ERROR_N
PCI_EXPRESS_FTS_IN_NON_
L0s_P
PCI_EXPRESS_FTS_IN_NON_
L0s_N
ALL_LANES_TX_P
ALL_LANES_TX_N

upstream device (counter proposer). This
check fires if valid D codes are detected on
only 7 lanes of the transmit interface.
Lane to lane deskew should
not exceed the specified
maximum limit of five
symbol times.
Allowed maximum skew across all lanes of

the receive interface of a port is 20 ns (five
symbols). This check fires when the skew
across active lanes of the receive interface of
a port exceeds five symbol times.
Device should enter

Disable state after
receiving two TS with
disable bit set.
This check fires if the device does not enter

in the Disable state after receiving two TS
OS with disable bit set.
Disable bit should be set in

at least 16 TS1 ordered sets
and should not be set in
more than 32 TS1 ordered
sets.
Disable link bit must not be set in 16 to 32

TS1 ordered sets. This check fires if the
number of transmitted TS1 ordered sets with
disable bit set is less than 16 or more than 32.
Fast training sequences

should be transmitted only
during L0s state of the
device.
When the device is in the power down mode,

it transmits Fast training sequences before
starting the transmission of a packet. The fast
training sequences should only be
transmitted when the device comes up from
the power down mode.
FTS ordered sets should be

detected on all lanes of the
link.
FTS Ordered sets should be detected on all

lanes of the configured link. This check fires
if FTS ordered sets are not detected on all
lanes of the configured link.
ALL_LANES_RX_P
ALL_LANES_RX_N
450
PCI Express
Monitor Checks

Check ID
Violation
Description
ALL_LANES_TX_P
Electrical idle ordered sets

should be detected on all
lanes of the link.
Electrical idle ordered sets should be

detected on all lanes of the configured link.
This check fires if electrical idle ordered sets
are not detected on all lanes of the
configured link.
At least 16 consecutive idle

data should be transmitted
after receiving one idle data
symbol.
When the device is in the Config.IDLE state

or Recovery.IDLE state, it transmits IDLE
data on all lanes of the configured link. The
transmitter should drive at least 16 IDLE
data symbols on the lanes after receiving one
IDLE data symbol. This check fires if less
than 16 consecutive IDLE data symbols are
transmitted. The monitor checks for 16
consecutive IDLE data symbols after
detecting one IDLE symbol during link
training.
ALL_LANES_TX_N
ALL_LANES_RX_P
ALL_LANES_RX_N
PCI_EXPRESS_IDLE_COUNT_
ERROR_P
PCI_EXPRESS_IDLE_COUNT_
ERROR_N
PCI_EXPRESS_IDLE_DATA_
BEFORE_NEG_TX_P
BEFORE_NEG_TX_N
BEFORE_NEG_RX_P
Idle data should be detected During link training, only training sequences
after link width negotiation. are transmitted and received. Idle data is
transmitted/received only after link training
and width negotiation. This check fires if
idle data is detected on the transmit/receive
interface before the completion of link width
negotiation.
BEFORE_NEG_RX_N
NOT_ALL_LANES_TX_P
NOT_ALL_LANES_TX_N
Idle data should be detected Idle data should be detected on all lanes of
on all lanes of the link.
the configured link. This check fires if idle
data is not detected on all lanes of the
configured link.
NOT_ALL_LANES_RX_P
NOT_ALL_LANES_RX_N
451
PCI Express
Monitor Checks

Check ID
Violation
Description
PCI_EXPRESS_ILLEGAL_IDLE_
DATA_P
PCI_EXPRESS_ILLEGAL_IDLE_
DATA_N
While waiting for eight

TS2 ordered sets, idle data
should not be transmitted
before receiving eight TS2
ordered sets.
During link training and link width

negotiation, the device starts transmitting
TS2 ordered sets after the width negotiation
is complete. The device waits for 8 TS2
ordered sets before transmitting the idle data
symbols. This check fires if idle data
symbols are transmitted before receiving 8
consecutive TS2 ordered sets. This check is
enabled only when the skip link training
option is not set.
PCI_EXPRESS_ILLEGAL_LINK_
WIDTH_P
Invalid negotiated link

width.
The protocol specifies the operating link

widths should be 1, 2, 4, 8,12,16, or 32. This
check fires if the negotiated link width is not
equal to 1, 2, 4, 8,12,16, or 32. This check is
option is not set.

TS2 ordered sets, TS1
ordered sets should not be
transmitted before
receiving eight TS2
ordered sets.
When the device is in the

Polling.Configuration state, the device
transmits and receives TS2 ordered sets. The
device changes its state only after receiving
eight TS2 ordered sets. This check fires if
TS1 ordered sets are transmitted before
receiving eight TS2 ordered sets. This check
is enabled only when the skip link training
option is not set.

TS1 ordered sets, TS2
ordered sets should not be
transmitted before
receiving eight TS1
ordered sets.
When the device is in the Polling.Active

state and Recovery.Lock state, the device
transmits and receives TS1 ordered sets. The
device changes its state only after receiving
eight TS1 ordered sets. This check fires if
TS2 ordered sets are transmitted before
receiving eight TS1 ordered sets. This check
is enabled only when the skip link training
option is not set.
The downstream ports

should assign valid lane
numbers on lanes for which
the upstream port has
responded with the link
number.
The lane numbers should be assigned to only

on those lanes or fewer number lanes for
which the upstream port has responded with
a valid D code in the link number field. This
check fires if lane numbers are initialized for
lanes other than for which the upstream port
has responded. This check is enabled only
when the skip link training option is not set.
PCI_EXPRESS_ILLEGAL_LINK_
WIDTH_N
PCI_EXPRESS_ILLEGAL_TS1_
OS_P
OS_N
OS_P
OS_N
PCI_EXPRESS_LANE_ASSIGN_
ERROR_TX_P
ERROR_TX_N
ERROR_RX_P
ERROR_RX_N
452
PCI Express
Monitor Checks

Check ID
Violation
Description
PCI_EXPRESS_LANE_INIT_
BEFORE_LINK_INIT_TX_P
Lane numbers should not

be initialized before the
valid link number is
assigned.
During link width negotiation, Link numbers

are initialized first and then the lane
numbers. This check fires when valid D
codes are detected in the
transmitted/received TS1/TS2 ordered sets
before the initialization of link numbers.
Once lane numbers are

assigned in the TS1/TS2
ordered sets, the number of
lanes on which valid lane
numbers are detected
should be equal to the
number of lanes on which
valid link numbers are
detected.
The number of lanes on which valid lane

numbers are detected should be equal to the
number of lanes on which valid link numbers
are detected. This check fires if there is a
mismatch.
BEFORE_LINK_INIT_TX_N
BEFORE_LINK_INIT_RX_P
BEFORE_LINK_INIT_RX_N
PCI_EXPRESS_LANE_LINK_
MISMATCH_TX_P
MISMATCH_TX_N
MISMATCH_RX_P
Example: This check fires if the downstream

port asserts valid link numbers on 8 lanes
and valid lane numbers on only 4 lanes.
MISMATCH_RX_N
PCI_EXPRESS_LANE_NT_
PAD_IN_CONFIG_START_P
In Configuration Linkwidth This check fires if the non-PAD lane number

Start, the lane number must is detected in TS1 in Configuration
be set to PAD.
Linkwidth Start.
PAD_IN_CONFIG_START_N
PAD_IN_POLLING_ACT_P
In Polling Active, the lane

number must be set to
PAD.
PAD_IN_POLLING_ACT_N
PAD_IN_POLLING_CFG_P
PAD_IN_POLLING_CFG_N
PCI_EXPRESS_LANE_PAD_
IN_CONFIG_COMPLETE_P
PCI_EXPRESS_LANE_PAD_
IN_CONFIG_COMPLETE_N
This check fires if non-PAD lane number is

detected in TS2 in Polling Configuration
state. This check is enabled only when the
In Polling Configuration,
This check fires if non-PAD lane number is
the lane number must be set detected in TS1 in Polling Active state. This
to PAD.
check is enabled only when the skip link
training option is not set.
In Configuration Complete This check fires if the lane number set to
State, the lane number must PAD is detected in TS2 OS in configuration
be non-PAD in TS2.
complete state. This check is enabled only
453
PCI Express
Monitor Checks

Check ID
Violation
Description
PCI_EXPRESS_LINK_CTRL_
NOT_SAME_TX_P
Link control field of all the

TS1/TS2 ordered sets
should be equal.
Link control field of TS1/TS2 ordered sets

detected on all lanes of the device or
configured link should be the same. This
check fires, if link control field of TS1/TS2
ordered set is not equal in all lanes. This
PCI_EXPRESS_LINK_MISMATCH_ In Recovery State, the link

IN_RECOVERY_P
number must be the same
as set in configuration.
PCI_EXPRESS_LINK_MISMATCH_
IN_RECOVERY_N
This check fires if the link number in

recovery state is different than set in
configuration. This check is enabled only
PCI_EXPRESS_LINK_NUM_
MISMATCH_P
Single link number must be

transmitted on all upstream
lanes in the configuration
state.
This check fires if the link number is

different on different lanes in configuration
state. This check is enabled only when the
In Configuration Complete
State, the link number must
be non-PAD in TS2.
This check fires if the link number set to

PAD is detected in TS2 OS in configuration
complete state. This check is enabled only
NOT_SAME_TX_N
NOT_SAME_RX_P
NOT_SAME_RX_N
PCI_EXPRESS_LINK_NUM_
MISMATCH_N
PCI_EXPRESS_LINK_PAD_
IN_CONFIG_P
IN_CONFIG_N
PCI_EXPRESS_LINK_RESET_
UPSTREAM_P
In Configuration State, the This check fires if TS1 is detected with the
link number must be nonlink number set to PAD in Configuration
PAD for downstream lanes. state for downstream lanes. This check is
option is not set.
Training control reset
should not be issued in the
upstream direction.
Link control reset should not be issued in the

upstream direction. This check fires if reset
bit of the link control field of TS1/TS2
ordered sets sent in the upstream direction is
set. This check is enabled only when the skip
Device should enter

Loopback state after
receiving two TS with
loopback bit set.

in the Loopback state after receiving two TS
OS with loopback bit set.
PCI_EXPRESS_LINK_RESET_
UPSTREAM_N
PCI_EXPRESS_LOOPBK_
NOT_ENTERED_P
PCI_EXPRESS_LOOPBK_
NOT_ENTERED_N
454
PCI Express
Monitor Checks

Check ID
Violation
Description
PCI_EXPRESS_MIN_TS1_
COUNT_VIOLATION_P
At least
MIN_TS1_COUNT
number of TS1 ordered sets
should be transmitted.
The device transmits at least 1024 TS1

ordered sets before transitioning in to
Polling.Configuration state from
Polling.Active state. The minimum number
of TS1 ordered sets that must be transmitted
can be configured through
MIN_TS1_COUNT parameter. By default,
this parameter is set to 1024. This check fires
if TS2 ordered sets are transmitted before
transmitting MIN_TS1_COUNT number of
TS1 ordered sets. This check is enabled only
N_FTS field of all the TS

ordered sets should be the
same.
N_FTS field off TS1/TS2 ordered sets

detected on all lanes of the device or
configured link should be same. This check
fires if n_fts field of TS1/TS2 ordered set is
not the same in all lanes. This check is
option is not set.
A single SKP ordered set

should always be
transmitted after the fast
training sequence.
A SKP ordered set is always transmitted

after the last FTS is transmitted. This check
fires if any other ordered set, Idle data, TL or
DLL packet is detected after the last FTS
ordered set.
COUNT_VIOLATION_N
PCI_EXPRESS_N_FTS_NOT_
SAME_TX_P
SAME_TX_N
SAME_RX_P
SAME_RX_N
PCI_EXPRESS_NO_SKP_
AFTER_FTS_P
PCI_EXPRESS_NO_SKP_
AFTER_FTS_N
PCI_EXPRESS_PROPOSED_
WIDTH_ERROR_TX_P
WIDTH_ERROR_TX_N
WIDTH_ERROR_RX_P
Illegal proposed link width. PCI Express links must consist of 1, 2, 4, 8,

12, 16, or 32 lanes in parallel. Valid D codes
should be detected in the link/lane number
field of the TS1/TS2 ordered sets only on 1,
2, 4, 8, 12, 16, or 32 lanes. This check fires if
valid D codes are detected on illegal number
of lanes. This check is enabled only when the
WIDTH_ERROR_RX_N

downstream port (proposer). This check fires
if D codes are detected only in 3 lanes of the
transmit interface.
upstream device (counter proposer). This
check fires if valid D codes are detected on
only in 7 lanes of the received interface.
PCI_EXPRESS_RECOCFG_
NOT_ENTERED_P
RecoCfg should be entered

first before moving to
RecoIdle.
This check fires if the device enters

Recovery Idle directly before going to
recovery Cfg from recovery LK.
PCI_EXPRESS_RECOCFG_
NOT_ENTERED_N
455
PCI Express
Monitor Checks

Check ID
Violation
Description
PCI_EXPRESS_RECOLK_
NOT_ENTERED_P
RecoLk should be entered

first before moving to
RecoCfg.
This check fires if TS2 is detected in L0

state.
Device should enter Link

Reset state after receiving
two TS with reset bit set.

in the Link Reset state after receiving two TS
OS with reset bit set.
Scrambling can only be

disabled at the end of
configuration state.
Device can disable scrambling in

configuration complete state. This check
fires if it is disabled in a state other than
configuration complete. This check is
option is not set.
SKP ordered sets must be

detected only on 1, 2, 4, 8,
12, 16, or 32 lanes and
must be detected on
consecutive lanes.
SKP Ordered sets should be detected on all

active lanes of the device or configured link.
Also, SKP ordered sets must be detected on
consecutive lanes only. This check fires if
SKP ordered sets are not detected on all
lanes of the device or configured link.
Skip ordered set must not

be transmitted while
compliance pattern is in
progress.
This check fires if SKP is detected during

polling compliance. This check is enabled
only when the skip link training option is not
set.
TS1 ordered sets must be

must be detected on
consecutive lanes.
During link width negotiation, TS1 ordered

sets are transmitted on all active lanes of the
device. After link width negotiation, the TS1
ordered sets should be detected on all lanes
of the configured link. Also, TS1 ordered
sets must be detected on consecutive lanes
only. This check fires if TS1 ordered sets are
not detected on all active lanes of the device,
or on all lanes of the configured link. This
check is enabled only when skip link training
option is not set.
PCI_EXPRESS_RECOLK_
NOT_ENTERED_N
PCI_EXPRESS_RESET_NOT_
ENTERED_P
PCI_EXPRESS_RESET_NOT_
ENTERED_N
PCI_EXPRESS_SCRAMBLING_
DISABLE_ERROR_P
PCI_EXPRESS_SCRAMBLING_
DISABLE_ERROR_N
ALL_LANES_TX_P
ALL_LANES_TX_N
ALL_LANES_RX_P
ALL_LANES_RX_N
PCI_EXPRESS_SKP_XMTD_
DURING_COMPLIANCE_P
PCI_EXPRESS_SKP_XMTD_
DURING_COMPLIANCE_N
PCI_EXPRESS_TS1_NOT_
ALL_LANES_TX_P
ALL_LANES_TX_N
ALL_LANES_RX_P
ALL_LANES_RX_N
456
PCI Express
Monitor Checks

Check ID
Violation
Description
PCI_EXPRESS_TS2_COUNT_
ERROR_P
At least 16 TS2 ordered

sets should be transmitted
after receiving one TS2
ordered set.
When the device is in the

Polling.Configuration,
Configuration.complete, or Recover.rcvrcfg
state, it transmits TS2 ordered sets. The
transmitter should transmit at least 16 TS2
ordered sets after receiving one TS2 ordered
set. This check fires if less than 16
consecutive TS2 ordered sets are detected.
The monitor checks for 16 consecutive TS2
ordered sets after detecting one TS2 ordered
set during link training. This check is
option is not set.
TS2 ordered sets must be

must be detected on
consecutive lanes.
During link width negotiation, TS2 ordered

sets are transmitted on all active lanes of the
device. After link width negotiation, the TS2
ordered sets should be detected on all lanes
of the configured link. Also, TS2 ordered
sets must be detected on consecutive lanes
only. This check fires if TS2 ordered sets are
not detected on all active lanes of the device,
or on all lanes of the configured link. This
Upstream ports should

assign lane numbers only
after they are initialized by
the downstream ports.
After detecting a valid D code in the link

number field, the downstream port initializes
the lane number field in the transmitted
TS1/TS2 ordered sets. The upstream ports
should acknowledge this by initializing the
lane numbers. This check fires if the
upstream port initializes the lane number
fields before the downstream port. This
Upstream ports should not

initiate the link width
negotiation.
Downstream ports initiate link width

negotiation by initializing the link number
field of the transmitted TS1/TS2 ordered
sets. This check fires if the device is an
upstream port and the device initializes the
link number (transmitted TS1/TS2 ordered
sets contain D codes in the link number
field). This check also fires if the device is a
downstream port and the device detects a
valid D code in the received TS1/TS2
ordered sets before they are initialized by the
device. This check is enabled only when the
PCI_EXPRESS_TS2_COUNT_
ERROR_N
ALL_LANES_TX_P
ALL_LANES_TX_N
ALL_LANES_RX_P
ALL_LANES_RX_N
PCI_EXPRESS_UPSTREAM_
PORT_INIT_LANE_NUM_TX_P
PORT_INIT_LANE_NUM_TX_N
PORT_INIT_LANE_NUM_RX_P
PORT_INIT_LANE_NUM_RX_N
PORT_STARTED_LINK_
WIDTH_NEG_TX_P
PORT_STARTED_LINK_
WIDTH_NEG_TX_N
PORT_STARTED_LINK_
WIDTH_NEG_RX_P
PORT_STARTED_LINK_
WIDTH_NEG_RX_N
457
PCI Express
Monitor Checks

Check ID
Violation
Description
PCI_EXPRESS_VALID_
LINK_NUM_TX_P
Link numbers should be

initialized only during the
link width negotiation.
The link number field of TS1/TS2 ordered

sets are initialized to PAD in the Polling state
of the device. This field is assigned with
valid link numbers when the device is in the
Configuration state. This check fires if valid
D codes are detected in the link number field
of TS1/TS2 ordered sets in the Polling state
of the device. This check is enabled only
when skip link training option is not set.
PCI_EXPRESS_VALID_
LINK_NUM_TX_N
PCI_EXPRESS_VALID_
LINK_NUM_RX_P
PCI_EXPRESS_VALID_
LINK_NUM_RX_N
Notes:
2. Checkers with a _TX_P or _TX_N suffix are performed in the transmit direction and
checkers with a _RX_P or _RX_N suffix are performed in the receive direction. All
other checks are performed in both directions.
Data Link Layer Check

Table 14-7 shows the data link layer checks performed by the PCI Express monitor.
Table 14-7. PCI Express Monitor Data Link Layer Checks
Check ID
Violation
Description
PCI_EXPRESS_ACKNAK_
SEQ_NUM_P
The AckNak sequence

number of the transmitted
DLLP should match with the
sequence number of any of
the TLPs in the retry buffer.
Acknowledgments should be issued only

when there are outstanding TLPs. This
check fires if Acknak sequence number of
the detected Ack/Nak DLLP does not match
with the sequence number of the TLPs in the
retry buffer.
Received TL packet should be

acknowledged by either the
Ack or Nak DLL packet
before the expiry of the
Ack_Nak timer.
Acknowledgments must be returned for the

TL packets received without error. This
check fires if the Ack/NAK DLL Packet is
not detected before the expiration of the
AckNak latency timer.
Once retransmission of the

retry buffer is initiated, then
all the contents of the retry
buffer should be retransmitted
before transmitting the new
TLP.
During retry, transmitter should start

retransmission of all old TLPs in the retry
buffer. This check fires if a new TL packet
is transmitted before the retransmission of
all the packets in the retry buffer.
PCI_EXPRESS_ACKNAK_
SEQ_NUM_N
PCI_EXPRESS_ACKNAK_
TIMER_EXPIRED_P
PCI_EXPRESS_ACKNAK_
TIMER_EXPIRED_N
PCI_EXPRESS_ALL_OLD_
TLPs_RETRANSMITTED_P
PCI_EXPRESS_ALL_OLD_
TLPs_RETRANSMITTED_N
458
PCI Express
Monitor Checks
Table 14-7. PCI Express Monitor Data Link Layer Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_CPD_FC1_
FC2_MISMATCH_P
Completion data credit should This check fires if value of completion data
match in InitFC1 and InitFC2. credit is different in InitFC1 and InitFC2.
PCI_EXPRESS_CPD_FC1_
FC2_MISMATCH_N
PCI_EXPRESS_CPH_FC1_
FC2_MISMATCH_P
Completion header credit

should match in InitFC1 and
InitFC2.
This check fires if value of completion

header credit is different in InitFC1 and
InitFC2.
Minimum initial credit

advertisement violation for
completion data credit type.
In the case of end points, the minimum

initial credits advertisement for completion
data should be infinite. In the case of
switches, the minimum initial credit
advertisement is specified as the largest
possible setting of the Max_Payload_Size
divided by FC unit size, or the size of the
largest read request that the switch will ever
generate. This check fires whenever the
specified minimum initial credit
advertisement for posted data is not detected
in InitFC1/2 (CPL) DLL packets.
For endpoints, the minimum

initial credit advertisement for
completion header credit type
should be infinite (8'h00).
In the case of end points, the minimum

initial credit advertisement for completion
header should be infinite. This check fires
whenever the specified minimum initial
credit advertisement for posted data is not
detected in InitFC1/2 (CPL) DLL packets.
DLL Packet should have a

valid 16-bit CRC.
The data integrity of the DLL packet is

ensured through a 16-bit CRC field in the
DLL packet. The CRC bits detected in the
DLL packet should match with the
computed CRC. All bits of the DLL packet
are used for CRC computation except for
framing symbols. This check fires if there is
a mismatch.
Length of DLL packet should

be 6 bytes.
DLL packets should consist of 6 bytes

excluding framing symbols. This check fires
if the length of the DLL packet is not 6
bytes.
DLL or TL packet should not

be detected in the DL_Down
state.
When the physical layer is in down state,

DLL packet or TL packet should not be
detected on the link. This check fires if a TL
or DLL packet is detected.
PCI_EXPRESS_CPH_FC1_
FC2_MISMATCH_N
PCI_EXPRESS_CPLD_
MINIMUM_CREDIT_
VIOLATION_P
PCI_EXPRESS_CPLD_
MINIMUM_CREDIT_
VIOLATION_N
PCI_EXPRESS_CPLH_
MINIMUM_CREDIT_
VIOLATION_P
PCI_EXPRESS_CPLH_
MINIMUM_CREDIT_
VIOLATION_N
PCI_EXPRESS_DLL_PKT_
16BIT_CRC_P
16BIT_CRC_N
LENGTH_P
LENGTH_N
PCI_EXPRESS_DLP_TLP_IN_
DL_DOWN_P
PCI_EXPRESS_DLP_TLP_IN_
DL_DOWN_N
459
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_FC_DLLP_
AFTER_INIT_P
InitFC1/InitFC2 DLLPs
should not be detected once
the VC initialization is done.
InitFC1 and InitFC2 DLL packets are

transmitted during flow control initialization
of the virtual channel. Once the initialization
is complete, these packets should not be
transmitted. This check fires if
InitFC1/InitFc2 DLL packets are detected
after flow control initialization.
InitFC1/InitFC2 DLLPs
should not be detected in the
DL_Active state.
InitFC1 and InitFC2 DLL packets are used

for flow control initialization only. These
packets should not be detected once flow
control initialization is complete for the
enabled virtual channel. This check fires if
InitFC1/InitFC2 DLL packets for VC0 are
detected after flow control initialization.
Sequence number of the first

TL packet detected should be
0000_0000_0000.
TL packets contain sequence number field.

This is a 12-bit field that is incremented
every time a TLP is transmitted. After reset,
this is set to 12'b0. The first TLP detected
should contain a sequence number of 12'b0.
This check fires if the sequence number of
first TLP detected is not zero.
Sequence numbers in the

successive TLPs should be in
the increasing order.
TL packets contain sequence number field.

This is a 12-bit field that is incremented
every time a TLP is transmitted. This check
fires if the sequence number of the
successive TLPs is not in the increasing
order.
This check is not valid for duplicate TLP.
More than 2047 credits

advertisement for completion
data.
This check fires if more than 2047 cpl

header credit detected in InitFC.
PCI_EXPRESS_INFC_CPH_
INVL_P
PCI_EXPRESS_INFC_CPH_
INVL_N

advertisement for cpl header.
This check fires if more than 127 cpl header

credit detected in InitFC.
PCI_EXPRESS_INFC_NPD_
INVL_P

advertisement for non-posted
data.
This check fires if more than 2047 nonposted header credit detected in InitFC.

advertisement for non-posted
header.
This check fires if more than 127 nonposted header credit detected in InitFC.
AFTER_INIT_N
IN_DL_ACTIVE_P
IN_DL_ACTIVE_N
PCI_EXPRESS_FIRST_TLP_
AFTER_LINK_UP_P
PCI_EXPRESS_FIRST_TLP_
AFTER_LINK_UP_N
PCI_EXPRESS_INCR_SEQ_
NUM_TLP_P
PCI_EXPRESS_INCR_SEQ_
NUM_TLP_N
PCI_EXPRESS_INFC_CPD_
INVL_P
PCI_EXPRESS_INFC_CPD_
INVL_N
PCI_EXPRESS_INFC_NPD_
INVL_N
PCI_EXPRESS_INFC_NPH_
INVL_P
PCI_EXPRESS_INFC_NPH_
INVL_N
460
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_INFC_PD_
INVL_P

This check fires if more than 2047 posted
advertisement for posted data. header credit detected in InitFC.
PCI_EXPRESS_INFC_PD_
INVL_N
PCI_EXPRESS_INFC_PH_
INVL_P
More than 127 credit

advertisement for posted
header.
This check fires if more than 127 posted

header credit detected in InitFC.
PCI_EXPRESS_INFC_PH_
INVL_N
PCI_EXPRESS_MAX_
UNACKD_TLP_P
PCI_EXPRESS_MAX_
UNACKD_TLP_N
PCI_EXPRESS_NO_ACK_
DLLP_FOR_TLP_P
Maximum number of
The maximum number of TLP packets that
unacknowledged TLPs should can be outstanding without an
not exceed 2048.
acknowledgment is 2047. This check fires if
a TLP is detected when there are 2047
outstanding TLPs without an
acknowledgment.
Transmitter should send a
NAK DLLP for TLPs
received with an error.
Negative acknowledgment must be returned

for a Nullified TL packet or for a TL packet
with an error. This check fires if the ACK
DLL packet is detected for the Null TL
packet or TL packet with an error.
Transmitter should send an

ACK DLLP for TLPs
received without an error.
Positive acknowledgment must be returned

for the TLPs received without an error. This
check fires if NAK DLLP is detected for the
TLP with no error.
Flow control initialization

must take place for VC0.
This check fires if no InitFCs are received

for VC0 before first TLP.
PCI_EXPRESS_NO_ACK_
DLLP_FOR_TLP_N
PCI_EXPRESS_NO_NAK_
DLLP_FOR_TLP_P
PCI_EXPRESS_NO_NAK_
DLLP_FOR_TLP_N
PCI_EXPRESS_NO_VC0_
INITIALIZTION_P
PCI_EXPRESS_NO_VC0_
INITIALIZTION_N
PCI_EXPRESS_NPD_FC1_
FC2_MISMATCH_P
Non-posted data credit should This check fires if value of non-posted data
PCI_EXPRESS_NPD_FC1_
FC2_MISMATCH_N
PCI_EXPRESS_NPH_FC1_
FC2_MISMATCH_P
Non-posted header credit

should match in InitFC1 and
InitFC2.
This check fires if value of non-posted

header credit is different in InitFC1 and
InitFC2.
Link CRC of the null TL

packet should be logical not
of the computed CRC.
A TL packet is said to be nullified TLP if an

EDB symbol is detected instead of the END
symbol. The CRC field of the nullified TL
packet should be logical not of the actual
CRC computed. This check fires if there is
mismatch.
PCI_EXPRESS_NPH_FC1_
FC2_MISMATCH_N
PCI_EXPRESS_NULL_TLP_
LINK_CRC_P
LINK_CRC_N
461
PCI Express
Monitor Checks
Check ID
Violation
Description
WITH_END_P
Nullified TL packet should

end with the EDB symbol.
A TL packet is said to be nullified TLP if an

EDB symbol is detected instead of the END
symbol. The CRC field of the nullified TL
packet should be logical not of the actual
CRC computed. This check fires if END is
detected instead of EDB and computed CRC
is logical not of the CRC detected.
WITH_END_N
PCI_EXPRESS_PD_FC1_
FC2_MISMATCH_P
Posted data credit should

This check fires if value of posted data
PCI_EXPRESS_PD_FC1_
FC2_MISMATCH_N
PCI_EXPRESS_PD_
MINIMUM_CREDIT_
VIOLATION_P
Minimum initial credit

advertisement violation for
posted data credit type.
PCI_EXPRESS_PD_
MINIMUM_CREDIT_
VIOLATION_N
PCI_EXPRESS_PH_FC1_
FC2_MISMATCH_P
Minimum initial credit advertisement for

posted data is specified as the largest
possible setting of Max_Payload_Size of the
component divided by FC unit size(4 DW).
This check fires whenever specified
minimum initial credit advertisement for
posted data is not detected in InitFC1/2 (P)
DLL packets.
Posted header credit should

This check fires if value of posted header
PCI_EXPRESS_PH_FC1_
FC2_MISMATCH_N
PCI_EXPRESS_REPLAY_
NUM_EXPIRED_P
This check fires if the replay num counter is

expired without receiving an Ack/Nak for
the retransmitted TLPs from the retry buffer.
PCI_EXPRESS_REPLAY_
NUM_EXPIRED_N
Replay num counter has been

expired without receiving an
Ack/Nak DLLP for the
retransmitted TLPs from the
retry buffer.
FIELD_ERROR_P
Reserved bits of DLL packet

should be set to 0.
All the reserved bits of the DLL packet

should be set to 1'b0. This check fires if 1'b1
is detected in reserved fields of the DLL
packet. This check is active if the parameter
RESERVED_FIELD_CHECK_ENABLE is
set.
Transmitter should retransmit

TLPs from the retry buffer
after receiving a Nak.
When Negative acknowledgement (NAK) is

received, the transmitter should start
transmission of retry buffer contents. This
check fires if there is no retransmission of
old TLPs from the retry buffer after the
reception of Nak.
FIELD_ERROR_N
PCI_EXPRESS_RETRY_
AFTER_NAK_P
PCI_EXPRESS_RETRY_
AFTER_NAK_N
462
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_RETRY_
TLPS_P
Transmitter should retransmit

the retry buffer starting from
the oldest unacknowledged
TLP.
For every TLP transmitted, there should be

an Ack/Nak DLLP before the expiry of the
replay timer. When a Nak DLLP is received
or the replay timer is expired, the transmitter
starts transmitting from the oldest
unacknowledged TLP from the retry buffer.
This check fires if the oldest TLPs are not
transmitted during retry.
The data link layer should not

retransmit the TLPs from the
retry buffer without the expiry
of the replay timer or a nak.
Transmitter should wait for the expiry of the

replay timer or the reception of nak before
retransmitting the already transmitted but
unacknowledged TLPs. This check fires if
the transmitter starts retransmitting the
TLPs in the retry buffer before expiry of the
reply timer.
Sequence number of the TLP

following the nullified TLP
should be the same as that of
nullified TLP.
The sequence number is not incremented for

nullified TLPs. The TLP following nullified
TLP should have the same sequence number
of that of nullified TLP. This check fires if
the sequence number of the TLP following
nullified TLP is not the same as that of the
nullified TLP.
TL packet should not be

detected in FC_INIT1 state.
TL packets are detected only when the flow

control initialization is complete. Flow
control initialization is complete when
InitFC2 DLL packets are exchanged
between the devices. This check fires if a
TL packet is detected before flow control
initialization is complete.
TLP should have a valid 32bit Link CRC.
The data integrity of the TL packet is

ensured through a 32-bit CRC field in the
TL packet. The CRC bits detected in the TL
packet should match with the computed
CRC. All bits of the TL packet are included
for CRC computation except for framing
symbols. This check fires if there is a
mismatch.
Uninterrupted sequence of
InitFC1-P, InitFC1-NP, and
InitFC1-Cpl DLLPs not
transmitted in the FC-Init1
state.
In the FC-Init1 state, the device should

transmit an uninterrupted sequence of
InitFC1-P, InitFC1-NP, InitFC1-Cpl
DLLps. This check fires if this sequence is
not proper or the sequence is incomplete.
PCI_EXPRESS_RETRY_
TLPS_N
PCI_EXPRESS_RETRY_
WITHOUT_REPLAY_OR_
NAK_P
PCI_EXPRESS_RETRY_
WITHOUT_REPLAY_OR_
NAK_N
PCI_EXPRESS_SEQ_NUM_
AFTER_NULL_TLP_P
PCI_EXPRESS_SEQ_NUM_
AFTER_NULL_TLP_N
PCI_EXPRESS_TLP_IN_FC_
INIT1_P
PCI_EXPRESS_TLP_IN_FC_
INIT1_N
PCI_EXPRESS_TLP_LINK_
CRC_P
PCI_EXPRESS_TLP_LINK_
CRC_N
PCI_EXPRESS_TX_FC_
DLLP_IN_FC_INIT1_P
PCI_EXPRESS_TX_FC_
DLLP_IN_FC_INIT1_N
Example: This check fires if InitFC1-P,

InitFC1-Cpl is detected.
463
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_TX_FC_
DLLP_IN_FC_INIT2_P
Uninterrupted sequence of
InitFC2-P, InitFC2-NP, and
InitFC2-Cpl DLLPs not
transmitted in the FC-Init2
state.
In the FC-Init2 state, the device should

transmit an uninterrupted sequence of
InitFC2-P, InitFC2-NP, InitFC2-Cpl
DLLps. This check fires if this sequence is
not proper or the sequence is incomplete.
PCI_EXPRESS_TX_FC_
DLLP_IN_FC_INIT2_N
Example: This check fires if InitFC2-P,

InitFC2-Cpl is detected.
PCI_EXPRESS_TX_SAME_
DATAFC_DLLP_FC_INIT1_P
DATAFC_DLLP_FC_INIT1_N
HDRFC_DLLP_FC_INIT1_P
HDRFC_DLLP_FC_INIT1_N
PCI_EXPRESS_UFC_BEFORE_
INITFC_P
Transmitted InitFC1 (P, NP,

Cpl) DLL packets for this
virtual channel should have
consistent DataFC fields.
The flow control packets, InitFC-P, InitFCNP, and InitFC-Cpl contain the credit limit
available. The credit limit values for data
should remain constant across the InitFC-P,
NP, CPL sequences. This check fires if the
credit limit is not constant across the
sequences.
Transmitted InitFC1 (P, NP,

Cpl) DLL Packets for this
virtual channel should have
consistent HdrFC fields.
The flow control packets, InitFC-P, InitFCNP, and InitFC-Cpl contain the Credit Limit
available. The Credit Limit values for
headers should remain constant across the
InitFC-P, NP, CPL sequences. This check
fires if the Credit Limit is not constant
across the sequences.
UFC must not be sent before

InitFC.
This check fires if UFC is detected before

flow control initialization.
UFC need not be transmitted

for infinite advertised cpl
header and data credit.
This check fires if UFC detected for infinite

advertised cpl header and data credit.
Cpl UFC should be

transmitted once every 30 us
(or 120 us for extended sync
bit set).
This check fires if cpl UFC is not detected in

every 30 us (or 120 us for extended sync bit
set).
Completion UFC should have

zero data credit for initialized
infinite completion data
credit.
This check fires if non-zero data credit

detected in completion UFC for infinite
advertised initial completion data credit.
Completion UFC should have

zero header credit for
initialized infinite completion
header credit.
This check fires if non-zero header credit

detected in completion UFC for infinite
advertised initial completion header credit.
PCI_EXPRESS_UFC_BEFORE_
INITFC_N
PCI_EXPRESS_UFC_CPL_
FOR_INFINIT_CREDIT_P
FOR_INFINIT_CREDIT_N
MISSING_P
MISSING_N
PCI_EXPRESS_UFC_CPLD_
INVL_P
PCI_EXPRESS_UFC_CPLD_
INVL_N
PCI_EXPRESS_UFC_CPLH_
INVL_P
PCI_EXPRESS_UFC_CPLH_
INVL_N
464
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_UFC_NP_
FOR_INFINIT_CREDIT_P
UFC need not be transmitted This check fires if UFC detected for infinite
for infinite advertised nonadvertised non-posted header and data
posted header and data credit. credit.
PCI_EXPRESS_UFC_NP_
FOR_INFINIT_CREDIT_N
PCI_EXPRESS_UFC_NP_
MISSING_P
PCI_EXPRESS_UFC_NP_
MISSING_N
PCI_EXPRESS_UFC_NPD_
INVL_P
PCI_EXPRESS_UFC_NPD_
INVL_N
PCI_EXPRESS_UFC_NPH_
INVL_P
PCI_EXPRESS_UFC_NPH_
INVL_N
PCI_EXPRESS_UFC_P_FOR_
INFINIT_CREDIT_P
Non-posted UFC should be

bit set).
This check fires if non-posted UFC is not

detected in every 30 us (or 120 us for
extended sync bit set).
Non-posted UFC should have

zero data credit for initialized
infinite non-posted data
credit.

detected in non-posted UFC for infinite
advertised initial non-posted data credit.
Non-posted UFC should have

zero header credit for
initialized infinite non-posted
header credit.

detected in non-posted UFC for infinite
advertised initial non-posted header credit.
UFC need not be transmitted

for infinite advertised posted
header and data credit.
This check fires if UFC detected for infinite

advertised posted header and data credit.
Posted UFC should be

bit set).
This check fires if posted UFC is not

detected in every 30 us (or 120 us for
extended sync bit set).
Posted UFC should have zero

data credit for initialized
infinite posted data credit.

detected in posted UFC for infinite
advertised initial posted data credit.
Posted UFC should have zero

header credit for initialized
infinite posted header credit.

detected in posted UFC for infinite
advertised initial posted header credit.
Undefined DLL Packet type

detected.
Type field of the data link layer packet

should contain defined values.This check
fires if an undefined value is detected in the
type field.
PCI_EXPRESS_UFC_P_FOR_
INFINIT_CREDIT_N
PCI_EXPRESS_UFC_P_
MISSING_P
PCI_EXPRESS_UFC_P_
MISSING_N
PCI_EXPRESS_UFC_PD_
INVL_P
PCI_EXPRESS_UFC_PD_
INVL_N
PCI_EXPRESS_UFC_PH_
INVL_P
PCI_EXPRESS_UFC_PH_
INVL_N
PCI_EXPRESS_UNDEFINED_
DLLP_ENCODING_P
DLLP_ENCODING_N
465
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_VENDOR_
SPEC_DLLP_TYPE_P
Vendor specific DLL packet

should not be detected.
By default, this check fires if a vendor

specific DLL packet type is detected. To
turn this check off, set VENDOR_
SPECIFIC_ ENCODING_ENABLE to 1.
PCI_EXPRESS_VENDOR_
SPEC_DLLP_TYPE_N
Note that checkers with a _P suffix are active on the rising edge of the clock. Those with an _N
Transaction Layer Checks

Table 14-8 shows the transaction layer checks performed by the PCI Express monitor.
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks
Check ID
Violation
Description
PCI_EXPRESS_ADDRESS_
FORMAT_ERROR_P
The 64-bit addressing format

should not be used when the
address requires only 32-bits.
When 64-bit address format is used (4

DW header), then the higher order 32bits of the address should not be zero.
This check fires if the higher order 32bits are zero.
Only RC/SW downstream

port can send the Attention
Indicator Blink message.
This check fires if Attention Indicator

Blink Message is detected from the
upstream port.
PCI_EXPRESS_ADDRESS_
FORMAT_ERROR_N
PCI_EXPRESS_AI_BL_MSG_
DIRECTION_INVL_P
PCI_EXPRESS_AI_BL_MSG_
DIRECTION_INVL_N
PCI_EXPRESS_AI_OFF_MSG_
DIRECTION_INVL_P
This check is valid for Gen1 only.

Indicator Off message.
PCI_EXPRESS_AI_OFF_MSG_
DIRECTION_INVL_N
PCI_EXPRESS_AI_ON_MSG_
DIRECTION_INVL_P

Indicator On message.
PCI_EXPRESS_AI_ON_MSG_
DIRECTION_INVL_N
PCI_EXPRESS_AT_BT_MSG_
DIRECTION_INVL_P
PCI_EXPRESS_AT_BT_MSG_
DIRECTION_INVL_N
PCI_EXPRESS_BUS_DEV_NOT_
0_FOR_CPL_BEFORE_INIT_
WR_P
PCI_EXPRESS_BUS_DEV_NOT_
0_FOR_CPL_BEFORE_INIT_
WR_N
466

Off Message is detected from the
upstream port.

On Message is detected from the
upstream port.
Only EP/SW upstream port

can send the Attention Button
Pressed message.
This check fires if Attention Button

Pressed Message is detected from the
upstream port.
All completions before initial If a function must generate a

configuration must have bus
Completion prior to the initial device
number and device number 0. Configuration Write Request, then 0s
must be entered into the Bus Number
and Device Number fields. This check
fires if the above rule is violated.
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_CFG1_CPL_NE_
UR_P
PCI EXPRESS Endpoint

must handle a type1
configuration request as an
unsupported request.
This check fires if CPL with status

other than UR is received from EP for
type 1 configuration request.
Attribute field of
configuration request should
be 2'b00.
Configuration requests should always

have default ordering, hardware
enforced cache coherency attribute.
This check fires if any other attribute is
detected for configuration requests.
PCI_EXPRESS_CFG1_CPL_NE_
UR_N
PCI_EXPRESS_CFG_REQ_
ATTR_FIELD_ERROR_P
ATTR_FIELD_ERROR_N
HDR_LENGTH_ERROR_P
HDR_LENGTH_ERROR_N
LEGACY_END_POINT_P
Configuration requests should Configuration requests should have a 3

have a header length of 3
DW header format. This check fires if
DWs.
Configuration requests do not contain a
3 DW header format.
Legacy endpoints should not
generate configuration
requests.
LEGACY_END_POINT_N
LENGTH_FIELD_ERROR_P
LENGTH_FIELD_ERROR_N
PCI_EXPRESS_CFG_REQ_PCI_
EXPRESS_END_POINT_P
Configuration requests should Configuration requests should always

have a length of one data
contain a value of 1 in the length field.
word.
The number of DWs that can be
transacted in a Configuration request is
1 DW. This check fires if the length
field of a configuration request contains
a value other than 1 DW.
PCI Express endpoints should
not generate configuration
requests.
A PCI Express end point must not

generate a configuration request. It
must complete the configuration
request. This check fires if a PCI
Express end point generates a
Configuration request.
Traffic class field of a

be 3'b000.
Configuration requests should always

belong to traffic class 0. This check
fires if the traffic class field of
Configuration request contains a
nonzero value.
BCM bit must not be set in

completion by PCI Express.
BCM Byte Count Modified must not

be set by PCI Express Completers and
can only be set by PCI-X completers.
This check fires if completion is
detected with this bit set.
Completion status for

unsupported request should
be UR.
For Unsupported Requests requiring

Completion, a Completion Status of UR
is returned. This check fires if above
rule is violate.
PCI_EXPRESS_CFG_REQ_PCI_
EXPRESS_END_POINT_N
PCI_EXPRESS_CFG_REQ_TC_
FIELD_ERROR_P
FIELD_ERROR_N
PCI_EXPRESS_COMPLETION_
BCM_BIT_SET_P
BCM_BIT_SET_N
FOR_UR_NE_UR_P
A Legacy end point must not generate

configuration request. This check fires
if a Legacy end point generates a
configuration request.
FOR_UR_NE_UR_N
467
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_COR_ERR_MSG_
DIRECTION_INVL_P

can send a correctable error
message.
This check fires if the correctable error

message is detected from the
downstream port.
Correctable error message

received.
This check fires if the correctable error

message is received.
Completions should have a

header length of 3 DWs.
Completion packets should have a 3

DW header format. This check fires if
Completions contain 4 DW header
format.
Length field is reserved for

Cpl, CplLk completion TLP
packets.
Length field is reserved for completion

packets that do not carry data payload.
This check fires if the length field of
TLP packets of type Cpl and CplLk is
not reserved. This check is active for
transmit interface and if the parameter
RESERVED_FIELD_CHECK_
ENABLE is set.
CPLLK should not be

received when lock is not
established.
This check fires if CPLLK is detected

when lock is not established.

not complete locked memory
read requests.

support Locked requests as a completer.
This check fires if a PCI Express end
point generates CplK completion
packets.
A Root complex should not

complete a locked memory
read request.
A Root complex must not support

Locked requests as a completer. This
check fires if a Cplk completion
packets are generated by a Root
complex.
CPLLK should have TC as 0.
This check fires if CPLLK is detected

with TC 0.
Completion status CA.
This check fires if the request is

completed with CA status.
PCI_EXPRESS_COR_ERR_MSG_
DIRECTION_INVL_N
PCI_EXPRESS_COR_ERR_P
PCI_EXPRESS_COR_ERR_N
PCI_EXPRESS_CPL_HEADER_
LENGTH_ERROR_P
PCI_EXPRESS_CPL_HEADER_
LENGTH_ERROR_N
PCI_EXPRESS_CPL_LENGTH_
FIELD_ERROR_P
PCI_EXPRESS_CPL_LENGTH_
FIELD_ERROR_N
PCI_EXPRESS_CPL_LK_ERR_P
PCI_EXPRESS_CPL_LK_ERR_N
PCI_EXPRESS_CPL_LK_REQ_
PCI_EXPRESS_END_POINT_P
PCI_EXPRESS_CPL_LK_REQ_P
CI_EXPRESS_END_POINT_N
ROOT_COMPLEX_P
ROOT_COMPLEX_N
PCI_EXPRESS_CPL_LK_TC_
NE_0_P
PCI_EXPRESS_CPL_LK_TC_
NE_0_N
PCI_EXPRESS_CPL_STATUS_
CA_P
CA_N
468
This check has severity INFO.
PCI Express
Monitor Checks
Check ID
Violation
Description
CRS_P
Completion status CRS.

completed with CRS status.
CRS_N
FIELD_ERROR_P

Status field of the completion
packets should have only
defined values.
Completion status can be either

Successful Completion (SC),
Unsupported Request (UR),
Configuration Retry Status (CRS), and
Completer Abort. This check fires if
any other status is detected in the status
field of the completion packets.
Completion status UR.

completed with UR status.
FIELD_ERROR_N
UR_P
UR_N
PCI_EXPRESS_ECRC_
ERROR_P

End to end CRC error.
The computed CRC should match with

the ECRC field of the TLP. ECRC is
calculated over the entire TLP packet.
This check fires if the computed CRC
does not match with the detected CRC.
Illegal error signaling

message code.
The message code used for Error

signaling must have defined values.
This check fires if the message code
contains an illegal value.
Error message should have

routing 000.
This check fires if routing other than

000 is detected in the Error message.

can send a fatal error
message.
This check fires if a fatal error message

is detected from the downstream port.
The first DWBE field of the

TLP header should not be
4'b0000 if the length field is
greater than 1.
If the length field for a request indicates

a length greater than 1 DW, the firs
tDWBE field must not equal 0000b.
This check fires if the First DWBE field
has a zero value when the length is
greater than 1 DW.
Fatal error message received.
This check fires if a fatal error message

is received.
PCI_EXPRESS_ECRC_
ERROR_ N
PCI_EXPRESS_ERR_MSG_
CODE_ERROR_P
CODE_ERROR_N
ROUTING_NT_000_P
ROUTING_NT_000_N
PCI_EXPRESS_FATAL_ERR_
MSG_DIRECTION_INVL_P
PCI_EXPRESS_FATAL_ERR_
MSG_DIRECTION_INVL_N
PCI_EXPRESS_FIRST_DW_BE_
NON_ZERO_ERROR_P
PCI_EXPRESS_FIRST_DW_BE_
NON_ZERO_ERROR_N
PCI_EXPRESS_FT_ERR_P
PCI_EXPRESS_FT_ERR_N
469
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_HOT_PLUG_
MSG_CODE_ERROR_P
Illegal hot plug signaling

message code.
The message code used for Hot plug

signaling support signaling must have
defined values. This check fires if the
message code contains an illegal value.
parameter HOT_PLUG_MESSAGE_
ENABLE is set to 1.
Hot Plug message should

have routing 100.

100 is detected in the Hot plug
message.
MSG_CODE_ERROR_N
MSG_ROUTING_NT_100_P
MSG_ROUTING_NT_100_N
PCI_EXPRESS_IGNORED_
MESSAGE_DETECTED_P

Ignored messages should not
be transmitted.
When Hot plug signaling messages are

not supported by the device, these
messages are termed as Ignored
messages. Ignored messages should not
be detected. This check fires if Ignored
messages are detected on the link.
The address and length

combination that results in a
memory access to cross 4K
boundary should not be
specified.
Requests must not specify an

Address/Length which causes a
memory space access to cross 4K
boundary. This check fires if an
Address/Length combination that
causes a memory space access to cross
4K boundary.
Illegal interrupt signaling

message code.
The message code used for interrupt

signaling must have defined values.
This check fires if the message code
contains an illegal value.
INTx message can only be

initiated from the upstream
port.
This check fires if interrupt messages

are detected from the downstream port.
All INTx message should

have the function number
reserved.
This check fires if the non-reserved

function number is detected in INTx
messages.
All INTx messages should

have routing 100.

100 is detected in INTx messages.
PCI_EXPRESS_IGNORED_
MESSAGE_DETECTED_N
ADDRESS_LENGTH_
COMBINATION_P
ADDRESS_LENGTH_
COMBINATION_N
PCI_EXPRESS_INTR_MSG_
CODE_ERROR_P
PCI_EXPRESS_INTR_MSG_
CODE_ERROR_N
PCI_EXPRESS_INTX_FROM_
DOWNSTREAM_PORT_P
PCI_EXPRESS_INTX_FROM_
DOWNSTREAM_PORT_N
PCI_EXPRESS_INTX_MSG_
NON_RSVD_FN_NUMBER_P
NON_RSVD_FN_NUMBER_N
ROUTING_NT_100_P
ROUTING_NT_100_N
470
PCI Express
Monitor Checks
Check ID
Violation
Description
COMPLETER_ID_P
All completions from EP

should have a valid completer
ID.
Functions must capture the Bus and

Device Numbers supplied with all
Configuration Write Requests (Type 0)
completed by the function and supply
these numbers in the Bus and Device
Number fields of the Completer ID for
all completions generated by the
device/function. This check fires if the
completer ID value does not match with
the bus and device number of the
received cfg write request.
All requests initiated from EP

should have a valid requester
ID.

Number fields of the Requester ID for
all Requests initiated by the
device/function. This check fires if the
requester ID value does not match with
the bus and device number of the
received cfg write request.
Attribute field of an I/O

request should be 2'b00.
I/O requests should always have default

ordering, hardware enforced cache
coherency attribute. This check fires if
any other attribute is detected for I/O
requests.
I/O requests should have a

header length of 3 DWs.
I/O requests should have a 3 data word

(DW) header format. This check fires if
the I/O requests do not contain a 3 DW
header format.
I/O requests should have a

length of one data word.
I/O requests should always contain a

value of 1 in the length field. The
number of DWs that can be transacted
in an I/O request is 1 DW. This check
fires if the length field of an I/O request
contains a value other than 1 DW.

not generate I/O requests.

generate I/O requests. This check fires
when the parameter
PCI_EXPRESS_DEVICE_TYPE is 0
and an I/O request is generated.
Traffic class field of an I/O

I/O requests should always belong to

traffic class 0. This check fires if the
traffic class field of I/O request contains
a nonzero value.
COMPLETER_ID_N
PCI_EXPRESS_INVALID_REQ_
ID_P
ID_N
PCI_EXPRESS_IO_REQ_ATTR_
FIELD_ERROR_P
PCI_EXPRESS_IO_REQ_ATTR_
FIELD_ERROR_N
PCI_EXPRESS_IO_REQ_HDR_
LENGTH_ERROR_P
LENGTH_ERROR_N
PCI_EXPRESS_IO_REQ_LENGTH
_FIELD_ERROR_P
PCI_EXPRESS_IO_REQ_LENGTH
_FIELD_ERROR_N
PCI_EXPRESS_IO_REQ_PCI_
EXPRESS_END_POINT_P
PCI_EXPRESS_IO_REQ_PCI_
EXPRESS_END_POINT_N
PCI_EXPRESS_IO_REQ_TC_
FIELD_ERROR_P
FIELD_ERROR_N
471
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_LAST_DW_BE_
ERROR_P
The last DWBE field of the

TLP header should be
4'b0000 if the length field
specified is 1.
If the length field of the TLP header

specifies a length of 1 DW, then the last
DWBE field of the header should
contain a value of 4'b0. This check fires
if the last DWBE field of the header has
a nonzero value when the length
specified is 1.
The last DWBE field of the

TLP header should be
nonzero if the length specified
is greater than 1.
If the length field of TLP header is

greater than 1, then the last DWBE field
should contain a nonzero value. This
check fires when the last DWBE field
of the header has a zero value when the
length specified is greater than 1.
Link is deactivated when

there are pending requests.
This check fires when there are pending

requests while link is deactivated.
Unlock message should not

be used when lock is not
established.
This check fires if unlock message is

detected when lock is not established.

generate locked memory read
requests.

Locked memory read requests. This
check fires if a Legacy end point
generates Locked memory read
requests.

not generate locked memory
read requests.

generate locked requests. This check
fires if a PCI Express end point
generates a Locked request.
Illegal locked transaction

support message code.
The message code used for Locked

transaction support signaling must have
ERROR_N
NON_ZERO_ERROR_P
NON_ZERO_ERROR_N
PCI_EXPRESS_LINK_DOWN_
PENDING_REQUESTS_P
PCI_EXPRESS_LINK_DOWN_
PENDING_REQUESTS_N
PCI_EXPRESS_LK_ERR_P
PCI_EXPRESS_LK_ERR_N
PCI_EXPRESS_LOCK_REQ_
LEGACY_END_POINT_P
LEGACY_END_POINT_N
PCI_EXPRESS_END_POINT_P
PCI_EXPRESS_END_POINT_N
PCI_EXPRESS_LOCKED_TRAN_
MSG_CODE_ERROR_P
PCI_EXPRESS_LOCKED_TRAN_
MSG_CODE_ERROR_N
PCI_EXPRESS_MAX_PAYLOAD_
SIZE_ERROR_P
PCI_EXPRESS_MAX_PAYLOAD_
SIZE_ERROR_N
472
Payload should not exceed the The maximum DWs that can be present
specified maximum number
on a TLP packet is specified in Device
of bytes.
Control Register. This check fires if a
TLP packet with a data payload more
than the specified maximum pay load
size is detected. The TLP packet can be
request or a completion packet.
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_MAX_READ_
REQ_SIZE_ERROR_P
Requester should not request

more than the specified
maximum number of bytes.
The maximum DWs that a device can

request is specified in Device Control
Register. This check fires if the device
requests more number of bytes than
specified by the maximum read request
size. This check is applicable for
memory read requests and Locked
memory read requests.
MRDLK should have TC as

0.
This check fires if MRDLK TLP is

detected with TC 0.
Vendor defined messages not

routed by ID should have byte
8 and 9 reserved.
If ID routing is not used in vendor

defined messages, then bytes 8 and 9
are Reserved. This check fires if nonzero value is detected in byte 8 and 9 of
vendor defined message not routed by
ID.
Attribute field of a message

Attribute field of Message requests is

reserved. Therefore, the attribute field
of message requests should contain a
value of 2'b0. This check fires if the
attribute field of the message request is
nonzero.
REQ_SIZE_ERROR_N
PCI_EXPRESS_MRD_LK_TC_
NE_0_P
PCI_EXPRESS_MRD_LK_TC_
NE_0_N
PCI_EXPRESS_MSG_NOT_
ROUTED_BY_ID_BYT8_9_
RSVD_ERROR_P
PCI_EXPRESS_MSG_NOT_
ROUTED_BY_ID_BYT8_9_
RSVD_ERROR_N
PCI_EXPRESS_MSG_REQ_ATTR_
FIELD_ERROR_P
PCI_EXPRESS_MSG_REQ_ATTR_
FIELD_ERROR_N
PCI_EXPRESS_MSG_REQ_HDR_
LENGTH_ERROR_P
PCI_EXPRESS_MSG_REQ_HDR_
LENGTH_ERROR_N
PCI_EXPRESS_MSG_REQ_
LENGTH_FIELD_ERROR_P
LENGTH_FIELD_ERROR_N
PCI_EXPRESS_MSG_REQ_TC_
FIELD_ERROR_P
Message requests should have Message requests should have a 4 DW

a header length of 4 DWs.
header format. This check fires if
Message requests contain 3 DW header
format.
Length field is reserved for all
messages except for Slot
power, Vendor specific, and
Hot plug signaling messages.
Length field is reserved for all message

requests except Slot power, Vendor
specific, and Hot plug signaling
messages. This check fires if the length
field is not reserved. This check is
active for transmit interface and if the
parameter RESERVED_FIELD_
CHECK_ENABLE is set.
Traffic class field of a

message request should be
3'b000.
Message requests should always belong

to traffic class 0. This check fires if the
traffic class field of message requests
contains a nonzero value.
RC should not initiate a

message packet with routing
000.
This check fires if any MSG/MSGD is

detected with routing 000 from RC.
PCI_EXPRESS_MSG_REQ_TC_
FIELD_ERROR_N
PCI_EXPRESS_MSG_ROUTING_
000_FROM_RC_P
000_FROM_RC_N
473
PCI Express
Monitor Checks
Check ID
Violation
Description
011_FROM_EP_P
EP should not initiate a

message packet with routing
011.
This check fires if any MSG/MSGD is

detected with routing 011 from EP.
Message request detected

should not be of type MsgD.
All messages, except slot power, limit

support and the vendor specified
messages should be of type Msg. These
messages should not carry data
payload. This check fires if detected
TLP type is MsgD for messages, except
slot power, limit support and the vendor
specified messages.
Non-fatal error message

received.
This check fires if a non-fatal error

message is received.
Only unlock message or

MRDLK should be used
when lock has been
established.
This check fires if other than unlock

message or MRDLK is detected when
lock has been established.
This check fires if SSPL is not received
before the first TLP.
PCI_EXPRESS_NO_SSPL_N
SSPL should be sent while

transitioning from
DL_DOWN to DL_UP.
PCI_EXPRESS_NO_TLP_
DIGEST_P
Packet should contain TLP

digest when TD field is 1.
When the header field of the TLP

specifies that the packet contains a TLP
digest, then TLP digest should be
detected. This check fires if TLP Digest
is not detected.
First DWBE should not be

non-contiguous for
Length = 2DW for non-QW
aligned memory request.
For non-QW aligned memory request

of length 2 DW, the first dw byte enable
should be contiguous. This check fires
if above rule is violated.
The first DWBE should not

be non-contiguous for
Length > 2DW.
First dw byte enable should be

contiguous for a length more than
2DW. This check fires if above rule is
violated
011_FROM_EP_N
PCI_EXPRESS_MSG_TYPE_
ERROR_P
PCI_EXPRESS_MSG_TYPE_
ERROR_N
PCI_EXPRESS_NFT_ERR_P
PCI_EXPRESS_NFT_ERR_N
PCI_EXPRESS_NO_LK_ERR_P
PCI_EXPRESS_NO_LK_ERR_N
PCI_EXPRESS_NO_SSPL_P
PCI_EXPRESS_NO_TLP_
DIGEST_N
PCI_EXPRESS_NON_
CONTIGUOUS_FIRST_DW_BE_
ERROR_FOR_LEN_EQ_2DW_
NON_QW_ALIGNED_P
PCI_EXPRESS_NON_
NON_QW_ALIGNED_N
PCI_EXPRESS_NON_
ERROR_FOR_LEN_MT_2DW_P
PCI_EXPRESS_NON_
ERROR_FOR_LEN_MT_2DW_N
474
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_NON_
CONTIGUOUS_LAST_DW_BE_
NON_QW_ALIGNED_P
Last DWBE should not be

non-contiguous for
Length = 2DW for non-QW
aligned memory request.
For non-QW aligned memory request

of length 2 DW, the last dw byte enable
should be contiguous. This check fires
if above rule is violated.
The last DWBE should not be

non-contiguous for
Length > 2DW.
Last dw byte enable should be

contiguous for a length more than
2DW. This check fires if above rule is
violated.

can send a non-fatal error
message.
This check fires if a non-fatal error

message is detected from the
downstream port.
Reserved fields in the TLP

packet should be driven to
zero.
Reserved field of the TLP header must

be 0. This check fires if a nonzero value
is detected in the reserved fields of the
TLP header. This check is active for
transmit interface and if the parameter
ENABLE is set.
PCI_EXPRESS_PARAM_DEVICE_
TYPE_ERR
Illegal value specified for PCI

Express device type.
This check fires if illegal values are

specified for
PCI_EXPRESS_DEVICE_TYPE
parameter.
PCI_EXPRESS_PARAM_MAX_
LINK_WIDTH_ERR
Illegal value specified for

maximum link width
supported.
PCI Express specification specifies that

the allowed link widths are 1, 2, 4, 8,
12, 16, 32. This check fires if the
maximum link width specified is not
equal to any of the above values.
PCI_EXPRESS_PI_BL_MSG_
DIRECTION_INVL_P

port can send the Power
Indicator Blink message.
This check fires if Power Indicator

Blink Message is detected from the
upstream port.
PCI_EXPRESS_NON_
NON_QW_ALIGNED_N
PCI_EXPRESS_NON_
ERROR_FOR_LEN_MT_2DW_P
PCI_EXPRESS_NON_
ERROR_FOR_LEN_MT_2DW_N
PCI_EXPRESS_NON_FATAL_
ERR_MSG_DIRECTION_INVL_P
PCI_EXPRESS_NON_FATAL_
ERR_MSG_DIRECTION_INVL_N
PCI_EXPRESS_NON_ZERO_
RESERVED_FIELD_ERROR_P
PCI_EXPRESS_NON_ZERO_
RESERVED_FIELD_ERROR_N
PCI_EXPRESS_PI_BL_MSG_
DIRECTION_INVL_N
PCI_EXPRESS_PI_OFF_MSG_
DIRECTION_INVL_P

Indicator Off message.
PCI_EXPRESS_PI_OFF_MSG_
DIRECTION_INVL_N
This check fires if Power Indicator Off

Message is detected from the upstream
port.
475
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_PI_ON_MSG_
DIRECTION_INVL_P

Indicator On message.
This check fires if Power Indicator On

Message is detected from the upstream
port.
PCI_EXPRESS_PI_ON_MSG_
DIRECTION_INVL_N
PCI_EXPRESS_PM_ASN_MSG_
ROUTING_NT_100_P

PM Active State Nak message This check fires if routing other than
should have routing 100.
100 is detected in the PM Active State
Nak message.
PCI_EXPRESS_PM_ASN_MSG_
ROUTING_NT_100_N
PCI_EXPRESS_PM_MSG_NON_
RSVD_FN_NUMBER_P
PM Active State Nak message This check fires if the non-reserved

should have the function
function number is detected in PM
number reserved.
Active State Nak message.
PCI_EXPRESS_PM_MSG_NON_
RSVD_FN_NUMBER_N
PCI_EXPRESS_PM_PME_MSG_
ROUTING_NT_000_P

PM PME message should
have routing 000.

000 is detected in the PM PME
message.
PME To Ack message should

have routing 101.

101 is detected in the PME To Ack
message.
Illegal power management

message code.
The message code used for Power

management signaling must have
PME Turnoff message should

have routing 011.

011 is detected in the PM Turnoff
message.
TLP is poisoned.
If the EP bit of TLP with data is 1, then

this check fires.
Reserved encoding for

maximum read request size
field of device control register
should not be used.
The maximum read request size for the

device as a requester can be 128, 256,
512, 1024, 2048, or 4096 bytes. This is
specified in the
maximum_read_request_size field of
the device control register. This check
fires if reserved encodings are specified
in the maximum read request size field
of the device control register.
PCI_EXPRESS_PM_PME_MSG_
ROUTING_NT_000_N
PCI_EXPRESS_PME_2_ACK_
MSG_ROUTING_NT_101_P
PCI_EXPRESS_PME_2_ACK_
MSG_ROUTING_NT_101_N
PCI_EXPRESS_PME_MSG_
CODE_ERROR_P
CODE_ERROR_N
PCI_EXPRESS_PME_TO_MSG_
ROUTING_NT_011_P
PCI_EXPRESS_PME_TO_MSG_
ROUTING_NT_011_N
PCI_EXPRESS_POISONED_TLP_P
PCI_EXPRESS_POISONED_TLP_N
VALUE_FOR_MAX_READ_
REQUEST_SIZE
476
PCI Express
Monitor Checks
Check ID
Violation
Description
VALUE_FOR_MAX_PAYLOAD_
SIZE
Reserved encoding for

maximum payload size field
of device control register
should not be used.
The maximum TLP payload size for the

device can be 128, 256, 512, 1024,
2048, or 4096 bytes. This is specified in
the maximum_payload_size field of the
device control register. This check fires
if reserved encodings are specified in
the maximum pay load size field of the
device control register.
PCI_EXPRESS_ROOT_
COMPLEX_RCVD_CFG_REQ_P
Configuration requests should Configuration requests are issued by

not be issued to root complex. root complex devices. Root complex
devices should not complete a
configuration request. This check fires
if a configuration request is issued to
root complex device.
PCI_EXPRESS_ROOT_
COMPLEX_RCVD_CFG_REQ_N
PCI_EXPRESS_RX_COMPLETION_
TC_ATTR_MISMATCH_P
TC_ATTR_MISMATCH_N
TIMEOUT_P
Received completions should

have the same value for TC
and ATTR fields of the
associated transmitted
requests.
The Traffic class and Attribute field of

the completion packets should match
with the Traffic class and Attribute
field of the request received. This check
fires if there is a mismatch.
Completion not received.
All non-posted TLPs requires

completion. This check fires if
completion is not received within
CPL_TIMEOUT_CLK after the nonposted request is issued.
Completion received without

a request.
Completion packets should not be

transmitted without a receiving request.
This check fires if the completion
packets are detected without a request.
Completions for I/O and

configuration requests should
have a value of 4 in the byte
count field.
I/O and Configuration requests must be

completed in exactly one completion.
That is, the Byte count field of the
completions for I/O and Configuration
requests must contain a value of 4. This
check fires if a value other than 4 is
detected in the Byte count field of I/O,
Configuration completions.
The received completion for

flush request must specify a
length of 1 DW.
All zero length/flush memory read

requests should have completion with a
length of 1 DW. This check fires if
completion with a length other than 1
DW is detected for the flush request.
Locked completions should

be responded to only locked
requests.
CplLK, CplDLK completion packets

should be returned to locked requests
only. This check fires if CplLK or
CplDLK completion packets are
returned to requests other than Locked
requests.
TIMEOUT_N
WITHOUT_REQUEST_P
WITHOUT_REQUEST_N
PCI_EXPRESS_RX_CPL_BYTE_
COUNT_VALUE_ERROR_P
PCI_EXPRESS_RX_CPL_BYTE_
COUNT_VALUE_ERROR_N
PCI_EXPRESS_RX_CPL_LEN_
NT_1DW_FOR_FLUSH_REQ_P
PCI_EXPRESS_RX_CPL_LEN_
NT_1DW_FOR_FLUSH_REQ_N
PCI_EXPRESS_RX_CPL_LK_
FOR_NON_LOCKED_REQ_P
PCI_EXPRESS_RX_CPL_LK_
FOR_NON_LOCKED_REQ_N
477
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_RX_CPL_LWR_
ADDRESS_VALUE_ERROR_P
Lower address field must be

set to zero for all completions
except for memory read
completion.
Lower address field of the completion

packets should be set to zero for all
completions except for memory read
completion. This check fires if the
lower address field of the completion
packet is not zero.
PCI_EXPRESS_RX_CPL_LWR_
ADDRESS_VALUE_ERROR_N
PCI_EXPRESS_RX_CPL_NOT_
UR_FOR_POISONED_CFG_WR_P
Completion with UR should

This check fires if completion with UR
be received for transmitted
is not received for poisoned CFG write
poisoned CFG Write Request. request.
UR_FOR_POISONED_CFG_WR_N
UR_FOR_POISONED_IO_WR_P

be received for transmitted
poisoned IO Write Request.

is not received for poisoned IO write
request.
The completion status CRS

should not be returned for
requests other than
configuration requests.
Completion status Configuration

Request Retry Status (CRS) is issued
only for the configuration requests.
This check fires if CRS status is
detected in the completion packets for
nonconfiguration requests received.
Illegal completion for I/O and

configuration write requests.
Completion packets with data should

not be returned for I/O and
Configuration write requests. This
check fires if completion packets with
data are transmitted for received I/O or
Configuration write requests.
Receiver should not detect a

Completion data when
sufficient credits are not
allocated for the virtual
channel VC-ID.
Receivers FIFO status of the device is

indicated in the flow control packets
transmitted. The transmitted flow
control packets specify the buffer
availability through CREDITS
ALLOCATED. Separate buffers are
maintained for Posted request headers,
Non-Posted request header, Completion
header, Posted data, Non-Posted data,
and Completion data. The far end
device should not transmit a TLP
packet if sufficient buffer space is not
advertised. This check fires if sufficient
buffer space is not available for
completion data.
Unsuccessful completions
should not contain data
payload.
If the completion status is not

Successful Completion, then the
completion packets should not contain
data. This check fires if a CplD packet
is detected with a status other than
Successful Completion.
UR_FOR_POISONED_IO_WR_N
PCI_EXPRESS_RX_CPL_STATUS_
CSR_FOR_NONCFG_
REQ_P
PCI_EXPRESS_RX_CPL_STATUS_
CSR_FOR_NONCFG_
REQ_N
PCI_EXPRESS_RX_CPLD_CPL_
FOR_IO_CFG_WRITE_REQ_P
PCI_EXPRESS_RX_CPLD_CPL_
FOR_IO_CFG_WRITE_REQ_N
PCI_EXPRESS_RX_CPLD_CREDIT_
LIMIT_VIOLATION_P
PCI_EXPRESS_RX_CPLD_CREDIT_
LIMIT_VIOLATION_N
PCI_EXPRESS_RX_CPLD_FOR_
UNSUCCESFUL_CPL_P
PCI_EXPRESS_RX_CPLD_FOR_
UNSUCCESFUL_CPL_N
478
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_RX_CPLH_
CREDIT_LIMIT_VIOLATION_P

completion header when
channel VC-ID.

buffer space is not available for
completion header.
PCI_EXPRESS_RX_MRD_CPL_
LOW_ADDR_N
For received MRD

completion, the lower address
field must indicate lower bits
of byte address for the first
enabled byte of data.
For all Memory Read Completions, the

Lower Address field must indicate the
lower bits of the byte address for the
first enabled byte of data returned with
the Completion. This check fires if
above rule is violated.
PCI_EXPRESS_RX_NO_LOCKED_
COMPLETION_FOR_
LOCKED_REQ_P
CplLK completions must be

returned to locked memory
requests.
Locked memory requests should be

completed by CplLK completions. This
check fires if Locked memory read
requests are responded with Cpl
completions.

Non-Posted data when
channel VC-ID.

buffer space is not available for NonPosted data.
CREDIT_LIMIT_VIOLATION_N
PCI_EXPRESS_RX_MRD_CPL_
LOW_ADDR_P
PCI_EXPRESS_RX_NO_LOCKED_
COMPLETION_FOR_
LOCKED_REQ_N
PCI_EXPRESS_RX_NPD_CREDIT_
LIMIT_VIOLATION_P
PCI_EXPRESS_RX_NPD_CREDIT_
LIMIT_VIOLATION_N
479
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_RX_NPH_CREDIT_
LIMIT_VIOLATION_P

Non-Posted header when
channel VC-ID.

buffer space is not available for NonPosted header.

Posted data when sufficient
credits are not allocated for
the virtual channel VC-ID.

buffer space is not available for Posted
data.

Posted header when sufficient
credits are not allocated for
the virtual channel VC-ID.

buffer space is not available for posted
header.
All read completions should

have data when completion
status is SC.
This check fires if completion without

data is received for the read cycle when
completion status is successful.
PCI_EXPRESS_RX_NPH_CREDIT_
LIMIT_VIOLATION_N
PCI_EXPRESS_RX_PD_CREDIT_
LIMIT_VIOLATION_P
PCI_EXPRESS_RX_PD_CREDIT_
LIMIT_VIOLATION_N
PCI_EXPRESS_RX_PH_CREDIT_
LIMIT_VIOLATION_P
PCI_EXPRESS_RX_PH_CREDIT_
LIMIT_VIOLATION_N
PCI_EXPRESS_RX_RD_CPL_
WITHOUT_DATA_P
PCI_EXPRESS_RX_RD_CPL_
WITHOUT_DATA_N
480
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_SLOT_PWR_MSG_
BIT_31_10_DATA_PAYLOAD_
ERROR_P
Slot power limit support

Data payload of SSPL message should
(SSPL) messages should have have bit 31:10 all 0s. This check fires if
bit 31:10 of data payload all 0. non-zero value is detected in bit 31:10
of the data payload of SSPL message.
BIT_31_10_DATA_PAYLOAD_
ERROR_N
CODE_ERROR_P
Illegal slot power limit

support message code.
The message code used for Slot Power

limit support signaling must have
Slot power limit support

messages should not be of
type Msg.
Slot power limit support messages

should carry a data payload and the
TLP type should be MsgD. This check
fires if the slot power limit support
messages are detected with TLP type
Msg.
SSPL message should have 1

DW length.
This check fires if length other than 1 is

detected in SSPL message.

port can send a SSPL
message.
This check fires if a SSPL message is

detected from the upstream port.
SSPL message should have

routing 100.

100 is detected in the SSPL message.
The higher order three bits of

the Tag field should be
3'b000.
If extended tag field is not supported,

then the maximum number of unique
requests that can be outstanding per
requester is 32. The higher order three
bits of the Tag field is reserved. This
check fires if the higher order three bits
of the tag field is nonzero. This check is
inactive if the extended tag field is
enabled in the Device Control Register.
Device is not permitted to

initiate any non-posted
request before the initial
configuration write cycle.
Prior to the initial Configuration Write

to a device, the device is not permitted
to initiate non-posted requests. This
check fires if any TLP is detected
before initial configuration.
CODE_ERROR_N
TYPE_ERROR_P
TYPE_ERROR_N
PCI_EXPRESS_SSPL_LENTH_
NT_1_P
PCI_EXPRESS_SSPL_LENTH_
NT_1_N
PCI_EXPRESS_SSPL_MSG_
DIRECTION_INVL_P
DIRECTION_INVL_N
ROUTING_NT_100_P
ROUTING_NT_100_N
PCI_EXPRESS_TAG_FIELD_
ERROR_P
PCI_EXPRESS_TAG_FIELD_
ERROR_N
PCI_EXPRESS_TLP_BEFORE_
INITIAL_CONFIG_WRITE_P
INITIAL_CONFIG_WRITE_N
481
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_TLP_DOESNOT_
MAP_TO_ANY_VC_P
TLP detected does not map to

any of the VCs.
A Transaction Layer packet with a

traffic class that is not mapped to any of
the enabled virtual channels enabled is
a malformed TLP. This check fires if a
TLP is detected and its traffic class is
not mapped to any of the enabled VCs.
Tag should be unique for

every non-posted request.
Multiple requests should issue a unique

tag. This check fires if any two requests
with the same tag is detected.
TL packet size error.
The TL packets should contain header,

pay load, TLP digest, Seq Num, and
LCRC. The payload can be present
based on the TLP type. This check fires
if any of the above fields are not
detected.
TLP must not use

uninitialized VC.
A TLP using an uninitialized VC is a

Malformed TLP. This check fires if
TLP is detected using VC, which was
not initialized.
Transmitted completions
should have the same value
for TC and ATTR fields of
the associated received
requests.
The Traffic class and Attribute field of

the completion packets should match
with the Traffic class and Attribute
field of the request received. This check
fires if this condition is violated.
Completion not transmitted.
All non-posted TLPs require

completion. This check fires if
completion is not transmitted within
CPL_TIMEOUT_CLK after the nonposted request is received.
Completion transmitted
without a request.
Completion packets should not be

transmitted without a request. This
check fires if the completion packets
are detected without a corresponding
request.
Completions for I/O and

configuration requests should
have a value of 4 in the byte
count field.
I/O and Configuration requests must be

completed in exactly one completion.
The Byte count field of the completions
for I/O and Configuration requests must
contain a value of 4. This check fires if
a value other than 4 is detected in the
Byte count field of I/O, Configuration
completions.
PCI_EXPRESS_TLP_DOESNOT_
MAP_TO_ANY_VC_N
PCI_EXPRESS_TLP_NON_
UNIQUE_TAG_P
PCI_EXPRESS_TLP_NON_
UNIQUE_TAG_N
PCI_EXPRESS_TLP_PKT_SIZE_
ERROR_P
PCI_EXPRESS_TLP_PKT_SIZE_
ERROR_N
PCI_EXPRESS_TLP_USING_
UNINIT_VC_P
PCI_EXPRESS_TLP_USING_
UNINIT_VC_N
PCI_EXPRESS_TX_COMPLETION_
TC_ATTR_MISMATCH_P
TC_ATTR_MISMATCH_N
TIMEOUT_P
TIMEOUT_N
WITHOUT_REQUEST_P
WITHOUT_REQUEST_N
PCI_EXPRESS_TX_CPL_BYTE_
COUNT_VALUE_ERROR_P
PCI_EXPRESS_TX_CPL_BYTE_
COUNT_VALUE_ERROR_N
482
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_TX_CPL_LEN_
NT_1DW_FOR_FLUSH_REQ_P
The transmitted completion

for received flush request
must specify a length of 1
DW.
All zero length/flush memory read

requests should have completion with a
length of 1 DW. This check fires if
completion with a length other than 1
DW is detected for the flush request.
Locked completions should

be responded to only locked
requests.
CplLK, CplDLK completion packets

should be returned to locked requests
only. This check fires if CplLK or
CplDLK completion packets are
returned to requests other than Locked
requests.
Lower address field must be

set to zero for all completions
except for memory read
completion.
Lower address field of the completion

packets should be set to zero for all
completions except for memory read
completion. This check fires if the
lower address field of the completion
packet is not zero.

be generated for received
poisoned IO Write Request.

is not generated for poisoned IO write
request.
PCI_EXPRESS_TX_CPL_LEN_
NT_1DW_FOR_FLUSH_REQ_N
PCI_EXPRESS_TX_CPL_LK_
FOR_NON_LOCKED_REQ_P
PCI_EXPRESS_TX_CPL_LK_
FOR_NON_LOCKED_REQ_N
PCI_EXPRESS_TX_CPL_LWR_
ADDRESS_VALUE_ERROR_P
PCI_EXPRESS_TX_CPL_LWR_
ADDRESS_VALUE_ERROR_N
PCI_EXPRESS_TX_CPL_NOT_
UR_FOR_POISONED_IO_WR_P
UR_FOR_POISONED_IO_WR_N
UR_FOR_POISONED_CFG_WR_P

be generated for received
is not generated for poisoned CFG
poisoned CFG Write Request. write request.
UR_FOR_POISONED_CFG_WR_N
PCI_EXPRESS_TX_CPL_STATUS_
CSR_FOR_NONCFG_REQ_P
PCI_EXPRESS_TX_CPL_STATUS_
CSR_FOR_NONCFG_REQ_N
PCI_EXPRESS_TX_CPLD_CPL_
FOR_IO_CFG_WRITE_REQ_P
The completion status CRS

should not be returned for
requests other than
configuration requests.
Completion status Configuration

Request Retry Status (CRS) is issued
only for the configuration requests.
This check fires if CRS status is
detected in the completion packets for
nonconfiguration requests.
Illegal completion for I/O and

configuration write requests.
Completion packets with data should

not be returned for I/O and
Configuration write requests. This
check fires if completion packets with
data are transmitted for received I/O or
Configuration write requests.
PCI_EXPRESS_TX_CPLD_CPL_
FOR_IO_CFG_WRITE_REQ_N
483
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_TX_CPLD_CREDIT_
LIMIT_VIOLATION_P
Transmitter should not

generate a Completion data
when sufficient credit limit is
not available for the virtual
channel VC-ID.
The FIFO status of the far end device is

received. The received flow control
packets specify the buffer availability
through CREDIT LIMITS. Separate
buffers are maintained for Posted
request headers, Non-Posted request
header, Completion header, Posted
data, Non-Posted data, and Completion
data. The transmitter should not
transmit a TLP packet if sufficient
buffer space is not advertised. This
check fires if sufficient buffer space is
not available for completion data.
Unsuccessful completions
should not contain data
payload.
If the completion status is other than

Successful Completion, then the
completion packets should not contain
data. This check fires if a CplD
completion packet is detected with a
status other than Successful
Completion.

generate a Completion packet
when the sufficient credit
limit is not available for the
virtual channel VC-ID.

request headers, Non Posted request
data, Non posted data, Completion data.
The transmitter should not transmit a
TLP packet if sufficient buffer space is
not advertised. This check fires if
sufficient buffer space is not available
for completion headers.
PCI_EXPRESS_TX_MRD_CPL_
LOW_ADDR_N
For transmitted MRD

completion, the lower address
field must indicate lower bits
of byte address for the first
enabled byte of data.
For all Memory Read Completions, the

Lower Address field must indicate the
lower bits of the byte address for the
first enabled byte of data returned with
the Completion. This check fires if
above rule is violated.
PCI_EXPRESS_TX_NO_
LOCKED_COMPLETION_FOR_
LOCKED_REQ_P
CplLK completions must be

returned to locked memory
requests.
Locked memory requests should be

completed by CplLK completions. This
check fires if Locked memory read
requests are responded with Cpl
completions.
PCI_EXPRESS_TX_CPLD_CREDIT_
LIMIT_VIOLATION_N
PCI_EXPRESS_TX_CPLD_FOR_
UNSUCCESFUL_CPL_P
PCI_EXPRESS_TX_CPLD_FOR_
UNSUCCESFUL_CPL_N
PCI_EXPRESS_TX_CPLH_
PCI_EXPRESS_TX_MRD_CPL_
LOW_ADDR_P
PCI_EXPRESS_TX_NO_
LOCKED_COMPLETION_FOR_
LOCKED_REQ_N
484
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_TX_NPD_

generate a Non-Posted data
channel VC-ID.

not available for Non-Posted data.

generate a Non-Posted header
channel VC-ID.

for non posted headers.

generate a Posted data when
sufficient credit limit is not
available for the virtual
channel VC-ID.

not available for posted data.
PCI_EXPRESS_TX_NPD_
PCI_EXPRESS_TX_NPH_
PCI_EXPRESS_TX_NPH_
PCI_EXPRESS_TX_PD_CREDIT_
LIMIT_VIOLATION_P
PCI_EXPRESS_TX_PD_CREDIT_
LIMIT_VIOLATION_N
485
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_TX_PH_CREDIT_
LIMIT_VIOLATION_P

generate a Posted header
when the sufficient credit
limit is not available for the
virtual channel VC-ID.
The FIFO status of the adjacent device

is indicated in the flow control packets
for posted headers.
All read completions should

have data when completion
status is SC.
This check fires if completion without

data is detected for the read cycle when
completion status is successful.
Undefined TLP packet type.
Packet type field of the TLP header

should contain only defined values.
This check fires if an undefined packet
type is detected in a TLP.
Undefined message code

group.
The message code should be any one of

the Base line Message group. This
check fires if the message code does not
belong to any of the Base line Message
group messages.
PCI_EXPRESS_TX_PH_CREDIT_
LIMIT_VIOLATION_N
PCI_EXPRESS_TX_RD_CPL_
WITHOUT_DATA_P
PCI_EXPRESS_TX_RD_CPL_
WITHOUT_DATA_N
HEADER_FIELD_P
HEADER_FIELD_N
MSG_CODE_GROUP_P
MSG_CODE_GROUP_N
PCI_EXPRESS_UNLOCK_MSG_
NON_RSVD_FN_NUMBER_P
Unlock message should have This check fires if the non-reserved

the function number reserved. function number is detected in unlock
message.
NON_RSVD_FN_NUMBER_N
ROUTING_NT_011_P
Unlock message should have

routing 011.

011 is detected in the Unlock message.
Vendor Defined messages

should have routing
100/011/010/000.

100/011/010/000 is detected in the
vendor Defined message.
ROUTING_NT_011_N
PCI_EXPRESS_VENDOR_MSG_
ROUTING_NT_VALID_P
PCI_EXPRESS_VENDOR_MSG_
ROUTING_NT_VALID_N
486
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_VENDOR_
SPECIFIC_MSG_CODE_
ERROR_P
Illegal vendor specific

message code.
The message code used for Vendor

defined message signaling must have
PCI_EXPRESS_VENDOR_
SPECIFIC_MSG_CODE_
ERROR_N
Note that checkers with a _P suffix are active on the rising edge of the clock. Those with an _N
Power Management Checks

Table 14-9 shows the power management checks performed by the PCI Express monitor.
Table 14-9. PCI Express Monitor Power Management Checks
Check ID
Violation
Description
PCI_EXPRESS_ACK_
WITHOUT_PM_
COMMAND_P
PCI_EXPRESS_ACK_
WITHOUT_PM_
COMMAND_N
PM_Request_Ack DLL
packet should not be
transmitted without receiving
PM_Enter_L1,
PM_Enter_L23, or
PM_Active_State_Request_
L1 DLL packet.
Downstream ports should transmit a

PM_Request_Ack DLL packet in response
to PM_Enter_L1, PM_Enter_L23, or
PM_Active_State_Request_L1 DLL packet
only. This check fires if a PM_Request_Ack
is transmitted without receiving a
PM_Enter_L1, PM_Enter_L23, or
PM_Active_State_Request_L1 DLL
packet.
PCI_EXPRESS_DLLP_IN_
L0S_P
No DLLP communication
allowed in L0s.
This check fires if DLLP is detected in L0s.
allowed in L1.
This check fires if DLLP is detected in L1.
allowed in L2.
This check fires if DLLP is detected in L2.
L0S_N
L1_P
L1_N
L2_P
L2_N
487
PCI Express
Monitor Checks
Table 14-9. PCI Express Monitor Power Management Checks (cont.)

Check ID
Violation
Description
PCI_EXPRESS_IDLE_OS_
WITHOUT_ACK_P
Downstream ports should not

transit to electrical idle state
without receiving
PM_Request_Ack DLL
packet.
Downstream ports should wait for a

PM_Request_Ack DLL packet before
transitioning its transmit lanes to an
electrical idle state. This check fires if an
electrical idle ordered set is transmitted
before receiving a PM_Request_Ack DLL
packet and any of PM_Enter_L1,
PM_Enter_L23, or
packets are transmitted.
Device must not enter L0s

when ASPM L0s entry is
disabled.
When the ASPM control field for a

component is set to 10b (L1 only), a ports
transmitter must not enter L0s. This check
fires if L0s_entry_supported is 0 and the
device enters L0s.
PM_Active_State_Nak
without receiving
L1 DLL packet.
Downstream ports should transmit a

PM_Active_State_Nak message in response
to a PM_Active_State_Request_L1 DLL
packet only. This check fires if a
PM_Active_State_Nak is transmitted
without receiving a PM_Active_
State_Request_L1 DLL packet.

transmit
PM_Active_State_Nak TL
packet.
The PM_Active_State_Nak message is

issued by downstream ports in response to a
packet. This check fires when a
PM_Active_State_Nak message is
transmitted by an upstream port
(downstream component).

transmit PM_Enter_L1,
PM_Enter_L23,
L1 DLL packets.
Upstream ports (downstream component)

initiate transition to L1, L23 states by
transmitting PM_Enter_L1,
PM_Enter_L23, and
packets. Downstream ports must respond to
these DLL packets. This check fires when a
PM_Active_State_Request_L1 DLL packet
is transmitted by a downstream port
(upstream component).
Upstream port should not

transmit PM_Enter_L23
DLL packet without
acknowledging the received
PME_Turn_Off message.
Upstream ports (downstream components)

initiate transition to an L2 state only after
acknowledging the received
PME_Turn_Off message with a
PME_TO_ACK message. This check fires
when PM_Enter_L23 DLL packet is
transmitted without acknowledging the
WITHOUT_ACK_N
PCI_EXPRESS_L0S_ENTRY_
WHEN_DISABLED_P
PCI_EXPRESS_L0s_ENTRY_
WHEN_DISABLED_N
PCI_EXPRESS_NAK_
WITHOUT_PM_REQ_P
PCI_EXPRESS_NAK_
WITHOUT_PM_REQ_N
PCI_EXPRESS_PM_ACTIVE_
STATE_NAK_UPSTREAM_P
PCI_EXPRESS_PM_ACTIVE_
STATE_NAK_UPSTREAM_N
PCI_EXPRESS_PM_ENTER_
DOWNSTREAM_P
DOWNSTREAM_N
L23_BEFORE_ACK_P
L23_BEFORE_ACK_N
488
PCI Express
Monitor Checks

Check ID
Violation
Description
PCI_EXPRESS_PM_PME_
DOWNSTREAM_P

transmit PM_PME message.
Upstream ports (downstream components)

are allowed to request a power management
event by transmitting a PM_PME message.
For example: End points can request a
power management event by issuing a
PM_PME message to the Root complex.
This check fires when a PM_PME message
is transmitted by a downstream port
(upstream component).
PCI_EXPRESS_PM_PME_
DOWNSTREAM_N
PCI_EXPRESS_PM_REQUEST_ Upstream ports should not

K_UPSTREAM_P
transmit PM_Request_Ack
DLL packet.
PCI_EXPRESS_PM_REQUEST_
ACK_UPSTREAM_N
PM_Request_Ack DLL packets are issued

by downstream ports in response to
PM_Enter_L1, PM_Enter_L23, and
packets issued by an upstream port. This
check fires when a PM_Request_Ack DLL
packet is transmitted by an upstream port
PCI_EXPRESS_PM_TURN_
OFF_UPSTREAM_P

transmit PME_Turn_Off
message.
The PME_Turn_Off message is a broadcast

message issued by a root complex. This
message must always be sent in the
downstream direction. This check fires
when a PME_Turn_Off message is
transmitted by an upstream port
PME_TO_Ack message
without receiving
Upstream ports should transmit a

PME_TO_Ack message in response to a
PME_Turn_Off message only. This check
fires if a PME_TO_Ack message is
transmitted without receiving a

transmit PME_TO_ACK
message.
Upstream ports (downstream component)

must acknowledge the PME_Turn_Off
request with a PME_TO_ACK DLL packet.
The PME_TO_ACK DLL packet is always
sent in the upstream direction. This check
fires when a PME_TO_ACK DLL packet is
transmitted by a downstream port (upstream
component).
No TLP communication
allowed in L0s.
This check fires if TLP is detected in L0s.
allowed in L1.
This check fires if TLP is detected in L1.
allowed in L2.
This check fires if TLP is detected in L2.
OFF_UPSTREAM_N
PCI_EXPRESS_PME_ACK_
WITHOUT_TURN_OFF_P
WITHOUT_TURN_OFF_N
PCI_EXPRESS_PME_TO_
ACK_DOWNSTREAM_P
PCI_EXPRESS_PME_TO_
ACK_DOWNSTREAM_N
PCI_EXPRESS_TLP_IN_L0S_P
PCI_EXPRESS_TLP_IN_L0S_N
PCI_EXPRESS_TLP_IN_L1_P
PCI_EXPRESS_TLP_IN_L1_N
PCI_EXPRESS_TLP_IN_L2_P
PCI_EXPRESS_TLP_IN_L2_N
489
PCI Express
Monitor Checks

Check ID
Violation
Description
PCI_EXPRESS_TLPS_AFTER_
ACK_P
New TL packets should not

be transmitted by the down
stream ports after
transmitting
PM_Request_Ack message.
Downstream ports should not transmit any

TL packet after issuing a PM_Request_Ack
DLL packet. This check fires when a TL
packet is transmitted after issuing a
PM_Request_Ack DLL packet.
New TL packets should not

be transmitted after
transmitting PM_Enter_L1,
PM_Enter_L23, or
L1 messages.
Upstream ports should not transmit any TL

packet after issuing a PM_Enter_L1,
PM_Enter_L23, or
PM_Active_State_Request DLL packet.
They can receive TL DLL packets. This
check fires when a TL packet is transmitted
after issuing a PM_Enter_L1,
PM_Enter_L23,or PM_Active_
State_Request_L1 DLL packet.
PM_Enter_L1,
PM_Enter_L23,
L1 DLL packets should not
be transmitted when TL
packets are outstanding.
Upstream ports wait until all the TL packets

are acknowledged before transmitting the
packets. This check fires if a PM_Enter_L1,
PM_Enter_L23, or PM_Active_State_
Request_L1 DLL packet is transmitted
when TL packets are outstanding.
PM_Request_Ack DLL
packet should not be
transmitted when TL packets
are outstanding.
Downstream ports wait until all the TL

packets are acknowledged before
transmitting a PM_Request_Ack DLL
packet. This check fires if a
PM_Request_Ack DLL packet is
transmitted when TL packets are
outstanding.
ACK_N
PM_P
PM_N
PCI_EXPRESS_TLPS_
OUTSTANDING_P
PCI_EXPRESS_TLPS_
OUTSTANDING_N
PCI_EXPRESS_TLPS_
OUTSTANDING_WHEN_
ACK_P
PCI_EXPRESS_TLPS_
OUTSTANDING_WHEN_
ACK_N
Notes:
2. Power management checks are active when both link layer and transaction layer checks
are enabled.
490
PCI Express
Monitor Checks
Table 14-10. Receive Checks

Check ID
Violation
Description
PCI_EXPRESS_ACK_RCVD_
WITHOUT_PM_ENTER_P
PM_Request_Ack should not be

issued in the downstream
direction without a
PM_Enter_L1, PM_Enter_L23,
or
PM_Active_State_Request_L1
DLL packet.
Upstream ports should receive a

PM_Request_Ack DLL packet in
response to PM_Enter_L1,
PM_Enter_L23, or
packet only. This check fires if a
PM_Request_Ack DLL packet is
received by an upstream port without
transmitting a PM_Enter_L1,
PM_Enter_L23, or
packet.
PM_Active_State_Nak message
upstream direction.
PM_Active_State_Nak messages are

issued by downstream ports in response
to an PM_Active_State_Request_L1
DLL packet. This check fires when a
received by a downstream port (upstream
component).
PM_Active_State_Nak message
downstream direction without a
DLL packet.

PM_Active_State_Nak message in
response to a
packet. This check fires if a
received by an upstream port without
transmitting a
packet.
PM_Enter_L23 DLL packet

should not be issued before the
PME_TO_Ack message is
issued.
Downstream ports should not receive a

PM_Enter_L23 DLL packet without
receiving a PME_TO_Ack message.
This check fires if a PM_Enter_L23 DLL
packet is received without a
PME_TO_Ack message.
and
DLL packets should not be
issued in the downstream
direction.
Upstream ports (downstream

components) initiates transition to L1,
L23 states by transmitting
PM_Enter_L1, PM_Enter_L23, and
packets. Downstream ports must respond
to these DLL packets. This check fires
when a PM_Enter_L1, PM_Enter_L23,
or PM_Active_State_Request_L1 DLL
packet is received by an upstream port
PCI_EXPRESS_ACK_RCVD_
WITHOUT_PM_ENTER_N
PCI_EXPRESS_ACTIVE_
STATE_NAK_
DOWNSTREAM_P
PCI_EXPRESS_ACTIVE_
STATE_NAK_
DOWNSTREAM_N
PCI_EXPRESS_NAK_
WITHOUT_REQ_
UPSTREAM_P
PCI_EXPRESS_NAK_
WITHOUT_REQ_
UPSTREAM_N
L23_BEFORE_ACK_
UPSTREAM_P
L23_BEFORE_ACK_
UPSTREAM_N
UPSTREAM_P
UPSTREAM_N
491
PCI Express
Monitor Checks
Table 14-10. Receive Checks (cont.)

Check ID
Violation
Description
PCI_EXPRESS_PM_REQUEST PM_Request_Ack DLL packet

_ACK_DOWNSTREAM_P
upstream direction.
PCI_EXPRESS_PM_REQUEST
_ACK_DOWNSTREAM_N
PM_Request_Ack DLL packets are

issued by downstream ports in response
to PM_Enter_L1, PM_Enter_L23, and
packets issued by an upstream port. This
check fires when a PM_Request_Ack
DLL packet is received by a downstream
port (upstream component).
PCI_EXPRESS_PM_PME_
UPSTREAM_P
PM_PME message should not

be issued in the downstream
direction.

components) are allowed to request a
power management event by transmitting
a PM_PME message. For example: End
points can request a power management
event by issuing a PM_PME message to
a root complex. This check fires when a
PM_PME message is received by an
upstream port (downstream component).
PME_Turn_Off message should

not be issued in the upstream
direction.
PME_Turn_Off messages are broadcast

messages issued by a root complex. This
message must always be sent in the
downstream direction. This check fires
when a PME_Turn_Off message is
received by a downstream port (upstream
component).
PME_TO_Ack message should

not be issued in the downstream
direction.

components) must acknowledge a
PME_Turn_Off request with a
PME_TO_ACK DLL packet. The
PME_TO_ACK DLL packet is always
sent in an upstream direction. This check
fires when a PME_TO_ACK DLL
packet is received by an upstream port
PME_TO_Ack message should

not be issued in the upstream
direction without a

PME_TO_Ack message without
transmitting a PME_Turn_Off message.
This check fires if a PME_TO_Ack
message is received without transmitting
a PME_Turn_Off message.

should not be detected without
transmitting PM_Request_Ack
DLL packet.
Downstream ports should not receive an

electrical idle ordered set on its receive
lanes without acknowledging the
received PM_Enter_L1, PM_Enter_L23,
or PM_Active_State_Request_L1 DLL
packet by a PM_Request_Ack DLL
packet. This check fires if the above rule
is violated.
PCI_EXPRESS_PM_PME_
UPSTREAM_N
OFF_DOWNSTREAM_P
OFF_DOWNSTREAM_N
PCI_EXPRESS_PME_TO_
ACK_UPSTREAM_P
PCI_EXPRESS_PME_TO_
ACK_UPSTREAM_N
PCI_EXPRESS_PME_TO_
ACK_WITHOUT_TURN_
OFF_P
PCI_EXPRESS_PME_TO_
ACK_WITHOUT_TURN_
OFF_N
PCI_EXPRESS_RX_IDLE_
OS_WITHOUT_ACK_P
PCI_EXPRESS_RX_IDLE_
OS_WITHOUT_ACK_N
492
PCI Express
Monitor Checks
Table 14-10. Receive Checks (cont.)

Check ID
Violation
Description
PCI_EXPRESS_RX_TLPS_
AFTER_PM_P
TL packets should not be issued

once PM_Enter_L1,
PM_Enter_L23, or
DLL packet is issued.
Downstream ports should not receive TL

packets after receiving a PM_Enter_L1,
PM_Enter_L23, or
packet. This check fires if the above rule
is violated.
PM_Request_Ack message
should not be issued when the
TL packets are outstanding.

PM_Request_Ack DLL packet only after
all the TL packets were acknowledged by
it. This check fires if a PM_Request_Ack
DLL packet is received when all the TL
packets are not acknowledged by the link
layer.
OUTSTANDING_PM_P
or
DLL packet should not be issued
when TL packets are
outstanding.

packet unless all the TL packets issued
by it have been acknowledged. This
check fires if the above rule is violated.
PCI_EXPRESS_TL_PKT_
AFTER_ACK_UPSTREAM_P
TL packets should not be issued Upstream ports should not receive any
once the PM_Request_Ack DLL TL packets after receiving a
packet is issued.
PM_Request_Ack DLL packet. This
check fires if a TL packet is received
after receiving a PM_Request_Ack DLL
packet.
AFTER_PM_P
OUTSTANDING_P
OUTSTANDING_N
PCI_EXPRESS_TL_PKT_
AFTER_ACK_UPSTREAM_N
Notes:
2. Power management checks are active when both link layer and transaction layer checks
are enabled.
PIPE Interface Checks

Table 14-11 shows the PIPE interface checks performed by a PIPE-configured monitor.
Table 14-11. PIPE Interface Checks
Check ID
Violation
Description
PIPE_16_BIT_COM_ON_
HIGH
For 16 bit interface, MAC

should always align the EIOS
so that COM is on the lower
order data lines TXData[7:0]
This check fires if COM is detected on the

higher order data lines during EIOS.
PIPE_DECODE_ERR_NO_
EDB_SYM
RxStatus indicates 8B/10B

Decode Error, but 'RxData'
does not contain EDB symbol.
When RxStatus indicates decode error,

then RxData should contain EDB symbol.
This check fires if above rule is violated.
493
PCI Express
Monitor Checks
Table 14-11. PIPE Interface Checks (cont.)

Check ID
Violation
Description
PIPE_DECODE_ERROR
Decode Error(RxStatus 100).
When RxStatus contains 100, it is a decode

error.
PIPE_DISPARITY_ERROR
Disparity Error(RxStatus 111).
When RxStatus contains 111, it is a

disparity error.
PIPE_EB_OVERERFLOW_
ERROR
Elastic Buffer Overflow Error.
When RxStatus contains 101, it is a elastic

buffer overflow error.
PIPE_EB_UNDERFLOW_
ERROR
Elastic Buffer Underflow Error. When RxStatus contains 110, it is a elastic

buffer underflow error.
PIPE_ILLEGAL_POWER_
DOWN_COMMAND
Illegal power down command.

MAC layer should direct the
PHY layer to legal states only.
P0, P0s, P1, and P2 are the power states of

a PHY component. MAC can transit the
PHY component only from P0 to P0s, P0
to P1, P0 to P2, P0s to P0, P1 to P0, and P2
to P1. All other transitions are illegal. This
check fires when the MAC layer initiates
an illegal transition. This check is enabled
only when the skip link training option is
not set.
PIPE_PHYSTATUS_
ASSERTED_MORE_
THAN_ONE_CLOCK
Phystatus should be asserted

for only one clock cycle.
The MAC Layer component directs the

PHY Layer components power states
transition by a driving suitable command
on the Power_Down[1:0] signals. The
PHY layer component indicates a
successful state transition by asserting the
Phystatus signal for only one clock cycle.
This check fires if the Phystatus signal is
asserted for more than one clock cycle.
This check is enabled only when skip link
PIPE_PHYSTATUS_
DURING_RESET
During Reset#, PhyStatus

should be asserted.
This check fires if Phystatus is de-asserted

during reset.
PIPE_POWERDOWN_
DURING_RESET
During Reset#, PowerDown

should be P1.
This check fires if Powerdown is not P1

state during reset.
PIPE_POWERDOWN_NOT_
P0_IN_L0
PowerDown should be P0 in L0
state.
This check fires if other than P0

Powerdown is detected in L0.
PIPE_POWERDOWN_NOT_
P0s_IN_L0s
PowerDown should be P0s

This check fires if other than P0s
when transmitter is in L0s state. Powerdown is detected in L0s.
PIPE_POWERDOWN_NOT_
P1_IN_L1_L2_DETECT_
DISABLE
PowerDown should be P1 in
This check fires if other than P1
L1, L2, Detect, or Disable state. Powerdown is detected in L1, L2, detect,
or disable state.
PIPE_REC_DETECT_
PHYSTATUS_DEASSERTED
During receiver detection,

PhyStatus should be asserted
when RxStatus is 011.
This check fires if PhyStaus is not asserted

when RxStatus contains the value 011
during receiver detection.
PIPE_REC_DETECT_
RXSTATUS_INVALID
During receiver detection,

RxStatus should contain value
000/011.
This check fires if RxStatus contains a

value other than 000/011 during receiver
detection.
494
PCI Express
Monitor Checks

Check ID
Violation
Description
PIPE_RX_POLARITY_
During Reset#, RxPolarity
ASSERTED_DURING_RESET should be de-asserted.
This check fires if RxPolarity is asserted

during reset.
PIPE_RX_POLARITY_IN_
OTHERTHAN_POL_CONFIG
RxPolarity can only be asserted

in the polling Configuration
state.
This check fires if RxPolarity is asserted in

a state other than Polling Configuration.
PIPE_RXSTATUS_001_
NOT_ALIGN_WITH_COM
RxStatus can be 001 only

during clock when COM of
SKIP OS is received.
This check fires if RxStatus is 001 in the

clock cycle not containing COM of SKIP
OS.
PIPE_RXSTATUS_010_
NOT_ALIGN_WITH_COM
RxStatus can be 010 only

during clock when COM of
SKIP OS is received.
This check fires if RxStatus is 010 in the

clock cycle not containing COM of SKIP
OS.
PIPE_SKP_ADDED_
RXSTATUS_NOT_001
RxStatus not containing 001,

but skip is added.
RxStatus 001 indicates addition of skip.

This check fires if skip is added, but
Rxstatus does not contains 001.
PIPE_SKP_REMOVED_
RXSTATUS_NOT_010
RxStatus not containing 010,

but skip is removed.
RxStatus 010 indicates removal of skip.

This check fires if skip is removed, but
Rxstatus does not contains 010.
PIPE_TX_COMPLIANCE_
During Reset#, TxCompliance
ASSERTED_DURING_RESET should be de-asserted.
This check fires if TxCompliance is

asserted during reset.
PIPE_TX_COMPLIANCE_
IN_OTHERTHAN_POL_
COMP
TxCompliance can only be

asserted in the polling
Compliance state.
This check fires if TxCompliance is

asserted in a state other than Polling
Compliance.
PIPE_TX_COMPLIANCE_
MORE_THAN_ONE_CLOCK
TxCompliance should not be

asserted more than one clock
cycle.
During the start of the transmission of the

compliance pattern, the running disparity is
set to -ve. TxCompliance signals the PHY
layer when to set the running disparity -ve.
The TxCompliance signal should be
asserted for only one clock. This check
fires if the signal is asserted for more than
one clock cycle. This check is enabled only
when the skip link training option is not
set.
PIPE_TX_DETECT_RX_
ASSERTED
TxDetectRx/Loopback should
be asserted only when the PHY
is P1, P0 state.
Receiver detection should be performed

when the PHY is in a P1 power state.
Loopback should be performed when the
PHY is in a P0 power state. When the PHY
is in a P0s or P2 state, neither receiver
detection nor loopback are performed. This
PIPE_TX_DETECT_RX_
During Reset#,
ASSERTED_DURING_RESET TxDetectRxLoopback should
be de-asserted.
This check fires if TxDetectRxLoopback is

asserted during reset.
495
PCI Express
Monitor Checks

Check ID
Violation
Description
PIPE_TX_DETECT_RX_
DEASSERT_ERROR
TxdetectRx/Loopback should
be de-asserted at the clock edge
where the PHY component
signals the completion of
receiver detection by asserting
PhyStatus for one clock.
While performing receiver detection, once

asserted the TxDetectRx/Loopback signal
should be kept asserted until the PHY
component completes the receiver
detection sequence. The completion of the
receiver detection sequence is indicated by
asserting the Phystatus signal for one clock
cycle. The MAC layer component should
de-assert the TxDetectRx/Loopback signal
when it samples the Phystatus signal
asserted. This check fires if the
TxdetectRx/Loopback signal is not kept
asserted until the assertion of the Phystatus
signal or is not de-asserted after sampling
the Phystatus signal. This check is enabled
only when the skip link training option is
not set.
PIPE_TX_ELECIDLE_
DEASSERTED_DURING_
RESET
During Reset#, TxElecIdle

should be asserted.
This check fires if TxElecIdle is deasserted during reset.
PIPE_TXCOMPLIANCE_
RXPOLARITY_ASSERTED
TxCompliance and RxPolarity

should only be asserted when
the PHY is in P0 state.
TxCompliance and RxPolarity signals

should be asserted only when the PHY is in
an active state (P0). This check fires if
TxCompliance and RxPolarity signals are
asserted in any other PHY states. This
PIPE_TXDETECTRX_
TXELECIDLE_ASSERTED
TxdetectRx/Loopback and
TxElecidle should not be
asserted together when the
PHY is in P0 state.
Receiver detection should be performed

when the PHY is in a P1 power state.
Loopback should be performed when the
PHY is in a P0 power state. When the PHY
is a P0 state, TxDetectRX/Loopback and
TxElecidle should not be asserted together.
PIPE_TXELECIDLE_NOT_
ASSERTED
TxElecidle must always be

asserted while in power down
states P0s and P1.
TxElecidle should be kept asserted as long

as the PHY is in P0s and P1 states. This
check fires if the TxElecidle signal is deasserted when the PHY is in P0s and P1
states. This check is enabled only when
496
PCI Express
Monitor Checks
Table 14-12. PCI Express Gen2 Physical Layer Checks

Check ID
Violation
Description
PCI_EXPRESS_GEN2_EIE_
SYMBOL_IN_2_5_GT_P
Electrical Idle exit(EIE K28.7)

symbol should not be used on
speed 2.5 GT/s.
EIE symbol is used in EIEOS and sent

prior to sending FTS on speeds other than
2.5 GT/s. This check fires if this symbol is
detected on 2.5 GT/s.
SYMBOL_IN_2_5_GT_N
INCONSISTENT_IN_EIEOS_P
EIE symbol should be part of

For Electrical Idle Exit Sequence Ordered
EIEOS consistently from index Set(EIEOS), EIE should consistently
1 to 14.
appear from symbol number 1 to 14. This
check fires if EIE count is not equal to 14
INCONSISTENT_IN_EIEOS_N
in EIEOS or it does not appear
consecutively.
IN_DLLP_TLP_P
EIE symbol should not be part

of DLL or TL packet.
IN_DLLP_TLP_N
PCI_EXPRESS_GEN2_
COMPLIANCE_RECEIVE_
SET_IN_TS2_P
EIE symbol should not be part of the TL or

DLL packet. It should always be part of
EIEOS or sent prior to FTS. This check
fires if an EIE symbol is detected in TL or
DLL packet.
Compliance Receive bit should Compliance receive bit can only be set in
not be set in TS2 OS.
TS1 OS. This bit is reserved in TS2. This
check fires if bit 4 of symbol 5 of TS2 is set
to 1.
PCI_EXPRESS_GEN2_
COMPLIANCE_RECEIVE_
SET_IN_TS2_N
PCI_EXPRESS_GEN2_
ILLEGAL_EIOS_COUNT_
ON_NON_2_5_GT_P
PCI_EXPRESS_GEN2_
ILLEGAL_EIOS_COUNT_
ON_NON_2_5_GT_N
PCI_EXPRESS_GEN2_
EIEOS_WITHOUT_D10_2_
SYMBOL_P
Two sets of a COM(K28.5)

followed by three IDL(K28.3)
should be transmitted as
electrical idle indication when
speed is greater than 2.5 GT/s.
At speed higher than 2.5 GT/s device

should send two sets of COM followed by
three IDL before entering electrical idle.
This check fires if only one set or no EIOS
is received on speeds greater than 2.5 GT/s
before entering electrical idle.
D10.2 symbol should appear at EIEOS consist of one COM followed by 14

the end of Electrical Idle Exit EIE and then one D10.2 symbol at the end.
sequence Ordered Set(EIEOS). This check fires if EIEOS is received
without D10.2 at the end.
PCI_EXPRESS_GEN2_
EIEOS_WITHOUT_D10_2_
SYMBOL_N
PCI_EXPRESS_GEN2_
MODIFIED_COMPLIANCE_
PATTERN_ERROR_P
Modified compliance pattern

error on this lane of TX/RX
interface.
PCI_EXPRESS_GEN2_
MODIFIED_COMPLIANCE_
PATTERN_ERROR_N
Modified compliance pattern consist of

K28.5, D21.5, K28.5, D10.2 Error status
symbol, Error status symbol, K28.5 and
K28.5 symbols. This check fires if above
mentioned sequence is not detected.
497
PCI Express
Monitor Checks
Table 14-13. PCI Express Gen2 Link Training and Width Negotiation Checks
Check ID
Violation
Description
PCI_EXPRESS_GEN2_
COMPLIANCE_RECEIVE_
SET_IN_NON_POLLING_
STATE_P
Compliance Receive bit can

only be set in Polling Active
state.
Device can enters the Polling Compliance

by seeing compliance receive bit in TS1 OS
from Polling active after 24 ms timeout.
This bit cannot be set to 1 in state other than
Polling Active. This check fires if TS1 is
detected with compliance receive bit set to
1 in state other than Polling.
Device must not change data

rate value while in
Configuration.Complete state.
A device is allowed to change the data rates

it supports only during entry to this
substate, and must not change the values
while in this substate. This check fires if
data rate changes while in this substate.
PCI_EXPRESS_GEN2_
Minimum four EIE symbol
EIE_LT_4_BEFORE_FTS_ON_ should be transmitted before
NON_2_5_GT_P
FTS on a speed other than 2.5
GT/s while exiting L0s.
PCI_EXPRESS_GEN2_
EIE_LT_4_BEFORE_FTS_ON_
NON_2_5_GT_N
On a speed greater than 2.5 GT/s, minimum

four consecutive EIE symbols should be
transmitted before the first FTS. This check
fires if less than 4 EIE symbols are detected
before the first FTS.
PCI_EXPRESS_GEN2_
EIE_MT_8_BEFORE_FTS_
ON_NON_2_5_GT_P
Maximum eight EIE symbol

can be transmitted before FTS
on a speed other than 2.5 GT/s
while exiting L0s.
On a speed greater than 2.5 GT/s, maximum

eight consecutive EIE symbols can be
transmitted before the first FTS. This check
fires if more than 8 EIE symbols are
detected before the first FTS.
Electrical Idle Exit sequence

Ordered Set(EIEOS) should be
transmitted after every 32
consecutive TS1 or TS2 OS on
a speed greater than 2.5 GT/s.
An EIEOS is required to be sent after

transmitting every 32 consecutive TS1 or
TS2 OS on a speed greater than 2.5 GT/s
except where TS2 is received that will set
the EIEOS counter to 0 again. This check
fires if EIEOS is not sent after every 32
consecutive TS1 or TS2.
EIEOS should not be

transmitted in states other than
Recovery.RcvrLk,
Recovery.RcvrCfg, and
Configuration.Linkwidth.Start.
This check fires if EIEOS is detected in

states other than Recovery. RcvrLk,
Recovery.RcvrCfg, and
Configuration.Linkwidth.Start.
PCI_EXPRESS_GEN2_
COMPLIANCE_RECEIVE_
SET_IN_NON_POLLING_
STATE_N
PCI_EXPRESS_GEN2_
DATA_RATE_CHANGE_IN_
CONFIG_COMPLETE_P
PCI_EXPRESS_GEN2_
DATA_RATE_CHANGE_IN_
CONFIG_COMPLETE_N
PCI_EXPRESS_GEN2_
EIE_MT_8_BEFORE_FTS_
ON_NON_2_5_GT_N
PCI_EXPRESS_GEN2_
EIEOS_ILLEGAL_COUNT_P
PCI_EXPRESS_GEN2_
EIEOS_ILLEGAL_COUNT_N
PCI_EXPRESS_GEN2_
EIEOS_IN_ILLEGAL_
STATE_P
PCI_EXPRESS_GEN2_
EIEOS_IN_ILLEGAL_
498
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_GEN2_
EIEOS_NOT_SENT_BEFORE_ Ordered Set(EIEOS) should be
FIRST_TS1_P
transmitted before first TS1 OS
in Recovery.RcvrLk/
PCI_EXPRESS_GEN2_
Configuration.Linkwidth.Start
EIEOS_NOT_SENT_BEFORE_ on a speed greater than 2.5
FIRST_TS1_N
GT/s.
This check fires if EIEOS is not detected

before the first TS1 in Recovery.RcvrLk/
Configuration.Linkwidth.Start on a speed
greater than 2.5 GT/s.
PCI_EXPRESS_GEN2_
EIEOS_ON_2_5_GT_P

Ordered Set(EIEOS) should be
transmitted only on a speed
greater than 2.5 GT/s.
When speed is greater than 2.5 GT/s,

EIEOS is transmitted in Recovery and
Configuration states. This check fires if
EIEOS is detected at speed 2.5 GT/s.
Electrical Idle Ordered

Set(EIOS) not sent prior to
entering electrical idle in
Recovery.Speed.
Prior to entering to recovery speed device

sends EIOS. This check fires if EIOS is not
detected before moving to recovery speed.
Illegal state transition from

Recovery.Speed to
Recover.Cfg.
This check fires if TS2 is detected in

Recovery. Speed state.
The speed change bit must be

set to 1 in all TS2 OS in
Recovery.RcvrCfg when it has
initiated speed change process
in Recover.RcvrLk.
When device has sent TS1 OS with speed

change bit set to 1 in recovery lock, it
should also transmit TS2 with speed change
bit set to 1 in recovery cfg. This check fires
if TS2 detected with speed change bit not
set while it was set in TS1.
Device should set

speed_change_bit in TS1 OS
after receiving 8 consecutive
TS1 OS with speed change bit
set.
During changing speed one of the device

starts transmitting TS1 OS with speed
change bit set to 1. Other device after
receiving 8 consecutive TS1 with speed
change bit set to 1 also starts transmitting
TS1 with speed change bit set to 1. This
check fires if other device does not transmit
TS1 with speed change bit set to 1 after
receiving 8 consecutive TS1 with speed
change bit set to 1.
PCI_EXPRESS_GEN2_
EIEOS_ON_2_5_GT_N
PCI_EXPRESS_GEN2_
EIOS_NOT_SENT_PRIOR_
TO_ENTERING_REC_
SPEED_P
PCI_EXPRESS_GEN2_
EIOS_NOT_SENT_PRIOR_
TO_ENTERING_REC_
SPEED_N
PCI_EXPRESS_GEN2_
ILLEGAL_RECO_SPEED_
TO_RECO_CFG_P
PCI_EXPRESS_GEN2_
ILLEGAL_RECO_SPEED_
TO_RECO_CFG_N
PCI_EXPRESS_GEN2_
ILLEGAL_SPEED_CHANGE_
BIT_IN_REC_CFG_P
PCI_EXPRESS_GEN2_
BIT_IN_REC_CFG_N
PCI_EXPRESS_GEN2_
BIT_IN_REC_LK_P
PCI_EXPRESS_GEN2_
BIT_IN_REC_LK_N
499
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_GEN2_
L1_IDLE_LT_40NS_ON_
SPEED_NOT_2_5_GT_P
Device should remain in

L1.Idle for minimum of 40 ns
on a speed greater than 2.5
GT/s.
This check fires if the device remains in

L1.Idle for less than 40 ns.
Device should enter to

Recovery.Lk from Config.Idle
after 2ms timeout if
idle_2rlock_transitioned
variable is 0.
If the idle_to_rlock_transitioned variable is

0b, then the next state is
Recovery.RcvrLock. This check fires if it
moves to Detect instead of recovery lock.
Device must not enter

Recover.Speed from
Recovery.RcvrCfg unless 32
TS2 are transmitted without
being interrupted by EIEOS.
This check fires if device transitions to

recovery speed from recovery cfg after
transmitting less than 32 TS2 OS.
Initiated speed change when

other device is not capable of
higher data rate.
Both devices tell the speed change

capability in TS2 OS in Configuration state
and initiate speed change while moving
from L0 to recovery. This check fires if
other device is not capable of speed change
but initiate the process of speed change.
Device is not capable of higher

data rate but initiated speed
change.
Device tells the speed change capability in

TS2 OS in Configuration state and initiate
speed change while moving from L0 to
recovery. This check fires if the device is
not capable of speed change but initiate the
process of speed change.
When speed change initiated

proposed data rate should be
different from current running
speed.
This check fires when same data rate as

current speed is advertise in speed change.
PCI_EXPRESS_GEN2_
L1_IDLE_LT_40NS_ON_
SPEED_NOT_2_5_GT_N
PCI_EXPRESS_GEN2_
RECO_LK_NOT_ENTERED_
FROM_CONFIG_IDLE_P
PCI_EXPRESS_GEN2_
RECO_LK_NOT_ENTERED_
FROM_CONFIG_IDLE_N
PCI_EXPRESS_GEN2_
RECO_SPEED_ILLEGAL_
TRANSITION_P
PCI_EXPRESS_GEN2_
RECO_SPEED_ILLEGAL_
TRANSITION_N
PCI_EXPRESS_GEN2_
SPEED_CHANGE_
INITIATED_WHEN_
OTHER_DEVICE_NOT_
CAPABLE_P
PCI_EXPRESS_GEN2_
SPEED_CHANGE_
INITIATED_WHEN_
OTHER_DEVICE_NOT_
CAPABLE_N
PCI_EXPRESS_GEN2_
SPEED_CHANGE_
INITIATED_WHEN_NOT_
CAPABLE_P
PCI_EXPRESS_GEN2_
SPEED_CHANGE_
INITIATED_WHEN_NOT_
CAPABLE_N
PCI_EXPRESS_GEN2_
SPEED_CHANGE_
MISMATCH_P
PCI_EXPRESS_GEN2_
SPEED_CHANGE_
MISMATCH_N
500
PCI Express
Monitor Checks
Check ID
Violation
Description
PCI_EXPRESS_GEN2_
SPEED_CHNG_NOT_0_P
The speed change bit should be

0 after successful speed
negotiation.
This check fires if speed change bit is set in

TS1/TS2 ordered set after successful speed
negotiation.
The speed change bit must not

be set to 1 in state other than
Recovery.
This check fires if speed change bit is set in

TS1/TS2 ordered set in state other than
recovery.
Device must not change

upconfiguration capability
bit(symbol 4 bit 6 of TS2)
while in
Configuration.Complete state.
A device is allowed to change its Link

width upconfigure capability advertised in
Link Upconfigure Capability (Symbol 4 bit
6) in the TS2 Ordered Set prior to entry to
this substate, and must not change the
values while in this substate. This check
fires if upconfiguration capability bit
changes while in this substate. This check is
option is not set.
Device is not capable of

upconfiguration but initiated
upconfiguration.
Device tells the upconfiguration capability

in TS2 OS in Configuration state and
initiate upconfiguration while moving from
recovery to configuration. This check fires
if the device is not capable of
upconfiguration, but initiate the process of
upconfiguration.
PCI_EXPRESS_GEN2_
SPEED_CHNG_NOT_0_N
PCI_EXPRESS_GEN2_
SPEED_CHNG_OTHER_
THAN_RECO_P
PCI_EXPRESS_GEN2_
SPEED_CHNG_OTHER_
THAN_RECO_N
PCI_EXPRESS_GEN2_
UPCONFIG_BIT_CHANGE_
PCI_EXPRESS_GEN2_
UPCONFIG_BIT_CHANGE_
PCI_EXPRESS_GEN2_
UPCONFIG_INITIATED_
WHEN_NOT_CAPABLE_P
PCI_EXPRESS_GEN2_
UPCONFIG_INITIATED_
WHEN_NOT_CAPABLE_N
Table 14-14. PCI Express Gen2 Transaction Layer Transmit Checks

Check ID
Violation
Description
PCI_EXPRESS_GEN2_
CFG_REQ_AT_FIELD_
ERROR_P
Address type (AT) field of

be 2'b00.
Configuration requests should always have

default/ untranslated(2'b00) AT[1:0] field.
This check fires if any other address type
field is detected for configuration requests.
Address type (AT) field of

completion should be 2'b00.
Completion packets should always have

field is detected for completion.
PCI_EXPRESS_GEN2_
CFG_REQ_AT_FIELD_
ERROR_N
PCI_EXPRESS_GEN2_
CPL_AT_FIELD_ERROR_P
PCI_EXPRESS_GEN2_
CPL_AT_FIELD_ERROR_N
501
PCI Express
Monitor Checks
Table 14-14. PCI Express Gen2 Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_GEN2_
DEPRECATED_TLP_
ERROR_P
Deprecated TLP
types(TCfgRd/ TcfgWr) are
malformed and should not be
issued.
Deprecated TLP types(TCfgRd and

TcfgWr) used for Trusted Configuration
Space(TCS) are not supported in version
higher than PCIe 1.1 and treated as
malformed by receiving device. This check
fires when such requests are initiated by
downstream port.

generate deprecated TLP
requests.

deprecated(TcfgRd/ TcfgWr) request. It
must complete the deprecated request. This
check fires if a legacy end point generates a
Deprecated request.

not generate deprecated TLP
requests.
A PCI Express end point must not generate

deprecated(TcfgRd/ TcfgWr) request. It
must complete the deprecated request. This
check fires if a PCI Express end point
generates a Deprecated request.
EP field of TLP without data

must not be 1.
EP field can be set to 1 only for TLPs that

include a data payload. This check fires if
any requests without data payload is
detected with EP bit set to 1.
Ignored message should have

routing 100.
This check fires if routing other than 100 is

detected in Ignored message.
Address type (AT) field of I/O

I/O requests should always have default/

untranslated(2'b00) AT[1:0] field. This
check fires if any other address type field is
detected for I/O requests.
Memory request initiated by

device should have default
address type(AT) field when
ACS translation is blocking.
When ACS Translation Blocking Enable is

set to 1 in ACS control register, all memory
requests initiated by device should have
address type(AT[1:0] as 2'b00. This check
fires if value of AT is other than 2'b00 in
memory request initiated by device for
ACS translation blocking mode.
PCI_EXPRESS_GEN2_
DEPRECATED_TLP_
ERROR_N
PCI_EXPRESS_GEN2_
DEPRECATED_TLP_
LEGACY_END_POINT_P
PCI_EXPRESS_GEN2_
DEPRECATED_TLP_
LEGACY_END_POINT_N
PCI_EXPRESS_GEN2_
DEPRECATED_TLP_PCI_
EXPRESS_END_POINT_P
PCI_EXPRESS_GEN2_
DEPRECATED_TLP_PCI_
EXPRESS_END_POINT_N
PCI_EXPRESS_GEN2_
EP_BIT_VIOLATION_P
PCI_EXPRESS_GEN2_
EP_BIT_VIOLATION_N
PCI_EXPRESS_GEN2_
IGNORED_MSG_ROUTING_
NT_100_P
PCI_EXPRESS_GEN2_
IGNORED_MSG_ROUTING_
NT_100_N
PCI_EXPRESS_GEN2_
IO_REQ_AT_FIELD_
ERROR_P
PCI_EXPRESS_GEN2_
IO_REQ_AT_FIELD_
ERROR_N
PCI_EXPRESS_GEN2_
MEM_REQ_ACS_
VIOLATION_P
PCI_EXPRESS_GEN2_
MEM_REQ_ACS_
VIOLATION_N
502
PCI Express
Monitor Checks
Table 14-14. PCI Express Gen2 Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_GEN2_
MSG_REQ_AT_FIELD_
ERROR_P
Address type (AT) field of a

message request should be
2'b00.
Message requests should always have

field is detected for message requests.
PME To Ack message should

have function number
reserved.
This check fires if non-reserved function

number is detected in PM E To Ack
message.
The completion for requests

having ACS violation should
have completion status as
completion abort (CA).
When ACS violation is detected in nonposted request, then completer must

generate a Completion with a Completion
Abort (CA) Completion Status. This check
fires if a completion with completion status
other than CA is detected for request that
had ACS violation.
The completion for requests

having ACS violation should
have completion status as
completion abort (CA).
When ACS violation is detected in nonposted request, then completer must

generate a Completion with a Completion
Abort (CA) Completion Status. This check
fires if a completion with completion status
other than CA is detected for request that
had ACS violation.
PCI_EXPRESS_GEN2_
MSG_REQ_AT_FIELD_
ERROR_N
PCI_EXPRESS_GEN2_
PME_2_ACK_MSG_NON_
RSVD_FN_NUMBER_P
PCI_EXPRESS_GEN2_
PME_2_ACK_MSG_NON_
RSVD_FN_NUMBER_N
PCI_EXPRESS_GEN2_
RX_CPL_STATUS_NON_CA_
FOR_ACS_VIOLATED_
REQ_P
PCI_EXPRESS_GEN2_
RX_CPL_STATUS_NON_CA_
FOR_ACS_VIOLATED_
REQ_N
PCI_EXPRESS_GEN2_
TX_CPL_STATUS_NON_CA_
FOR_ACS_VIOLATED_
REQ_P
PCI_EXPRESS_GEN2_
TX_CPL_STATUS_NON_CA_
FOR_ACS_VIOLATED_
REQ_N
Table 14-15. PCI Express Gen2 Power Management Checks

Check ID
Violation
Description
PCI_EXPRESS_GEN2_
ILLEGAL_ROUTING_FOR_
NON_PME_TO_ACK_MSG_P
Routing 101 for MSG other

than PME_TO_ACK is
malformed TLP.
This check fires if other power

management message than
PME_TO_ACK are transmitted with
routing field 101.
PCI_EXPRESS_GEN2_
ILLEGAL_ROUTING_FOR_
NON_PME_TO_ACK_MSG_N
503
PCI Express
Monitor Checks
Table 14-16. PCI Express Gen2 PIPE Interface Checks

Check ID
Violation
Description
PIPE_GEN2_RATE_CHANGE_
IN_P1_P2
Rate can only be changed when

MAC is in P0 state.

PHY Layer component for speed change
by changing Rate signal to appropriate
value in P0 state. This check fires if Rate
signal changes in state other than P0.
PIPE_GEN2_RATE_CHANGES_
WHEN_TXELECIDLE_
DEASSERTED
Rate signal should be changed

only when TxElecidle is
asserted.
Signaling rate can only be changed in P0

state when TxElecidle is asserted. This
check fires if Rate changes when
TxElecidle is de-asserted.
PIPE_GEN2_RATE_INVALID_
DURING_P1_P2
Before transitioning to P1 or P2,

Rate must be set to 2.5 GT/s
signaling rate.
Rate signal from MAC indicates the

current speed of operation. If 0 indicates
2.5 GT/s and if 1 indicates 5.0 GT/s.
While in P1 or P2 state, the MAC should
have Rate signal set to 2.5 GT/s.
PIPE_GEN2_RATE_INVALID_
DURING_RESET
While reset is asserted, Rate

must be set to 2.5 GT/s signaling
rate.
Rate signal from MAC indicates the

current speed of operation. If 0 indicates
2.5 GT/s and if 1 indicates 5.0 GT/s.
While reset is asserted, the MAC should
have Rate signal set to 2.5 GT/s.
PIPE_GEN2_TXDEEMPH_
CHANGE_IN_P1_P2
TxDeemph can only be changed

when MAC is in P0 state.

PHY Layer component for selectable deemphasis change by changing the
TxDeemph signal to appropriate value in
P0 state. This check fires if TxDeemph
signal changes in state other than P0.
PIPE_GEN2_TXELECIDLE_
DEASSERTED_BEFORE_
PHYSTATUS_ASSERTED_
DURING_RATE_CHANGES
During signaling rate change,

TxElecidle should be asserted
until there is PhyStatus from
PHY.
After Rate changes, TxElecidle must not

be de-asserted until there is PhyStatus
assertion from PHY. PhyStatus assertion
indicates that PHY has successfully
changed the data rate. This check fires if
above mentioned rule is violate.
PIPE_GEN2_TXMARGIN_
CHANGE_IN_P1_P2
TxMargin can only be changed

when MAC is in P0 state.

PHY Layer component for transmitter
Margin change by changing TxMargin
signal to appropriate value in P0 state.
This check fires if TxMargin signal
changes in state other than P0.
Compliance Rules Cross-Reference

Table 14-17 through Table 14-26 show the cross-references to the compliance checks for the
PCI Express protocol. These compliance checks are common for PCI Express End point, Root
complex, and Switch devices.
504
Table 14-17 on page 506: PCI Express Compliance Checklist: Topology
PCI Express
Monitor Checks
Table 14-18 on page 506: PCI Express Compliance Checklist: Transaction Protocol
Table 14-19 on page 530: PCI Express Compliance Checklist: Link Protocol
Table 14-20 on page 538: PCI Express Compliance Checklist: Link-Physical Layer
Interface
Table 14-21 on page 567: PCI Express Compliance Checklist: Electrical
Table 14-22 on page 567: PCI Express Compliance Checklist: Power Management
Table 14-23 on page 572: PCI Express Compliance Checklist: System Architecture
Table 14-24 on page 573: PCI Express Compliance Checklist: Configuration
Table 14-25 on page 573: PCI Express Compliance Checklist: Isochronous Applications
Table 14-26 on page 574: PCI Express Compliance Checklist: Electromechanical
The following tables show the checklist applicable for the respective PCI Express devices:
Table 14-27 on page 574: Checklist Applicable for End Point Only
Table 14-28 on page 589: Checklist Applicable for Root Complex Only
Table 14-29 on page 601: Checklist Applicable for Switch Only
Checks Not Performed by the Monitor

The monitor does not perform certain checks for various reasons. These are identified by the
following Check IDs:
Monitor cannot perform this check.

Implementing logic for the check is not possible. For example:
Monitor cannot check for initial minimum credit advertisement, because it is not
clear when to perform the checks and when to fire. Some checks relate to timing that
spans 8 us. Only after 8 us are firings possible. (e.g., TXN 6.1# 18, 19, 20, and 21.)
Most of the checks in the link training section cannot be performed because the
monitor changes its state on bus activity.
Monitor sits on the interface and it is not possible to track the events within the
device that do not appear on the interface.
Not a monitor check.

Including logic for the check is not feasible. For example:
o
Device configuration through software, electrical parameters.
Usage of certain requests by the devices (INTx).
505
PCI Express
Monitor Checks
Monitor does not perform this check.

Logic for the check is not implemented, typically because the specification or the
implementation is ambiguous. For example,
o
TXN5.1#3 and TXN5.2#3 check whether or not the user has configured TC/VC
mapping properly.
TXN2.21#16 and TXN 2.21#18 are not performed as the monitor does not track the
device configuration.
Table 14-17. PCI Express Compliance Checklist: Topology

Type
Rule
Check ID
Violation
PCI Express Fabric

Topology Configuration
TPL.4.0#1
Monitor cannot
perform this check.
Devices and functions operating under

the PCI compatible mechanism must
support 100% binary compatibility with
PCI 2.3 or later operating systems, and
their corresponding bus enumeration
and configuration software.
Table 14-18. PCI Express Compliance Checklist: Transaction Protocol

Type
Rule
Check ID
Violation
Transaction Layer
Protocol Packet
Definition
TXN.2.0#2
PCI_EXPRESS_ NON_ZERO_
RESERVED_ FIELD
All TLP fields marked Reserved

(R) in the PCI Express Base
Specification must be filled with all
0s when a TLP is formed.
TXN.2.0#3
Monitor cannot perform this

check. However, for computation
of ECRC and LCRC, these bits are
considered by the monitor.
Values in TLP reserved fields must

be ignored by receivers from a
functional view, but are included in
all LCRC and ECRC calculations.
TXN.2.1#1
LENGTH_ERROR
All Transaction Layer Packet (TLP)

headers must follow the field
format specified in Figure 2-4 of
the PCI Express Base Specification.
Common Packet
Header Fields
HDR_ LENGTH_ERROR
HDR_ LENGTH_ERROR
PCI_EXPRESS_ CPL_HDR_
LENGTH_ ERROR
TXN.2.1#2
506
PCI_EXPRESS_ UNDEFINED_
HEADER_FIELD
Permitted Fmt[1:0] and Type[4:0]

field values are shown in Table 2-3
of the PCI Express Base
Specification. All other encodings
are reserved.
PCI Express
Monitor Checks
Table 14-18. PCI Express Compliance Checklist: Transaction Protocol (cont.)

Type
TLPs with Data

Payloads Rules
Rule
Check ID
Violation
TXN.2.1#3
PCI_EXPRESS_NO_TLP_
DIGEST
TD Field 1b indicates presence of

TLP digest in the form of a single
DW at the end of the TLP.
TXN.2.1#4
PCI_EXPRESS_TLP_PKT_
SIZE_ ERROR
TLP data must be four-byte

naturally aligned and in increments
of four-Byte Double Words (DW).
TXN.2.1#5
PCI_EXPRESS_
CPL_LENGTH_
FIELD_ ERROR
Length[9:0] is a reserved field for

TLPs that do not contain or refer to
data payloads, including Cpl,
CplLk, and Msg.
TXN.2.2#1
Monitor checks fire when

malformed TLPs are detected.
All required and implemented

optional checks for malformed
TLPs must be detected and reported
by the receiver as errors associated
with the receiving port (per the PCI
Express Base Specification Section
6.2).
TXN.2.2#3
PCI_EXPRESS_
MAX_PAYLOAD_
SIZE_ERROR
The Transmitter of a TLP with a

data payload must not allow the
data payload length to exceed the
length specified by the value in the
Max_Payload_Size field of the
Transmitters Device Control
Register (see PCI Express Base
Specification Section 7.8.4).
TXN.2.2#4
PCI_EXPRESS_
MAX_PAYLOAD_
SIZE_ERROR
The data payload of a TLP must not

exceed the length specified by the
value in the Max_Payload_Size
field of the Device Control
Register.
TXN.2.2#5
PCI_EXPRESS_
TLP_PKT_SIZE_ ERROR
For TLPs that include data, the

value in the Length field and the
actual amount of data included in
the TLP must be equal; otherwise,
the TLP is Malformed.
TXN.2.2#6
PCI_EXPRESS_
MAX_PAYLOAD_
SIZE_ERROR
Receivers must check for violations

of TXN2.2#4. If a Receiver
determines that a TLP violates this
rule, then the TLP is a Malformed
TLP and is reported as an error
associated with the Receiving Port
(per. Base Spec Section 6.2).
TXN.2.2#7

check. However, for computing
the length of the TLP packet, TLP
digest is not included.
The value in the TLP Length field

applies only to data (Transaction
Digest is not included in the
Length).
507
PCI Express
Monitor Checks

Type
Address Based
Routing Rules
ID Based Routing
Rules
First/Last DW Byte
Enable Rules
508
Rule
Check ID
Violation
TXN.2.2#8

check.
When a data payload is included in

a TLP, the first Byte of data
following the header corresponds to
the Byte address closest to zero,
and the succeeding Bytes are in
increasing Byte address sequence.
TXN.2.2#9
PCI_EXPRESS_MAX_
PAYLOAD_SIZE_ERROR
The data payload of a Received

TLP must not exceed the length
specified by the value in the
Max_Payload_Size field of the
Receivers Device Control Register
(see PCI Express Base
TXN.2.2#10
PCI_EXPRESS_MAX_
PAYLOAD_SIZE_ERROR

of TXN.2.2#9. If a Receiver
determines that a TLP violates this
rule, then the TLP is a Malformed
TLP, and this is a reported error
associated with the Receiving Port
Specification Section 6.2).
Note: Two address formats are specified, a 64-bit format used with a 4 DW Header and
a 32-bit format used with a 3 DW Header.
TXN.2.4#3

check.
All PCI Express Agents must

decode all address bits in the header
(address aliasing is not allowed).
TXN.2.5#1

check.
ID routing is used with

Configuration Requests.
TXN.2.5#3

check.
ID routing uses the Bus, Device,

and Function Numbers to specify
the destination Device for the TLP.
TXN.2.5#4
Monitor does not perform this

check.
ID routing header field locations

must comply with the Base
specification.
Note: Two address formats are specified, a 64-bit format used with a 4 DW Header and
a 32-bit format used with a 3 DW Header.
TXN.2.6#1
PCI_EXPRESS_
FIRST_DW_BE_
NON_ZERO_ ERROR
If the Length field for a Request

indicates a length of greater than 1
DW then the byte enables for the
first (or only) DW BE[3:0]
referenced by the Request must not
be 0000b.
TXN.2.6#2
PCI_EXPRESS_
LAST_DW_BE_ ERROR

indicates a length of 1 DW, then the
byte enables for the last DW
BE[3:0] referenced by the Request
must equal 0000b.
PCI Express
Monitor Checks

Type
Transaction
Descriptor
Transaction ID
Field
Rule
Check ID
Violation
TXN.2.6#3
PCI_EXPRESS_
LAST_DW_BE_
NON_ZERO_ ERROR

indicates a length of greater than 1
DW, then the last DW BE[3:0]
Field must not equal 0000b.
TXN.2.6#4

check.
For each bit of the Byte Enables

Fields: a value of 0b indicates that
the corresponding Byte of Data
must not be written or, if
nonprefetchable, must not be read
at the Completer.
TXN.2.6#5

check.
For each bit of the Byte Enables

Fields: a value of 1b indicates that
the corresponding Byte of Data
must be written or read at the
Completer.
TXN.2.6#7

check.
A Write Request with a length of 1

DW with no Bytes enabled must
have no effect at the Completer.
TXN.2.6#8
A Memory Read Request of 1 DW

with no Bytes enabled (zero length
Read) can be used by devices as a
type of Flush Request. All
Completers must implement the
functionality associated with the
Flush Semantic.
TXN.2.7#1

check.
Tag[7:0] is a 8-bit field generated

by each Requestor that must be
unique for all outstanding Requests
that require a Completion for that
Requester (Figure 2-11 of the PCI
Express Base Specification).
TXN.2.7#2
PCI_EXPRESS_TAG_ FIELD_
ERROR
By default, the maximum number

of outstanding Requests per
device/function shall be limited to
32, and only the lower 5 bits of the
Tag field are used with the
remaining upper 3 bits required to
be all 0s.
TXN.2.7#3
PCI_EXPRESS_TAG_ FIELD_
ERROR
If the Extended Tag Field Enable

bit is set, then the maximum
number of outstanding Requests per
device/function is increased to 256,
and the entire Tag field is used.
TXN.2.7#5

check.
For Requests that do not require

Completion (Posted Requests), the
value in the Tag[7:0] field is
undefined and must not affect
Receiver processing of the Request.
509
PCI Express
Monitor Checks

Type
Relaxed Ordering
Attribute
Rule
Check ID
Violation
TXN.2.7#7

check.
Transaction ID is included with all

Requests and Completions.
TXN.2.7#13
Each function associated with a

logical device must be designed to
respond to a unique Function
Number for Configuration Requests
addressing that logical device.
TXN.2.8#1
PCI_EXPRESS_IO_REQ_
ATTR_FIELD_ERROR
The Relaxed Ordering Attribute

must be set to 0 for configuration
requests, I/O requests, memory
requests that are Message Signaled
Interrupts, and message requests
(except where specifically
permitted in the PCI Express Base
Specification).
ATTR_FIELD_ERROR
ATTR_FIELD_ERROR
No Snoop Attribute
TXN.2.9#1
PCI_EXPRESS_IO_REQ_
ATTR_FIELD_ERROR
ATTR_FIELD_ERROR
ATTR_FIELD_ERROR
The No Snoop Attribute must be set

to 0 for configuration requests, I/O
requests, memory requests that are
Message Signaled Interrupts, and
message requests (except where
specifically permitted in the PCI
Express Base Specification).
Transaction
Descriptor Traffic
Class Field
TXN.2.10#1

check.
TC0 is the default TC and must be

supported by every PCI Express
device.
Memory, I/O, and

Configuration
Request Rules
TXN.2.11#1
PCI_EXPRESS_IO_REQ_
HDR_LENGTH_ERROR
All Memory, I/O, and

Configuration Requests include the
following fields in addition to the
common header fields:
Requester ID[15:0]
andTag[7:0], forming the
Transaction ID
Last DW BE[3:0] and 1st DW
BE[3:0]
HDR_LENGTH_ERROR
HDR_LENGTH_ERROR
510
TXN.2.11#2

check.
Memory Requests route by address,

using either 64-bit or 32-bit
Addressing (see PCI Express Base
Specification, Figure 2-13 and
Figure 2-14).
TXN.2.11#3
PCI_EXPRESS_IO_REQ_
HDR_ LENGTH_ERROR
I/O Requests route by address,

using 32-bit Addressing (see PCI
Express Base Specification, Figure
2-15).
PCI Express
Monitor Checks

Type
Rule
Check ID
Violation
TXN.2.11#4
PCI_EXPRESS_IO_REQ_
ATTR_FIELD_ ERROR
I/O Requests have the following

restrictions:
FIELD_ ERROR
PCI_EXPRESS_IO_REQ_
LENGTH_ FIELD_ERROR
0001b
Last DW BE[3:0] must be
0000b
TXN.2.11#5
HDR_LENGTH_ERROR
Configuration Requests route by

ID, and use a 3 DW Header.
TXN.2.11#6

check.
In addition to the header fields

included in all Memory, I/O, and
Configuration Requests and the ID
routing fields, Configuration
Requests contain the following
additional fields:
Register Number[5:0]
Extended Register
Number[3:0]
TXN.2.11#7
ATTR_FIELD_ERROR
Configuration Requests have the

following restrictions:
TC[2:0] must be 000b
Attr[1:0] must be 00b
Length[9:0] must be 00
00000001b
Last DW BE[3:0] must be
0000b
FIELD_ERROR
LENGTH_FIELD_ERROR
TXN.2.11#8
Message Request
Rules
TC[2:0] must be 000b

Attr[1:0] must be 00b
Length[9:0] must be 00 0000

check.
The Request format used for MSIs

is identical to the Memory Write
Request format and MSIs are
indistinguishable from memory
writes with regard to ordering,
Flow Control, and data integrity.
Note: The following rules apply to all Baseline Message Group Requests.
511
PCI Express
Monitor Checks

Type
Rule
Check ID
Violation
TXN.2.12#1
HDR_LENGTH_ERROR
All Message Requests include the

following fields in addition to the
common header fields (see PCI
Express Base Specification, Figure
2-17):
Requester ID[15:0] and
Tag[7:0], forming the
Transaction ID
Message Code[7:0] Specifies
the particular Message
embodied in the Request
TXN.2.12#2
MSG_ CODE_ GROUP
All Message Requests use the Msg

Type field encoding, except for the
Vendor_Defined messages, which
can use either Msg or MsgD.
TXN.2.12#3

check.
The Message Code[7:0] field must

be fully decoded (Message aliasing
is not permitted).
TXN.2.12#4
ATTR_ FIELD_
Except as noted in the PCI Express

Base Specification, the Attr[1:0]
field is reserved.
TXN.2.12#5
PCI_EXPRESS_COMPLETION_ Message Requests are posted and

WITHOUT_REQ
do not require Completion.
TXN.2.12#6

check.
Message Requests follow the same

ordering rules as Memory Write
Requests.
TXN.2.12#7

check. (monitor does not track
ordering rules).
Message routing is determined

using the r[2:0] subfield value of
the Type field as defined in the PCI
Express Base Specification, Table
2-11.
TXN.2.13#7
TC_FIELD_ERROR
Assert_INTx and De-assert INTx

interrupt Messages must use the
default Traffic Class designator
(TC0).
TXN.2.13#8
Monitor fires on both TX and RX

sides if violations are detected.

of TXN.2.13#7. If a violation has
occurred, then the TLP is
Malformed and is reported as an
error with the Receiving Port.
INTx Interrupt
Signaling Rules
TXN.2.13#10 Not a monitor check.
512
An Assert_INTx represents the

active going transition of the INTx
(x = A, B, C, or D) virtual wire.
PCI Express
Monitor Checks

Type
Rule
Check ID
Violation
TXN.2.13#11 PCI_EXPRESS_INTR_MSG_
CODE_ERROR
The INTx messages must adhere to

the encoding defined in Table 2-12
of the PCI Express Base
Specification.
TXN.2.13#13 Monitor does not perform this

check.
INTx Interrupt Signaling is

disabled with the Interrupt Disable
bit of the Command Register (see
PCI Express Base Specification,
Section 7.5.1.1).
TXN.2.13#21 Not a monitor check.
The Requester ID of an Assert

INTx/Deassert INTx Message will
correspond to the Transmitter of the
message on that Link (not
necessarily to the original source of
the interrupt)
TXN.2.14#1
CODE_ ERROR
Power Management Messages must

comply with the encoding defined
in the PCI Express Base
Specification Table 2-14
TXN.2.14#2
PCI_EXPRESS_ MSG_TYPE_
ERROR
Power Management Messages do

not include a data payload (TLP
Type field encoding is Msg)
TXN.2.14#3
LENGTH_FIELD_ERROR
Within Power Management

Messages the TLP Header
Length[9:0] field is a reserved field
TXN.2.14#4
TC_FIELD_ERROR
Power Management Messages must

use the default Traffic Class
designator (TC0).
TXN.2.14#5
Monitor fires if violations are

detected.

of TXN.2.14#4 if a violation has
occurred the TLP is Malformed and
is reported as an error with the
Receiving Port.
Error Signaling
Messages
TXN.2.15#1
CODE_ ERROR
Error Signaling Messages must

comply with the encoding in the
PCI Express Base Specification
Table 2-15.
Locked Transactions
Support
Note: The following rules apply to the formation of the Unlock Message.
Power Management
Messages
TXN.2.16#1
PCI_EXPRESS_LOCKED_
TRAN_ MESSAGE_CODE_
ERROR
Unlock Messages must comply

with the encoding in the PCI
Express Base Specification Table 216.
TXN.2.16#2
ERROR
The Unlock Message does not

include a data payload (TLP Type
field encoding is Msg).
513
PCI Express
Monitor Checks

Type
Slot Power Limit

Support
514
Rule
Check ID
Violation
TXN.2.16#3
LENGTH_FIELD_ERROR
The TLP Header Length[9:0] field

is reserved a reserved field for
Unlock Messages.
TXN.2.16#4
TC_ FIELD_ERROR
The Unlock Message must use the

default Traffic Class designator
(TC0).
TXN.2.16#5
Monitor fires whenever violation

occurs.

TXN.2.17#1
PCI_EXPRESS_SLOT_PWR_
MSG_ CODE_ERROR
Set_Slot_Power_Limit Messages
must comply with the encoding in
the PCI Express Base Specification
Table 2-17.
TXN.2.17#2
PCI_EXPRESS_SLOT_PWR_
MSG_ TYPE_ERROR
The Set_Slot_Power_Limit
Message includes a one DW data
payload (TLP Type is MsgD).
TXN.2.17#3
message data payload must be
copied from the Slot Capabilities
Register of the Downstream Port
and is written into the Device
Capabilities Register of the
Upstream Port on the other side of
the Link. See exception,
TXN.2.17#4.
TXN.2.17#4
Only components that are targeted

for integration on the system planar
or on a card/module where power
consumption of the entire
card/module is below the lowest
power limit specified for the
card/module form factor (as defined
in the corresponding
electromechanical specification)
are permitted to hard wire the value
0 in the Slot Power Limit Scale
and Slot Power Limit Value fields
of the Device Capabilities Register.
They are not required to copy the
Set_Slot_Power limit payload into
that register.
TXN.2.17#5

check.
Set_Slot_Power_Limit Message:
Bits 9:8 of the data payload map to
the Slot Power Limit Scale field.
TXN.2.17#6

check.
Bits 7:0 of the data payload map to
the Slot Power Limit Value field.
PCI Express
Monitor Checks

Type
Vendor Defined
Messages
Rule
Check ID
Violation
TXN.2.17#7

check.
Bits 31:10 of the data payload must
be set to all 0s by the transmitter.
TXN.2.17#8

check.
Bits 31:10 of the data payload must
be ignored by the receiver.
TXN.2.17#11 PCI_EXPRESS_MSG_REQ_
TC_FIELD_ ERROR
Message must use the default
Traffic Class designator (TC0).
TXN.2.17#12 Monitor fires if a violation is

detected.

TXN.2.18#1
HDR_ LENGTH_ ERROR
The Vendor_Defined Messages

must use the TLP Header format
shown in Base Specification, Table
2-18.
TXN.2.18#2

check.
If ID routing is used, bytes 8 and 9

of the TLP Header (Base
Specification, Figure 2-18) form a
16-bit field for the Destination ID.
TXN.2.18#3

check.
If ID routing is not used, then bytes

8 and 9 are Reserved.
TXN.2.18#4

check.
Bytes 10 and 11 form a 16-bit field

for the Vendor ID, as defined by
PCI-SIG, of the vendor defining the
message.
TXN.2.18#5

check.
Vendor_Defined Message type 0 or

type 1 use MsgD if a data payload
is included.
TXN.2.18#6

check.
Vendor_Defined Message type 0 or

type 1 use Msg if a data payload is
NOT included.
TXN.2.18#7
Messages defined by different

vendors or by PCI SIG are
distinguished by the value in the
Vendor ID field.
TXN.2.18#8

check.
Receivers silently discard

Vendor_Defined Type 1 Messages
that they are not designed to receive
(this is not reported as an error
condition).
515
PCI Express
Monitor Checks

Type
Hot Plug Signaling

Messages
Completion Rules
516
Rule
Check ID
Violation
TXN.2.18#9
Monitor fires based on

VENDOR_SPECIFIEC_
ENCODING_ENABLE
parameter is not set.
Receivers handle the receipt of an

unsupported Vendor_Defined Type
0 Message as an Unsupported
Request, and the error is reported
according to the PCI Express Base
Specification Section 6.2.
TXN.2.19#1
MSG_CODE_ERROR
Components must accept received

hot plug signaling messages as
defined in the Support column of
the PCI Express Base Specification,
Table 2-19 without indicating an
error.
TXN.2.19#2

check.
Components that implement or

support the associated action in the
Support column of the PCI Express
Base Specification Table 2-19 must
process the received message and
take the corresponding action.
TXN.2.19#3

check.
Components that do not implement

or support the associated action in
the Support Column of the PCI
Express Base Specification Table 219 discard the received message.
TXN.2.19#4
MSG_CODE_ERROR
Hot Plug Signaling Messages must

comply with the encoding in the
Table 2-19.
TXN.2.21#1
PCI_EXPRESS_COMPLETION_ All Read Requests and Non-Posted

TIMEOUT
Write Requests require
Completion.
TXN.2.21#2
PCI_EXPRESS_CPL_HDR_
LENGTH_ ERROR
Completions route by ID, and use a

3 DW Header.
TXN.2.21#3
The routing ID fields correspond

directly to the Requester ID
supplied with the corresponding
Request.
TXN.2.21#4
PCI_EXPRESS_CPL_HDR_
LENGTH_ ERROR
Completions must adhere to the

header format specified in the PCI
Express Base Specification Figure
2-21.
TXN.2.21#5

check.
Completer ID[15:0] must be

encoded to identify the Completer.
TXN.2.21#6
FIELD_ ERROR
Completion Status[2:0] must be

encoded to indicate the status for a
Completion (see PCI Express Base
Specification, Table 2-20).
PCI Express
Monitor Checks

Type
Handling of Received
TLPs
Rule
Check ID
Violation
TXN.2.21#7
FIELD_ERROR
Completion Status[2:0] field value

must be encoded per the PCI
2.3.1.
TXN.2.21#8
PCI_EXPRESS_COMPLETION_ BCM Byte Count Modified The

BCM_BIT_SET
bit must not be set by PCI Express
Completers, and can only be set by
PCI-X completers.
TXN.2.21#11 Monitor cannot perform this

check.
Completion Header Tag[7:0] in

combination with the Requester ID
field, must correspond to the
Transaction ID.
TXN.2.21#18 Monitor does not perform this

check as the monitor does not take
info on functions of the device.
If a Completion with the UR status

is generated by a multifunction
device without associating the
Completion with a specific function
within the device, then the Function
Number field is Reserved.
TXN.2.21#20 Monitor cannot perform this

check.
The Requestor must ignore the

value returned in the Completer ID
field until the completing device
has finished software initialization
and configuration using at least one
Configuration Write Request.
TXN.2.21#21 PCI_EXPRESS_CPL_BYTE_
COUNT_ VALUE_ERROR
For Memory Read Completions,

Byte Count[11:0] is set according
to the rules in the PCI Express Base
Specification Section 2.3.1.1.
TXN.2.21#22 PCI_EXPRESS_CPL_BYTE_
COUNT_ VALUE_ERROR
For Completions other than

Memory Read Completions, Byte
Count[11:0] must be 4,
TXN.3.0#1
PCI_EXPRESS_ NON_ZERO_
RESERVED_ FIELD_ERROR
Values in Reserved fields must be

ignored by the Receiver.
TXN.3.0#2

check.
Receiver Flow Control tracking

information must be updated for all
valid TLPs received.
TXN.3.0#3
Monitor fires if malformed TLPs

are detected.
All Received TLPs that fail the

required (and implemented
optional) checks of TLP formation
rules or that use undefined Type
field values are Malformed TLPs,
and they must be discarded without
updating Receiver Flow Control
information.
517
PCI Express
Monitor Checks

Type
Rule
Check ID
Violation
Request Handling
Rules
TXN.3.1#1
PCI_EXPRESS_ UNDEFINED_
HEADER_FIELD
A Request Type defined in the PCI

Express Base Specification Table 23 that is not supported by the
receiving device is an Unsupported
Request and is reported according
to the PCI Express Base
TXN.3.1#2
PCI_EXPRESS_COMPLETION_ For Unsupported Requests

FOR_UR_NE_UR
requiring Completion, a
Completion Status of UR is
returned (see PCI Express Base
TXN.3.1#3

check.
Message Requests that specify an

undefined or unsupported value
(other than Vendor_Defined Type 1
see PCI Express Base
Specification Section 2.2.8.1.6) are
Unsupported Requests and are
reported according to the PCI
6.2.
TXN.3.1#6

check.
For Request requiring Completion

that are treated as a Completer
Abort, a Completion Status of CA
is returned (see PCI Express Base
TXN.3.1#8

check.
A completer that is unable to

process the request due to a device
specific error condition must handle
the Request as Completer Abort if
functionally able to do so.
TXN.3.1#9

check.
TXN.3.1#8 is an error associated

with the Receiving device/function
in the component and must be
reported as such (see PCI Express
Base Specification Section 6.2).
TXN.3.1#10

check.
If the Completer of a supported

request is permanently unable to
process the Request due to a
device-specific error condition,
then the Completer must, if
possible, handle the Request as a
Completer Abort.
TXN.3.1#11
CSR_FOR_NONCFG_REQ
Configuration Request Retry Status

Completion must not be used to
terminate any request other than a
Configuration Request following a
reset.
518
PCI Express
Monitor Checks

Type
Rule
Check ID
Violation
TXN.3.1#12
CSR_FOR_NONCFG_REQ
Sending Configuration Request

Retry Status in response to any
other Request type besides a
Configuration Request will result in
the generation of an error condition
(Malformed TLP see PCI Express
TXN.3.2#3
PCI_EXPRESS_CPL_BYTE_
COUNT_ VALUE_ERROR
I/O and Configuration Reads must

be completed with exactly one
Completion.
TXN.3.2#4

check.
The Completion Status for a Read

Completion corresponds only to the
status associated with the data
returned with that Completion.
TXN.3.2#5

check.
A Read Completion with status

other than Successful Completion
terminates the Completions for a
single Read Request.
TXN.3.2#6

check.
In the case described in TXN.3.2#5,

the value in the Length field is
undefined, and must be ignored by
the Receiver.
TXN.3.2#7
PCI_EXPRESS_MAX_
PAYLOAD_SIZE_ERROR
Completions must not include more

data than permitted by the
Max_Payload_Size parameter Receivers must check for
violations. TLPs in violation are
Malformed TLPs. This is a reported
error associated with the Receiving
Port (see PCI Express Base
TXN.3.2#27
PCI_EXPRESS_MRD_CPL_LO
W_ADDR
For all Memory Read Completions,

the Lower Address field must
indicate the lower bits of the byte
address for the first enabled byte of
data returned with the Completion
(per PCI Express Base
Specification Table 2-22).
TXN.3.2#33
PCI_EXPRESS_COMPLETION_ When a Read Completion is

WITHOUT_REQUEST
generated with a Completion Status
other than Successful Completion,
the Completion is the final
Completion for the Request. The
Completer must not transmit
additional Completions for this
Request.
Data Return for Read

Requests
519
PCI Express
Monitor Checks

Type
Rule
Check ID
Violation
TXN.3.2#35

check
When a Read Completion is

generated with a Completion Status
other than Successful Completion,
the Byte Count field must indicate
the remaining number of bytes that
would be required to complete the
Request (as if the Completion
Status were Successful
Completion).
Completion Handling
Rules
TXN.3.3#1

check.
An Agent receiving an Unexpected

Completion must discard the
Completion.
Transaction Ordering
TXN.4.0#2 to Monitor does not track ordering

TXN.4.2#1
rules.
Virtual Channel (VC)

Mechanism
NOTE: Conceptually, traffic that flows through VCs is multiplexed onto a common
physical Link resource on the transmit side and de-multiplexed into separate VC paths
on the receive side.
TXN.5.0#2

check.
PCI Express Requesters that do not

implement the optional PCI
Express Virtual Channel Capability
Structure must only generate
requests with a TC0 label.
TXN.5.0#3

check.
PCI Express Completers that do not

Structure must accept requests with
TC labels other than TC0.
TXN.5.0#4
PCI_EXPRESS_TX_
COMPLETION_TC_ATTR_
MISMATCH
All PCI Express Completers,

including those that do not
Structure, must generate
Completions with the same TC
label as the label of the
corresponding Request
(Completions are not returned for a
Malformed TLP).
PCI_EXPRESS_RX_
COMPLETION_TC_ATTR _
MISMATCH
520
PCI Express
Monitor Checks

Type
Rule
Check ID
Violation
TXN.5.0#7

check.
For a Requester to be permitted to

issue requests with a TC label other
than TC0, the Requester must
implement the PCI Express Virtual
Channel Capability Structure, even
if it only supports the default VC.
(For peer-to-peer traffic between
Root Ports, the RC is not
considered to be a Requester). In
this scenario, the RC behaves as a
pass-through device (the same way
as a Switch device) and therefore, is
allowed to forward packets with
TCs other than TC0 even if it does
not implement the VC Capability
Structure.
Virtual Channel
Identification (VC
ID)
TXN.5.1#1

check.
All PCI Express Ports that support

more than VC0 must provide the
VC Capability Structure according
to the definition in the PCI Express
Base Specification Section 7.11.
TC to VC Mapping
TXN.5.2#1

check.
Every Traffic Class that is

supported must be mapped to one
of the Virtual Channels.
VC and TC Rules
TXN.5.3#1

check.
All PCI Express devices must

support the general purpose I/O
Traffic Class, (i.e., TC0 and must
implement the default VC0).
TXN.5.3#6
PCI_EXPRESS_TLP_
DOESNOT_
MAP_TO_ANY_VC
Transactions with a TC that is not

mapped to any enabled VC in a PCI
Express Ingress Port are treated as
malformed transactions by the
receiving device.
Ordering and
Receive Buffer Flow
Control
Flow Control Rules
Note: The Flow Control mechanism is used by the Requester to track the queue/buffer
space available in the Agent across the Link.
TXN.6.0#3
Not a monitor check
LCRC, Packet Framing Symbols,

other Special Symbols, and Data
Link Layer to Data Link Layer
inter-communication packets are
not associated with Flow Control
Credits and therefore, must be
processed by the receiver at the rate
they arrive (except as explicitly
noted in the PCI Express Base
Specification).
TXN.6.1#2

check.
The unit of Flow Control credit is 4

DW for Data.
521
PCI Express
Monitor Checks

Type
522
Rule
Check ID
Violation
TXN.6.1#3

check.
For headers, the unit of Flow

Control credit is one maximum-size
header plus TLP digest.
TXN.6.1#5

check.
There are six types of information

that must be tracked by Flow
Control for each Virtual Channel,
as shown in the PCI Express Base
Specification, Table 2-25.
TXN.6.1#6

check.
TLPs consume Flow Control

credits as shown in the PCI Express
Base Specification, Table 2-26.
TXN.6.1#7

check.
Components must implement

independent Flow Control for all
Virtual Channels that are supported
by that component.
TXN.6.1#8

check.
Flow Control is initialized

autonomously by hardware only for
the default Virtual Channel (VC0).
TXN.6.1#9

check.
VC0 is initialized when the Data

Link Layer is in the DL_Init state
following reset (see PCI Express
Base Specification, Sections 3.2
and 3.3).
TXN.6.1#10
Not a monitor check
When other Virtual Channels are

enabled by software, each newly
enabled VC follows the Flow
Control initialization protocol (see
Section 3.3).
TXN.6.1#13

check.
Disabling a Virtual Channel for a

component resets the Flow Control
tracking mechanisms for that
Virtual Channel in that component.
TXN.6.1#14
PCI_EXPRESS_FC_DLLP_IN_
DL_ACTIVE
InitFC1 and InitFC2 FCPs are used

only for Flow Control initialization
Specification, Section 3.3).
TXN.6.1#15

check.
An InitFC1, InitFC2, or UpdateFC

FCP that specifies a Virtual
Channel as disabled is discarded
without effect.
PCI Express
Monitor Checks

Type
Rule
Check ID
Violation
TXN.6.1#16
PCI_EXPRESS_PD_CREDIT_
LIMIT_VIOLATION
During FC initialization for any

Virtual Channel, including the
default VC initialized as a part of
Link initialization, Receivers must
initially advertise VC credit values
equal to or greater than those shown
in the PCI Express Base
Specification, Table 2-27.
PCI_EXPRESS_CPLH_
CREDIT_ LIMIT_VIOLATION
PCI_EXPRESS_CPLD_
TXN.6.1#17
PCI_EXPRESS_PD_CREDIT_
LIMIT_VIOLATION
PCI_EXPRESS_CPLH_
PCI_EXPRESS_CPLD_
TXN.6.1#18
Components can optionally check

for violations of TXN.6.1#16. If a
component implementing this
check determines a violation of this
rule, then the violation is a Flow
Control Protocol Error (FCPE) and
is a reported error associated with
the Receiving Port (see PCI
Express Base Specification, Section
6.2).
PCI_EXPRESS_UFC_P_FOR_IN If an Infinite Credit advertisement

FINIT_CREDIT
(value of 00h or 000h) has been
made during initialization, no Flow
PCI_EXPRESS_UFC_NP_FOR_I Control updates are required
NFINIT_CREDIT
following initialization.
PCI_EXPRESS_UFC_CPL_FOR
_INFINIT_CREDIT
TXN.6.1#19

check.
If only the Data or Header

advertisement (but not both) for a
given type (N, NP, or CPL) has
been made with infinite credits
during initialization, then the
transmission of UpdateFC DLLPs
is still required.
TXN.6.1#20
PCI_EXPRESS_UFC_PH_INVL

during initialization then the credit
field corresponding to the
Data/Header (advertised as infinite)
must be set to zero by the
Transmitter.
PCI_EXPRESS_UFC_PD_INVL
PCI_EXPRESS_UFC_NPH_INV
L
PCI_EXPRESS_UFC_NPD_INV
L
PCI_EXPRESS_UFC_CPLH_IN
VL
PCI_EXPRESS_UFC_CPLD_IN
VL
523
PCI Express
Monitor Checks

Type
Rule
Check ID
Violation
TXN.6.1#21
PCI_EXPRESS_UFC_PH_INVL
Components can optionally check

for violations of TXN.6.1#20. If a
component implementing this
check determines a violation of this
rule, then the violation is a Flow
Control Protocol Error (FCPE) and
is a reported error associated with
the Receiving Port (see PCI
6.2).
PCI_EXPRESS_UFC_PD_INVL
PCI_EXPRESS_UFC_NPH_INV
L
PCI_EXPRESS_UFC_NPD_INV
L
PCI_EXPRESS_UFC_CPLH_IN
VL
PCI_EXPRESS_UFC_CPLD_IN
VL
FC Information
Tracked by
Transmitter
524
TXN.6.1#22

check.

during initialization, then the credit
field corresponding to the
Data/Header (advertised as infinite)
must be ignored by the Receiver.
TXN.6.1#23

check.
The receiver can optionally check

for nonzero update values (in
violation of TXN.6.1#22). If a
receiver implementing this check
determines a violation of this rule,
then the violation is a Flow Control
Protocol Error (FCPE) and is a
reported error associated with the
Receiving Port (see PCI Express
TXN.6.1#24
PCI_EXPRESS_TLP_USING_U
NIT_VC
A TLP using an uninitialized VC is

a Malformed TLP. This is a
Receiving Port (see PCI Express
TXN.6.1#25

check.
Referring to TXN.6.1#22, if
UpdateFC DLLPs are sent, then the
credit value fields must be set to
zero and must be ignored by the
receiver.
TXN.6.2#1

check.
CREDITS_CONSUMED is set to
all 0s at the Interface Initialization.
PCI Express
Monitor Checks

Type
Rule
Check ID
Violation
TXN.6.2#2

check.
CREDITS_CONSUMED is
updated for each TLP the
Transaction Layer allows to pass
the Flow Control gate for
Transmission
CREDITS_CONSUMED :=
(CREDITS_CONSUMED +
Increment) modulo 2[Field Size] where [Field Size] is 8 for PH,
NPH, and CPLH and 12 for PD,
NPD and CPLD where Increment
is the size in FC credits of the
corresponding part of the TLP
passed through the gate.
TXN.6.2#4

check.
CREDIT_LIMIT is undefined at
Interface Initialization.
TXN.6.2#5

check.
CREDIT_LIMIT is set to the value

indicated at Flow Control
Initialization.
TXN.6.2#6

check.
CREDIT_LIMIT is the most recent

number of FC units legally
advertised by the Receiver. This
quantity must represent the total
number of FC credits made
available by the Receiver since
Flow Control initialization, modulo
2[Field Size] where [Field Size] is
8 for PH, NPH, and CPLH and 12
for PD, NPD, and CPLD.
TXN.6.2#7

check.
For each FC update received, if

CREDIT_LIMIT is not equal to the
update value, set CREDIT_LIMIT
to update value.
TXN.6.2#8
PCI_EXPRESS_TX_PH_
CREDIT_LIMIT_ VIOLATION
If the Transmitter does not have

enough credits to transmit a TLP,
then it must block the transmission
of that TLP.
PCI_EXPRESS_TX_NPH_
CREDIT_ LIMIT_ VIOLATION
PCI_EXPRESS_TX_PD_
PCI_EXPRESS_TX_NPD_
PCI_EXPRESS_TX_CPLD_
525
PCI Express
Monitor Checks

Type
FC Information
Tracked by Receiver
526
Rule
Check ID
Violation
TXN.6.2#9

check.
The Transmitter must follow the

ordering and deadlock avoidance
rules specified in the PCI Express
Base Specification, Section 2.4.
TXN.6.2#10

check.
The Transmitter gating function test

is performed as specified in the PCI
2.6.1.1.
TXN.6.2#11

check.
When accounting for credit use and

return, information from different
TLPs is never mixed within one
credit.
TXN.6.2#12

check.
When a TLP is blocked from

Transmission by a lack of FC
Credit, Transmitters must follow
the ordering rules specified in the
Section 2.4 when determining what
types of TLPs must be permitted to
bypass the stalled TLP.
TXN.6.2#13
Not a monitor check
Flow Control credit return is used

for receive buffer management
only, and Agents must not make
any judgment about the Completion
status or system visibility of a
Transaction based on the return or
lack of return of Flow Control
information.
TXN.6.2#14

check.
When a Transmitter sends a

nullified TLP (with inverted LCRC
and using EDB as the end Symbol),
the Transmitter does not modify
CREDITS_CONSUMED for that
TLP (see PCI Express Base
Specification Section 3.5.2.1).
TXN.6.3#1

check.
CREDITS_ALLOCATED is
initially set according to the buffer
size and allocation policies of the
Receiver.
PCI Express
Monitor Checks

Type
Rule
Check ID
Violation
TXN.6.3#2

check.
CREDITS_ALLOCATED is
incremented as the Receiver
Transaction Layer makes additional
receive buffer space available as
follows:
CREDITS_ALLOCATED :=
CREDITS_ALLOCATED +
Increment) modulo 2[Field Size]
where [Field Size] is 8 for PH,
NPH, and CPLH and 12 for PD,
NPD, and CPLD
where Increment corresponds to the
credits made available.
TXN.6.3#3

check.
CREDITS_RECEIVED set to all 0s

at Interface Initialization.
TXN.6.3#4

check.
CREDITS_RECEIVED (optional)
is the count of the total number of
FC units consumed by valid TLPs
Received since Flow Control
initialization.
TXN.6.3#6

check.
If a Receiver implements the

CREDITS_RECEIVED counter,
then when a nullified TLP (with
inverted LCRC and using EDB as
the end Symbol) is received, the
Receiver does not modify
CREDITS_RECEIVED for that
TLP.
TXN.6.3#7

check.

optional receiver overflow error
check and detects an overflow
condition, then the Receiver must
discard the TLP(s) without
modifying the
CREDITS_RECEIVED.
TXN.6.3#8

check.

condition, then the Receiver must
de-allocate any resources that it had
allocated for the TLP(s).
527
PCI Express
Monitor Checks

Type
Rule
Check ID
Violation
TXN.6.3#9
PCI_EXPRESS_RX_PH_

condition, then this is a reported
error associated with the Receiving
PCI_EXPRESS_RX_NPH_
PCI_EXPRESS_RX_PD_
PCI_EXPRESS_RX_NPD_
PCI_EXPRESS_RX_CPLD_
TXN.6.3#10

check.
For noninfinite NPH, NPD, PH,

and CPLH types, an UpdateFC FCP
must be scheduled for Transmission
each time the following sequence of
events occurs:
All advertised FC units for a
528
particular type of credit are

consumed by TLPs received.
One or more units of that type
are made available by TLPs
processed.
TXN.6.3#11

check.
For noninfinite PD and CPLD

types, when the number of
available credits is less than
Max_Payload_Size, an UpdateFC
FCP must be scheduled for
Transmission each time one or
more units of that type are made
available by TLPs processed.
TXN.6.3#12

check.
When the Link is in the L0 or L0s

Link state, Update FCPs for each
enabled type of noninfinite FC
credit must be scheduled for
transmission at least once every
30 s (-0%/+50%).
TXN.7.1#3

check.
If a device reports the capability to

check ECRC, it must support
Advanced Error Reporting (see PCI
6.2).
PCI Express
Monitor Checks

Type
Error Forwarding
Usage Model
Rule
Check ID
TXN.7.1#4
PCI_EXPRESS_ ECRC_ ERROR If a device is enabled to check

ECRC, then it must do so for all
TLPs received by the device that
include the ECRC.
TXN.7.1#6
PCI_EXPRESS_ ECRC_ ERROR A 32b ECRC is calculated for the

entire TLP (header and data
payload) using the algorithm
specified in the PCI Express Base
Specification, Section 2.7.1.
TXN.7.1#7
PCI_EXPRESS_ ECRC_ ERROR The seed value (initial value for

ECRC storage registers) is FFFF
FFFFh.
TXN.7.1#8
PCI_EXPRESS_ ECRC_ ERROR All invariant fields of the TLP

header and the entire data payload
(if present) are included in the
ECRC calculation, all bits in
variant fields must be set to 1 for
ECRC calculations.
TXN.7.1#9
PCI_EXPRESS_ ECRC_ ERROR ECRC calculation starts with bit 0

of Byte 0 and proceeds from bit 0 to
bit 7 of each Byte of the TLP.
TXN.7.1#10
PCI_EXPRESS_ ECRC_ ERROR The result of the ECRC calculation

is complemented, and the
complemented result bits are
mapped into the 32b TLP Digest
field as shown in the PCI Express
Base Specification, Table 2-29.
TXN.7.1#11
PCI_EXPRESS_ ECRC_ ERROR The 32b ECRC value is placed in

the TLP Digest field at the end of
the TLP.
TXN.7.2#1

check.
Error Forwarding is only used for

Read Completion Data or Write
Data.
TXN.7.2#2

check.
Error Forwarding should never be

used in cases where there are errors
in the header (request phase,
address/command, etc.).
TXN.7.2#3

check.
Error Forwarding does not cause

Link Layer Retry.
TXN.7.2#4

check.
Poisoned TLPs will be retried only

if there are transmission errors on
PCI Express as determined by the
TLP error detection mechanisms in
the Data Link Layer.
Violation
529
PCI Express
Monitor Checks

Type
Rule
Check ID
Rules for Use of Data

Poisoning
TXN.7.3#1
PCI_EXPRESS_GEN2_EP_BIT_ Data Poisoning applies only to the

VIOLATION
data within a Write Request (Posted
or Non-Posted) or a Read
Completion.
TXN.7.3#2
PCI_EXPRESS_POISONNED_T
LP
Poisoning of a TLP is indicated by

a 1b value in the EP field.
TXN.7.3#3
PCI_EXPRESS_POISONNED_T
LP
If a Transmitter supports data

poisoning, TLPs that are known to
the Transmitter to include bad data
must use the poisoning mechanism.
TXN.7.3#4
PCI_EXPRESS_ ECRC_ ERROR Receipt of a poisoned TLP is a

Receiving device/function (see PCI
6.2).
TXN.7.3#5

check.
A poisoned I/O, Memory Write

Request, Configuration Write, or a
Message with data (except for
Vendor_Defined Messages) that
addresses a control register or
control structure in the Completer
must be handled as an Unsupported
Request (UR) by the Completer.
TXN.9.1#7

check.
For a Port on an Endpoint, and the

Port on a Switch, or the Bridge that
is closest to the Root Complex,
DL_Down status is handled as a
Link reset by returning all PCI
Express-specific registers, state
machines, and externally
observable state to the specified
default or initial conditions (except
for registers defined as sticky
Specification, Section 7.4)).
Transaction Layer
Behavior in
DL_Down Status
Violation
Table 14-19. PCI Express Compliance Checklist: Link Protocol

Type
Rule
Check IDs
Violation
Data Link Control

and Management
State Machine
DLL.2.1#1
Monitor cannot perform

this check.
A components link must enter the

DL_Inactive state within 80 ms of the
end of Fundamental Reset as it
observes (Derived from Section 6.6 of
the PCI Express Base Specification).
530
PCI Express
Monitor Checks
Table 14-19. PCI Express Compliance Checklist: Link Protocol (cont.)

Type
Rule
Check IDs
Violation
DLL.2.1#2

this check.
All components must be ready to receive

configuration requests within 100 ms of
the end of reset (cold/warm/hot) as they
observe. (Derived from Section 6.6 of the
PCI Express Base Specification.)
DLL.2.1#11

this check.
Upon entry into DL_Inactive state, the

contents of the Data Link Layer Retry
Buffer must be discarded.
DLL.2.1#12

this check.
DL_Inactive : While in DL_Inactive:

Report DL_Down status to the
Transaction Layer as well as to the
rest of the Data Link Layer.
DLL.2.1#13
PCI_EXPRESS_DLP_
TLP_IN_DL_DOWN

Discard TLP information from the
Transaction and Physical Layers.
DLL.2.1#14
PCI_EXPRESS_DLP_
TLP_IN_DL_DOWN

Do not generate or accept DLLPs.
DLL.2.1#15
PCI_EXPRESS_DLP_
TLP_IN_DL_DOWN
DL_Inactive : Exit to DL_Init if and only

if:
Indication from the Transaction
Layer that the Link is not disabled by
software and the Physical Layer
reports Physical LinkUp = 1.
DLL.2.1#16

this check.
While in DL_Init and state FC_INIT1,

report DL_Down status.
DLL.2.1#17

this check.
While in DL_Init and in state FC_INIT2,

report DL_Up status.
DLL.2.1#18

this check.
While in DL_Init, exit to DL_Active if:

Flow Control initialization completes
successfully and the Physical Layer
continues to report Physical LinkUp = 1.
DLL.2.1#19

this check.
While in DL_Init, terminate attempt to

initialize Flow Control for VC0 and Exit
to DL_Inactive if: Physical Layer reports
Physical LinkUp = 0.
DLL.2.1#20

this check.
While in DL_Active, report DL_Up

status to the Transaction and Data Link
Layers.
DLL2.1#21

this check.
While in DL_Active, exit to DL_Inactive

if the Physical layer reports physical
linkup = 0.
Flow Control
DLL.3.1#1
Initialization Protocol

this check.
Disabling of VCx (x!=0) during

initialization of VCx terminates the
initialization process for VCx.
531
PCI Express
Monitor Checks

Type
532
Rule
Check IDs
Violation
DLL.3.1#2
PCI_EXPRESS_TLP_
IN_FC_INIT1
For any VCx, while in FC_INIT1, all

TLPs for that VCx are blocked by the
transaction layer.
DLL.3.1#3
PCI_EXPRESS_FC_
DLLP_IN_FC_INIT1
For VC0, while in FC_INIT1,

uninterrupted ordered (P, NP, and Cpl)
triplets of IntiFC1 DLLPs must be sent at
the maximum rate possible on the Link.
DLL.3.1#4
PCI_EXPRESS_FC_
DLLP_IN_FC_INIT1
For all VCx (x!=0), while in FC_INIT1

triplet of InitFC1 DLLPs must be sent
when there are no TLPs or DLLPs for
transmission but no less frequently than
at an interval of 17uSec(-0%/+100%)
measured from the start of the preceding
sequence.
DLL.3.1#5

this check.
For any VCx, while in FC_INIT1 exit to

FC_INIT2 only after the FC Unit values
have been recorded for each of P, NP,
and Cpl for that VCx.
DLL.3.1#6
PCI_EXPRESS_FC_
DLLP_IN_FC_INIT2
For VC0, while in FC_INIT2 an

triplet of InitFC2 DLLPs must be
transmitted, once transmission of an
InitFC2 DLLP (P) starts.
DLL.3.1#6.1

this check.
For any VCx, while in FC_INIT2, the

Flow Control State machine must ignore
the FC unit values received.
DLL.3.1#7
PCI_EXPRESS_FC_
DLLP_IN_FC_INIT2
For all VCx (x!=0), while in FC_INIT2

uninterrupted ordered (P, NP, Cpl) triplet
of InitFC2 DLLPs must be sent when
there are no TLPs or DLLPs for
transmission but no less frequently than
at an interval of 17uSec(-0%/+100%)
measured from the start of the preceding
sequence.
DLL.3.1#8

this check.
For any VCx, Flow control initialization

state machine must exit out of FC_INIT2
if an InitFC2 DLLP for that VCx has
been received.
DLL.3.1#9

this check.

if a TLP has been received for that VCx.
DLL.3.1#10

this check.

if an UpdateFC DLLP has been received
for that VCx.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
Data Link Layer

Packet Rules
EP and RC only
DLL.4.1#1
PCI_EXPRESS_
RESERVED_
FIELD_ERROR
All fields marked reserved in a DLLP

must be filled with 0s before
transmission.
DLL.4.1#2
PCI_EXPRESS_
RESERVED_
FIELD_ ERROR
Upon receiving a DLLP, the Data Link

Layer receiver state machine must ignore
reserved fields.
DLL.4.1#3
PCI_EXPRESS_DLL_
PKT_16BIT_CRC
Byte +4 and byte +5 of any DLLP shall

hold the 16bit CRC value for that DLLP.
DLL.4.1#4
PCI_EXPRESS_FC_
DLLP_IN_DL_ACTIVE
InitFC1 and InitFC2 DLLPs MUST be

used only during a virtual channel
initialization.
DLL.4.1#5

this check.
Bits 7:0 of Type must be 0000 0000b for

an ACK DLLP.
DLL.4.1#6

this check.

a NAK DLLP.
DLL.4.1#7
PCI_EXPRESS_
RESERVED_
FIELD_ERROR
Bits 7:0 of Byte 1 and 7:4 of Byte 2 of

ACK/NAK DLLP are reserved.
DLL.4.1#8

this check.
Bits 7:4 of Type must be 0100b for

InitFC1-P (Posted) DLLPs.
DLL.4.1#9

this check.

InitFC1-NP (Non-Posted) DLLPs.
DLL.4.1#10

this check.
Bits7:4 of Type must be 0110b for

InitFC1-Cpl (Completion) DLLPs.
DLL.4.1#11
PCI_EXPRESS_
RESERVED_
FIELD_ERROR
Bit 3 of byte +0 must be zero for IntiFC1

DLLPs.
DLL.4.1#12

this check.
Bits 2:0 of byte +0 must specify the

Virtual Channel ID for which this
InitFC1 DLLP applies.
DLL.4.1#13

this check.
Bits 5:0 of byte +1 and bits 7:6 of byte +2

of an InitFC1 DLLP must specify the
Flow credits for Headers.
DLL.4.1#14

this check.

Flow credits for Data.
DLL.4.1#15

this check.

InitFC2-P (Posted) DLLPs.
DLL.4.1#16

this check.
Bits 7:4 of Type must be 1101b InitFC2NP (Non-Posted) DLLPs.
DLL.4.1#17

this check.

InitFC2-Cpl (Completion) DLLPs.
533
PCI Express
Monitor Checks

Type
534
Rule
Check IDs
Violation
DLL.4.1#18
PCI_EXPRESS_
RESERVED_
FIELD_ERROR
Bit 3 of byte +0 must be zero for IntiFC2

DLLPs.
DLL.4.1#19

this check.

InitFC2 DLLP applies.
DLL.4.1#20

this check.

DLL.4.1#21

this check.

DLL.4.1#22

this check.

UpdateFC-P (Posted) DLLPs.
DLL.4.1#23

this check.
Bits 7:4 of Type must be 1001b for NP

(Non-Posted) UpdateFC-NP (NonPosted) DLLPs.
DLL.4.1#24

this check.
Bits 7:4 of Type must be 1010b for Cpl

(Completion) UpdateFC-Cpl
(Completion) DLLPs.
DLL.4.1#25
PCI_EXPRESS_
RESERVED_
FIELD_ERROR
Bit 3 of byte +0 must be zero for

UpdateFC DLLPs.
DLL.4.1#26

this check.

UpdateFC DLLP applies.
DLL.4.1#27

this check.

of an UpdateFC DLLP must specify the
DLL.4.1#28

this check.

of an UpdateFC DLLP must specify the
DLL.4.1#29

this check.

PM_Enter_L1 DLLPs.
DLL.4.1#30

this check.

PM_Enter_L23 DLLPs.
DLL.4.1#31

this check.

PM_Active_State_Request_L1 DLLPs.
DLL.4.1#32

this check.

PM_Request_Ack DLLPs.
DLL.4.1#33

this check.

Vendor Specific DLLPs.
PCI Express
Monitor Checks

Type
LCRC and Sequence

Number Rules (TLP
Transmitter)
Rule
Check IDs
Violation
DLL.4.1#34
PCI_EXPRESS_DLL_
PKT_16BIT_CRC
All DLLPs must be covered by a 16-bit

CRC in bytes +4 and +5.
DLL.4.1#34.1
PCI_EXPRESS_DLL_
PKT_16BIT_CRC
The 16-bit CRC for all DLLPs must be

based on the polynomial with coefficient
100Bh.
DLL.4.1#34.2
PCI_EXPRESS_DLL_
PKT_16BIT_CRC
The 16-bit CRC for all DLLPs must be

based on seed value (initial value for
CRC storage registers) of FFFFh.
DLL.4.1#34.3
PCI_EXPRESS_DLL_
PKT_16BIT_CRC
The calculation of the 16-bit CRC for all

DLLPs must start with bit 0 of byte 0 and
proceeds from bit 0 to bit 7 of each byte.
DLL.4.1#34.4
PCI_EXPRESS_DLL_
PKT_16BIT_CRC
The 16-bit CRC for all DLLPs cover all

fields in the DLLP including reserved
fields.
DLL.5.2#1
PCI_EXPRESS_RETRY_ The link transmitter must start REPLAY

AFTER_NAK
of its RETRY_BUF as soon as (after
finishing the current TLP in progress) a
NAK is received.
DLL.5.2#1.1
PCI_EXPRESS_RETRY_ The link transmitter must start REPLAY

AFTER_NAK
of its RETRY_BUF upon its
REPLAY_TIMER expiring when there
are still some TLPs which have not
received Ack or Nak DLLPs.
DLL.5.2#1.2
PCI_EXPRESS_
REPLAY_NUM_
EXPIRED
A TLP must be retransmitted until a

positive acknowledgement has been sent
by the receiver and received by the
transmitter and REPLAY_NUM does not
overflow while retransmitting (subject to
timeout values in Table 3.4 including RxL0s_Adjustment and Table 3.5 including
Tx_L0s_Adjustment).
DLL.5.2#1.3

this check.
The REPLAY_TIMER timeout value is

measured at the Port of the TLP
transmitter from the last Symbol of TLP
to the First Symbol of TLP
retransmission and is as shown in the PCI
Express Base Specification Table 3.4
(including Rx_L0s_Adjustment) for
different Max_Payload_Size and Link
Operating Width combinations.
DLL.5.2#2
PCI_EXPRESS_
REPLY_NUM_
EXPIRED
If repeated retries fail and

REPLAY_NUM overflows, then the link
transmitter must ask the Physical Layer
to retrain the link. There must be a
reported error to correspond to this as per
Section 6.2.
535
PCI Express
Monitor Checks

Type
536
Rule
Check IDs
Violation
DLL.5.2#3
PCI_EXPRESS_FIRST_
TLP_AFTER_LINK_ UP
The first TLP transmitted after coming

out of DL_Inactive state must have TLP
sequence number equal to zero.
DLL.5.2#4

this check.
The REPLAY_NUM counter that counts

the number of times the Retry buffer has
been retransmitted must be reset to zero
in DL_Inactive state.
DLL.5.2#5
PCI_EXPRESS_MAX_
UNACKD_TLP
If there are 2048 or more TLPs that have

not received Ack or Nak DLLPs, then the
link transmitter must stop accepting
TLPs from the Transaction Layer for that
virtual channel.
DLL.5.2#6
PCI_EXPRESS_SEQ_
NUM_AFTER_ NULL_
TLP
When a TLP is issued with the final

framing symbol == EDB and LCRC is
inverted the next TLP transmit sequence
number must be the same as that in the
TLP with the EDB framing symbol.
DLL.5.2#7

this check
The link state (including the contents of

retry buffer) must not change in link
retraining if Physical LinkUp=1.
DLL.5.2#8

this check
The link transmitter must not accept new

TLPs from the Transaction Layer while
in replay.
DLL.5.2#9
This is a redundant check.
Before starting replay, any TLP currently

in transmission must be completed.
DLL.5.2#10
PCI_EXPRESS_
RETRY_TLP
Oldest unacknowledged TLP must be

sent first in replay and followed by the
rest of the unacknowledged TLPs in the
original transmission order.
DLL.5.2#12

this check.
While in replay, if multiple Acks and

Naks are collapsed, then an ACK
received for the latest TLP (with a latest
sequence number) should make the Acks
and Naks received for prior TLPs
irrelevant.
DLL.5.2#13
PCI_EXPRESS_RETRY_ A TLP can only be retransmitted after the

WITHOUT_ REPLY_
timer value (-0% / +100%) specified by
OR_NAK
Table 3.4 plus ReceiverL0s adjustment
offset (if L0s is enabled, otherwise the
adjustment is 0) expires (for a given
Max_Payload size and link width) and if
no ACK or NAK (for that TLP) has been
received by the transmitter within that
time.
DLL.5.2#14

this check.
If Physical Layer indicates a Receive

Error, discard any DLLP currently being
received and free storage for that DLLP.
PCI Express
Monitor Checks

Type
LCRC and Sequence

Number Rules (TLP
Receiver)
Rule
Check IDs
Violation
DLL.5.2#15
All corrupt DLLPs must be discarded and

be reported as an error associated with
the port.
DLL.5.2#16
PCI_EXPRESS_
UNDEFINED_
DLLP_ ENCODING
A DLLP with undefined encodings shall

be dropped silently by the receiver with
no error associated.
DLL.5.2#17
PCI_EXPRESS_
ACKNAK_SEQ_
NUM_ ERROR
If an Ack DLLP does not have a

sequence number of an unacknowledged
TLP, or of the most recently
acknowledged TLP, it must be reported
as a DL Layer protocol error associated
with the port.
DLL.5.2#18
Once the transmitter has started to

retransmit a TLP, it must complete
transmission of that TLP in all cases.
DLL.5.2#19

this check.
If all TLPs transmitted have been

acknowledged (Retry buffer empty), then
the replay must be terminated and normal
operation must restart including
accepting new TLPs at the transaction
layer.
DLL.5.2#20
PCI_EXPRESS_ TLP_
LINK_CRC
TLP integrity is protected at the data link

layer by a 32-bit LCRC applied by a link
transmitter.
DLL.5.3#1

this check.
If a TLP is received with EDB end

framing symbol, and the LCRC is the
logical NOT of the calculated value, then
discard the TLP and free any storage
associated with it. Not an error.
DLL.5.3#2
PCI_EXPRESS_NO_
NAK_DLLP_FOR_TLP
If a normal TLP (one with END framing

symbol) is received and its LCRC does
not match calculated CRC, then discard
the TLP, free any storage associated with
it, schedule a NAK DLLP for
transmission if one is not already
scheduled, and report an error associated
with the Port.
DLL.5.3#3
PCI_EXPRESS_INCR_
SEQ_NUM_TLP
If the sequence number does not match

with expected value, then discard the
TLP and free any storage associated with
it.
537
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
DLL.5.3#4
PCI_EXPRESS_
ACKNAK_
TIMER_ EXPIRED
An Ack or Nak shall be issued by the

receiver if the
AckNak_LATENCY_TIMER reaches or
exceeds the time limit set in the PCI
Express Base Specification Table 3.5
plus Tx_L0s_adjustment (if L0s is
enabled otherwise the adjustment value is
0) for a given Max_Payload_Size and
link width.
DLL.5.3#5

this check.
The AckNak LATENCY_TIMER must

start from zero every time an Ack or Nak
DLLP has been scheduled for
transmission.
DLL.5.3#6
PCI_EXPRESS_ TLP_
LINK_CRC
The LCRC value of a received TLP is

checked by applying the same algorithm
used in calculation on the transmission
side.
DLL.5.4#1
PCI_EXPRESS_
RESERVED_
FIELD_ERROR
All fields marked as reserved must be

filled with zeros (0) before transmission.
Table 14-20. PCI Express Compliance Checklist: Link-Physical Layer Interface

Type
Rule
Check IDs
Violation
Symbol Encoding
PHY.2.1#1
ERROR
Valid received symbols are found in

the proper column of Appendix B
corresponding to the current running
disparity.
PHY.2.1#2
PCI_EXPRESS_10B_
CODING_VIOLATION
Received symbols found in the column

of Appendix B corresponding to the
incorrect running disparity or not
corresponding to either column are
invalid, and the Physical Layer must
notify the Data Link Layer that the
received symbol is invalid.
538
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
Framing and
Application of
Symbols to Lanes
PHY.2.2#1
ALL_LANES
Ordered-sets are always transmitted

serially on each lane such that a fullordered set appears simultaneously on
all lanes of a multilane link.
ALL_LANES
ALL_LANES
ALL_LANES
ALL_LANES
PHY.2.2#2
PCI_EXPRESS_END_
WITHOUT_STP_SDP
The Framing mechanism uses Special

Symbol K28.2 SDP to start a DLLP.
PHY.2.2#3
PCI_EXPRESS_END_
WITHOUT_STP_SDP

Symbol K27.7 STP to start a TLP.
PHY.2.2#4
FOLLOWED_BY_END_EDB

Symbol K29.7 END to mark the end
of either a TLP or DLLP.
PHY.2.3#1

check.
TLPs must be framed by placing an

STP Symbol at the start of the TLP and
an END Symbol or EDB Symbol at the
end of the TLP (see Figure 4-9).
PHY.2.3#2

check.
DLLPs must be framed by placing an

SDP Symbol at the start of the DLLP
and an END Symbol at the end of the
DLLP (see PCI Express Base
Specification Figure 4-11).
PHY.2.3#3
DATA
When the transmitter is in Logical Idle,

the Idle data character (00h) shall be
transmitted on all lanes. This is
scrambled according to the rules in the
Section 4.2.3.
PHY.2.3#4

check.
Receivers must ignore incoming

Logical Idle data, and must not have
any dependency other than scramble
sequencing on any specific data
patterns.
PHY.2.3#5
PCI_EXPRESS_NO_SDP_
STP_LANE0
For Links wider than x1, the STP

Symbol (representing the start of a
TLP) must be placed in Lane 0 when
starting Transmission of a TLP from a
Logical Idle Link condition.
539
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PHY.2.3#6
PCI_EXPRESS_NO_SDP_
STP_LANE0
For Links wider than x1, the SDP

Symbol (representing the start of a
DLLP) must be placed in Lane 0 when
starting Transmission of a DLLP from
a Logical Idle Link condition.
PHY.2.3#7
PCI_EXPRESS_MORE_
THAN_ONE_STP
The STP symbol must not be placed on

the Link more frequently than once per
Symbol Time.
PHY.2.3#8
PCI_EXPRESS_MORE_
THAN_ONE_SDP
The SDP symbol must not be placed

on the Link more frequently than once
per Symbol Time.
PHY.2.3#9
PCI_EXPRESS_MORE_
THAN_ONE_STP
TLP and DLLP Transmissions are

permitted to follow each other
successively as long as the STP and
SDP Symbols are not placed on the
Link more frequently than once per
Symbol Time.
PCI_EXPRESS_MORE_
THAN_ONE_SDP
Data Scrambling
540
PHY.2.3#10
ERROR
For xN Links where N is 8 or more, if

an END or EDB Symbol is placed in a
Lane K, where K does not equal N-1,
PCI_EXPRESS_PAD_WHEN_ and is not followed by a STP or SDP
LINK_WIDTH_1_2_4
Symbol in Lane K+1 (i.e., there is no
TLP or DLLP immediately following),
then PAD Symbols must be placed in
Lanes K+1 to Lane N-1.
PHY.2.3#11
WITH_END
The EDB Symbol is used to mark the

end of a nullified TLP.
PHY.2.3#12
Monitor fires when an error is

detected.
Receivers can optionally check for

violations of the rules of this section.
Any violation is a Receiver Error and
is a reported error associated with the
PHY.2.4#1

check.
When there is more than one transmit

Linear Feedback Shift Register (LFSR)
per Link, these must operate in concert,
maintaining the same simultaneous
(see PCI Express Base Specification
Table 4-5, Lane-to-Lane Output Skew)
value in each LFSR.
PHY.2.4#2

check.
When there is more than one receive

LFSR per Link, these must operate in
concert, maintaining the same
simultaneous (see PCI Express Base
Specification Table 4-6, Total Skew)
value in each LFSR.
PHY.2.4#3

check.
The COM character initializes the

LFSR.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PHY.2.4#4

check.
The LFSR value is advanced eight

serial shifts for each character, except
the SKP.
PHY.2.4#5

check.
All data characters (D codes), except

those within a Training Sequence
Ordered-sets (TS1, TS2), and the
Compliance Pattern are scrambled.
PHY.2.4#6

check.
All special characters (K codes) are not

scrambled.
PHY.2.4#7

check.
The initialized value of an LFSR seed

(D0-D15) is FFFFh.
PHY.2.4#8

check.
Immediately after a COM exits the

transmit LFSR, the LFSR on the
transmit side is initialized. Every time
a COM enters the receive LFSR on any
Lane of that Link, the LFSR on the
receive side is initialized.
PHY.2.4#9
PCI_EXPRESS_SCRAMBLIN
G_DISABLE_ERROR
Scrambling can only be disabled at the

end of Configuration.
PHY.2.4#10
This is not a monitor check
Scrambling does not apply to a

Loopback Slave.
PHY.2.4#11

check.
Scrambling is always enabled in Detect

by default.
Monitor checks fire if a training

error is detected.

violations of the Link Initialization and
Training Protocols. If such checking is
implemented, then any violation is a
Training Error. A Training Error is a
reported error associated with the Port
Section 6.2) and is considered fatal to
the Link.
Link Initialization and PHY.2.5#1

Training
Training Sequence Ordered-sets

PHY.2.6#1

check.
Training sequence ordered-sets are

never scrambled but always 8b/10b
encoded.
PHY.2.6#2

check
Training sequences (TS1 or TS2) are

transmitted consecutively and can only
be interrupted by SKP ordered sets (see
Section 4.2.7).
PHY.2.6#3

check.
In order for N_FTS to be valid two or

more TSx, ordered-sets must be
received with the same value.
Lane Polarity Inversion
541
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PHY.2.7#1
Not a check.
Lane polarity inversion occurs when

the TS1 symbols 6-15 received are
D21.5 as opposed to the expected
D10.2 and symbols 6-15 of the TS2
ordered-set are D26.5 as opposed to
the expected D5.2.
PHY.2.7#2

check.
Receiver inverts received data when

polarity inversion is detected. The
transmitters must never insert the
transmitted data.
PHY.2.7#3

check.
Lane Polarity Inversion supported

across all Lanes.
Fast Training Sequence

PHY.2.8#1
PCI_EXPRESS_FTS_
COUNT_ERROR
The maximum number of FTS

ordered-sets (N_FTS) that a
component can request is 255
(providing a bit lock time of 4 * 255 *
10 * UI).
PHY.2.8#2
PCI_EXPRESS_FTS_
COUNT_ERROR
4096 FTS ordered-sets are sent when

the Extended Synch bit is set.
PHY.2.8#3
PCI_EXPRESS_SKP_OS_
NOT_XMTD
PCI_EXPRESS_SKP_OS_
NOT_RCVD
SKP ordered-sets must be scheduled

and transmitted between FTS orderedsets as necessary to meet the
definitions in the PCI Express Base
Specification Section 4.2.7 with the
exception that no SKP ordered-sets can
be scheduled during the first N_FTS
FTS ordered-sets.
PHY.2.8#4
PCI_EXPRESS_NO_SKP_
AFTER_FTS
A single SKP ordered-set is always

sent after the last FTS is transmitted.
PHY.2.8#5

check.
If the N_FTS period of time expires

before the Receiver obtains bit,
Symbol, and Lane-to-Lane de-skew on
all Lanes of the configured Link, then
the Receiver must transition to
Recovery (see PCI Express Base
Link Error Recovery

PHY.2.9#1
542
Yes
8b/10b de-code errors trigger a

Receiver Error (Table 4-4).
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PHY.2.9#2

check.
On a configured Link in L0, error

recovery will at a minimum be
managed in a Layer above the Physical
Layer (see PCI Express Base
Specification Section 3.5) by directing
the Link to transition to Recovery.
(Note: Link Errors can also result in
the Physical Layer initiating a LTSSM
state transition from L0 to Recovery).
PHY.2.9#3

check.
All LTSSM states other than L0 make

progress when Link Errors occur
(Note: Link errors that occur, while in
LTSSM states other than L0, must not
result in the Physical Layer initiating a
LTSSM state transition).
PHY.2.9#4

check.
If a Lane detects an 8b/10b decode

error, then symbol lock must be
verified or re-established as soon as
possible.
Fundamental Reset
PHY.2.10#1
Fundamental Reset applies only when

Main power is present.
PHY.2.10#2
Fundamental Reset does not apply with

no power or only Aux power.
PHY.2.10#3
When Fundamental Reset is asserted:

Receiver terminations are required
to only meet.
RX-HIGH-IMP-DC (see PCI
Express Base Specification Table
4-6).
Transmitter terminations are
required to only meet ZTX-DC
Specification Table 4-6).
Transmitter holds a constant DC
common mode voltage.
PHY.2.10#4
When Fundamental Reset is deasserted, the Port LTSSM (PCI

4.2.5) is initialized (i.e., Detect is
immediately entered).
Link Data Rate Negotiation

PHY.2.11#1
DATA_RATE
All devices are required to start Link

initialization using a generation 1 data
rate on each Lane.
543
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PHY.2.11#2

check.
A field in the training sequence

ordered-set advertises all supported
data rates. Any higher speed supported
by both sides of the Link will be
initiated during Polling.Speed.
Link Width and Lane Sequence Negotiation

PHY.2.12#1
LINK_WIDTH
PCI Express Links consist of 1, 2, 4, 8,

12, 16, or 32 Lanes in parallel (referred
to as x1, x2, x4, x8, x12, x16, and x32
links respectively).
PHY.2.12#2
All Lanes within a Link shall

simultaneously (as defined by
LTX-SKEW in the PCI Express Base
Specification Table 4-5) transmit data
based on the exact same frequency.
PHY.2.12#3

check.
The negotiation establishes values for

Link Number and Lane Number for
each Lane that is part of a valid Link;
each Lane that is not part of a valid
Link exits the negotiation to become a
separate Link or remain in Electrical
Idle.
PHY.2.12#4
PCI_EXPRESS_DESKEW_
LIMIT_EXCEEDED
During Link width and Lane number

negotiation, the two communicating
ports must accommodate the maximum
allowed Lane-Lane skew as specified
by LRX-SKEW in the PCI Express
Base Specification Table 4-6.
Required/Optional Port Behavior
544
PHY.2.13#1
LINK_WIDTH
The ability for a xN port to form a xN

Link as well as a x1 Link (where N can
be 32, 16, 12, 8, 4, 2, and 1) is
required.
PHY.2.13#2

check.
The ability for a xN Port to form any

Link width between N and 1 is
optional.
PHY.2.13#3
The ability to split a Port into two or

more links is optional.
PHY.2.13#4
Support for Lane reversal is optional.

(Note: Lane reversal must be done for
both the transmitter and receiver of a
given Port for a multi-Lane Link).
PHY.2.13#5

check.
Support for formation of a crosslink is

optional.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
Lane-to-Lane
De-skew
PHY.2.14#1
PCI_EXPRESS_DESKEW_
LIMIT_EXCEEDED
The receiver must compensate for the

allowable skew between Lanes within
a multi-Lane Link (see PCI Express
Base Specification Tables 4-5 and 4-6)
before delivering the data and control
to the Data Link Layer.
PHY.2.14#2

check.
Lane-to-Lane de-skew shall be done

across all Lanes within multi-Lane
links.
PHY.2.14#3

check.
Lane-to-Lane de-skew must be

performed during Configuration,
Recovery, and L0s in the LTSSM.
PHY.2.15#1
DATA_RATE_IDENTIFIER
For Lanes to configure properly into a

desired link, the TS1 and TS2 orderedsets must have the appropriate fields
(symbol 3, 4, and 5) set to the same
value on all Lanes.
Lane vs. Link

Training
LINK_CONTROL_FIELD
Link Training and

Status State Machine
(LTSSM)
Descriptions
PHY.2.15#2

check.
Links are formed at the conclusion of

Configuration. (Note: If the optional
behavior of a Port being able to
configure multiple links is employed,
then a separate LTSSM is needed for
the maximum number of links that are
desired to be configured by any given
Port).
PHY.2.16#1

check
All timeout values must be set to the

specified values after power-on/reset.
PHY.2.16#1

check.
All counter values must be set to the

specified values after power-on/reset.
PHY.2.17#1

check.
In Detect.Quiet:
Transmitter is in Electrical Idle
state.
Generation 1 data rate is selected.
LinkUp=0.
PHY.2.17#2

check.
From Detect.Quiet, the LTSSM enters

Detect.Active after a 12 ms timeout or
if Electrical Idle is broken on any
Lane.
PHY.2.17#3

check.
In Detect.Active, the transmitter

performs a Receiver Detection
sequence on all unconfigured Lanes
that can form one or more Links (see
Section 4.3.1.8).
Detect
545
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PHY.2.17#4

check.
The LTSSM exits to Polling if a

receiver is detected on all unconfigured
Lanes.
PHY.2.17#5

check.
The LTSSM exits to Detect.Quiet if a

Receiver is not detected on any Lanes.
PHY.2.17#6

check.
If at least one, but not all,

un-.configured Lanes detect a receiver,
then the following:
Wait for 12 ms.
The transmitter performs a
Receiver Detection sequence on
all unconfigured Lanes that can
form one or more Links (see PCI
Express Base Specification
Section 4.3.1.8).
PHY.2.17#7

check.
If exactly the same lanes detect a

Receiver as the first Receiver
Detection sequence, then the LTSSM
enters Polling. (Note: Lanes that did
not detect a receiver must either be
associated with a new LTSSM (if this
optional feature is supported) or
transition to Electrical Idle.)
PHY.2.17#8

check.
If exactly the same lanes do not detect

a receiver as in the first Receiver
Detection sequence, then the LTSSM
reverts to Detect.Quiet.
PHY.2.18#1
PCI_EXPRESS_VALID_
LINK_NUM
In Polling.Active, the transmitter sends

TS1 ordered-sets with Lane and Link
numbers set to PAD (K23.7) on all
Lanes that detected a Receiver during
Detect.
PHY.2.18#2
COUNT_ERROR
From Polling.Active, the LTSSM

enters Polling.Configuration after 8
consecutive TS1 or TS2 ordered-sets
or their complement is received with
the Lane and Link numbers set to PAD
(K23.7) on all Lanes that detected a
receiver during Detect and at least
1024 TS1 Ordered sets were
transmitted.
Polling
546
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PHY.2.18#3

check.
After a 24 ms timeout in
Polling.Active, the LTSSM enters
Polling.Configuration if any Lane,
which detected a Receiver during
Detect, received 8 consecutive TS1 or
TS2 ordered-sets (or their
complement) with the Lane and Link
numbers set to PAD (K23.7), and a
minimum of 1024 TS1s are transmitted
after receiving one TS1;
and all lanes that detected a Receiver
during Detect have detected an exit
from Electrical Idle at least once since
entering Polling.
PHY.2.18#4

check.
Polling.Compliance if at least one
Lanes Receiver, which detected a
Receiver during Detect, has never
detected an exit from Electrical Idle
since entering Polling.Active.
PHY.2.18#5

check.
Detect if no TS1 or TS2 ordered-set is
received with Link and Lane number
set to Pad on any Lane. The highest
advertised speed in TS1 and TS2 is
lowered (unless generation 1 is the
highest advertised speed).
PHY.2.18#6

check.
In Polling.Compliance, the transmitter

sends out the compliance pattern on all
Lanes that detected a Receiver during
Detect at the data rate that was
employed upon entry to
Polling.Compliance (see PCI Express
Base Specification Section 4.2.8).
PHY.2.18#7

check.
From Polling.Compliance, the LTSSM

returns to Polling.Active if Electrical
Idle exit has been detected at the
receiver of all Lanes that detected a
Receiver during Detect.
PHY.2.18#8

check.
In Polling.Configuration, the Receiver

must invert polarity if necessary (see
Section 4.2.4.2).
PHY.2.18#9
PCI_EXPRESS_VALID_LINK In Polling.Configuration, the

_NUM
Transmitter sends TS2 ordered-sets
with link and lane numbers set to PAD
(K23.7) on all Lanes that detected a
Receiver during Detect.
547
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PHY.2.18#10 PCI_EXPRESS_TS2_
COUNT_ERROR
From Polling.Configuration, the

LTSSM exits to Configuration after 8
consecutive TS2 ordered-sets are
received on any Lanes that detected a
Receiver during Detect, 16 TS2
ordered-sets are transmitted after
receiving one TS2 ordered-set, and
none of those same Lanes is
transmitting and receiving a higher
Data Rate Identifier.
PHY.2.18#11 PCI_EXPRESS_TS2_
COUNT_ERROR

LTSSM enters Polling.Speed after 8
received on any Lanes that detected a
Receiver during Detect, 16 TS2
ordered-sets are transmitted after
receiving one TS2 ordered-set, and at
least one of those same Lanes is
transmitting and receiving a higher
Data Rate Identifier.
PHY.2.18#12 Monitor cannot perform this

check.
In Polling.Speed:
The transmitter enters Electrical
Idle for a minimum of TTX-IDLEMIN (see PCI Express Base
Specification Table 4-5) and no
longer than 2 ms.
Data rate is changed on all lanes to
the highest common data rate
supported on both sides of the
Link indicated by the training
sequence (see PCI Express Base
Specification Section 4.2.4.1).
The LTSSM then reverts back to
Polling.Active.

check.

LTSSM exits to Detect after 48 ms of
timeout.
Configuration
548
PHY.2.19#1

check.
(Downstream Lanes) In
Configuration.Linkwidth.Start, the
LTSSM exits to Disable if directed.
PHY.2.19#2

check.
LTSSM exits to Loopback if directed,
and the Transmitter is capable of being
a Loopback Master.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PHY.2.19#3

check.
Configuration.Linkwidth.Start, where
a cross-link is supported, LTSSM exits
to Disable after all Lanes that detected
a Receiver during Detect and are
receiving TS1 ordered-sets with the
Disable Link bit asserted in 2
consecutive TS1 ordered-sets.
PHY.2.19#4

check.
LTSSM exits to Loopback if all Lanes
that detected a Receiver during Detect
receive the Loopback bit asserted in 2
consecutive TS1 ordered-sets on all
Lanes receiving a TS1 ordered-set.
PHY.2.19#5
PCI_EXPRESS_VALID_
LINK_NUM
Transmitter sends TS1 ordered-sets
with selected Link numbers and sets
Lane numbers to PAD (K23.7) on
Downstream Lanes that are in
Configuration.
PHY.2.19#6

check.
Configuration.Linkwidth.Start, if any
Lanes first received at least one or
more TS1 ordered-sets with a Link and
Lane number set to PAD (K23.7), then
the next state is
Configuration.Linkwidth.Accept
immediately after any of those same
downstream Lanes receive 2
consecutive TS1 ordered-sets with a
non-PAD Link number that matches
any of the transmitted Link.
PHY.2.19#7

check.
(Downstream Lanes) If cross-links are

supported and all Downstream Lanes
initially receive 2 consecutive TS1
ordered set with a Link number
different than PAD (K23.7) and a Lane
Number set to PAD, then the
Downstream Lanes are now designated
as Upstream Lanes and a new random
cross Link timeout is chosen (see
Tcrosslink in the PCI Express Base
Specification Table 4-5). The next state
is Configuration.Linkwidth.Start as
Upstream Lanes.
549
PCI Express
Monitor Checks

Type
550
Rule
Check IDs
Violation
PHY.2.19#8

check.
LTSSM exits to Detect after a 24 ms
timeout.
PHY.2.19#9

check.
(Upstream Lanes) In
Configuration.Linkwidth.Start, where
a cross-link is supported, the LTSSM
exits to Disable if directed (by a higher
Layer to assert the Disable Link bit
(TS1 and TS2) on all Lanes that
detected a receiver during Detect).

check.
(Upstream Lanes) In
LTSSM exits to Loopback if directed
(by a higher Layer to assert the
Loopback bit (TS1 and TS2) on all
Lanes that detected a receiver during
Detect), and the Transmitter is capable
of being a Loopback Master.

check.
(Upstream Lanes) In
LTSSM exits to Disable after any
Lanes (all Lanes in the optional case
where a cross-link is supported) that
detected a Receiver during Detect and
are receiving TS1 ordered-sets with the
Disable Link bit asserted in 2
consecutive TS1 ordered-sets.

check.
(Upstream Lanes) In
LTSSM exits to Loopback if all Lanes
that detected a Receiver during Detect,
that are also receiving TS1 ordered
sets, receive the Loopback bit asserted
in 2 consecutive TS1 ordered-sets.
PHY.2.19#13 PCI_EXPRESS_VALID_
LINK_NUM
(Upstream Lanes) In
Transmitter sends out TS1 ordered-sets
with Link numbers and Lane numbers
set to PAD (K23.7) on Upstream Lanes
that detected a Receiver during Detect.
PCI Express
Monitor Checks

Type
Rule
Check IDs
PHY.2.19#14 PCI_EXPRESS_
UPSTREAM_
PORT_STARTED_LINK_
WIDTH_NEG
Violation
(Upstream Lanes) In
Configuration.Linkwidth.Start, if any
Lanes receive 2 consecutive TS1
ordered sets with Link numbers that
are different than PAD (K23.7), a
single Link number is selected and
transmitted on all Lanes that both
detected a Receiver and also received
two consecutive TS1 ordered sets with
Link numbers that are different than
PAD (K23.7) and Lane number is set
to PAD (K23.7). Any leftover Lanes
that detected a Receiver during Detect
must transmit TS1 ordered-sets with
the Link and Lane number set to PAD
(K23.7). The next state is
Configuration.Linkwidth.Accept.
Optionally, if cross-links are supported
and all Upstream Lanes first receive 2
consecutive TS1 ordered set with Link
and Lane numbers set to PAD (K23.7),
then the following:
The Transmitter continues to send
out TS1 ordered-sets with Link
numbers and Lane numbers set to
PAD (K23.7).
If any Lanes receive 2 consecutive
TS1 ordered sets with Link
numbers that are different than
PAD (K23.7), then a single Link
number is selected and transmitted
on all Lanes that both detected a
Receiver and also received two
consecutive TS1 ordered sets with
Link numbers that are different
than PAD (K23.7) and Lane
number is set to PAD (K23.7).
Any left over Lanes that detected a
Receiver during Detect must
transmit TS1 ordered-sets with the
Link and Lane number set to PAD
(K23.7). The next state is
Configuration.Linkwidth.Accept.
Otherwise, after a Tcrosslink
timeout the Upstream Lanes
become Downstream Lanes and
the next state is
Configuration.Linkwidth.Start as
Downstream Lanes.
551
PCI Express
Monitor Checks

Type
552
Rule
Check IDs
Violation

check.
(Upstream Lanes) In
timeout.
PHY.2.19#16 PCI_EXPRESS_ILLEGAL_
LANE_NUMBER_
ASSIGNED
Configuration.Linkwidth.Accept, if a
configured Link can be formed with at
least one group of Lanes that received
2 consecutive TS1 ordered-sets with
the same received Link number (nonPAD and matching one that was
transmitted by the Downstream
Lanes), then TS1 ordered sets are
transmitted with the same Link number
and unique non-PAD Lane numbers
are assigned to all these same Lanes
NOTE: The assigned non-PAD Lane
numbers must range from 0 to n 1, be
assigned sequentially to the same
grouping of Lanes that are receiving
the same Link numbers, and
Downstream Lanes that are not
receiving TS1 ordered sets must not
disrupt the initial sequential numbering
of the widest possible Link.
Any leftover Lanes must transmit TS1
ordered sets with the Link and Lane
number set to PAD (K23.7). The
LTSSM then enters
Configuration.Lanenum.Wait.

check.
Configuration.Linkwidth.Accept, the
timeout or if no Link can be configured
or if all Lanes receive 2 consecutive
TS1 ordered-sets with Link and Lane
numbers set to PAD (K23.7).
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
LANE_NUMBER_
ASSIGNED
(Upstream Lanes) In
Configuration.Linkwidth.Accept, if a
configured Link can be formed using
Lanes that transmitted a non-PAD Link
number which are receiving 2
consecutive TS1 ordered-sets with the
same (non-PAD) Link number and any
non-PAD Lane number, then TS1 Lane
numbers are transmitted that if possible
match the received Lane numbers or
are different if necessary (i.e., lanereversed).
NOTE: the newly assigned transmitted
Lane numbers must range from 0 to
m-1, be assigned sequentially only to
some continuous grouping of Lanes
that are receiving non-PAD Lane
numbers (i.e., Lanes which are not
receiving any TS1 ordered sets always
disrupt a continuous grouping and
must not be included in the grouping),
must include either Lane 0 or n-1
(largest received Lane number), and
m-1 must be equal to or smaller than
the largest received Lane number
(n-1).
Remaining Lanes must transmit TS1
with Link and Lane numbers set to
PAD (K23.7). The LTSSM then enters
Configuration.Lanenum.Wait.

check.
(Upstream Lanes) In
Configuration.Linkwidth.Accept, the
timeout or if no Link can be configured
or if all Lanes receive 2 consecutive
TS1 ordered-sets with Link and Lane
numbers set to PAD (K23.7).

check.
Configuration.Lanenum.Wait, the
LTSSM enters
Configuration.Lanenum.Accept if any
of the Lanes receive 2 consecutive TS1
that have a Lane number different from
when it first entered
Configuration.Lanenum.Wait, and not
all the Lanes Link numbers are set to
PAD (K23.7).
553
PCI Express
Monitor Checks

Type
554
Rule
Check IDs
Violation

check.
timeout or if all Lanes receive 2
consecutive TS1 ordered-sets with
Link and Lane numbers set to PAD
(K23.7).

check.
(Upstream Lanes) In
LTSSM transitions to
Configuration.Lanenum.Accept if the
following:
Any of the Lanes receive 2
consecutive TS1 that have a Lane
number different from when it first
entered
Configuration.Lanenum.Wait, and
not all the Lanes Link numbers
are set to PAD (K23.7), or
Any Lane receives 2 consecutive
TS2 ordered-sets.

check.
(Upstream Lanes) In
timeout or if all Lanes receive 2
(K23.7).

check.
Configuration.Lanenum.Accept, the
LTSSM enters
Configuration.Complete if two
received with non-PAD Link and nonPAD Lane numbers (or reversed Lane
numbers if Lane reversal is optionally
supported) that are being transmitted in
Downstream Lane TS1 ordered-sets.

check.
LTSSM transmits TS1 ordered-sets
with new Lane numbers assigned and
enters Configuration.Lanenum.Wait if
a configured Link can be formed with
any subset of the Lanes that receive
two consecutive TS1 ordered sets with
the same transmitted non-PAD Link
numbers and any non-PAD Lane
numbers.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation

check.
LTSSM exits to Detect if no Link can
be configured or if all Lanes receive 2
(K23.7).

check.
(Upstream Lanes) In
LTSSM enters
Configuration.Complete if two
received with non-PAD Link and nonPAD Lane numbers that match all nonPAD Link and non-PAD Lane
numbers that are being transmitted in
Upstream Lane TS1 ordered-sets.

check.
(Upstream Lanes) In
LTSSM transmits TS1 ordered-sets
with new Lane numbers assigned and
enters Configuration.Lanenum.Wait if
a configured Link can be formed with
any subset of the Lanes that receive
two consecutive TS1 ordered-sets with
the same transmitted non-PAD Link
numbers and any non-PAD Lane
numbers.

check.
LTSSM exits to Detect if no Link can
be configured or if all Lanes receive 2
(K23.7).
555
PCI Express
Monitor Checks

Type
556
Rule
Check IDs
Violation

check.
Configuration.Complete,
TS2 ordered-sets are transmitted
using Link and Lane numbers that
match the received TS1 Link and
Lane numbers.
N_FTS must be noted for use in
L0s when leaving this state.
completed when leaving this state.
Scrambling is disabled if all
configured Lanes have the Disable
Scrambling bit asserted in 2
consecutively-received TS2
ordered-sets.
IDLE_DATA
Configuration.Complete, the LTSSM
transitions to Configuration.Idle
immediately after all Lanes that are
transmitting TS2 ordered-sets receive 8
matching Lane and Link numbers
(non-PAD) and 16 TS2 ordered-sets
are sent after receiving one TS2
ordered-set.

check.
exits to Detect after a 2 ms timeout.

check.
(Upstream Lanes) In
Configuration.Complete,
TS2 ordered-sets are transmitted
using Link and Lane numbers that
match the received TS2 Link and
Lane numbers.
N_FTS must be noted for use in
L0s when leaving this state.
completed when leaving this state.
Scrambling is disabled if all
configured Lanes have the Disable
Scrambling bit asserted in 2
consecutively received TS2
ordered-sets.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
IDLE_DATA
(Upstream Lanes) In
transitions to Configuration.Idle
immediately after all Lanes that are
transmitting TS2 ordered-sets receive 8
matching Lane and Link numbers
(non-PAD) and 16 TS2 ordered-sets
are sent after receiving one TS2
ordered-set.

check.
(Upstream Lanes) In
PHY.2.19#36 PCI_EXPRESS_IDLE_DATA_ In Configuration.Idle,

NOT_ALL_LANES
Transmitter sends Idle data
symbols on all configured Lanes.
Receiver waits for Idle data.
LinkUp = 1.
PHY.2.19#37 PCI_EXPRESS_IDLE_
COUNT_ERROR
From Configuration.Idle, the LTSSM

exits to L0 if 8 consecutive Symbol
Times of Idle data received on all
configured Lanes and 16 Idle data
Symbols are sent after receiving one
Idle data Symbol.

check.
From Configuration.Idle, the LTSSM

exits to Detect after a minimum 2ms
timeout
Recovery
PHY.2.20#1
ALL_LANES
In Recovery.RcvrLock, the transmitter

sends TS1 ordered-sets on all
configured Lanes using the same Link
and Lane numbers that were set after
leaving Configuration.
PHY.2.20#2
TS2_OS
In Recovery.RcvrLock, the LTSSM

enters Recovery.RcvrCfg if 8
consecutive TS1 or TS2 ordered-sets
are received on all configured Lanes
with the same Link and Lane numbers
that match what is being transmitted on
those same Lanes.
557
PCI Express
Monitor Checks

Type
558
Rule
Check IDs
Violation
PHY.2.20#3

check.
In Recovery.RcvrLock, after a 24 ms
timeout, the LTSSM reverts to
Configuration if all the configured
Lanes that are receiving a TS1 or TS2
ordered-set have received at least one
TS1 or TS2 with Link and Lane
numbers that match what is being
transmitted on those same Lanes.
Otherwise, the LTSSM reverts to
Detect.
PHY.2.20#4
ALL_LANES
In Recovery.RcvrCfg, the transmitter

sends TS2 ordered-sets on all
configured Lanes using the same Link
and Lane numbers that were set after
leaving Configuration.
PHY.2.20#5
IDLE_DATA
From Recovery.RcvrCfg, the LTSSM

enters Recovery.Idle if 8 consecutive
TS2 ordered-sets are received on all
configured Lanes with the same Link
and Lane numbers that match what is
being transmitted on those same Lanes,
and 16 TS2 ordered-sets are sent after
receiving one TS2 ordered-set.
PHY.2.20#6

check.

falls back to Configuration if 8
received on any configured Lanes with
Link or Lane numbers that do not
match what is being transmitted on
those same Lanes, and 16 TS2 orderedsets are sent after receiving one TS2
ordered-set.
PHY.2.20#7

check.

PHY.2.20#8

check.
From Recovery.Idle, the LTSSM of a

downstream or optional cross-link Port
exits to Disabled if directed by a higher
Layer to assert the Disable Link bit
(TS1 and TS2) on the Link.
PHY.2.20#9

check.
From Recovery.Idle, the LTSSM of a

downstream or optional cross-Link
port exits to Hot Reset if directed by a
higher Layer to assert the Hot Reset bit
(TS1 and TS2) on the Link.

check.
From Recovery.Idle, the LTSSM exits

to Configuration if directed by a higher
Layer to optionally reconfigure the
Link (i.e., different width Link).
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation

check.

to Loopback if directed by a higher
Layer to assert the Loopback bit (TS1
and TS2) on the Link and the
transmitter is capable of being a
Loopback Master.

check.
From Recovery.Idle, the LTSSM of

upstream and optional cross-Link ports
exits to Disabled immediately after any
configured Lane has the Disable Link
bit asserted in 2 consecutively received
TS1 ordered-sets.

check.
From Recovery.Idle, the LTSSM of

upstream and optional cross-Link ports
exits to Hot Reset immediately after
any configured Lane has the Hot Reset
bit asserted in 2 consecutive TS1
ordered-sets.

check.

to Configuration if 2 consecutive TS1
ordered-sets are received on any
configured Lane with a Lane number
set to PAD.

check.

to Loopback if any configured Lane
has the Loopback bit asserted in 2
consecutive TS1 ordered-sets. (Note:
Device receiving the ordered-set with
the Loopback bit set becomes the
Loopback Slave.)
DATA_NOT_ALL_LANES
In Recovery.Idle, the transmitter sends

Idle data on all configured Lanes.
COUNT_ERROR

to L0 if 8 consecutive symbol times of
Idle data is received on all configured
Lanes, and 16 Idle data symbols are
sent after receiving one Idle data
symbol.

check.

to Detect after a 2 ms timeout.
L0
PHY.2.21#1

check.
In L0, LinkUp = 1.
PHY.2.21#2

check.
From L0, the LTSSM exits to

Recovery if a TS1 or TS2 ordered-set
received on any configured Lane.
559
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PHY.2.21#3

check.
From L0, the LTSSM exits to

Recovery if directed by a higher Layer
or if Electrical Idle is detected without
receiving an Electrical Idle orderedset.
PHY.2.21#4

check.
From L0, the transmitter transitions to

L0s if directed by a higher Layer.
PHY.2.21#5

check.
From L0, the receiver transitions to

L0s if the receiver detects an Electrical
Idle ordered-set and is not directed to
the L1 or L2 states.
PHY.2.21#6

check.
From L0, the LTSSM transitions to L1

if directed (both ends of the Link have
agreed to enter L1), and an Electrical
Idle ordered-set is received and
transmitted.
PHY.2.21#7

check.
From L0, the LTSSM transitions to L2

if directed (both ends of the Link have
agreed to enter L2), and an Electrical
Idle ordered-set is received and
transmitted.
PHY.2.22#1

check.
From Rx_L0s.Entry, the Receiver

enters Rx_L0s.Idle after a TTX-IDLESET-TO-IDLE (see PCI Express Base
Specification Table 4-5) timeout.
PHY.2.22#2

check.
From Rx_L0s.Idle, the Receiver enters

Rx_L0s.FTS if the receiver detects an
exit from Electrical Idle on any Lane of
the configured Link.
PHY.2.22#3
ALL_LANES
From Rx_L0s.FTS, the Receiver exits

to L0 if a SKP ordered-set is received
on all configured Lanes of the Link.
PHY.2.22#4

check.
From Rx_L0s.FTS, the Receiver enters

Recovery after the N_FTS timeout.
PHY.2.22#5

check.
In Tx_L0s.Entry, the Transmitter sends

the Electrical Idle ordered-set and
enters Electrical Idle.
PHY.2.22#6

check.
In Tx_L0s.Entry, the Transmitter

enters Tx_L0s.Idle after a TTX-IDLEMIN (see PCI Express Base
Specification Table 4-5) timeout.
PHY.2.22#7

check.
In Tx_L0s.Idle, the Transmitter enters

Tx_L0s.FTS if directed.
L0s
560
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PHY.2.22#8
PCI_EXPRESS_FTS_
COUNT_ERROR
In Tx_L0s.FTS, the Transmitter exits

to L0 after sending N_FTS Fast
Training Sequences and a single SKP
ordered-set on all configured Lanes.
PHY.2.23#1

check.
In L1.Entry, all configured

Transmitters should be in Electrical
Idle.
PHY.2.23#2

check.
From L1.Entry, the LTSSM transitions

to L1.Idle after a TTX-IDLE-MIN (see
PCI Express Base Specification Table
4-5) timeout.
PHY.2.23#3

check.
In L1.Idle, the Transmitter remains in

Electrical Idle.
PHY.2.23#4

check.
From L1.Idle, the LTSSM exits to

Recovery if directed or any Receiver
detects exit from Electrical Idle.
PHY.2.24#1
In L2.Idle, all Rx terminations must

remain in low impedance.
PHY.2.24#2

check.
In L2.Idle, all configured Transmitters

must remain in Electrical Idle for a
minimum time of TTX-IDLE-MIN
Table 4-5).
PHY.2.24#3
For downstream Lanes in L2.Idle, a

Root Port shall transition to Detect if a
Beacon is received on at least Lane 0
or if directed.
PHY.2.24#4
For downstream Lanes in L2.Idle, the

upstream Port of a Switch must
transition to L2.TransmitWake if a
Beacon is received on at least Lane 0.
PHY.2.24#5

check.
Upstream Lanes in L2.Idle shall

transition to Detect if Electrical Idle
Exit is detected on any Lane. (NOTE:
A Switch must transition any
Downstream Lanes to Detect.)
PHY.2.24#6
An upstream port in L2.Idle shall

transition to L2.TransmitWake if
directed to transmit a Beacon. (NOTE:
Beacons can only be transmitted on
upstream Ports in the direction of the
Root Complex.)
L1
L2
561
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PHY.2.24#7
In L2.TransmitWake, upstream Ports

shall transmit the Beacon on at least
Lane 0.
PHY.2.24#8

check.
In L2.TransmitWake, upstream Ports

shall transition to Detect if Electrical
Idle exit is detected on any Upstream
Ports Receiver.
PHY.2.25#1
PCI_EXPRESS_DISABLE_
OS_ERROR
In Disabled, all Lanes transmit 16 to 32

TS1 ordered-sets with the Disable Link
bit (bit 1) asserted and then transition
to Electrical Idle. (NOTE: An
Electrical Idle ordered-set must be sent
prior to entering Electrical Idle.)
PHY.2.25#2

check.
In Disabled, if an Electrical Idle

ordered-set was transmitted and
received (even while transmitting TS1
with the Disable Link bit asserted),
then LinkUp = (False) and the LTSSM
exits to Detect when directed or if
Electrical Idle is exited.
PHY.2.25#3

check.
In Disabled, if no Electrical Idle

ordered-set is received after a 2 ms
timeout, then the LTSSM exits to
Detect.
PHY.2.26#1

check.
In Loopback.Entry, LinkUp=0 (False).
PHY.2.26#2

check.
In Loopback Entry, the Loopback

Master device transmits TS1 orderedsets with the Loopback bit (Bit 2)
asserted until the Loopback Master
receives identical TS1 ordered sets
with the Loopback bit asserted and
then enters Loopback.Active.
PHY.2.26#3

check.
In Loopback.Entry, the Loopback

Slave immediately transitions to
Loopback.Active.
PHY.2.26#4
PCI_EXPRESS_CODE_
VIOLATION_LOOPBACK
In Loopback.Active, the
Loopback.Master must send valid
8b/10b characters and enter
Loopback.Exit if directed.
Disabled
Loopback
562
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PHY.2.26#5

check
In Loopback.Active, a Loopback Slave

is required to retransmit each 10b data
and control symbols exactly as
received without applying
scrambling/descrambling, or disparity
corrections with the following three
exceptions:
If a received 10b symbol is
determined to be an invalid 10b
code, then the slave must instead
transmit the EDB symbol in the
corresponding time slot of the
invalid symbol. Either positive or
negative disparity can be chosen
for the EDB symbol.
If a SKP ordered set
retransmission requires adding a
SKP symbol to accommodate
timing tolerance correction, then
the SKP symbol is inserted in the
retransmitted symbol stream
anywhere in the SKP ordered-set
following the COM symbol. Either
positive or negative disparity can
be chosen for the inserted SKP
symbol.
If a SKP ordered-set
retransmission requires dropping a
SKP symbol to accommodate
timing tolerance correction, then
the SKP symbol is not
retransmitted, and transmission
continues with the next received
symbol or an EDB, as defined
above.
PHY.2.26#6

check.
In Loopback.Active, a Loopback Slave

shall enter Loopback.Exit when an
Electrical Idle ordered-set is received
or Electrical Idle is detected.
PHY.2.26#7

check.
In Loopback.Active, the Loopback

Master enters Loopback.Exit if
directed.
563
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PHY.2.26#8

check.
In Loopback.Exit:
The Loopback Master sends an
Electrical Idle ordered-set and
enters Electrical Idle on all Lanes
for a minimum of 2 ms.
The Loopback Master must
transition to a valid Electrical Idle
condition on all Lanes within
TTX-IDLE-SET-TO-IDLE after
sending the Electrical Idle
ordered-set.
The Loopback Slave must enter
Electrical Idle on all Lanes for a
minimum of 2 ms. NOTE: Before
entering Electrical Idle, the
Loopback Slave must Loopback
all Symbols that were received
prior to detecting Electrical Idle.
The Loopback Master and Slave
then exit to Detect.

check.
Lanes that were directed by a higher

Layer to initiate Hot Reset:
All Lanes in the configured Link
Hot Reset bit (bit 0) asserted and
the configured Link and Lane
numbers.
If two consecutive TS1 ordered
sets with the Hot Reset bit (bit 0)
asserted are received, then the
following:
LinkUp=0 (False).
Next state is Detect if no higher
Layer is directing the physical
Layer to remain in Hot Reset.
Otherwise, all Lanes in the
configured Link continue to
transmit TS1 ordered-sets with
the Hot Reset bit (bit 0) asserted
and the configured Link and
Lane numbers.
Otherwise, after a 2 mS
timeout, the next state is Detect.
Hot Reset
PHY.2.27#1
564
PCI Express
Monitor Checks

Type
Clock Tolerance
Compensation
Rule
Check IDs
Violation
PHY.2.27#2

check.
Lanes that were not directed by a

higher Layer to initiate Hot Reset (i.e.,
received two consecutive TS1 orderedsets with the Hot Reset bit (bit 0)
asserted on any configured Lanes):
LinkUp=0 (False).
If any Lane of an Upstream Port of
a Switch receives a training
sequence with the Hot Reset bit
asserted, then all configured
Downstream Ports must transition
to Hot Reset as soon as possible.
All Lanes in the configured Link
Hot Reset bit (bit 0) asserted and
the configured Link and Lane
numbers.
If two consecutive TS1 orderedsets were received with the Hot
Reset bit (bit 0) asserted and the
configured Link and Lane
numbers, then the next state is Hot
Reset.
Otherwise, after a 2 ms timeout,
the next state is Detect.
PHY.2.28#1

check.
The Receiver Physical Layer logical

sub-block must include elastic
buffering to compensate for
differences in frequencies between bit
rates at the two ends of a link.
PHY.2.28#2
(Transmitters) All Lanes shall transmit

Symbols at the same frequency.
PHY.2.28#3
ALL_LANES
(Transmitters) When transmitted, SKP

ordered-sets shall be transmitted
simultaneously on all Lanes of a multiLane Link.
PHY.2.28#4
PCI_EXPRESS_SKP_
ORDERED_SET_ERROR
(Transmitters) The transmitted SKP

ordered-set is as follows: one COM
Symbol followed by three consecutive
SKP Symbols.
PHY.2.28#5
PCI_EXPRESS_SKP_OS_
NOT_XMTD
(Transmitters) The SKP ordered-sets

shall be scheduled for insertion at an
interval between 1180 and 1538
Symbol Times.
565
PCI Express
Monitor Checks

Type
566
Rule
Check IDs
Violation
PHY.2.28#6
PCI_EXPRESS_SKP_OS_
NOT_XMTD
(Transmitters) Scheduled SKP

ordered-sets shall be transmitted if a
packet or ordered-set is not already in
progress; otherwise, they are
accumulated and then inserted
consecutively at the next packet or
ordered-set boundary.
PHY.2.28#7

check.
(Transmitters) SKP ordered-sets do not

count as an interruption when
monitoring for consecutive characters
or ordered-sets.
PHY.2.28#8
PCI_EXPRESS_SKP_
ORDERED_SET_ERROR
(Receivers) Receivers shall recognize

received SKP ordered-sets consisting
of one COM Symbol followed
consecutively by one to five SKP
Symbols. (NOTE: The number of
received SKP symbols in an orderedset shall not vary from Lane to Lane in
a multi-Lane Link.)
PHY.2.28#9
PCI_EXPRESS_SKP_OS_
NOT_RECEIVED
Receivers shall be tolerant to receive

and process SKP ordered-sets at an
average interval between 1180 to 1538
symbol times.

check.
(Receivers) Receivers shall be tolerant

to receive and process consecutive
SKP ordered-sets. (NOTE: Receivers
shall be tolerant to receive and process
SKP-ordered sets that have a
maximum separation dependent on the
maximum payload size (in bytes) a
component supports. The formula for
the maximum number of Symbols (N)
between SKP ordered-sets is as
follows:
N = 1538 + (Max_Payload_Size + 26)
PHY.2.28#11 Monitor does not perform this

check.
SKP ordered-sets must not be

transmitted while the Compliance
Pattern is in progress during
Polling.Compliance.

check.
Any and all time spent in any lower

power Link state (L0s, L1, L2) does
not count in the 1180 to 1538 Symbol
interval used to schedule the
transmission of SKP ordered-sets.

check.
During all lower power Link states any

counter(s) or other mechanisms used to
schedule the SKP ordered-sets must be
reset.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
Compliance Pattern
PHY.2.29#1

check.
During Polling, the

Polling.Compliance substate must be
entered if test equipment is attached to
one Lane of a possible Link and being
detected during the Detect State.
PHY.2.29#2
PCI_EXPRESS_
COMPLIANCE_
PATTERN_ERROR
The compliance pattern consists of the

sequence of 8b/10b symbols K28.5,
D21.5, K28.5, and D10.2 repeating.
PHY.2.29#4

check
For any given device that has multiple

lanes, every eighth Lane is delayed by
a total of four symbols. A two symbol
(K28.5) delay occurs at both the
beginning and end of the four symbol
sequence. After the eight symbols are
sent, the delay symbols are advanced
to the next Lane and the process is
repeated.
PHY.2.29#5

check.
The compliance pattern can be exited

only when an Electrical Idle Exit is
detected at all the Lanes that detected a
receiver during Detect.
Table 14-21. PCI Express Compliance Checklist: Electrical

Type
Rule
Check IDs
PHY.3.1#1 to PHY.3.4#11
Violation
Table 14-22. PCI Express Compliance Checklist: Power Management

Type
Rule
Check IDs
Violation
General High Level

Power Management
Requirements
PMG.1.0#1
All components (except RC) must

meet minimum requirements
defined by PCI-PM Software
compatible PCI Express-PM
features.
PMG.2.0#11

check.
An upstream initiated transaction

targeting a Link in L0sor L1 must
cause the Link to transition back to
L0.
PMG.3.7#1
A function that supports Wakeup

from D3-cold must maintain the full
PME context (power management
status and control register) for
software use.
567
PCI Express
Monitor Checks
Table 14-22. PCI Express Compliance Checklist: Power Management (cont.)

Type
General L0 and L0s

Requirements
Rule
Check IDs
Violation
PMG.3.7#2
A function can only generate

Wakeup from D3-cold if the
platform supplies a Vaux supply, or
if they have an independent source
of power and the device is enabled
for Wake functionality.
PMG.1.1#2
Active State Link Power

Management using the L0s state
must be supported by all PCI
Express components.
PMG.2.0#1
All PCI Express components must

support the L0 active state.
PMG.2.0#2
All power supplies, component

reference clocks, and components
internal PLLs must be active during
L0 and L0s.
PMG.2.0#3
PCI_EXPRESS_TLP_IN_L0S
No TLP or DLLP communication is

allowed over a side of a link in the
L0s state.
PCI_EXPRESS_DLLP_IN_L0S
General L1
Requirements
PMG.2.0#4
PCI_EXPRESS_TLP_IN_L1
No TLP or DLLP communication is

allowed over a link the L1 state.
PCI_EXPRESS_DLLP_IN_L1
General L2/L3
Ready, L2, and L3
Requirements
PMG.2.0#5

support the L1 state.
PMG.2.0#8
Not a monitor check
The L2/L3 Ready transition protocol

must be supported.
PMG.2.0#9
TLP and DLLP communication over

a Link that is in L2/L3 Ready is
prohibited.
PMG.2.0#10
Not a monitor check
After successful completion of the

L2/L3 ready transition protocol, a
Link must transition to L3 when
main power is removed if the system
does not provide a Vaux supply. It
must not transition before the main
power is removed.
PMG.2.0#15
TLLP and DLLP communication

over a Link that is in L2 is
prohibited.
568
PMG.2.0#16

check.
TLLP and DLLP communication

over a Link that is in L3 is
prohibited.
PMG.2.0#19
A component can only consume

VAUX power if enabled to do so.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
Device Power
Management States
(D-States)
PMG.3.1#1

check.
PCI Express functions must support

D0 and D3.
PMG.3.2#1

check.
When a PCI Express function is

powered on it must initially default
to the D0-uninitialized state.
PMG.3.2#2

check.
A function must enter the D0-active

state whenever the Memory Space
Enable, I/O Space Enable, or Bus
Master Enable bits have been set.
PMG.3.2#3

check.
A function must not initiate any bus

cycles from the D0-uninitialized
state.
PMG.3.3#1

check.
All TLPs except configuration

requests must be handled as
unsupported requests by a function
in the D1 state.
PMG.3.3#3
Any outstanding TLPs for a function

must be terminated before it can
transition to D1.
PMG.3.4#2
All TLPs except configuration

requests must be handled as
unsupported requests by a function
in the D2 state.
PMG.3.4#3

must be terminated before it can
transition to D2.
PMG.3.5#1
If a function supports PME

generation from D3, then it must
support it for both D3-cold and
D3-hot.
PMG.3.5#2
A function must be able to resume

normal operation within 10 ms of a
D3-hot to D0 transition.
PMG.3.5#3
Functions must support both D3-hot

and D3-cold.
PMG.3.6#1
When a function is in D3-hot, it

must respond to configuration
requests and the
PM_Turn_Off/PM_TO_Ack
protocol. All other TLPs targeting
the function must be treated as
unsupported requests.
PMG.3.6#2

must be terminated before
transitioning to D3-hot.
569
PCI Express
Monitor Checks

Type
General
Requirements for
Software Control of
the Link Power
Management State
Rule
Check IDs
Violation
PMG.3.6#3
Having D0 written to its PMCSR

register must cause a function in D3hot to transition to the D0uninitialized state.
NOTE: These are steady-state requirements.
PMG.3.8#9
When a downstream component is

in D3-cold, its link must be in L2 or
L3.
Entry to the L1 State PMG.3.9#9

in Software
Controlled Power
Management
Downstream
Components
Once both ends of a link are in L1,

the components must suspend
operation of Flow Control Update,
DLLP ACK/NAK Latency, and the
TLP Completion Timeout counter
mechanisms.

in Software
Controlled Power
Management
Upstream
Components

check.
A downstream component must

schedule a completion response
corresponding to a configuration
write to the PMSCR field when it
receives a TLP request that
transitions the device to D1, D2, or
D3-hot. It must suspend all new TLP
scheduling.
PME
Synchronization
Before Power
Removal
PMG.3.13#2
WITHOUT_TURN_OFF
When a PME_Turn_Off broadcast

message is received, a downstream
component must respond with a
PME_TO_ACK message. This
requirement applies when the
component is in D3-hot.
Additional PME
Rules
PMG.3.15#1

check.
All components must implement the

PCI-PM PMC and PMCSR registers
in accordance with the PCI-PM
specification.
PMG.3.15#2
PME capable functions must

implement the PME_Status bit and
related behavior in their PMCSR
configuration register.
PMG.4.1#1

check.
If the L0s state is enabled in a

device, then it must bring any
transmit Link into the L0s state
whenever that Link is not in use.
PMG.4.1#2

check.

support the L0s state from within the
D0 state.
Active State Power

Management
570
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
General Active L0s

Rules
PMG.4.2#1

check.
All PCI Express devices must

support the L0s low power link
state.
PMG.4.2#2

check.
Transaction Layer and Link Layer

timers must not be affected by the
transition to the L0s state.
PMG.4.3#1

check.
A device not enabled for L0s must

be able to handle having its receive
lanes brought in/out of the L0s state
while continuing to function
normally.
PMG.4.3#2

check.
A port enabled for L0s must

transition its transmit lanes to L0s
within 7 microseconds if the defined
idle conditions are met.
PMG.4.4#1

check.
A lack of FC credits must not

prevent a link from transitioning
from L0s to L0.
PMG.4.4#4

check.
A component must initiate L0s exit

when it has a TLP or DLLP to
transmit across the link.

(Optional)

check.
If a PM_Active_State_Request_L1
DLLP is sent and refused, then the
Link must enter L0s ASAP if the
L0s entry conditions are met.
PMG.4.7#9
PCI_EXPRESS_L0S_ENTRY_
WHEN_DISABLED

component is set to 10b (L1 only), a
ports transmitter must not enter
L0s.
PMG.4.7#10

check.

component is set to 11b, the port
must bring its link into the L0s state
(unless an L1 entry attempt is
successful).
Auxiliary Power
Support
PMG.5.1#2
A component must not draw Aux

power unless enabled.
Power Management
and System
Messages and
DLLPs
PMG.6.0#1
LENGTH_FIELD_ERROR
The length and address field must be

reserved in all Power Management
System Messages.
PMG.6.0#2
ATTR_FIELD_ERROR
The attribute field must be all zeroes

in all Power Management System
Messages.
Entry to the L0s

State
Exit from the L0s

State
Active State Link PM

Configuration
571
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PMG.6.0#4

check.
For PM_PME messages, the device

and function number must correctly
indicate where the PME originated.
PMG.6.0#5
TC_FIELD_ERROR
The traffic class field for all Power

Management and System Messages
must use the default class (TC0).
Table 14-23. PCI Express Compliance Checklist: System Architecture

Type
Rule
Check IDs
Interrupt Support
Requirements
SYS.1.1#2 to
SYS.1.2#4
General Error
Reporting
Requirements
SYS.2.1#1 to
SYS.2.3#1
Error Logging
Requirements
SYS.2.4#1 to
SYS.2.6#1
Error Listing and

Rules
SYS.2.7#1 to
SYS.2.7#24
PCI Mapping
SYS.2.8#1,2,3
Isochronous
Support Rules for
Software
Configuration
SYS.3.3#2 to
SYS.3.4#2
Isochronous
Rules for
Requesters
SYS.3.4#1,2
Isochronous
Rules for
Completers
SYS.3.5#3, 4
Device
Synchronization
SYS.4.0#1 to
SYS.4.0#5
SYS.5.1#3
PCI_EXPRESS_CPL_LK_
REQ_ ROOT_COMPLEX
Only the root complex in a PCI

Express hierarchy can initiate a
locked access.
SYS.5.2#2
Not a monitor check
Locked requests that are

completed with a status other than
successful completion must not
establish lock.
Initiation and
Propagation of
Locked
Transactions
572
Violation
PCI Express
Monitor Checks
Table 14-23. PCI Express Compliance Checklist: System Architecture (cont.)

Type
Rule
Check IDs
Violation
SYS.5.2#3

check.
Any device not involved in a

locked sequence must ignore the
Unlock Message. A switch is
permitted to broadcast the unlock
message downstream.
SYS.5.2#6
PCI_EXPRESS_NO_LOCKED_
COMPLETION_FOR_
LOCKED_REQ
The completions for any MRdLk

request must use the CplDLk or
CplLk completion types.
SYS.5.6#1

check.
A legacy endpoint must be locked

if it transmits a successful
completion for the first read
request of the locked access.
SYS.5.6#2

check.
Once an endpoint is locked, it must

remain locked until it receives the
unlock message.
SYS.5.6#3

check.
While it is locked, a legacy

endpoint must not issue any
requests using traffic classes that
map to VC0.
SYS.5.7#1
PCI_EXPRESS_CPL_LK_
REQ_PCI_EXPRESS_
ENDPOINT
A PCI Express endpoint (not

legacy) must treat an MRdLk
request as an Unsupported
Request.
PCI Express
Reset - Rules
SYS.6.0.#1,2,3

check.
PCI Express
Native Hot Plug
Support
SYS.7.3#1 to
SYS.7.9#1
Table 14-24. PCI Express Compliance Checklist: Configuration

Type
Rule
Check IDs
CFG.1.0#1 to CFG.13.4#1
Violation
Table 14-25. PCI Express Compliance Checklist: Isochronous Applications

Type
Rule
Check IDs
Violation
Checks related to Isochronous applications are not monitor checks.
573
PCI Express
Monitor Checks
Table 14-26. PCI Express Compliance Checklist: Electromechanical

Type
Rule
Check IDs
EM.6#4
Violation
Table 14-27. Checklist Applicable for End Point Only

Type
Rule
Check IDs
Violation
DLL.4.1#1
FIELD_ERROR

transmission.
TPL.3.2#1
PCI_ EXPRESS_ END_POINT
A Legacy Endpoint must support

Configuration Requests as a Completer.
TPL.3.2#2
PCI_EXPRESS_ END_POINT
A Legacy Endpoint must not issue a

Locked Request.
TPL.3.3#1
A PCI Express Endpoint must support

Configuration Requests as a Completer.
TPL.3.3#2

check.
A PCI Express Endpoint must not depend

on the operating system allocation of I/O
resources claimed through BAR(s) (Base
Address Registers).
TPL.3.3#3
PCI_EXPRESS_IO_ REQ_
A PCI Express Endpoint must not

generate I/O Requests.
TPL.3.3#4
PCI_EXPRESS_LOC_REQ_
PCI_EXPRESS_END_ POINT
A PCI Express Endpoint must not

support Locked Requests as a Completer
or generate them as a Requestor.
PCI_ EXPRESS_END_ POINT
TPL.4.0#1

check.
Devices and functions operating under

the PCI compatible mechanism must
support 100% binary compatibility with
PCI 2.3 or later operating systems, and
their corresponding bus enumeration and
configuration software.
TXN.2.3#1
PCI_EXPRESS_NO_TLP_
DIGEST
The presence or absence of the TLP

Digest field must be checked
(algebraically: Length(DW) + (DW *
TDset) = length of TLP following
header) for all TLPs. A TLP where the
TD field value does not correspond with
the observed size (accounting for the data
payload, if present) is a Malformed TLP.
SIZE_ERROR
574
PCI Express
Monitor Checks
Table 14-27. Checklist Applicable for End Point Only (cont.)

Type
Rule
Check IDs
Violation
TXN.2.3#2
PCI_EXPRESS_NO_TLP_
DIGEST

SIZE_ ERROR
TXN.2.3#3

check.
If the device at the ultimate destination of

the TLP does not support ECRC
checking, then the device must ignore the
TLP Digest.
TXN.2.3#5
PCI_EXPRESS_ ECRC_ERROR

the TLP supports ECRC checking, the
device interprets the value in the TLP
Digest field as an ECRC value, according
Specification Section 2.7.1.
TXN.2.4#1
PCI_EXPRESS_ ADDRESS_
FORMAT_ERROR
For Memory Read Requests and Memory

Write Requests with addresses below 4
GB, Requesters must use the 32-bit
format.
TXN.2.4#2
PCI_EXPRESS_IO_REQ_
HDR_ LENGTH_ERROR
I/O Read Requests and I/O Write

Requests use the 32-bit format.
TXN.2.6#6
PCI_EXPRESS_NON_CONTIG Byte enables must comply with the

UOUS_FIRST_DW_BE_ERROR Request Header mapping to referenced
_FOR_LEN_MT_2DW
data as specified in the PCI Express Base
Specification Table 2-7.
PCI_EXPRESS_NON_CONTIG
UOUS_LAST_DW_BE_ERROR
_FOR_LEN_MT_2DW
UOUS_FIRST_DW_BE_ERROR
_FOR_LEN_EQ_2DW_NON_Q
W_ALLIGNED
W_ALLIGNED
TXN.2.6#9
PCI_EXPRESS_CPL_LEN_NT_
1DW_FOR_FLUSH_REQ
The Completion for a zero length

read/Flush must specify a Length of 1
DW, and include a data payload of 1
DW. The contents of the data payload
within the Completion packet is
unspecified and can be any value.
575
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
TXN.2.6#10

check.
A Flush Request applies only to traffic in

the same Traffic Class on the Completer
as the zero length Read.
TXN.2.6#11
UOUS_FIRST_DW_BE_ERROR
W_ALLIGNED
All Memory Requests with a length of 3

DW or more must enable only bytes that
are contiguous with the data between the
first and last DW of the Request.
W_ALLIGNED
576
TXN.2.6#12

check.
The completion of a zero length

read/Flush must specify a length of 1 DW
and include a data payload of 1 DW. The
contents of the data payload within the
completion packet is unspecified and can
be any value.
TXN.2.7#4

check.
If Phantom Function Numbers are used

to extend the number of outstanding
requests, then the combination of the
phantom function number and the Tag
field must be unique for all outstanding
Requests that require a Completion for
that Requester.
TXN.2.7#6
Requester ID and Tag combined form the

Transaction ID, which must be a unique
global identifier for each Transaction
within a Hierarchy.
TXN.2.7#8
The Requester ID is a 16-bit value that is

unique for every PCI Express function
within a hierarchy.
TXN.2.7#9
PCI_EXPRESS_INVALID_REQ
_ID

Number fields of the Requester ID for all
Requests initiated by the device/function.
TXN.2.7#10
Bus Number and Device Number can be

changed at run time so it is necessary for
Functions to recapture this information
with each and every Configuration Write
Request.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
TXN.2.7#11
INIT_CONFIG_WRITE
Prior to the initial Configuration Write to

a device, the device is not permitted to
initiate requests (exception: Logical
devices within a Root Complex are
permitted to initiate Requests prior to
software-initiated configuration for
accesses to system boot device(s)).
TXN.2.11#9
ADDRESS_ LENGTH_
COMBINATION
For Memory Read Requests, Length

must not exceed the value specified by
Max_Read_Request_Size (see PCI
7.8.4),
TXN.2.11#10
REQ_SIZE_ ERROR
For Memory Read Requests, Length

must not exceed the value specified by
7.8.4),
TXN.2.13#3
ERROR
Assert_INTx/Deassert_INTx Messages
do not include a data payload (TLP Type
field encoding is Msg).
TXN.2.13#4
ERROR
The TLP Header Length[9:0] field is a

reserved field for INTx Signaling
messages.
TXN.2.13#6
Monitor fires on both TX and RX

sides if violations are detected.

violations of TXN.2.13#5. If a violation
has occurred, then the TLP is Malformed
and is reported as an error with the
Receiving Port.
TXN.2.13#9
The components at both ends of each

Link must track the logical state of the
four virtual wires using the
Assert/Deassert Messages to represent
the active and inactive transitions
(respectively) of each corresponding
virtual wire.
TXN.2.13#12
When the local logical state of an INTx

virtual wire changes at an Upstream Port,
the Port must communicate this change
in state to the Downstream Port on the
other side of the same Link using the
appropriate Assert_INTx or
Deassert_INTx Message.
TXN.2.13#14
Any INTx virtual wires that are active

when the Interrupt Disable bit is set must
be de-asserted by transmitting the
appropriate Deassert_INTx Message(s).
577
PCI Express
Monitor Checks

Type
578
Rule
Check IDs
Violation
TXN.2.13#17

check.
If a Downstream Port goes to DL_Down

status, then the INTx virtual wires
associated with that Port must be deasserted, and the Upstream Port virtual
wire state updated accordingly.
TXN.2.13#18

check.
If TXN.2.13#17 results in de-assertion of

any Upstream INTx virtual wires, then
the appropriate De assert INTx
message(s) must be sent by the Upstream
Port.
TXN.2.13#22
System software (including BIOS and

operating system) needs to comprehend
the remapping of legacy interrupts (INTx
mechanism) in the entire topology of the
system (including hierarchical connected
Switches and subordinate PCI
Express/PCI Bridges) to establish proper
correlation between PCI Express device
interrupt and associated interrupt
resources in the system interrupt
controller.
TXN.2.15#1
CODE_ ERROR
Error Signaling Messages must comply

with the encoding in the PCI Express
Base Specification Table 2-15.
TXN.2.15#2
ERROR
Error Signaling Messages do not include

a data payload (TLP Type field encoding
is Msg).
TXN.2.15#3
LENGTH_FIELD_ERROR
Within Error Signaling Messages the

TLP Header Length[9:0] field is a
reserved field.
TXN.2.15#4
TC_FIELD_ERROR
Error Signaling Messages must use the

default Traffic Class designator (TC0).
TXN.2.21#10

check.
The Byte Count[11:0] value for Memory

Read Completions must be specified as a
binary number, with 0000 0000 0001b
indicating 1 byte, 1111 1111 1111b
indicating 4095 bytes, and 0000 0000
0000b indicating 4096 bytes.
TXN.2.21#11

check.

combination with the Requester ID field,
must correspond to the Transaction ID.
TXN.2.21#12
PCI_EXPRESS_MRD_CPL_LO
W_ADDR
Lower Address[6:0] for Memory Read

Completions the value in this field must
be the byte address for the first enabled
byte of data returned with the
Completion.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
TXN.2.21#13
PCI_EXPRESS_CPL_LWR_
ADDRESS_ VALUE_ERROR
Lower Address[6:0] must be set to all 0s

for all types of Completions other than
Memory Read Completions.
TXN.2.21#14

check.
The Completer ID[15:0] is a 16-bit value

that must be unique for every PCI
Express function within the hierarchy.
TXN.2.21#15
PCI_EXPRESS_INVALID_CO
MPLETER_ID

Device Numbers supplied with all Type 0
Configuration Write Requests completed
by the function, and supply these
numbers in the Bus and Device Number
fields of the Completer ID for all
Completions generated by the
device/function.
TXN.2.21#16
PCI_EXPRESS_BUS_DEV_NO If a function must generate a Completion

T_0_FOR_CPL_BEFORE_INIT_ prior to the initial device Configuration
WRITE
Write Request, 0s must be entered into
the Bus Number and Device Number
fields (exception: The assignment of bus
numbers to the logical devices within a
Root Complex can be done in an
implementation specific way).
TXN.2.21#19
PCI_EXPRESS_
COMPLETION_TC_ATTR_
MISMATCH
If a Completion with the UR status is

generated by a multifunction device
without associating the Completion with
a specific function within the device, then
the Function Number field is Reserved.
TXN.3.1#4

check.
If the Request violates the programming

model of the device, then the device can
optionally treat the Request as a
Completer Abort, instead of handling the
Request normally.
TXN.3.1#5

check.
If the Request is treated as a Completer

Abort, then this is a reported error
associated with the device/function (see
PCI Express Base Specification Section
6.2).
TXN.3.2#1

check
Total Completions for a given Request,

when combined, must return exactly the
amount of data Requested in the Read
Request.
TXN.3.2#2

check.
Completions for different Requests

cannot be combined.
TXN.3.2#11
Not a monitor check
For all system elements other than the

Root Complex, RCB is 128B.
579
PCI Express
Monitor Checks

Type
580
Rule
Check IDs
Violation
TXN.3.2#12
Not a monitor check
Completions for Read Requests that do

not cross the naturally aligned address
boundaries at integer multiples of RCB
Bytes must include all data specified in
the Request.
TXN.3.2#13
Not a monitor check
Read Requests that cross the address

Bytes can be completed using more than
one completion, but the data must not be
fragmented (except along the address
boundaries).
TXN.3.2#14
Not a monitor check
For Read Requests crossing address

Bytes, the first Read Completion must
start with the address specified in the
Request, and must end at one of the
following: the address specified in the
Request plus the length specified by the
Request (i.e., the entire Request) and an
address boundary between the start and
end of the Request at an integer multiple
of RCB Bytes.
TXN.3.2#15
Not a monitor check

Bytes, the final Read Completion must
end with the address specified in the
Request.
TXN.3.2#16
Not a monitor check

Bytes, all Read Completions between,
but not including, the first and final
Completions must be an integer multiple
of RCB Bytes in length.
TXN.3.2#17
Not a monitor check
Receivers of Read Requests can

optionally check for violations of RCB. If
a Receiver implementing this check
determines that a Completion violates
this rule, then it must handle the
Completion as a Malformed TLP. This is
a reported error associated with the
Receiving Port (see PCI Express Base
TXN.3.2#18

check.
Multiple Memory Read Completions for

a single Read Request must return data in
increasing address order.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
TXN.3.2#19

check.
For each Memory Read Completion, the

Byte Count field must indicate the
remaining number of bytes required to
complete the Request including the
number of bytes returned with the
Completion, except when the BCM field
is 1b.
TXN.3.2#21

check.
The total byte count required to complete

a Memory Read Request is calculated as
shown in the PCI Express Base
TXN.3.2#23

check.
If a Memory Read Request is completed

using multiple Completions, the Byte
Count value for each successive
Completion is the value indicated by the
preceding Completion minus the number
of bytes returned with the preceding
Completion.
TXN.3.2#25

check.
A PCI Express Memory Read Requester

must recognize that the BCM bit is used
by a PCI-X Completer to indicate that the
Byte Count field reports the size of just
that first packet and should not conclude
that packets of a Read Completion are
missing.
TXN.3.2#32
PCI_EXPRESS_ CPLD_FOR_
UNSUCCESFUL_ CPL
When a Read Completion is generated

with a Completion Status other than
Successful Completion, no data is
included with the Completion and the
Cpl (or CplLk) encoding is used instead
of CplD (or CplDLk).
TXN.3.2#36

check.

Successful Completion, the Lower
Address field must indicate the lower bits
of the byte address for the first enabled
byte of data that would have been
returned with the Completion (as if the
Completion Status were Successful
Completion).
TXN.3.2#36

check
In all cases, the boundaries specified by

RCB must be respected for all reads that
the device will Complete with Successful
Completion status.
TXN.3.3#1

check.

Completion must discard the
Completion.
581
PCI Express
Monitor Checks

Type
582
Rule
Check IDs
Violation
TXN.3.3#2
PCI_EXPRESS_
COMPLETION_
WITHOUT_ REQUEST
An Unexpected Completion is a reported

error associated with the Receiving Port
Section 6.2).
TXN.3.3#3

check.
Completions with a Completion Status

other than Successful Completion, or
Configuration Request Retry Status (in
response to Configuration Request only)
must cause the Requester to:
Free Completion buffer space and
other resources associated with the
Request.
Report the error according to the
rules in the PCI Express Base
TXN.3.3#5
CSR_FOR_ NONCFG_REQ
Completions with a Configuration

Request Retry Status in response to a
Request other than a Configuration
Request are Malformed TLPs. This is a
TXN.3.3#6
FIELD_ ERROR
Completions with a Reserved

Completion Status value are treated as if
the Completion Status was Unsupported
Request (UR). This is a reported error
associated with the Receiving
device/function, normally the same as the
Requestor (see PCI Express Base
TXN.5.1#1

check.
All PCI Express Ports that support more

than VC0 must provide the VC
Capability Structure according to the
definition in the PCI Express Base
TXN.5.1#2

check.
VC ID assignment must be unique per

PCI Express Port (the same VC ID
cannot be assigned to different VC
hardware resources within the same
Port).
TXN.5.1#3

check.
VC ID 0 is assigned and fixed to the

default VC.
TXN.5.2#1

check.
Every Traffic Class that is supported

must be mapped to one of the Virtual
Channels.
TXN.5.2#3

check.
One TC must not be mapped to multiple

VCs in any PCI Express Port.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
TXN.6.3#5

check.
CREDITS_RECEIVED is updated as
follows:
CREDITS_RECEIVED
:CREDITS_RECEIVED (optional) is the
count of the total number of FC units
consumed by valid TLPs Received since
Flow Control initialization.
(CREDITS_ RECEIVED + Increment)
modulo 2[Field Size]
where [Field Size] is 8 for
PCREDITS_RECEIVED (optional)
is the count of the total number of FC
units consumed by valid TLPs
received since Flow Control
initialization H, NPH, and CPLH and
12 for PD, NPD, and CPLD, where
Increment corresponds to the credits
received.
TXN.7.1#1
PCI_EXPRESS_NO_TLP_
DIGEST
If a device is enabled to generate ECRC,

it must calculate and apply ECRC for all
TLPs originated by the device.
TXN.8.0#1

check.
Completion Timeout support is required

of the Root Complex, PCI Express-PCI
Bridges, and Endpoint devices.
TXN.8.0#2
PCI_EXPRESS_COMPLETION
_TIMEOUT
PCI Express devices that issue Requests

requiring Completions must implement
Completion Timeout mechanism. An
exception is made for Configuration
Requests (see PCI Express Base
TXN.8.0#3
PCI_EXPRESS_COMPLETION
_TIMEOUT
The Completion Timeout timer must not

expire (i.e., cause a timeout event) in less
than 50 s. It is strongly recommend that
unless an application requires this level
of timer granularity that the minimum
time should not expire in less than 10 ms.
TXN.8.0#4

check.
The Completion Timeout timer must

expire if a Request is not completed in 50
ms.
TXN.8.0#5

check.
A Completion Timeout is a reported error

associated with the Requestor
device/function (see PCI Express Base
583
PCI Express
Monitor Checks

Type
584
Rule
Check IDs
Violation
TXN.8.0#6

check.
A Memory Read Request for which there

are multiple Completions must be
considered completed only when all
Completions have been received by the
Requester.
TXN.9.1#8
PCI_EXPRESS_ LINK_DOWN_ For a Port on an Endpoint, and the Port

PENDING_ REQUESTS
on a Switch, or the Bridge that is closest
to the Root Complex, DL_Down status is
handled by discarding all TLPs being
processed
PMG.2.0#7

check.
A downstream components Link must

enter the L1 state if all of its functions are
programmed to a D state other than D0.
PMG.3.3#2
A function must not initiate any TLPs

while in the D1 state except the
PM_PME message.
PMG.3.4#1
A function in D2 must not initiate any

TLPs except the PM_PME message.
PMG.3.8#1
If a downstream component is in D0,

then an upstream component must be in
D0.
PMG.3.8#2
If the upstream component and

downstream component are both in D0,
then the link must be in L0, L0s, or L1.
PMG.3.8#3
If a downstream component is in D1,

then the upstream component must be in
D0 or D1.
PMG.3.8#4
If the downstream component is in D1,

then the link must be in L1.
PMG.3.8#5

D0, D1, or D2.
PMG.3.8#6

PMG.3.8#7
If the downstream component is in D3hot, then the upstream component cannot

be in D3-cold.
PMG.3.8#8
When the downstream component is in

D3-hot, the link must be in L1 or L2/L3
Ready.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PMG.3.8#10
When all functions on a multifunction

downstream component are programmed
to D3-hot, the downstream component
must request the transition of its link to
L1 using the PM_ENTER_L1_DLLP. It
must not make the request until all
functions are programmed to D3-hot.
PMG.3.8#11

check.
When a downstream component enters

D3-hot and it has completed the
PM_Turn_Off/PME_TO_ACK
handshake, then it must request a link
transition to L2/L3 Ready using the
PM_ENTER_L23 DLLP.
PMG.3.8#12
If a switch or single function endpoint

device has its upstream port transitioned
to D1, D2, or D3-hot, then it must initiate
a Link state transition of its upstream port
to L1.
PMG.3.8#13
A multifunction endpoint must not

initiate a Link state transaction to L1
until all of the functions have been
programmed to a non-D0 state.
PMG.3.9#1

check.
A downstream component must schedule

a completion response corresponding to a
configuration write to the PMSCR field
when it receives a TLP request that
transitions the device to D1, D2, or D3hot. It must suspend all new TLP
scheduling.
PMG.3.9#2

check.
Once an acknowledgement for the

PMCSR write completion and all other
outstanding TLPs are completed and the
downstream component has accumulated
enough credits to send the largest
possible packet for any FC type, then the
downstream component must transmit a
PM_Enter_L1_DLLP onto its upstream
directed port.
PMG.3.9#3
PCI_EXPRESS_TLPS_
AFTER_PM
Once a downstream component sends a

PM_Enter_L1_DLLP, it must continue to
send it continuously until a response
from the upstream component is
received. It must not initiate any new
TLPs.
585
PCI Express
Monitor Checks

Type
586
Rule
Check IDs
Violation
PMG.3.9#6
WITHOUT_ACK
When a downstream component receives

a PM_Request_Ack_DLLP on its receive
lanes, it must disable its Link layer, send
one electrical idle ordered set, and bring
the upstream physical link into the
electrical idle state.
PMG.3.9#8

check.
While sending PM_Enter_L1 DLLP, a

downstream component must continue to
accept TLPs and DLLPs from the
upstream component. It must continue to
respond to DLLPs.
PMG.3.9#9

check.
Once both ends of a link are in L1, the

components must suspend operation of
Flow Control Update, DLLP ACK/NAK
Latency, and the TLP Completion
Timeout counter mechanisms.
PMG.3.11#1

check.
A downstream component must not send

PM_Enter_L23_DLLP upstream until it
is prepared to lose power.
PMG.3.12#2

check.
A device must cease requesting Link

reactivation of any form once it has
entered the D0-uninitialized state.
PMG.3.12#3

check.
A device initiating PM_PME after

reactivation from a noncommunicating
state must only send PM_PME after
entering D0-initialized using the new
Requester ID.
PMG.3.12#6
PCI Express components that support

wakeup must support beacon unless they
follow the PCI Express Card
Electromechanical or Mini PCI Express
Card Electromechanical specifications
and support Wake#.
PMG.3.12#7
A component that uses Wake# must

continue to drive it until power has been
restored.
PMG.3.13#4

check.
After a downstream component sends a

PME_TO_ACK message in response to a
PME_Turn_off message, it must generate
one electrical idle ordered set, bring its
transmit lines to electrical idle, and
transition its upstream port to L2/L3
ready.
PMG.3.14#3

check.
If an agent sends a PM_PME message

and its PME_Status bit has not been
cleared after 100 ms (+50% / -5%), then
it must resend the PM_PME message
(waking up its link if necessary).
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PMG.3.15#4

check.
When a function indicates Link

reactivation or issues a PM_PME
Message, it must set the PME_Status bit.
PMG.4.1#3
If any function of a multifunction

endpoint device is in D0 and has Active
State Power Link Management disabled,
then it is disabled for the entire device.
PMG.4.1#4
If any function of a multifunction

endpoint device is in D0 and enabled for
L0s only (and none are disabled), then
the entire device is enabled for L0s only.
PMG.4.1#5
If neither PMG.4.1#.3 or PMG.4.1#.4 is

true of a multifunction endpoint device,
then it is enabled for both L0s and L1.
PMG.4.5#4

check.
A component must wait until it

accumulates the minimum number of
credits required to send the largest
possible packet for any FC type before
sending a PM_Active_State_Request_
L1_DLLP on its transmit lines.
PMG.4.5#5
PCI_EXPRESS_TLPS_
OUTSTANDING
A downstream component must block

scheduling of TLPs and wait until an
acknowledgement is sent for the last TLP
before sending a PM_Active_State_
Request_L1_DLLP on its transmit lines.
PMG.4.5#7

check
A downstream component sending a

PM_Active_State_Request_L1_DLLP
on its transmit lines must send it
continuously until a response is received.
PMG.4.5#8
PCI_EXPRESS_TLPS_
AFTER_PM
A component continuously sending

must not initiate any TLP transfers.
PMG.4.5#9

check.

must accept TLPs and DLLPs from an
upstream component and respond to
DLLPs as needed.
PMG.4.5#10

check.
Before sending a
PM_Request_Ack_DLLP downstream,
an upstream component must acquire the
minimum number of credits required to
send the largest possible packet for any
FC type.
587
PCI Express
Monitor Checks

Type
588
Rule
Check IDs
Violation
PMG.4.5#13
WITHOUT_ACK
When a PM_Request_Ack_DLLP is
detected on its receive lanes, the
must cease being sent and the link layer
must be disabled, an electrical idle
ordered set sent, and the transmit lanes
brought into the electrical idle state.
PMG.4.5#16

check.
The transaction layer completion timeout

mechanism must not be affected by the
L1 state.
PMG.4.5#17

check.
Flow control update times must be frozen

while in L1.
PMG.4.7#2

check.
A component must not issue

PM_Active_State_Request_L1 DLLPs
when it is not enabled for L1 entry.
PMG.4.7#3

check.
A port enabled for L0s entry only must

bring the port to L0s if all conditions
defined in the PCI Express Specification
are met.
PMG.4.7#4

check.

component is set to 00b (Disabled), the
port must not bring a link into the L0s
state or issue
commands.
PMG.4.7#6

check.

component is set to 01b (L0s only), a port
must bring a link into L0s when allowed.
PMG.4.7#8

check.

component is set to 01b (L0s only), an
upstream port must not send a
PM_Active_State_Request_L1_DLLP.
PMG.6.0#3

check.
For all Power Management system

messages, except PM_PME, the
requester ID must report the actual
upstream Link bus number and device
number. The function number must be
zero.
SYS.5.1#1
PCI_EXPRESS_LOCKED_
REQ_PCI_EXPRESS_END_
POINT
PCI Express endpoints must not support

locked accesses unless necessary for
legacy software compatibility. The only
endpoint type that has the option of
supporting locked accesses is a legacy
PCI Express endpoint.
SYS.5.1#2
PCI Express aware software must not use

locked accesses.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
SYS.5.2#4

check.
When an Unlock message is received, a

locked component must unlock itself.
Table 14-28. Checklist Applicable for Root Complex Only

Type
Rule
Check IDs
Violation
DLL.4.1#1
FIELD_ERROR

transmission.
TXN.2.3#1
PCI_EXPRESS_NO_
TLP_DIGEST

PCI_EXPRESS_
TLP_PKT_SIZE_ERROR
TXN.2.3#2
PCI_EXPRESS_NO_
TLP_DIGEST

PCI_EXPRESS_ TLP_PKT_SIZE_ TDset) = length of TLP following
ERROR
TXN.2.3#3

the TLP does not support ECRC
checking, then the device must ignore the
TLP Digest.
TXN.2.3#5

the TLP supports ECRC checking, the
device interprets the value in the TLP
Digest field as an ECRC value, according
Specification Section 2.7.1.
TXN.2.4#1
PCI_EXPRESS_ ADDRESS_
FORMAT_ERROR
For Memory Read Requests and Memory

Write Requests with addresses below 4
GB, Requesters must use the 32-bit
format.
TXN.2.4#2
PCI_EXPRESS_IO_REQ_
HDR_ LENGTH_ERROR
I/O Read Requests and I/O Write

Requests use the 32-bit format.
589
PCI Express
Monitor Checks
Table 14-28. Checklist Applicable for Root Complex Only (cont.)

Type
Rule
Check IDs
Violation
TXN.2.6#9
PCI_EXPRESS_CPL_LEN_NT_1
DW_FOR_FLUSH_REQ
The Completion for a zero length

read/Flush must specify a Length of 1
DW, and include a data payload of 1 DW.
The contents of the data payload within
the Completion packet is unspecified and
can be any value.
TXN.2.6#10
A Flush Request applies only to traffic in

the same Traffic Class on the Completer
as the zero length Read.
TXN.2.6#11
PCI_EXPRESS_NON_CONTIGU
OUS_FIRST_DW_BE_ERROR_F
OR_LEN_MT_2DW
All Memory Requests with a length of 3

DW or more must enable only bytes that
are contiguous with the data between the
first and last DW of the Request.
PCI_EXPRESS_NON_CONTIGU
OUS_LAST_DW_BE_ERROR_F
OR_LEN_MT_2DW
590
TXN.2.6#12
PCI_EXPRESS_CPL_LEN_NT_1
DW_FOR_FLUSH_REQ
The completion of a zero length

read/Flush must specify a length of 1 DW
and include a data payload of 1 DW. The
contents of the data payload within the
completion packet is unspecified and can
be any value.
TXN.2.7#4
If Phantom Function Numbers are used to

extend the number of outstanding
requests, then the combination of the
phantom function number and the Tag
field must be unique for all outstanding
Requests that require a Completion for
that Requester.
TXN.2.7#9
PCI_EXPRESS_INVALID_REQ_I Functions must capture the Bus and

D
Number fields of the Requester ID for all
Requests initiated by the device/function.
TXN.2.7#10

with each and every Configuration Write
Request.
TXN.2.7#11
PCI_EXPRESS_TLP_BEFORE_I
NITIAL_CONFIG_WRITE
Prior to the initial Configuration Write to

a device, the device is not permitted to
initiate requests (exception: Logical
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
TXN.2.11#9
ADDRESS_ LENGTH_
COMBINATION
For Memory Read Requests, Length must

not exceed the value specified by
7.8.4),
TXN.2.11#10
REQ_SIZE_ ERROR
For Memory Read Requests, Length must

not exceed the value specified by
7.8.4),
TXN.2.13#9
The components at both ends of each

Link must track the logical state of the
four virtual wires using the
Assert/Deassert Messages to represent
the active and inactive transitions
(respectively) of each corresponding
virtual wire.
TXN.2.13#22
System software (including BIOS and

operating system) needs to comprehend
the remapping of legacy interrupts (INTx
mechanism) in the entire topology of the
system (including hierarchical connected
Switches and subordinate PCI
Express/PCI Bridges) to establish proper
correlation between PCI Express device
interrupt and associated interrupt
resources in the system interrupt
controller.
TXN.2.15#1
PCI_EXPRESS_ERR_ MSG_
CODE_ ERROR
Error Signaling Messages must comply

with the encoding in Base Specification.
TXN.2.15#2
ERROR
Error Signaling Messages do not include

a data payload (TLP Type field encoding
is Msg).
TXN.2.15#3
PCI_EXPRESS_MSG_ REQ_
LENGTH_FIELD_ERROR
Within Error Signaling Messages the

TLP Header Length[9:0] field is a
reserved field.
TXN.2.21#10
The Byte Count[11:0] value for Memory

Read Completions must be specified as a
binary number, with 0000 0000 0001b
indicating 1 byte, 1111 1111 1111b
indicating 4095 bytes, and 0000 0000
0000b indicating 4096 bytes.
TXN.2.21#11

combination with the Requester ID field,
must correspond to the Transaction ID.
591
PCI Express
Monitor Checks

Type
592
Rule
Check IDs
Violation
TXN.2.21#12
PCI_EXPRESS_MRD_CPL_LOW
_ADDR
Lower Address[6:0] for Memory Read

Completions the value in this field must
be the byte address for the first enabled
byte of data returned with the
Completion.
TXN.2.21#13
PCI_EXPRESS_CPL_LWR_
ADDRESS_ VALUE_ERROR
Lower Address[6:0] must be set to all 0s

for all types of Completions other than
Memory Read Completions.
TXN.3.1#14
When used in systems including PCI

Express to PCI/PCIx bridges, the root
complex must comprehend the
initialization time limit Thrfa for
PCI/PCI-x agents.
TXN.3.1#16
In systems running legacy PCI/PCI-X

based software, the Root Complex must
reissue Configuration requests using a
hardware mechanism when a completion
with CRS status is received.
TXN.3.2#1

check
Total Completions for a given Request,

when combined, must return exactly the
amount of data Requested in the Read
Request.
TXN.3.2#2
Completions for different Requests

cannot be combined.
TXN.3.2#10
For a Root Complex, RCB is 64B or

128B. This value is reported through a
configuration register (see PCI Express
Base Specification Section 7.8)
TXN.3.2#12
Not a monitor check
Completions for Read Requests that do

not cross the naturally aligned address
Bytes must include all data specified in
the Request.
TXN.3.2#13
Not a monitor check
Read Requests that cross the address

Bytes can be completed using more than
one completion, but the data must not be
fragmented (except along the address
boundaries).
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
TXN.3.2#14
Not a monitor check

Bytes, the first Read Completion must
start with the address specified in the
Request, and must end at one of the
following: the address specified in the
Request (i.e., the entire Request), and an
address boundary between the start and
end of the Request at an integer multiple
of RCB Bytes.
TXN.3.2#15
Not a monitor check

Bytes, the final Read Completion must
end with the address specified in the
Request.
TXN.3.2#16
Not a monitor check

Bytes, all Read Completions between,
but not including, the first and final
Completions must be an integer multiple
of RCB Bytes in length.
TXN.3.2#17
Not a monitor check
Receivers of Read Requests can

optionally check for violations of RCB. If
a Receiver implementing this check
determines that a Completion violates
this rule, then it must handle the
Completion as a Malformed TLP. This is
a reported error associated with the
TXN.3.2#18
Multiple Memory Read Completions for

a single Read Request must return data in
increasing address order.
TXN.3.2#19
For each Memory Read Completion, the

Byte Count field must indicate the
remaining number of bytes required to
complete the Request including the
number of bytes returned with the
Completion, except when the BCM field
is 1b.
TXN.3.2#21
The total byte count required to complete

a Memory Read Request is calculated as
shown in the PCI Express Base
593
PCI Express
Monitor Checks

Type
594
Rule
Check IDs
Violation
TXN.3.2#23
If a Memory Read Request is completed

using multiple Completions, the Byte
Count value for each successive
Completion is the value indicated by the
preceding Completion minus the number
of bytes returned with the preceding
Completion.
TXN.3.2#25
A PCI Express Memory Read Requester

must recognize that the BCM bit is used
by a PCI-X Completer to indicate that the
Byte Count field reports the size of just
that first packet and should not conclude
that packets of a Read Completion are
missing.
TXN.3.2#30

check.
For Completions generated by a Root

Complex with an RCB value of 64B, the
most significant bit of the Lower Address
field will toggle according to the
alignment of the 64B data payload.
TXN.3.2#32
PCI_EXPRESS_ CPLD_FOR_
UNSUCCESFUL_ CPL

Successful Completion, no data is
included with the Completion and the Cpl
(or CplLk) encoding is used instead of
CplD (or CplDLk).
TXN.3.2#34

Successful Completion, the Byte Count
field must indicate the remaining number
of bytes that would be required to
complete the Request (as if the
Completion).
TXN.3.2#35
PCI_EXPRESS_MRD_CPL_LOW
_ADDR

Successful Completion, the Lower
Address field must indicate the lower bits
of the byte address for the first enabled
byte of data that would have been
returned with the Completion (as if the
Completion).
TXN.3.2#36

check
In all cases, the boundaries specified by

RCB must be respected for all reads that
the device will Complete with Successful
Completion status.
TXN.3.3#1

Completion must discard the Completion.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
TXN.3.3#2
PCI_EXPRESS_ COMPLETION_
WITHOUT_ REQUEST
An Unexpected Completion is a reported

error associated with the Receiving Port
Section 6.2).
TXN.3.3#3
Completions with a Completion Status

other than Successful Completion, or
Configuration Request Retry Status (in
response to Configuration Request only)
must cause the Requester to:
Free Completion buffer space and
other resources associated with the
Request.
Report the error according to the
rules in the PCI Express Base
TXN.3.3#5
CSR_FOR_ NONCFG_REQ
Completions with a Configuration

Request Retry Status in response to a
Request other than a Configuration
Request are Malformed TLPs. This is a
TXN.3.3#6
FIELD_ ERROR
Completions with a Reserved

Completion Status value are treated as if
the Completion Status was Unsupported
Request (UR). This is a reported error
associated with the Receiving
device/function, normally the same as the
Requestor (see PCI Express Base
TXN.7.1#1
PCI_EXPRESS_NO_TLP_
DIGEST
If a device is enabled to generate ECRC,

it must calculate and apply ECRC for all
TLPs originated by the device.
TXN.8.0#1
PCI_EXPRESS_COMPLETION_T Completion Timeout support is required

IMEOUT
of the Root Complex, PCI Express-PCI
Bridges, and Endpoint devices.
TXN.8.0#2

check.
TXN.8.0#3
PCI_EXPRESS_COMPLETION_T The Completion Timeout timer must not

IMEOUT
expire (i.e., cause a timeout event) in less
than 50 s. It is strongly recommend that
unless an application requires this level
of timer granularity that the minimum
time should not expire in less than 10 ms.
PCI Express devices that issue Requests

requiring Completions must implement
Completion Timeout mechanism. An
exception is made for Configuration
Requests (see PCI Express Base
595
PCI Express
Monitor Checks

Type
596
Rule
Check IDs
Violation
TXN.8.0#4

check.
The Completion Timeout timer must

expire if a Request is not completed in 50
ms.
TXN.8.0#5

check.
A Completion Timeout is a reported error

associated with the Requestor
device/function (see PCI Express Base
TXN.8.0#6
A Memory Read Request for which there

are multiple Completions must be
considered completed only when all
Completions have been received by the
Requester.
TXN.2.15#4
PCI_EXPRESS_ MSG_REQ_TC_
FIELD_ERROR
Error Signaling Messages must use the

default Traffic Class designator (TC0).
TPL.03.01#03
PCI_EXPRESS_CPL_LK_
REQ_ROOT_ COMPLEX
A Root Complex must not support Lock

semantics as a Completer.
TPL.04.00#02
This is not a monitor check.
(From RC/Switch point of view) Each

PCI Express Link is mapped through a
virtual PCI-to-PCI Bridge structure and
has a logical PCI bus associated with it.
TXN.02.13#20 Monitor cannot perform this check.
If a Downstream Port of the Root

Complex goes to DL_Down status, the
INTx virtual wires associated with that
Port must be de-asserted, and any
associated system interrupt resource
request(s) must be discarded.
TXN.02.13#05 PCI_EXPRESS_INTX_FROM_D
OWNSTREAM_PORT
Assert_INTx/Deassert_INTx Messages
are only issued by Upstream Ports.
TXN.02.15#05 PCI_EXPRESS_MSG_REQ_
TC_FIELD_ ERROR
If a receiver receives an Error Signaling

Message on a TC other than TC0, it is
reported as an error on the receiving port.
The Set_Slot_Power_Limit Message is

sent automatically by the
Downstream Port On a Configuration
Write to the Slot Capabilities
Register (see PCI Express Base
Specification Section 7.8.9) when the
Data Link Layer reports DL_Up status.
The Set_Slot_Power_Limit Message is

sent automatically by the
Downstream Port any time a Link
transitions from a non-DL Up status to a
DL Up status (see PCI Express Base
TXN.5.1#4
VC ID 0 is assigned to fixed default VC.

check.
PCI Express
Monitor Checks

Type
Rule
Check IDs
TXN.5.3#8
PCI_EXPRESS_TLP_DOESNOT_ For a Root Port, transactions with a TC

MAP_TO_ ANY_VC
that is not mapped to any of the enabled
VCs in the target RCRB are treated as
malformed TLPs.
TXN.5.3#10
Root Complex must support independent

TC/VC mapping configuration for each
RCRB and the associated Root Ports.
TXN.9.1#1
For a Root Complex, or any Port on a

Switch other than the one closest to the
Root Complex, DL_Down status is
handled by initializing back to their
default state any buffers or internal state
associated with outstanding requests
transmitted downstream.
(Note: Port configuration registers must
not be affected, except as required to
update status associated with the
transition to DL_Down).
TXN.9.1#2

handled by forming completions for any
Requests submitted by the device core for
Transmission, returning Unsupported
Request Completion Status, then
discarding the Requests.
TXN.9.1#3
TXN.9.1#2 is a reported error associated

with the device/function for the (virtual)
Bridge associated with the Port (see PCI
Express Base Specification Section 6.2).
TXN.9.1#4
During handling of TXN.9.1#2, requests

already being processed by the
Transaction Layer, for which it might not
be practical to return Completions, are
discarded.
TXN.9.1#5
Monitor does not implement

timeouts as they are in the order of
ms.
Discarded requests (related to handling of

TXN.9.1#2) are handled by the Requester
using the Completion Timeout
mechanism.
TXN.9.1#6

handled by discarding all Completions
submitted by the device core for
Transmission.
Violation
597
PCI Express
Monitor Checks

Type
598
Rule
Check IDs
Violation
TXN.9.2#1
For a Downstream Port on a Root

Complex or a Switch when transitioning
from a non-DL_Up Status to a DL_Up
Status, the Port must initiate the
transmission of a Set_Slot_Power_Limit
message to the other component on the
Link to convey the value programmed in
the Slot Power Limit Scale and Value
fields of the Slot Capabilities register.
SYS.5.2#2
Monitor cannot perform this check
Locked requests that are completed with

a status other than successful completion
must not establish lock.
SYS.5.2#5
A locked transaction sequence must be

started with a MRdLk Request.
SYS.6.0#8
The secondary side of the bridge must

undergo a hot reset if the Secondary Bus
Reset bit of the bridge control register is
set.
SYS.6.0#15

check.
A system must terminate an initial

configuration request to a device that
does not respond within 1.5 seconds.
PMG.2.0#7
A downstream components Link must

enter the L1 state if all of its functions are
programmed to a D state other than D0.
PMG.3.3#2
A function must not initiate any TLPs

while in the D1 state except the
PM_PME message.
PMG.3.4#1
A function in D2 must not initiate any

TLPs except the PM_PME message.
PMG.3.8#2
If the upstream component and

downstream component are both in D0,
then the link must be in L0, L0s, or L1.
PMG.3.8#3
If a downstream component is in D1, then

the upstream component must be in D0 or
D1.
PMG.3.8#4

PMG.3.8#5

D0, D1, or D2.
PMG.3.8#6

PMG.3.8#7
If the downstream component is in D3hot, then the upstream component cannot

be in D3-cold.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PMG.3.8#8
When the downstream component is in

D3-hot, the link must be in L1 or L2/L3
Ready.
PMG.3.8#10
When all functions on a multifunction

downstream component are programmed
to D3-hot, the downstream component
must request the transition of its link to
L1 using the PM_ENTER_L1_DLLP. It
must not make the request until all
functions are programmed to D3-hot.
PMG3.8#14
PCI_EXPRESS_ACK_
WITHOUT_PM_ COMMAND
When an upstream component receives

PM_ENTER_L23_DLLP, it must reply
with the PM_Req_ACK DLLP.
PMG.3.9#1
A downstream component must schedule

a completion response corresponding to a
configuration write to the PMSCR field
when it receives a TLP request that
transitions the device to D1, D2, or D3hot. It must suspend all new TLP
scheduling.
PMG3.9#4
PCI_EXPRESS_TLPS_
AFTER_ACK
Upon receiving a PM_Enter_L1_DLLP,

an upstream component must complete
all outstanding TLPs and block
scheduling of new TLPs.
PMG3.9#5
PCI_EXPRESS_TLPS_
OUTSTANDING_WHEN_ACK
The upstream component that received a

PM_Enter_L1_DLLP must send a
PM_Request_Ack_DLLP downstream
once all its outstanding TLPs have
completed, and it has accumulated at
least the minimum number of credits
required to send the largest possible
packet for any FC type. It must send this
DLLP continuously until it receives an
electrical idle set or observes its receive
lanes enter the idle state.
PMG3.9#7
When an upstream component observes

its receive lanes enter the electrical idle
state, it must stop sending
PM_Request_Ack DLLPs, disable its
Link layer, send one electrical idle
ordered set and bring its transmit Lanes
to electrical idle. Once both ends of a link
are in the L1 state, the upstream
component must suspend operation of
Flow Control Updates.
PMG3.10#1
An upstream component must detect

when a packet is targeted at a
downstream Link in the L1 state, and
initiate the transition of the link to L0.
599
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PMG3.10#2
Once an upstream component has

successfully completed Link training to
bring a link from L1 to L0, it must send
the packet for the downstream
component.
PMG4.5#2
PCI_EXPRESS_TLPS_
OUTSTANDING
A root complex root port or Switch

Downstream port must accept a request
to enter L1 if the following are true:
The port supports active state link

PM L1 entry, and it is enabled.
No TLP is scheduled for

transmission.
No Ack or Nak DLLP is scheduled

for transmission.
PMG4.5#6
PCI_EXPRESS_NAK_
WITHOUT_PM_REQ
PCI_EXPRESS_ACK_
WITHOUT_PM_ COMMAND
600
A component receiving a
must respond immediately with an
acceptance or a rejection.
PMG4.5#11
PCI_EXPRESS_TLPS_
OUTSTANDING_WHEN_ACK
Before sending a
an upstream component must block TLP
scheduling and receive an
acknowledgement for the last TLP it sent.
PMG4.5#12

check.
A component sending
PM_Request_ACK_DLLP downstream
must do so continuously until its receive
lanes enter the electrical idle state.
PMG4.5#14
WITHOUT_ACK
When an electrical idle ordered set or

electrical idle is detected on its receive
lanes, a component continuously sending
^M PM_Request_Ack_DLLP must stop,
disable its link layer, send one electrical
idle ordered set, and bring the
downstream direction of the link into the
idle state.
PMG4.5#15
If the upstream component denies L1

entry by sending PM_Active_State_Nak,
it must schedule this message
immediately and not initiate any other
TLP or DLLP transfers until it is sent.
PMG4.5#17
Flow control update times must be frozen

while in L1.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PMG4.7#1

check.
A component must respond negatively to

all PM_Active_State_Request_L1 DLLP
requests when its Active State Link PM
Control field is not enabled for L1 entry.
PMG4.7#3
PCI_EXPRESS_TLPS_
OUTSTANDING
A port enabled for L0s entry only must

defined in the PCI Express Specification
are met.
PMG4.7#5

check.

component is set to 00b, a port receiving
a PM_Active_State_Request_L1_DLLP
command must respond with
PM_Active_State_Nak.
PMG4.7#7

check.

downstream port is set to 01b (L0s only),
it must respond to an L1 entry request
with PM_Active_State_Nak.
PMG4.7#9

check.

component is set to 10b (L1 only), a
ports transmitter must not enter L0s.
PMG4.7#10

component is set to 11b, the port must
bring its link into the L0s state (unless an
L1 entry attempt is successful).
SYS.5.1#2
PCI Express aware software must not use

locked accesses.
SYS.5.2#4
When an Unlock message is received, a

locked component must unlock itself.
Table 14-29. Checklist Applicable for Switch Only

Type
Rule
Check IDs
DLL.05.02#11
Monitor cannot perform this check. After replay has successfully received
all expected Acks, re-enable receiving
TLPs from the Transaction Layer.
TXN.2.7#9
ID
Violation

completed by the function, and supply
Number fields of the Requester ID for
all Requests initiated by the
device/function.
601
PCI Express
Monitor Checks
Table 14-29. Checklist Applicable for Switch Only (cont.)

Type
602
Rule
Check IDs
Violation
TXN.2.7#10

with each and every Configuration
Write Request.
TXN.2.7#11
PCI_EXPRESS_TLP_BEFORE_I
NITIAL_CONFIG_WRITE
Prior to the initial Configuration Write

to a device, the device is not permitted
to initiate requests (exception: Logical
TXN.2.7#15
Monitor cannot perform this check. A Switch must forward Requests

without modifying the Transaction ID.
TXN.2.13#12
When the local logical state of an INTx

virtual wire changes at an Upstream
Port, the Port must communicate this
change in state to the Downstream Port
on the other side of the same Link using
the appropriate Assert_INTx or
Deassert_INTx Message.
TXN.2.13#15
Virtual and actual PCI to PCI Bridges

must map the virtual wires tracked on
the secondary side of the Bridge
according to the Device Number of the
Device on the secondary side of the
Bridge, (see PCI Express Base
Specification, Table 2-13).
TXN.2.13#16
Switches must track the state of the four

virtual wires independently for each
Downstream Port, and present a
collapsed set of virtual wires on its
Upstream Port.
TXN.2.13#23
The remapping described by the PCI

Express Base Specification, Table 2-13
is applied hierarchical at every Switch.
TXN.2.13#24
Monitor cannot perform this check. Messages specifying Local (0100b)

routing or a reserved field value are
terminated locally at the Receiving Port
on a Switch.
TXN.2.13#25
Monitor cannot perform this check. Duplicate Assert_INTx/Deassert_INTx

Messages have no effect and must not
be reported as errors.
TXN.2.15#05
PCI_EXPRESS_ MSG_REQ_
TC_ FIELD_ERROR
If a receiver receives an Error Signaling

Message on a TC other than TC0, then it
is reported as an error on the receiving
port.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
TXN.2.21#15
PCI_EXPRESS_INVALID_COM
PLETER_ID

Device Numbers supplied with all Type
0 Configuration Write Requests
completed by the function, and supply
Number fields of the Completer ID for
all Completions generated by the
device/function.
TXN.2.21#16
PCI_EXPRESS_BUS_DEV_NOT
_0_FOR_CPL_BEFORE_INIT_W
R
If a function must generate a

Completion prior to the initial device
Configuration Write Request, 0s must
be entered into the Bus Number and
Device Number fields (exception: The
assignment of bus numbers to the
logical devices within a Root Complex
can be done in an implementation
specific way).
TXN.2.21#19
TC_ ATTR_MISMATCH
If a Completion with the UR status is

generated by a multifunction device
without associating the Completion with
a specific function within the device,
then the Function Number field is
Reserved.
TXN.3.1#4
Monitor cannot perform this check. If the Request violates the programming
model of the device, then the device can
optionally treat the Request as a
Completer Abort, instead of handling
the Request normally.
TXN.3.1#5
Monitor cannot perform this check. If the Request is treated as a Completer

Abort, then this is a reported error
associated with the device/function (see
PCI Express Base Specification Section
6.2).
TXN.9.1#8
PCI_EXPRESS_ LINK_DOWN_
PENDING_ REQUESTS
TXN.02.17#09
Monitor cannot perform this check. The Set_Slot_Power_Limit Message is

sent automatically by the Downstream
Port On a Configuration Write to the
Slot Capabilities Register (see PCI
7.8.9) when the Data Link Layer reports
DL_Up status.
For a Port on an Endpoint, and the Port

on a Switch, or the Bridge that is closest
to the Root Complex, the DL_Down
status is handled by discarding all TLPs
being processed.
603
PCI Express
Monitor Checks

Type
604
Rule
Check IDs
Violation
TXN.02.17#10
Monitor cannot perform this check. The Set_Slot_Power_Limit Message is

sent automatically by the Downstream
Port any time a Link transitions from a
non-DL Up status to a DL Up status (see
PCI Express Base Specification, Section
2.9.2).
TXN.03.00#04
Monitor cannot perform this check. Switches must process both TLPs that
address resources within the Switch as
well as TLPs that address resources
residing outside the Switch.
TXN.03.00#05
Monitor cannot perform this check. Switches handle all TLPs that address
internal resources of the Switch
(according to the PCI Express Base
Specification, (flow chart) Figure 2-23).
TXN.03.00#06
Monitor cannot perform this check. TLPs that pass through the Switch, or
that address the Switch as well as
passing through it, are handled
according to the PCI Express Base
Specification, (flow chart) Figure 2-24.
TXN.05.00#05
Monitor cannot perform this check. Switches that do not implement the
optional PCI Express Virtual Channel
Capability Structure must map all TCs
to VC0.
TXN.05.00#06
Monitor cannot perform this check. Switches that do not implement the
optional PCI Express Virtual Channel
Capability Structure must forward all
transactions regardless of the TC Label.
TXN.05.01#04

check.
TXN.05.03#05
Monitor cannot perform this check. A Switch peer-to-peer capability applies

to all Virtual Channels supported by the
switch.
TXN.05.03#07
PCI_EXPRESS_TLP_
DOESNOT_ MAP_TO_
ANY_VC
TXN.05.03#09
Monitor cannot perform this check. Switches must support independent

TC/VC mapping configuration for each
port.
TXN.07.01#02
Monitor cannot perform this check. Switches must pass TLPs with ECRC
unchanged from the Ingress Port to the
Egress port.
TXN.07.01#05
VC ID 0 is assigned and fixed to the

default VC.
For Switches, transactions with a TC

that is not mapped to any of the enabled
VCs in the target Egress Port are treated
as malformed TLPs.
ECRC Errors detected by a Switch are

reported in the same way any other
device would report them, but the
Switch does not alter the TLPs passage
through the Switch.
PCI Express
Monitor Checks

Type
Rule
Check IDs
TXN.07.03#07
Monitor cannot perform this check. A Switch (that is not also the Completer
for the Request) must route a poisoned
I/O, or Memory Write Request, or a
message with data in the same way it
would route a non-poisoned request of
the same type.
TXN.09.01#01
Monitor cannot perform this check. For a Root Complex, or any Port on a
handled by initializing back to their
default state any buffers or internal state
associated with outstanding requests
transmitted downstream. (Note: Port
configuration registers must not be
affected, except as required to update
status associated with the transition to
DL_Down).
TXN.09.01#02
Monitor cannot perform this check. For a Root Complex, or any Port on a
handled by forming completions for any
Requests submitted by the device core
for Transmission, returning
Unsupported Request Completion
Status, and then discarding the
Requests.
TXN.09.01#03
Monitor cannot perform this check. TXN.9.1#2 is a reported error associated

with the device/function for the (virtual)
Bridge associated with the Port (see PCI
6.2).
TXN.09.01#04
Monitor cannot perform this check. During handling of TXN.9.1#2, requests

already being processed by the
Transaction Layer, for which it might
not be practical to return Completions,
are discarded.
TXN.09.02#01
Monitor cannot perform this check. For a Downstream Port on a Root

Complex or a Switch when transitioning
from a non-DL_Up Status to a DL_Up
Status, the Port must initiate the
transmission of a Set_Slot_Power_Limit
message to the other component on the
Link to convey the value programmed in
the Slot Power Limit Scale and Value
fields of the Slot Capabilities register.
PMG.1.01#2
Monitor cannot perform this check. Active State Link Power Management
using the L0s state must be supported by
all PCI Express components.
Violation
605
PCI Express
Monitor Checks

Type
606
Rule
Check IDs
Violation
PMG.3.08#14
PCI_EXPRESS_ACK_
WITHOUT_ PM_COMMAND
When an upstream component receives

PM_ENTER_L23_DLLP, it must reply
with the PM_Req_ACK DLLP.
PMG.3.09#04
Monitor cannot perform this check. Upon receiving a PM_Enter_L1_DLLP,

an upstream component must complete
all outstanding TLPs and block
scheduling of the new TLPs.
PMG.3.09#05
PCI_EXPRESS_ TLPS_
OUTSTANDING_
WHEN_ACK
PMG.3.09#07
Monitor cannot perform this check. When an upstream component observes

its receive lanes enter the electrical idle
state, it must stop sending
PM_Request_Ack DLLPs and disable
its Link layer, send one electrical idle
ordered set and bring its transmit Lanes
to electrical idle.
PMG.3.10#01
Monitor cannot perform this check. An upstream component must detect

when a packet is targeted at a
downstream Link in the L1 state and
initiate the transition of the link to L0.
PMG.3.10#02
Monitor cannot perform this check. Once an upstream component has

successfully completed Link training to
bring a link from L1 to L0, it must send
the packet for the downstream
component.
PMG.3.13#02
PCI_EXPRESS_ PME_TO_
ACK_ WITHOUT_TURN_OFF
PMG.3.13#03
Monitor cannot perform this check. When a PM_Turn_Off message is

originated upstream of the PCI Express
Switch, the switch must report an
aggregate acknowledgement only after
having received PME_TO_ACK
packets from each of the active
downstream ports.
The upstream component that received a

PM_Enter_L1_DLLP must send a
PM_Request_Ack_DLLP downstream
once all its outstanding TLPs have
completed and it has accumulated at
least the minimum number of credits
required to send the largest possible
packet for any FC type. It must send this
DLLP continuously until it receives an
electrical idle set or observes its receive
lanes enter the idle state.
When a PME_Turn_Off broadcast

message is received, a downstream
component must respond with a
PME_TO_ACK message. This
requirement applies when the
component is in D3-hot.
PCI Express
Monitor Checks

Type
Rule
Check IDs
PMG.3.13#05
Monitor cannot perform this check. A switch must send a PME_TO_Ack

message upstream in response to a
PME_Turn_off message only after all
its downstream ports transition to L2/L3
ready. It must then transition its
upstream port to L2/L3 ready.
PMG.3.15#03
Monitor cannot perform this check. A PM_PME received on any

downstream port must be routed to the
upstream port.
PMG.4.04#02
Monitor cannot perform this check. If the upstream port of the switch
receive lanes are transitioned from L0s
to L0, then the downstream port
transmit lanes must be transition to L0
for all downstream components in the
D0 state.
PMG.4.05#02
Monitor cannot perform this check. A root complex root port or Switch
Downstream port must accept a request
to enter L1 if the following are true:
The port supports active state link
PM L1 entry, and it is enabled.
No TLP is scheduled for
transmission.
No Ack or Nak DLLP is scheduled
for transmission.
PMG.4.05#03
Monitor cannot perform this check. If any of the following conditions are
false, then a Switch must not request L1
entry on its upstream port:
The upstream port supports Active
State Link PM L1 entry and is
enabled.
All of the Switchs Downstream
Port Links are in the L1 state (or
deeper).
No pending TLPs to transmit.
No pending DLLPs to transmit.
The Upstream Ports receive lanes
are idle.
PMG.4.06#01
Monitor cannot perform this check. If a switch downstream port starts an L1

to L0 transition, then the Switch must
initiate a L1 exit transition on its
upstream port transmit lines within 1
microsecond of the beginning of the L1
to L0 transition on its downstream port.
Violation
607
PCI Express
Monitor Checks

Type
608
Rule
Check IDs
Violation
PMG.4.06#02
Monitor cannot perform this check. If a switch upstream port starts an L1 to

L0 transition, then the switch must
initiate L1 to L0 transitions on all of its
downstream ports in L1 within 1
microsecond of the beginning of the L1
to L0 transition on its downstream port.
(Unless the downstream component is
not in D0).
PMG.4.07#05
Monitor cannot perform this check. When the ASPM control field for a
component is set to 00b, a port receiving
a PM_Active_State_Request_L1_DLLP
command must respond with
PM_Active_State_Nak.
PMG.4.07#07
downstream port is set to 01b (L0s
only), it must respond to an L1 entry
request with PM_Active_State_Nak.
PMG.5.01#02
PMG.3.8#11
Monitor cannot perform this check. When a downstream component enters

D3-hot and it has completed the
PM_Turn_Off/PME_TO_ACK
handshake, then it must request a link
transition to L2/L3 Ready using the
PM_ENTER_L23 DLLP.
PMG.3.8#12
PMG.3.9#2
Monitor cannot perform this check. Once an acknowledgement for the

PMCSR write completion and all other
outstanding TLPs are completed and the
downstream component has
accumulated enough credits to send the
largest possible packet for any FC type,
then the downstream component must
transmit a PM_Enter_L1_DLLP onto its
upstream directed port.
PMG.3.9#3
PCI_EXPRESS_TLPS_
AFTER_PM
A component must not draw Aux power

unless enabled.
If a switch or single function endpoint

device has its upstream port transitioned
to D1, D2, or D3-hot, then it must
initiate a Link state transition of its
upstream port to L1.
Once a downstream component sends a

PM_Enter_L1_DLLP, it must continue
to send it continuously until a response
from the upstream component is
received. It must not initiate any new
TLPs.
PCI Express
Monitor Checks

Type
Rule
Check IDs
Violation
PMG.3.9#6
WITHOUT_ACK
When a downstream component

receives a PM_Request_Ack_DLLP on
its receive lanes, it must disable its Link
layer, send one electrical idle ordered
set, and bring the upstream physical link
into the electrical idle state.
PMG.3.9#8
Monitor cannot perform this check. While sending PM_Enter_L1 DLLP, a

downstream component must continue
to accept TLPs and DLLPs from the
upstream component. It must continue
to respond to DLLPs.
PMG.3.9#9
Monitor cannot perform this check. Once both ends of a link are in L1, the
components must suspend operation of
Flow Control Update, DLLP
ACK/NAK Latency, and the TLP
Completion Timeout counter
mechanisms.
PMG.3.11#1
Monitor cannot perform this check. A downstream component must not

send PM_Enter_L23_DLLP upstream
until it is prepared to lose power.
PMG.3.12#2
Monitor cannot perform this check. A device must cease requesting Link
reactivation of any form once it has
entered the D0-uninitialized state.
PMG.3.12#3
Monitor cannot perform this check. A device initiating PM_PME after

reactivation from a noncommunicating
state must only send PM_PME after
entering D0-initialized using the new
Requester ID.
PMG.3.12#6
PCI Express components that support

wakeup must support beacon unless
they follow the PCI Express Card
Electromechanical or Mini PCI Express
Card Electromechanical specifications
and support Wake#.
PMG.3.12#7
A component that uses Wake# must

continue to drive it until power has been
restored.
PMG.3.15#4
Monitor cannot perform this check. When a function indicates Link

reactivation or issues a PM_PME
Message, it must set the PME_Status
bit.
PMG.4.5#4

check.
A component must wait until it

accumulates the minimum number of
credits required to send the largest
possible packet for any FC type before
sending a
on its transmit lines.
609
PCI Express
Monitor Checks

Type
610
Rule
Check IDs
Violation
PMG.4.5#5
PCI_EXPRESS_TLPS_
OUTSTANDING
A downstream component must block

scheduling of TLPs and wait until an
acknowledgement is sent for the last
TLP before sending a
on its transmit lines.
PMG.4.5#7

check.
A downstream component sending a

on its transmit lines must send it
continuously until a response is
received.
PMG.4.5#8
PCI_EXPRESS_TLPS_
AFTER_PM

must not initiate any TLP transfers.
PMG.4.5#9
Monitor cannot perform this check. A component continuously sending

must accept TLPs and DLLPs from an
upstream component and respond to
DLLPs as needed.
PMG.4.5#10
Monitor cannot perform this check. Before sending a

an upstream component must acquire
the minimum number of credits required
to send the largest possible packet for
any FC type.
PMG.4.5#13
WITHOUT_ACK
PMG.4.5#16
Monitor cannot perform this check. The transaction layer completion

timeout mechanism must not be affected
by the L1 state.
PMG.4.5#17
Monitor cannot perform this check. Flow control update times must be
frozen while in L1.
PMG.4.7#2
Monitor cannot perform this check. A component must not issue

when it is not enabled for L1 entry.
PMG.4.7#3
Monitor cannot perform this check. A port enabled for L0s entry only must
defined in the PCI Express Base
Specification are met.
When a PM_Request_Ack_DLLP is
detected on its receive lanes, the
must cease being sent and the link layer
must be disabled, an electrical idle
ordered set sent, and the transmit lanes
brought into the electrical idle state.
PCI Express
Monitor Checks

Type
Rule
Check IDs
PMG.4.7#4
component is set to 00b (Disabled), the
port must not bring a link into the L0s
state or issue
commands.
PMG.4.7#6
component is set to 01b (L0s only), a
port must bring a link into L0s when
allowed.
PMG.4.7#8
component is set to 01b (L0s only), an
upstream port must not send a
PM_Active_State_Request_L1_DLLP.
SYS.01.01#05
PCI_EXPRESS_ MSG_REQ_
TC_ FIELD_ERROR
INTx emulation messages must use

TC0.
SYS.05.03#01

check.
Locked accesses are always limited to

TC0/VC0.
SYS.05.03#02
Monitor cannot perform this check. When a switch propagates a MRdLk

request from the Ingress port to the
egress port, it must block all subsequent
requests that map to VC0 to the egress
port.
SYS.05.03#04
Monitor cannot perform this check. When a CplDLk for the first MRdLk is
returned with a successful completion
status, the switch must block all requests
from all ports from being propagated to
either port involved in the locked
access, except for Requests that map to
non-VC0 on the egress port.
SYS.05.03#06
Monitor cannot perform this check. An unlock message received at the

switch locked ingress port must be
forwarded to the locked egress port. It
can simply be broadcast to all egress
ports.
SYS.05.03#07
Monitor cannot perform this check. A locked ingress port must be

unblocked when an Unlock Message
arrives.
SYS.05.03#08
Monitor cannot perform this check. A locked egress port must be unblocked
following the transmission of the
Unlock Message out of the egress port.
SYS.05.03#09
Monitor cannot perform this check. Ports that are not involved in a locked
access must not be affected by an
Unlock Message.
SYS.06.00#02
Monitor cannot perform this check. A component must enter the initial
active Link Training state within 20 ms
of the end of Fundamental Reset.
Violation
611
PCI Express
Monitor Checks

Type
612
Rule
Check IDs
Violation
SYS.06.00#03
Monitor cannot perform this check. At the end of Link Training, a

component must be able to receive and
process TLPs and DLLPs.
SYS.06.00#08
Monitor cannot perform this check. The secondary side of the bridge must
undergo a hot reset if the Secondary Bus
Reset bit of the bridge control register is
set.
SYS.06.00#11
Monitor cannot perform this check. A hot reset must be sent on all
downstream ports if the Secondary Bus
Reset bit of the upstream port is set.
SYS.06.00#12
Monitor cannot perform this check. A hot reset must be sent on all
downstream ports if the data link layer
of the upstream port reports
DL_DOWN.
SYS.06.00#13
Monitor cannot perform this check. When a hot reset is received on the
upstream port of the switch, a hot reset
must be sent on all downstream ports.
SYS.07.01#01
Monitor cannot perform this check. PCI Express hot plug capable ports must
meet the PCI Standard Hot-Plug
Controller and Subsystem Specification,
Revision 1.0 usage model. (Appear
identical from a user perspective to ports
meeting that specification).
SYS.07.02#01
Monitor cannot perform this check. Indicators must have three states: On,
Off, and blinking.
SYS.07.02#02
Monitor cannot perform this check. Blinking indicators must operate at a

frequency of 1 to 2 Hz.
SYS.07.02#03
Monitor cannot perform this check. The state of an indicator must only be
controlled by software unless hardware
detects a stuck-on power fault.
SYS.7.9 to
SYS.9.5
PCI Express

Table 14-30 shows the corner cases maintained by the PCI Express monitor for the physical
layer. These corner cases are collected for the transmit and receive interface.
Table 14-30. Physical Layer Corner Cases Maintained by the PCI Express
Monitor
Corner Cases
Description
COM Symbols
Total number of COM special symbols.
Data link layer packets
Total number of data link layer packets.
Total number of Electrical idle ordered sets.
FTS ordered sets
Total number of FTS ordered sets.
Nullified TLPs
Total number of transaction layer packets ending with EDB.
PAD symbol occurrences
Total number of symbol times when the END/EDB symbol is followed

by PAD symbol. This corner case is applicable for x8 and wider links.
SDP and STP occurrences in a

symbol time
Total number of symbol times both STP and SDP symbols were
sampled on the link. This corner case is applicable for multilane links.
SKIP ordered sets
Total number of SKIP ordered sets.
Transaction layer packets
Total number of transaction layer packets.
TS1 ordered sets
Total number of TS1 ordered sets.
TS1/TS2 ordered sets with disable
Total number of TS1/TS2 ordered sets with disable bit set.
TS1/TS2 ordered sets with disable

scrambling
Total number of TS1/TS2 ordered sets with disable scrambling bit set.
TS1/TS2 ordered sets with loopback
Total number of TS1/TS2 ordered sets with loopback bit set.
TS1/TS2 ordered sets with reset
Total number of TS1/TS2 ordered sets with reset bit set.
TS2 ordered sets
Total number of TS2 ordered sets.
Table 14-31 shows the corner cases maintained by the PCI Express monitor for the data link
layer. These corner cases are collected for both transmit and receive interface.
Table 14-31. Data Link Layer Corner Cases Maintained by the PCI Express
Monitor
Corner Cases
Description
ACK DLLPs
Total number of ACK DLL packets.
Duplicate TLPs
Number of duplicate TLPs. Valid only for received TLPs.
InitFC1-Cpl DLLPs
Total number of InitFC1-Cpl DLL packets.
InitFC1-NP DLLPs
Total number of InitFC1-NP DLL packets.
InitFC1-P DLLPs
Total number of InitFC1-P DLL packets.
613
PCI Express
Table 14-31. Data Link Layer Corner Cases Maintained by the PCI Express
Monitor (cont.)
Corner Cases
Description
InitFC2-Cpl DLLPs
Total number of InitFC2-Cpl DLL packets.
InitFC2-NP DLLPs
Total number of InitFC2-NP DLL packets.
InitFC2-P DLLPs
Total number of InitFC2-P DLL packets.
NAK DLLPs
Total number of NAK DLL packets.
PM_Active_State_Request_L0s DLLPs
Total number of PM_Active_State_Request_L0s DLL packets.
Total number of PM_Active_State_Request_L1 DLL packets.
PM_Enter_L1 DLLPs
Total number of PM_Enter_L1 DLL packets.
PM_Enter_L23 DLLPs
Total number of PM_Enter_L23 DLL packets.
PM_Request_Ack DLLPs
Total number of PM_Request_Ack DLL packets.
TLP retransmissions
Total number of TLP retransmissions.
UpdateFC-Cpl DLLPs
Total number of UpdateFC-Cpl DLL packets.
UpdateFC-NP DLLPs
Total number of UpdateFC-NP DLL packets.
UpdateFC-P DLLPs
Total number of UpdateFC-P DLL packets.
Vendor specific DLLPs
Total number of vendor specific DLL packets.
Table 14-32 shows the corner cases maintained by the PCI Express monitor for the transaction
layer. These corner cases are collected for the transmit and receive interfaces.
Table 14-32. Transaction Layer Corner Cases Maintained by the PCI Express
Monitor
Corner Cases
Description
Completer aborts
Total number of completions with Completer Abort (CA) status.
Completion packets
Total number of completion TLPs.
Completions with configuration

request retry status
Total number of completions with Configuration Request Retry (CRS)

status.
I/O read requests
Total number of I/O read requests.
I/O write requests
Total number of I/O write requests.
Locked completions
Total number of locked completions.
Locked memory read requests
Total number of locked memory read requests. This statistic is

applicable only when the device is allowed to initiate a locked
transaction.
Example: Root complex.
Memory read requests
Total number of memory read requests.
Memory write requests
Total number of memory write requests.
614
PCI Express
Monitor Statistics
Table 14-32. Transaction Layer Corner Cases Maintained by the PCI Express
Monitor (cont.)
Corner Cases
Description
Message requests
Total number of message requests.
TLPs with digests
Total number of TLPs with TLP digest.
Type 0 configuration read requests
Total number of Type 0 configuration read requests.
Type 0 configuration write requests
Total number of Type 0 configuration write requests.
Type 1 configuration read requests
Total number of Type 1 configuration read requests.
Type 1 configuration write requests
Total number of Type 1 configuration write requests.
Unsupported request completions
Total number of completions with Unsupported Request (UR) status.
Monitor Statistics
Table 14-33 shows the statistics maintained by the PCI Express monitor for the physical layer.
These statistics are collected for the transmit and receive interface.
Table 14-33. Physical Layer Statistics
Statistics
Description
Number of packets
Total number of packets.
Table 14-34 shows the statistics maintained by the PCI Express monitor for the data link layer.
Table 14-34. Data Link Layer Statistics
Statistics
Description
No statistics are maintained by the PCI Express monitor for the data link layer
Table 14-35 shows the statistics maintained by the PCI Express monitor for the transaction
layer. These statistics are collected for the transmit and receive interface.
Table 14-35. Transaction Layer Statistics
Statistics
Description
TLPs with ECRC Error
Total number of transaction layer packets with ECRC error.
TLPs with LCRC Error
Total number of transaction layer packets with LCRC error.
Malformed TLPs
Total number of malformed TLPs.
615
PCI Express
Monitor Gen2 Corner Cases
Table 14-35. Transaction Layer Statistics (cont.)

Statistics
Description
TLPs started on non zero lane
Total number of TLPs started on lanes other than lane number zero.
Multiple packets ending in a

symbol time count
Total number of symbol times where more than one packet ended in a
symbol time.
Monitor Gen2 Corner Cases

Table 14-36 shows the corner cases maintained by the PCI Express monitor for the physical
layer. These corner cases are collected for the transmit and receive interface.
Table 14-36. Physical Layer Corner Cases PCI Express Monitor Gen2
Corner Cases
Description
Electrical Idle ordered sets on

speed greater than 2.5 GT/s.
Total number of EIOS(Two set of Com, Idle, Idle and Idle) on speed greater
than 2.5 GT/s.
FTS ordered sets on speed greater

than 2.5 GT/s.
Total number of FTS on speed greater than 2.5 GT/s.
Electrical idle exit sequence

ordered sets.
Total number of EIEOS.
TS1 ordered sets with speed

change bit.
Total number of TS1 ordered sets with speed change bit set.
TS2 ordered sets with speed

change bit.
Total number of TS2 ordered sets with speed change bit set.
TS1/TS2 ordered sets with 2.5

GT/s data rate.
Total number of TS1/TS2 ordered sets with gen1 speed.
TS1/TS2 ordered sets with 5.0.

GT/s data rate.
Total number of TS1/TS2 ordered sets with gen2 speed.
TS1/TS2 ordered sets with

autonomous bit.
Total number of TS1/TS2 ordered sets with autonomous bit set.
TS1 ordered sets with compliance Total number of TS1 ordered sets with compliance receive bit set.
receive bit.
More than 4 EIE symbol
occurrence before FTS.
Total number of times more than 4 EIE symbol before FTS on speed greater
than 2.5 GT/s.
Modified compliance pattern.
Total number of Modified compliance pattern.
Speed change through L1.
Number of times transition from L1 to Recovery for speed change purpose.
Recovery Lock to Recovery

Speed after timeout.
Number of times state transition from RecoLk to RecoSpeed after timeout.
L0s transition on 5.0 GT/s.
Number of times state transition to L0s on speed greater than 2.5 GT/s.
L1 transition on 5.0 GT/s.
Number of times state transition to L1 on speed greater than 2.5 GT/s.
L2 transition on 5.0 GT/s.
Number of times state transition to L2 on speed greater than 2.5 GT/s.
616
PCI Express
Monitor Gen2 Statistics
Table 14-37 shows there are no corner cases maintained by the PCI Express Monitor Gen2 for
the data link layer.
Table 14-37. Data Link Layer Corner Cases PCI Express Monitor Gen2
Statistics
Description
There are no corner cases maintained by the PCI Express Monitor Gen2 for the data link layer.
Table 14-38 shows the corner cases maintained by the PCI Express monitor for the transaction
layer. These corner cases are collected for the transmit and receive interfaces.
Table 14-38. Transaction Layer Corner Cases PCI Express Monitor Gen2
Corner Cases
Description
Deprecated TLP.
Total number of deprecated TLP.
Translation request(AT=01) Memory.
Number of memory request with AT as translation request.
Translated request(AT=10) Memory.
Number of memory request with AT as translated request.

Table 14-39 shows the statistics maintained by the PCI Express monitor for the physical layer.
Table 14-39. Physical Layer Statistics PCI Express Monitor Gen2
Statistics
Description
Polling Compliance entry.
Number of times state transition to Polling compliance from polling

active.
Speed change attempt from 2.5 GT/s

to 5.0 GT/s.
Number of attempts to change speed from 2.5 GT/s to 5.0 GT/s.
Speed change attempt from 5.0 GT/s

to 2.5 GT/s.
Number of attempts to change speed from 5 GT/s to 2.5 GT/s.
Successful speed change from 2.5

GT/s to 5.0 GT/s.
Number of successful speed change from 2.5 GT/s to 5.0 GT/s.
Successful speed change from 5.0

GT/s to 2.5 GT/s.
Number of successful speed change from 5.0 GT/s to 2.5 GT/s.
State transition from Recovery.LK

to RecoSPeed.
Number of times state transition from Reco LK to Reco Speed.
State transition from Recovery.Cfg

to RecoSPeed.
Number of times state transition from Reco Cfg to Reco Speed.
617
PCI Express
Table 14-40 shows the statistics maintained by the PCI Express monitor for the data link layer.
Table 14-40. Data Link Layer Statistics PCI Express Monitor Gen2
Statistics
Description
ACK on 5.0 GT/s.
Total number of ACK DLLP on speed 5.0 GT/s.
Update FC-P on 5.0 GT/s.
Total number of posted Update FC on speed 5.0 GT/s.
Update FC-NP on 5.0 GT/s.
Total number of non-posted Update FC on speed 5.0 GT/s.
Update FC-CPL on 5.0 GT/s.
Total number of completion Update FC on speed 5.0 GT/s.
Table 14-35 shows the statistics maintained by the PCI Express monitor for the transaction
layer. These statistics are collected for the transmit and receive interface.
Table 14-41. Transaction Layer Statistics PCI Express Monitor Gen2
618
Statistics
Description
Memory write on 5.0 GT/s.
Total number of Memory write TLP on 5.0 GT/s.
Memory read on 5.0 GT/s.
Total number of Memory read TLP on 5.0 GT/s.
IO write on 5.0 GT/s.
Total number of IO write TLP on 5.0 GT/s.
IO read on 5.0 GT/s.
Total number of IO read TLP on 5.0 GT/s.
CFG write on 5.0 GT/s.
Total number of CFG write TLP on 5.0 GT/s.
CFG read on 5.0 GT/s.
Total number of CFG read TLP on 5.0 GT/s.
MSG/MSGD on 5.0 GT/s.
Total number of MSG/MSGD TLP on 5.0 GT/s.
CPL/CPLD on 5.0 GT/s.
Total number of CPL/CPLD TLP on 5.0 GT/s.
PCI Express
Monitor FAQ
Monitor FAQ
Following are answers to frequently asked questions (FAQ) about the QVL PCI Express
monitor.
What are the various interfaces supported by the monitor?
Serial interface (instantiate the PCIE monitor).
10B parallel interface (instantiate the PCIE monitor).
PIPE interface (instantiate the PIPE monitor).
What do the tx_ and rx_ prefixes signify?

The tx_ prefix indicates the transmit lanes of the design under test, and rx_ prefix
indicates the receive lanes of the design under test.
Does the monitor track link width negotiation?
Yes.
Is there an option to skip the link training sequence?
The monitor provides an option to skip link training and width negotiation sequences.
When the skip link training option is enabled, the monitor expects a few TS1/TS2
ordered sets to achieve symbol lock.
What is the link width when the link training sequence is skipped?
When the skip link training option is enabled, no link width negotiation is performed.
Link width is set by the MAX_LANE_WIDTH parameter.
What is the MAX_REQUESTS_ADDR_WIDTH parameter? Why is this required?
The PCI Express monitor supports tracking of requests with completions. The monitor
stores all issued requests and matches them with their completions. The parameter
MAX_REQUESTS_ADDR_WIDTH configures the number of requests that can be outstanding
without a completion. By default, a maximum of 32 requests can be outstanding without
completions. For example, if the parameter MAX_REQUESTS_ADDR_WIDTH is set to 4,
then a maximum of
2 ^ (MAX_REQUESTS_ADDR_WIDTH) = 16
requests can be outstanding.

Does the monitor support multiple VCs?
Yes. The VC_SUPPORT parameter configures the monitor to support multiple VCs.
If I have multiple VCs, how do I configure the TC/VC mapping?
619
PCI Express
Monitor FAQ
The monitor provides tc_mapped_to_vcx ports for accepting the TC/VC mapping. By
default, all TCs are mapped to VC0, and only VC0 is supported. For example, if TC0
and TC1 are mapped to VC0, then the port tc_mapped_to_vc0 should be set to
8'b0000_0011.
Does the monitor track ordering rules?
No.
Why is the DOUBLE_DATA_RATE parameter provided?
The DOUBLE_DATA_RATE parameter configures the active edges of the PCI Express
clock. By default, the clocks are active on only the rising edge. The monitor can be
configured such that the clock is active on the rising edge as well as the falling edge.
Is there an option to configure the monitor to track short training sequences?
Yes. The MIN_TS1_COUNT parameter configures the monitor for the number of TS1
ordered sets. By default, the monitor expects 1024 TS1 ordered sets to be transmitted in
the Polling.Active state of the LTSSM.
Can I turn off the checks for individual layers?
The phy_layer_checks_disable, link_layer_checks_disable, and
transaction_layer_checks_disable monitor inputs disable checks for
the
individual layers (see Monitor Connectivity on page 421 and Monitor Connectivity
(PIPE) on page 431).
How do I disable scrambling?
Scrambling and de-scrambling are disabled by transmitting and receiving a few
TS1/TS2 ordered sets with the disable scramble bit set. Also, for the PIPE monitor, the
user can disable scrambling using the disable_descrambler port.
What happens if the skip link training is set and the DUT performs link training?
If skip link training is set, then the link width is configured through the
MAX_LANE_WIDTH parameter. It is OK to perform link training and width negotiation if
the negotiated link width matches the value of the MAX_LANE_WIDTH parameter.
Otherwise, the monitor will not be synchronized with the DUT.
Is it possible to disable scrambling for TX lanes only?
No. Scrambling and de-scrambling is disabled only for the test mode of operation and
only can be disabled for the device as a whole.
How do I hook up the monitor when 9B signals (8 data bits/lane and 1 control bit/lane) are
available?
620
PCI Express
Monitor FAQ
The user can hook up PIPE monitor when 9B signals are available, but the PIPE
interface signals that are not relevant should be set to either 1'b0 or 1'b1 as required (see
Instantiation Examples (PIPE) on page 438.
How does the monitor perform symbol lock?
The monitor uses the COM symbol to perform symbol lock. The monitor samples the
serial bits and waits until a proper COM symbol is detected. The monitor considers
detection of a COM symbol as symbol lock.
Does the monitor support a multilane PIPE interface?
Yes.
Does the PCI Express monitor support polarity inversion?
Yes. The monitor determines the polarity inversion through the TS1 and TS2 identifiers.
Is it possible to configure the Ack_Nak and Reply timer values?
Yes. The OVERRIDE_TIMER_VALUES parameter configures the Ack_Nak and Reply
Timer values. By default, the monitor determines the Ack_Nak and Reply Timer
values based on the Max_Payload_Size configured.
Is it possible to instantiate the monitor on the Link or Transaction layer only?
No. These interfaces being implementation specific, the user cannot instantiate the
monitor on Link layer, Transaction layer, etc. The monitor must be instantiated at the
interface between the transceiver and the PCI Express component or at the PIPE
interface.
Is it possible to turn off/on the layer checks dynamically?
Yes. The user can turn off/on the layer checks dynamically through the monitor input
ports provided. Even though the checks are turned off, the monitor will be in sync with
the device. When the checks are enabled, all the checks are performed.
Why does the PCI Express monitor have clock signals when the PCI Express interface
does not specify clock signals?
The monitor does not perform the clock recovery function. It expects clock signals.
Does the monitor handle lane-to-lane skew?
Yes. The user must configure the DESKEW_SUPPORT parameter accordingly. By default,
the monitor does not support lane-to-lane skew.
Does the monitor track/check only the packets detected on the transmit lanes?
621
PCI Express
Monitor FAQ
No. As the monitor sits on the bus as a whole, in general it performs all the checks on
receive lanes as well as on transmit lanes.
622
Chapter 15
Serial Attached SCSI (SAS)
Introduction
The Serial Attached SCSI (SAS) protocol defines the transmission of the SCSI protocol over a
Serial ATA compatible physical layer and defines addressing of multiple target devices for the
Serial ATA protocol. The SAS link consists of two signal groups: transmit and receive. The
QVL SAS monitor is designed for checking SAS implementations.
This SAS monitor is modeled from the requirements provided in the following document:
Serial Attached SCSI, Revision 1.1.r04, March 13, 2004
Supported Features
Primitives
The monitor tracks SAS primitives (e.g., AIP, ALIGN, CHANGE, etc.).
The monitor tracks SSP and SMP primitives (e.g., ACK, NAK, DONE, SOF, EOF and
RRDY).
The monitor tracks STP primitives (e.g., SATA_HOLD, SATA_HOLDA, etc.).
Data Integrity
The monitor supports data integrity checking for Address frames, SSP, STP, and SMP
frames.
Flow Control
The monitor tracks the flow control for SSP, SMP, and STP frames.
Reset Sequence and Identification Sequence
The monitor tracks the PHY reset sequence including the speed negotiation sequence.
The monitor tracks the Identification sequence.
The monitor tracks the Hard reset sequence.
623

Implementations
The monitor can be instantiated in any of the following implementations in a SAS domain for
the following connections:
SCSI initiator port using SSP or SMP protocol.
SCSI target port using SSP or SMP protocol.
ATA initiator port using STP protocol.
Expander port using SSP, SMP, or STP protocol.
This monitor cannot be instantiated in the ATA target port (using SATA protocol) in a
SAS domain.

To use the QVL SAS monitor, place an instance of the monitor inside a SAS initiator port, SAS
target port, or Expander port.
The monitor can be instantiated in either serial mode or in parallel mode. If the implementation
under test does not include a serializer/deserializer block, then the SAS monitor must be
instantiated in parallel mode. If the implementation under test includes a serializer/deserializer
block, then the monitor must be instantiated in serial mode. In either mode, input to the monitor
should be 10b encoded values.
The qvl_sas_monitor module is a wrapper module that sets speed negotiation controls as
parameters. If you want this implementation (for backward compatibility), then instantiate the
qvl_sas_monitor module (see Figure 15-1).
624

Figure 15-1. SAS Monitor Implementation
SAS Device
SAS
Monitor
Rx_interface
Tx_interface
rx_data_plus
rx_data_minus
rx_idle_signal
rx_clk
tx_data_plus
tx_data_minus
tx_idle_signal
tx_clk
bypass_reset_sequence
reset
areset
start_speed_negotiation
The qvl_sas_dynamic_timer_values_monitor has speed negotiation controls as port

signals. Those values can be changed dynamically during simulation and the Formal run. If you
want this capability, instantiate the qvl_sas_dynamic_timer_values_monitor module (see
Figure 15-2). Both monitors perform the same checks and have the same coverage information.
They differ only by their instantiations.
625

Figure 15-2. SAS Monitor (dynamic timer values) Implementation

SAS Device
Rx_interface
Tx_interface
SAS
Monitor
rx_data_plus
rx_data_minus
rx_idle_signal
rx_clk
rx_cominit_idle_time_min
rx_cominit_idle_time_max
rx_comsas_idle_time_min
rx_comsas_idle_time_max
rx_cominit_neg_time
rx_comsas_neg_time
tx_data_plus
tx_data_minus
tx_idle_signal
tx_clk
reset
areset
tx_cominit_idle_time
tx_comsas_idle_time
tx_cominit_neg_time
tx_comsas_neg_time
rate_change_delay
spd_neg_lock_time
spd_neg_transmit_time
hotplug_timeout
comsas_timeout
hard_reset_timeout
ident_frame_timeout
break_timeout
open_addr_res_timeout
credit_timeout
ack_nak_timeout
close_timeout
done_timeout
Connect the SAS monitor pins as specified in the pin out Table 15-1 and illustrated in
Figure 15-3.
626

Figure 15-3. SAS Monitor Pin Diagram

tx_clk
tx_data_plus
tx_data_minus
tx_idle_signal
rx_clk
rx_data_plus
rx_data_minus
rx_idle_signal
reset
areset
SAS Monitor
tx_clk
tx_data_plus
tx_data_minus
tx_idle_signal
rx_clk
rx_data_plus
rx_data_minus
rx_idle_signal
reset
areset
tx_comsas_idle_time
tx_cominit_neg_time
tx_comsas_neg_time
rx_cominit_neg_time
rx_comsas_neg_time
rate_change_delay
spd_neg_lock_time
hotplug_timeout
comsas_timeout
hard_reset_timeout
ident_frame_timeout
break_timeout
credit_timeout
ack_nak_timeout
close_timeout
done_timeout
SAS Monitor
(dynamic timer values)
627

Table 15-1. SAS Monitor Pins
628
Pin
Description
ack_nak_timeout
Configures the ACK/NAK timeout period. If the port sends an SSP frame, it
should be acknowledged within 1 millisecond.
areset
Asynchronous reset, Active high. This is not part of the SAS interface.
break_timeout
Configures the break timeout period. If the port sends a break, it should receive
the break within one 1 millisecond.
Configure this port to 1'b0 to track the PHY reset sequence. Configure this port
to 1'b1 to skip tracking the PHY reset sequence.
close_timeout
Configures the Close timeout period. If the port sends a close, it should receive
a close within one 1 millisecond.
comsas_timeout
Configures the time period within which a COMSAS sequence must be

received after transmitting a COMSAS sequence.
credit_timeout
Configures the credit timeout period. Port which accepts an open address frame
should send credit within 1 millisecond.
done_timeout
Configures the done timeout period. If the port sends a done, then it should
receive a done within one 1 millisecond.
hard_reset_timeout
Configures the hard reset period. After a port detects hard reset, it should not
send any valid primitives within one millisecond.
hotplug_timeout
Configures the time period within which a COMINIT sequence must be

received after transmitting a COMINIT sequence.
ident_frame_timeout
Configures the identification address frame timeout period. If the port transmits
an identification address frame, it should receive the same from the other side
within one millisecond.
Configures the open address response timeout period. After a port sends an
open address frame, it should receive a response within 1 millisecond.
rate_change_delay
Specifies the time the transmitter transmits D.C. idle between rates during
speed negotiation. The idle time period must be specified in UIs.
reset
Synchronous reset, Active high. This is not part of the SAS interface.
rx_clk
Receive clock.The receiver uses this clock to sample the bit pattern. The
monitor uses this clock to sample the received bit pattern. The clock is active on
posedge or on both edges based on the mode of operation.
Configures the receiver idle time period between ALIGN bursts in a COMINIT
sequence. The idle time period must be specified in UIs.
Configures the receiver idle time period between ALIGN bursts in a COMINIT
rx_cominit_neg_time
Configures the receiver negation time after a COMINIT sequence. The idle
time period must be specified in UIs.
Configures the receiver idle time period between ALIGN bursts in a COMSAS
Configures the receiver idle time period between ALIGN bursts in a COMSAS

Table 15-1. SAS Monitor Pins (cont.)

Pin
Description
rx_comsas_neg_time
Configures the receiver negation time after a COMSAS sequence. The idle time
period must be specified in UIs.
rx_data_minus
Input to SAS device. In serial mode, connect this input to the D input of the
device. In parallel mode, leave this input unconnected.
rx_data_plus
Input to the SAS device. In serial mode, connect this input to the D+ input of
the device. In parallel mode, connect this input to the 10B encoded data.
rx_idle_signal
Receive electrical idle signal. In parallel mode, this signal indicates an electrical
idle period. An active high on this signal indicates electrical idle. The SAS
monitor also provides an alternate method of indicating electrical idle on the
parallel 10b bus, apart from using the rx_idle_signal. You can configure the
parameter provided (see Monitor Parameters on page 630) and when the
value on the parallel bus equals the programmed parameter value, the monitor
infers an electrical idle scenario.
You should connect rx_idle_signal to 1'b0 during monitor instantiation if you
want to use the parameter method of indicating electrical idle on the bus.
spd_neg_lock_time
Specifies the maximum time during the speed negotiation window for a
transmitter to reply with ALIGN (1).
Specifies time during which ALIGN (0) or ALIGN (1) is transmitted at each
physical link rate during the speed negotiation sequence.
Configures the monitor to track from the speed negotiation sequence. This
signal is active high. The rising edge of this signal indicates the starting point of
an RCD period. This signal is used only when the monitor is configured in the
parallel mode (i.e., parameter INTERFACE_TYPE is 1 or 2). In serial mode,
this signal must be connected to 1'b0.
tx_clk
Transmit clock. This clock is used by the transmitter to drive the bit pattern.
The monitor uses this clock to sample the transmitted bit pattern. The clock is
active on posedge or on both edges based on the mode of operation.
Configures the idle time period between ALIGN bursts in a COMINIT

tx_cominit_neg_time
Configures the negation time after a COMINIT sequence. The idle time period
must be specified in UIs.
tx_comsas_idle_time
Configures the idle time period between ALIGN bursts in a COMSAS

tx_comsas_neg_time
Configures the negation time after a COMSAS sequence. The idle time period
must be specified in UIs.
tx_data_minus
Output from SAS device. In serial mode, connect this input to the D output of
the device. In parallel mode, leave this input unconnected.
tx_data_plus
Output from the SAS device. In serial mode, connect this input to the D+ output
of the device. In parallel mode, connect this input to the 10B encoded data.
tx_idle_signal
Transmit electrical idle signal. In parallel mode, this signal indicates an

electrical idle period. An active high on this signal indicates electrical idle.
The SAS monitor also provides an alternate method of indicating electrical idle
on the parallel 10b bus, apart from using the tx_idle_signal. The user can
configure the parameter provided (see Monitor Parameters on page 630) and
when the value on the parallel bus equals the programmed parameter value, the
monitor infers an electrical idle scenario.
You should connect tx_idle_signal to 1'b0 during monitor instantiation if you
want to use the parameter method of indicating electrical idle on the bus.
629

Connectivity Notes
In parallel mode, connect the encoded 10B symbols as follows:
tx_data_plus[9:0] = {j,h,g,f,i,e,d,c,b,a}
where bit a is the LSB of the 10B data and bit j is the MSB of the 10B data.
Monitor Parameters
The parameters shown in Table 15-2 configure the SAS monitor.
Table 15-2. SAS Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode

2.
SAS_DEVICE_TYPE
Configures the monitor to track a initiator/target

device or an expander/fanout expander device. Set
this parameter to 1 to track an expander/fanout
expander device. By default, the monitor tracks an
initiator/target device.
3.
INTERFACE_TYPE

instantiated on a parallel interface. By default, the
monitor is instantiated on a serial interface. See
Note 3.
4.
DOUBLE_DATA_RATE
Configures the active edge of the tx_clk/rx_clk

clocks. Set this parameter to 1 if both edges of
tx_clk/rx_clk clocks are active. Set this parameter
to 0 if tx_clk/rx_clk is active on only the rising
edge. By default, tx_clk/rx_clk is active on only the
rising edge. See Note 3.
5.
TX_DEVICE_SPEED_RATE
Configures the rate at which ALIGNs are

transmitted after power up. Set this parameter to 1
if ALIGNs are transmitted at a G2 (3.0 Gbps) rate.
By default, ALIGNs are transmitted at a G1 (1.5
Gbps) rate.
6.
RX_DEVICE_SPEED_RATE
Configures the rate at which ALIGNs are received

after power-up. Set this parameter to 1 if ALIGNs
are received at a G2 (3.0 Gbps) rate. By default,
ALIGNs are received at a G1 (1.5G bps) rate.
7.
TX_COMINIT_IDLE_TIME
480
Configures the idle time period between ALIGN

bursts in a COMINIT sequence. The idle time
period is specified in UIs. By default, the idle time
period is 480.
8.
TX_COMSAS_IDLE_TIME
1440
Configures the idle time period between ALIGN

bursts in a COMSAS sequence. The idle time
period is specified in UIs. By default, the idle time
period is 1440.
630

Table 15-2. SAS Monitor Parameters (cont.)

Order Parameter
Default Description
9.
TX_COMINIT_NEGATION_
TIME_PERIOD
800
Configures the negation time after a COMINIT

sequence. By default, the negation time is set to
800. Values are mentioned in UIs.
10.
TX_COMSAS_NEGATION_
TIME_PERIOD
2400
Configures the negation time (in UIs) after a

COMSAS sequence. By default, the negation time
after a COMSAS sequence is 2400.
11.
ELECTRICAL_IDLE_TIME_
BIT_PATTERN
1023
Specifies the value of the encoded 10B data during

electrical idle conditions. This parameter is
applicable only when INTERFACE_TYPE is set
to1 or 2 (parallel mode of operation). The default
value of the parameter is the value equivalent to
3FFh, the assumed 10-bit encoded value for
electrical idle. In serial mode, the monitor detects
an electrical idle when both D+ and D inputs are
driven to same level.
12.
RATE_CHANGE_DELAY
750000
Specifies the time (in UIs) the transmitter transmits

D.C. idle between two physical link rates during
speed negotiation. The default value is 750000.
13.
SPEED_NEGOTIATION_
LOCK_TIME
153600
Specifies the maximum time (in UIs) within the

speed negotiation window for a transmitter to reply
with ALIGN(1). The default value is 153600.
14.
SPEED_NEGOTIATION_
TRANSMIT_TIME
163840
Specifies the time (in UIs) in which ALIGN(0) or

ALIGN(1) is transmitted at each physical link rate
during the speed negotiation sequence.The default
value is 163840.
15.
TX_MAX_SUPPORTED_RATE
Configures the maximum rate supported by the

device. Set this to 1 if G2 (3.0 Gbps) is the
maximum rate supported. Set this to 0 if G1 (1.5
Gbps) is the maximum rate supported.
16.
RX_MAX_SUPPORTED_RATE

17.
REPEATED_PRIMITIVE_SEQ
Configures the monitor to track repetitive primitive

sequences. Set this parameter to 0 to disable the
tracking of repeated primitive sequences. By
default, the monitor tracks repetitive primitive
sequences.
18.
TRANSPORT_LAYER_
CHECKS_ENABLE
Configures the monitor to perform the transport

layer checks. Set this parameter to 0 to configure
the monitor to omit transport layer checks. By
default, the transport layer checks are turned on.
19.
HOTPLUG_TIMEOUT_
PERIOD
1499250
Configures the time period (in UIs) within which a

COMINIT or COMSAS sequence must be received
after transmitting a COMINIT sequence. By
default, the hot plug timeout period is set to 1
millisecond.
631


Order Parameter
Default Description
20.
COMSAS_TIMEOUT_
PERIOD
20480
Configures the time period (in UIs) within which a

COMSAS sequence must be received after
transmitting a COMSAS sequence. By default, the
COMSAS timeout period is 13.65 microseconds.
21.
HARD_RESET_PERIOD
1499250
Configures the hard reset period (in UIs). After a

port detects a hard reset, it should not send any
valid primitives within one millisecond.
22.
DISABLE_DESCRAMBLER
Configures the monitor to perform descrambling of

decoded 8-bit data. Set this parameter to 1 to
disable descrambling. By default, descrambling is
enabled.
23.
IDENT_TIMEOUT
1499250
Configures the identification address frame timeout

period (in UIs). If the port transmits an
identification address frame, it should receive the
same from the other side within one millisecond.
24.
BREAK_TIMEOUT
1499250
Configures the break timeout period (in UIs). If the

port sends a break, then it should receive a break
25.
OPEN_ADDR_RES_TIMEOUT
1499250
Configures the open address response timeout

period (in UIs). After a port sends an open address
frame, it should receive a response within one
millisecond.
26.
CREDIT_TIMEOUT
1499250
Configures the credit timeout period (in UIs). A

port that accepts an open address frame should send
a credit within one millisecond.
27.
ACK_NAK_TIMEOUT
1499250
Configures the ACK/NAK timeout period (in UIs).

If the port sends an SSP frame, then it should be
acknowledged within one millisecond.
28.
CLOSE_TIMEOUT
1499250
Configures the close timeout period (in UIs). If the

port sends a close, then it should receive a close
29.
DONE_TIMEOUT
1499250
Configures the done timeout period (in UIs). If the

port sends a done, then it should receive a done
30.
PHY_RESET_SEQ_CHECK_
ENABLE
Configures the monitor to perform checks during

PHY reset sequence. Set the parameter to 1 to
configure the monitor to perform reset sequence
checks. By default, reset sequence checks are
turned off.
31.
ENABLE
Configures the monitor to perform the check for

reserved values of the Link layer and Transport
layer frames. Set this parameter to 1 to configure
the monitor to perform the reserved value checks.
By default, the monitor checks for reserved values
of the Link layer and Transport layer frames.
632


Order Parameter
Default Description
32.
VENDOR_SPECIFIC_
ENCODING_ENABLE
Configures the monitor to check for vendor-specific

encodings in the SSP and SMP frames. Set this
parameter to 1 to configure the monitor to perform
the check for vendor-specific encodings. By
default, the monitor allows vendor-specific
encodings.
33.
RX_COMINIT_IDLE_
TIME_MIN
260
Configures the receiver idle time period between

ALIGN bursts in a COMINIT sequence. The idle
34.
RX_COMINIT_IDLE_TIME_
MAX
780

ALIGN bursts in a COMINIT sequence. The idle
35.
RX_COMSAS_IDLE_TIME_
MIN
780

ALIGN bursts in a COMSAS sequence. The idle
36.
RX_COMSAS_IDLE_TIME_
MAX
2360

ALIGN bursts in a COMSAS sequence. The idle
37.
RX_COMINIT_NEGATION_
TIME_PERIOD
780
Configures the receiver negation time after a

COMINIT sequence. The idle time period must be
specified in UIs.
38.
RX_COMSAS_NEGATION_
TIME_PERIOD
2360
Configures the receiver negation time after a

COMSAS sequence. The idle time period must be
specified in UIs.
The term UI (Unit Interval) is the number of active edges of the clock.
The SAS monitor supports 20-bit parallel interface implementations (with some
restrictions). To configure the monitor to track a 20-bit parallel interface, set the
INTERFACE_TYPE parameter to 2. In this mode, the monitor cannot be configured for
double data rate operation, (i.e., the parameter DOUBLE_DATA_RATE must be set to 0). In
other words, the monitor supports only single data rate implementations in 20-bit
parallel mode.
The parameters shown in Table 15-3 configure the SAS (dynamic timer values) monitor.
Table 15-3. SAS Monitor (dynamic timer values) Parameters
Order
Parameter
Default Description
1.
Constraints_Mode

633

Table 15-3. SAS Monitor (dynamic timer values) Parameters (cont.)
634
Order
Parameter
Default Description
2.
SAS_DEVICE_TYPE
Configures the monitor to track an initiator/target

device or an expander/fanout expander device. Set
this parameter to 1 to track an expander/fanout
expander device. By default, the monitor tracks an
initiator/target device.
3.
INTERFACE_TYPE

instantiated on a parallel interface. By default, the
monitor is instantiated on a serial interface. See
Note 3.
4.
DOUBLE_DATA_RATE
Configures the active edge of the tx_clk/rx_clk

clocks. Set this parameter to 1 if both edges of
tx_clk/rx_clk clocks are active. Set this parameter
to 0 if tx_clk/rx_clk is active on only the rising
edge. By default, tx_clk/rx_clk is active on only the
rising edge. See Note 3.
5.
TX_DEVICE_SPEED_RATE
Configures the rate at which ALIGNs are

transmitted after power up. Set this parameter to 1
if ALIGNs are transmitted at a G2 (3.0 Gbps) rate.
By default, ALIGNs are transmitted at a G1 (1.5
Gbps) rate.
6.
RX_DEVICE_SPEED_RATE
Configures the rate at which ALIGNs are received

after power-up. Set this parameter to 1 if ALIGNs
are received at a G2 (3.0 Gbps) rate. By default,
ALIGNs are received at a G1 (1.5G bps) rate.
7.
ELECTRICAL_IDLE_TIME_
BIT_PATTERN
1023
Specifies the value of the encoded 10B data during

electrical idle conditions. This parameter is
applicable only when INTERFACE_TYPE is set to
1 or 2 (parallel mode of operation). The default
value of the parameter is the value equivalent to
3FFh, the assumed 10-bit encoded value for
electrical idle. In serial mode, the monitor detects
an electrical idle when both D+ and D inputs are
driven to the same level.
8.
TX_MAX_SUPPORTED_RATE

9.
RX_MAX_SUPPORTED_RATE

10.
Configures the monitor to track repetitive primitive

sequences. Set this parameter to 0 to disable the
tracking of repeated primitive sequences. By
default, the monitor tracks repetitive primitive
sequences.
11.
TRANSPORT_LAYER_
CHECKS_ENABLE
Configures the monitor to perform the transport

layer checks. Set this parameter to 0 to configure
the monitor to omit transport layer checks. By
default, the transport layer checks are turned on.

Table 15-3. SAS Monitor (dynamic timer values) Parameters (cont.)

Order
Parameter
Default Description
12.
DISABLE_DESCRAMBLER
Configures the monitor to perform descrambling of

decoded 8-bit data. Set this parameter to 1 to
disable descrambling. By default, descrambling is
enabled.
13.
PHY_RESET_SEQ_CHECK_
ENABLE
Configures the monitor to perform checks during

PHY reset sequence. Set the parameter to 1 to
configure the monitor to perform reset sequence
checks. By default, reset sequence checks are
turned off.
14.
ENABLE
Configures the monitor to perform the check for

reserved values of the Link layer and Transport
layer frames. Set this parameter to 1 to configure
the monitor to perform the reserved value checks.
By default, the monitor checks for reserved values
of the Link layer and Transport layer frames.
15.
VENDOR_SPECIFIC_
ENCODING_ENABLE
Configures the monitor to check for vendorspecific encodings in the SSP and SMP frames. Set
this parameter to 1 to configure the monitor to
perform the check for vendor-specific encodings.
By default, the monitor allows vendor-specific
encodings.
The term UI (Unit Interval) is the number of active edges of the clock.
The SAS monitor supports 20-bit parallel interface implementations (with some
restrictions). To configure the monitor to track a 20-bit parallel interface, set the
INTERFACE_TYPE parameter to 2. In this mode, the monitor cannot be configured for
double data rate operation, (i.e., the parameter DOUBLE_DATA_RATE must be set to 0). In
other words, the monitor supports only single data rate implementations in 20-bit
parallel mode.
Example 15-1 and Example 15-2 show instantiating an SAS monitor. Example 15-3 and
Example 15-4 shows instantiating an SAS (dynamic timer values) monitor.
Example 1
Example 15-1 instantiates an SAS monitor within an SAS device. The input to the device is
serial data. The clocks are active on the rising edge. The value of bypass_reset_sequence is
set to 1'b1. This instance does not track the PHY reset sequence.
635

Example 15-1. SAS Monitor Within an SAS Device

qvl_sas_monitor
#( 0,
/* Constraints_Mode *
0,
/* SAS_DEVICE_TYPE *
0,
0,
0,
/* TX_DEVICE_SPEED_RATE */
0,
/* RX_DEVICE_SPEED_RATE */
480,
/* TX_COMINIT_IDLE_TIME *
1440,
/* TX_COMSAS_IDLE_TIME */
800,
/* TX_COMINIT_NEGATION_TIME_PERIOD */
2400,
/* TX_COMSAS_NEGATION_TIME_PERIOD */
1023,
/* ELECTRICAL_IDLE_TIME_BIT_PATTERN */
750000, /* RATE_CHANGE_DELAY */
153600, /* SPEED_NEGOTIATION_LOCK_TIME */
163840, /* SPEED_NEGOTIATION_TRANSMIT_TIME */
0,
/* TX_MAX_SUPPORTED_RATE */
0,
/* RX_MAX_SUPPORTED_RATE */
1,
/* REPEATED_PRIMITIVE_SEQ */
1,
/* TRANSPORT_LAYER_CHECKS_ENABLE */
1499250, /* HOTPLUG_TIMEOUT_PERIOD *
20480,
/* COMSAS_TIMEOUT_PERIOD */
1499250, /* HARD_RESET_PERIOD */
0,
/* DISABLE_DESCRAMBLER */
1499250, /* IDENT_TIMEOUT */
1499250, /* BREAK_TIMEOUT */
1499250, /* OPEN_ADDR_RES_TIMEOUT */
1499250, /* CREDIT_TIMEOUT */
1499250, /* ACK_NAK_TIMEOUT */
1499250, /* CLOSE_TIMEOUT */
1499250, /* DONE_TIMEOUT */
0,
/* PHY_RESET_SEQ_CHECK_ENABLE*/
1,
0,
/* VENDOR_SPECIFIC_CHECK_ENABLE */
260,
/* RX_COMINIT_IDLE_TIME_MIN */
780,
/* RX_COMINIT_IDLE_TIME_MAX */
780,
/* RX_COMSAS_IDLE_TIME_MIN */
2360,
/* RX_COMSAS_IDLE_TIME_MAX */
780,
/* RX_COMINIT_NEGATION_TIME_PERIOD */
2360)
/* RX_COMSAS_NEGATION_TIME_PERIOD */
SERIAL_MODE (
.areset
(areset),
.reset
(reset),
.tx_clk
(tx_clk),
.tx_data_plus
(tx_data_plus)
.tx_data_minus
(tx_data_minus),
.tx_idle_signal
(tx_idle_signal),
.rx_clk
(rx_clk),
.rx_data_plus
(rx_data_plus),
.rx_data_minus
(rx_data_minus),
.rx_idle_signal
(rx_idle_signal),
.bypass_reset_sequence (1'b1),
.start_speed_negotiation(1'b0) );
636

Example 2
Example 15-2 instantiates an SAS monitor within an expander device. The inputs to the
expander device are parallel 10B data. The clocks are active on both edges. The value of
bypass_reset_sequence is set to 1'b0. This instance will track the PHY reset sequence.
Example 15-2. SAS Monitor Within an Expander Device
qvl_sas_monitor
#( 0,
1,
/* SAS_DEVICE_TYPE */
1,
1,
0,
0,
48,
/* TX_COMINIT_IDLE_TIME */
144,
/* TX_COMSAS_IDLE_TIME */
80,
/* TX_COMINIT_NEGATION_TIME_PERIOD */
240,
/* TX_COMSAS_NEGATION_TIME_PERIOD */
1023,
/* ELECTRICAL_IDLE_TIME_BIT_PATTERN */
75000,
/* RATE_CHANGE_DELAY */
15360,
/* SPEED_NEGOTIATION_LOCK_TIME */
16384,
/* SPEED_NEGOTIATION_TRANSMIT_TIME */
0,
0,
1,
1,
149925, /* HOTPLUG_TIMEOUT_PERIOD */
2048,
/* COMSAS_TIMEOUT_PERIOD */
149925, /* HARD_RESET_PERIOD */
0,
149925, /* IDENT_TIMEOUT */
149925, /* BREAK_TIMEOUT */
149925, /* OPEN_ADDR_RES_TIMEOUT */
149925, /* CREDIT_TIMEOUT */
149925, /* ACK_NAK_TIMEOUT */
149925, /* CLOSE_TIMEOUT */
149925, /* DONE_TIMEOUT */
0,
1,
0,
/* VENDOR_SPECIFIC_CHECK_ENABLE */
26,
/* RX_COMINIT_IDLE_TIME_MIN */
78,
/* RX_COMINIT_IDLE_TIME_MAX */
78,
/* RX_COMSAS_IDLE_TIME_MIN */
236,
/* RX_COMSAS_IDLE_TIME_MAX */
78,
/* RX_COMINIT_NEGATION_TIME_PERIOD */
236)
/* RX_COMSAS_NEGATION_TIME_PERIOD */
PARALLEL_MODE (
.areset
(areset),
.reset
(reset),
.tx_clk
(tx_clk),
.tx_data_plus
(tx_data_plus),
.tx_data_minus
(tx_data_minus),
.tx_idle_signal
(tx_idle_signal),
.rx_clk
(rx_clk),
.rx_data_plus
(rx_data_plus),
637

.rx_data_minus
(rx_data_minus),
.rx_idle_signal
(rx_idle_signal),
.bypass_reset_sequence (1'b0)
.start_speed_negotiation (start_speed_negotiation) );
Example 3
Example 15-3 instantiates an SAS monitor within a SAS device. The input to the device is serial
data. The clocks are active on the rising edge. The value of bypass_reset_sequence is set to
1'b1. This instance does not track the PHY reset sequence.
Example 15-3. SAS Monitor Within a SAS Device
qvl_sas_dynamic_timer_values_monitor
#( 0,
0,
0,
0,
0,
0,
1023, /* ELECTRICAL_IDLE_TIME_BIT_PATTERN */
0,
0,
1,
1,
0,
0,
1,
0)
/* VENDOR_SPECIFIC_ENCODING_ENABLE*/
SERIAL_MODE (
.areset
(areset),
.reset
(reset),
.tx_clk
(tx_clk),
.tx_data_plus
(tx_data_plus),
.tx_data_minus
(tx_data_minus),
.tx_idle_signal
(tx_idle_signal),
.rx_clk
(rx_clk),
.rx_data_plus
(rx_data_plus),
.rx_data_minus
(rx_data_minus),
.rx_idle_signal
(rx_idle_signal),
.bypass_reset_sequence
(1'b1),
.start_speed_negotiation
(1'b0),
.tx_cominit_idle_time
(cominit_idle_time),
.tx_comsas_idle_time
(comsas_idle_time),
.rx_cominit_idle_time_min (cominit_neg_time),
.rx_cominit_idle_time_max (comsas_neg_time),
.rx_comsas_idle_time_min
(rate_change_delay),
.rx_comsas_idle_time_max
(spd_neg_lock_time),
.tx_cominit_neg_time
(spd_neg_transmit_time),
.tx_comsas_neg_time
(hotplug_timeout),
.rx_cominit_neg_time
(comsas_timeout),
.rx_comsas_neg_time
(hard_reset_timeout),
.rate_change_delay
(ident_frame_timeout),
.spd_neg_lock_time
(break_timeout),
.spd_neg_transmit_time
(open_addr_res_timeout),
638

.hotplug_timeout
.comsas_timeout
.hard_reset_timeout
.ident_frame_timeout
.break_timeout
.open_addr_res_timeout
.credit_timeout
.ack_nak_timeout
.close_timeout
.done_timeout
(credit_timeout),
(ack_nak_timeout),
(close_timeout) );
Example 4
Example 15-4 instantiates an SAS monitor within an expander device. The inputs to the
expander device are parallel 10B data. The clocks are active on both edges. The value of
bypass_reset_sequence is set to 1'b0. This instance will track the PHY reset sequence.
Example 15-4. SAS Monitor Within an Expander Device
qvl_sas_dynamic_timer_values_monitor
#( 0,
1,
1,
1,
0,
0,
1023, /* ELECTRICAL_IDLE_TIME_BIT_PATTERN */
0,
0,
1,
1,
0,
0,
1,
0)
/* VENDOR_SPECIFIC_ENCODING_ENABLE*/
PARALLEL_MODE (
.areset
(areset),
.reset
(reset),
.tx_clk
(tx_clk),
.tx_data_plus
(tx_data_plus),
.tx_data_minus
(tx_data_minus),
.tx_idle_signal
(tx_idle_signal),
.rx_clk
(rx_clk),
.rx_data_plus
(rx_data_plus),
.rx_data_minus
(rx_data_minus),
.rx_idle_signal
(rx_idle_signal),
.bypass_reset_sequence
(1'b0)
(start_speed_negotiation)
.tx_cominit_idle_time
(tx_cominit_idle_time),
(tx_comsas_idle_time),
.rx_cominit_idle_time_min (rx_cominit_idle_time_min),
.rx_cominit_idle_time_max (rx_cominit_idle_time_max),
(rx_comsas_idle_time_min),
(rx_comsas_idle_time_max),
(tx_cominit_neg_time),
639

.tx_comsas_neg_time
.rx_comsas_neg_time
.rate_change_delay
.spd_neg_lock_time
.hotplug_timeout
.comsas_timeout
.hard_reset_timeout
.break_timeout
.credit_timeout
.ack_nak_timeout
.close_timeout
.done_timeout
(tx_comsas_neg_time),
(rx_cominit_neg_time),
(rx_comsas_neg_time),
(hotplug_timeout),
(comsas_timeout),
(break_timeout),
(credit_timeout),
(ack_nak_timeout),
(close_timeout)
(done_timeout));
Connecting Clocks in Serial Mode

On the SAS interface, the clock is embedded in the data streams. However, the monitor expects
the clock signal as it does not perform the clock recovery operation. Figure 15-4 shows how to
instantiate the monitor to track a device (A).
Figure 15-4. Connecting Clocks in Serial Mode
Clk_Recovery
Tx
Rx
tx_data
Device A
Device B
Rx
Tx
rx_data
Clk_Recovery
recovered_clock
recovered_clock
rx_clk
tx_clk
SAS Monitor
Clock Recovery Module

If clocks are not available from the design, then you can use the clock recovery module
(qvl_clock_recovery.v) to recover the clocks (see Figure 15-5). Each clock is recovered from
the serial data D+ and D- on the bus. Signals tx_data_plus, tx_data_minus,
rx_data_plus, and rx_data_minus are inputs to the clock recovery modules. Signals
640

tx_recovered_clk and rx_recovered_clk are output from the clock recovery modules.
Connect the recovered_clk signals to the monitor clock ports. The parameters shown in
Table 15-4 configure the clock recovery modules. Example 15-5 shows an instantiation
example.
Figure 15-5. Connecting Clock Recovery Modules
rx_data_plus
tx_data_plus
Rx Clk Recovery
Tx Clk Recovery
rx_data_minus
tx_data_minus
rx_recovered_clock
tx_recovered_clock
rx_clk
tx_clk
SAS Monitor
Note that the clock recovery module is used for simulation with assertions only (not formal
verification).
Do not use the clock recovery module if a pulse width of 1 UI for a particular speed (G1 or G2)
changes dynamically during simulation.
Table 15-4. Clock Recovery Module Parameters

Order Parameter
Default Description
1.
ELECTRICAL_IDLE_LENGTH
30000
If the bus has no activity for a long period, then

clock generation from the module is stalled. The
clock recovery module will resynchronize when
D+ and D signals transition on the bus. This
parameter configures the bus inactivity period,
which should equal the RATE CHANGE
DELAY period of the speed negotiation phase of
the devices.
2.
TIME_UNIT
Selects the time unit for the module. Clock

recovery uses the default time unit set in the
testbench (using `timescale). Set this parameter to
1 if the time unit is in fs. By default, the clock
recovery module assumes a time unit in ps. That
is, UI is of width 333 ps (G2 rate) and 666 ps (G1
rate).
Example 15-5 instantiates a clock recovery monitor. The RATE CHANGE DELAY period is
250000 UIs and the time unit used in the testbench is in fs (i.e., 1 UI at a G2 rate equals 333000
fs and 1 UI at a G1 rate equals 666000 fs).
641

Monitor Checks
Example 15-5. Clock Recovery Monitor Instantiation

qvl_clock_recovery
#( 250000,
/* ELECTRICAL_IDLE_LENGTH */
1)
/* TIME_UNIT */
CLK_RECOVERY (
.pos_data
(serial_data_plus),
.neg_data
(serial_data_minus),
.clock
(recovered_clock));
Monitor Checks
The checks performed by the SAS monitor are classified as follows:
Physical layer checks.
Link layer checks.
Transport layer checks.
Physical Layer Checks

Table 15-5 shows the physical layer checks performed by the SAS monitor.
Table 15-5. SAS Monitor Physical Layer Checks
Check ID
Violation
Description
SAS_10B_CODING_
VIOLATION_P
Invalid 10b code on

interface.
Valid 10B data should be detected on the

interface. This check fires if an invalid
10B symbol is detected on the interface.
SAS_10B_CODING_
VIOLATION_N
SAS_ADDR_FRAME_TYPE_
VIOLATION_P
SAS_ADDR_FRAME_TYPE_
VIOLATION_N
SAS_AIP_DWORD_COUNT_
VIOLATION_P
SAS_AIP_DWORD_COUNT_
VIOLATION_N
642
Address Frame Type field in Address frame type field in the address
the Address Frame should
frame should be equal to 0h or 1h. This
have the value 0h or 1h.
check fires if the address frame type is not
0h or 1h, and the
ENABLE parameter is set.
AIP primitives should be
detected once in every 128
dwords.
Expander devices should transmit AIP

primitives once in every 128 dwords. This
check fires if more than 128 dwords are
detected without an AIP primitive.

Monitor Checks
Table 15-5. SAS Monitor Physical Layer Checks (cont.)

Check ID
Violation
Description
SAS_ALIGN0_TO_ALIGN1_
TRANS_VIOLATION_P
ALIGN(0) to ALIGN(1)
transition should happen
within speed negotiation
lock time (SNLT).
During the speed negotiation sequence,

devices indicate synchronization with the
incoming ALIGN(0)s by transmitting
ALIGN(1)s instead of ALIGN(0)s. The
ALIGN(0) to ALIGN(1) transition in a
speed negotiation window should happen
within the specified SNLT window. This
check fires if the transition from
ALIGN(0) to ALIGN(1) occurs outside
the SNLT window.
Number of ALIGNs in the

ALIGN burst is not equal to
the number of ALIGNs
required.
During PHY reset sequence, number of

ALIGNs transmitted in the ALIGN burst
should be equal to 4, which corresponds
to160UIs (in G1 rate). The ALIGN count
doubles for G2 rate. This check fires if the
ALIGN count for the given rate is
violated. If parameter
PHY_RESET_SEQ_CHECK_ENABLE
is 1, G1 align burst should have 4 ALIGNs
and G2 align burst should have 8 ALIGNs.
ALIGN primitives should

be detected once in every
2048 dwords.
No more than 2048 dwords can be

detected without an ALIGN in the SAS
port. This check fires if more than 2048
dwords are detected without an ALIGN
primitive.
For a SMP initiator, the

connection tag field of an
open address frame should
be ffffh.
Connection tag field of the open address

frames transmitted by a SMP initiator
should have a value of ffffh. This check
fires if the connection tag field is not equal
to ffffh.
6'b000111 should be
beginning of the sub-block
is positive.

000111b or 0011b are generated only
when the running disparity at the
beginning of the sub-block is positive. The
monitor fires when this is violated.

beginning of the sub-block is positive. The

beginning of the sub-block is negative.The
SAS_ALIGN0_TO_ALIGN1_
TRANS_VIOLATION_N
SAS_ALIGN_COUNT_
VIOLATION_P
SAS_ALIGN_COUNT_
VIOLATION_N
SAS_ALIGN_DWORD_COUNT_
VIOLATION_P
SAS_ALIGN_DWORD_COUNT_
VIOLATION_N
SAS_CONNECTION_TAG_
VIOLATION_P
SAS_CONNECTION_TAG_
VIOLATION_N
SAS_DISPARITY_NEUTRAL_
000111_ERROR_P
000111_ERROR _N
0011_ERROR_P
0011_ERROR_N
1100_ERROR_P
1100_ERROR_N
643

Monitor Checks

Check ID
Violation
Description
111000_ERROR_P
6'b111000 should be
is negative.

beginning of the sub-block is negative.
The monitor fires when this is violated.
Electrical idle detected

during Speed Negotiation
Transmit Time (SNTT).
SAS devices transmit ALIGN(0)

primitives during the SNTT window to
indicate the particular rate that is
supported. Electrical idle should not be
detected within the SNTT window once
ALIGNs are transmitted. This check fires
if the monitor detects ALIGNS first and
then electrical idle during the SNTT
window.
ALIGN0 was not detected

in G1 phase of speed
negotiation window.
The maximum rates supported by the

devices are configured by the parameters
TX_MAX_SUPPORTED_RATE and
RX_MAX_SUPPORTED_RATE.
ALIGN(0) must be transmitted within the
G1 speed negotiation window, if the G1
rate is specified as the max rate supported.
This check fires if ALIGN(0)s are not
detected within the Speed Negotiation
Lock Time (SNLT) window for a device
with the max rate of G1 that is supported
for the device in which the monitor is
instantiated.
ALIGN0 was not detected

in G2 phase of speed
negotiation window.
The maximum rates supported by the

devices are configured by the user using
the parameters
TX_MAX_SUPPORTED_RATE and
RX_MAX_SUPPORTED_RATE.
ALIGN(0) must be transmitted within the
G2 speed negotiation window if the G2
rate is specified to be the maximum rate
supported. This check fires if ALIGN(0)s
are not detected during the Speed
Negotiation Lock Time (SNLT) window
for a device with the maximum rate of G2
that is supported for the device in which
the monitor is instantiated.
111000_ERROR_N
SAS_ELECTRICAL_IDLE_
DETECTED_DURING_SNTT_P
SAS_ELECTRICAL_IDLE_
DETECTED_DURING_SNTT_N
SAS_G1_RATE_SUPPORTED_
WITHOUT_ALIGN_P
WITHOUT_ALIGN_N
WITHOUT_ALIGN_P
WITHOUT_ALIGN_N
SAS_HARD_RESET_PRIMITIVE_ HARD RESET primitive

VIOLATION_P
should be detected 6 times.
SAS_HARD_RESET_PRIMITIVE_
VIOLATION_N
SAS_IAF_DEV_TYPE_
VIOLATION_P
SAS_IAF_DEV_TYPE_
VIOLATION_N
644
Device Type field in the

Identification Address
Frame should be 1h, 2h, or
3h.
HARD RESET primitive is a redundant

primitive and it should be detected six
times. This check fires if six consecutive
HARD RESET primitives are not
detected.
Device type field in the Identification
address frame should have the values 1h,
2h, or 3h. This check fires if the device
type is not END DEVICE(1h),
EXPANDER DEVICE(2h), or FANOUT
EXPANDER DEVICE(3h), and the

Monitor Checks

Check ID
Violation
Description
SAS_IAF_FRAME_SIZE_
VIOLATION_P
Identification Address
Frame should contain 32
bytes.
Length of the Identification address frame

should be equal to 32 bytes. This check
fires if the identification address frame
length is not equal to 32 bytes.
Idle time violation during

reset sequence.
Idle time between two ALIGN bursts

should be equal to the parameter
COMINIT_IDLE or COMSAS_IDLE
depending on whether it is a COMINIT
sequence or a COMSAS sequence. This
check fires if the specified idle time is
violated after detecting four COMINIT or
COMSAS ALIGN bursts. If parameter
PHY_RESET_SEQ_CHECK_ENABLE
is 1, then the idle period in G1 rate should
be 480 UIs during a COMINIT sequence
and 1440 UIs during a COMSAS
sequence.
Illegal Primitive detected.
The detected primitive is not a valid SAS

primitive. This check fires if the detected
primitive is not listed in table 43 through
45 of the reference documentation.
Illegal primitive detected

outside the connection.
Primitives are dwords whose first

characters are control characters. Some
primitives that are valid only inside a
connection should not be transmitted
outside the connection. For example, a
CLOSE primitive should be transmitted
only within a connection. This check fires
if a primitive that must be transmitted only
within a connection is detected outside
connections.
No more than 3 consecutive

AIP primitives should be
detected without an
intermediate idle dword.
Expander devices should not transmit

more than 3 AIP primitives consecutively
without an idle dword in between. This
check fires if more than 3 consecutive AIP
primitives are detected without an idle
dword.
Only ALIGN(0) and

ALIGN(1) primitives are
allowed inside the speed
negotiation window.
SAS devices should transmit either

ALIGN(0) or ALIGN(1) during the entire
speed negotiation sequence. This check
fires if any other primitives are detected
during speed negotiation.
Feature field in the Open

Address Frame should be
set to zero.
Feature field in the open address frame

should be equal to zero. This check fires if
the feature field is set to a nonzero value
and the RESERVED_FIELD_CHECK_
SAS_IAF_FRAME_SIZE_
VIOLATION_N
SAS_IDLE_COUNT_
VIOLATION_P
SAS_IDLE_COUNT_
VIOLATION_N
SAS_ILLEGAL_PRIMITIVE_P
SAS_ILLEGAL_PRIMITIVE_N
SAS_ILLEGAL_PRIMITIVE_
OUTSIDE_CONNECTION_P
OUTSIDE_CONNECTION_N
SAS_MORE_THAN_
3CONSECUTIVE_AIP_P
SAS_MORE_THAN_
3CONSECUTIVE_AIP_N
SAS_NON_ALIGN_PRIMITIVE_
IN_SPD_NEG_WINDOW_P
SAS_NON_ALIGN_PRIMTIVE_
IN_SPD_NEG_WINDOW_N
SAS_OAF_FEATURE_
VIOLATION_P
SAS_OAF_FEATURE_
VIOLATION_N
SAS_OAF_FRAME_SIZE_
VIOLATION_P
SAS_OAF_FRAME_SIZE_
VIOLATION_N
Open Address Frame should Length of the Open address frame should
contain 32 bytes.
be equal to 32 bytes. This check fires if the
open address frame length is not equal to
32 bytes.
645

Monitor Checks

Check ID
Violation
SAS_OAF_LINK_RATE_
VIOLATION_P
Link Rate field in the Open Current link rate field in the Open address
Address Frame should be 0h frame should be either 0h (1.5Gbps) or 1h
or 1h.
(3.0Gbps). This check fires if the link rate
field contains a value other than 0h or 1h,
and the RESERVED_FIELD_CHECK_
SAS_OAF_LINK_RATE_
VIOLATION_N
SAS_OAF_PROTOCOL_
VIOLATION_P
Description
Protocol field in the Open

Address Frame should have
the value 0h,1h, or 2h.
Protocol field in the Open address frame

should have SSP, SMP, or STP protocols
specified. This check fires if the protocol
field contains a value other than 0h,1h, or
2h, and the
RESERVED_FIELD_CHECK_ENABLE
parameter is set.
A nonexpander device
should not transmit OPEN
REJECT (BAD
DESTINATION).
OPEN REJECT (BAD DESTINATION)

should be transmitted by an expander
device. This check fires if an OPEN
REJECT (BAD DESTINATION)
primitive is transmitted by a nonexpander
device (i.e., parameter
SAS_DEVICE_TYPE set to zero).
REJECT (NO
DESTINATION).
OPEN REJECT (NO DESTINATION)

should be transmitted by an expander
device. This check fires if an OPEN
REJECT (NO DESTINATION) primitive
is transmitted by a nonexpander device
(i.e., parameter SAS_DEVICE_TYPE set
to zero).
REJECT(PATHWAY
BLOCKED).
OPEN REJECT (PATHWAY

BLOCKED) should be transmitted by an
expander device. This check fires if an
OPEN REJECT (PATHWAY
BLOCKED) primitive is transmitted by a
nonexpander device (i.e., parameter
Reserved AIP primitives

Reserved AIP primitives should not be

detected on the SAS interface. This check
fires if reserved AIP primitives are
detected on the SAS interface.
Reserved BROADCAST
primitives should not be
detected on SAS interface.
Reserved BROADCAST primitives

should not be detected. This check fires if
reserved BROADCAST primitives are
Allowed K-codes in SAS

protocol are K28.5 and
K28.3.
K28.5 and K28.3 are the allowed K-codes

in SAS protocol. This check fires if any of
the K-codes listed in the table 33 of the
reference documentation other than K28.5
and K28.3.
SAS_OAF_PROTOCOL_
VIOLATION_N
SAS_OPEN_REJ_BAD_
DESTINATION_VIOLATION_P
SAS_OPEN_REJ_BAD_
DESTINATION_VIOLATION_N
SAS_OPEN_REJ_NO_
DESTINATION_VIOLATION_P
SAS_OPEN_REJ_NO_
DESTINATION_VIOLATION_N
SAS_OPEN_REJ_PATHWAY_
BLOCK_VIOLATION_P
SAS_OPEN_REJ_PATHWAY_
BLOCK_VIOLATION_N
SAS_RESERVED_AIP_
PRIMITIVE_P
SAS_RESERVED_AIP_
PRIMITIVE_N
SAS_RESERVED_BROADCAST_
PRIMITIVE_P
SAS_RESERVED_BROADCAST_
PRIMITIVE_N
SAS_RESERVED_K_CODE_P
SAS_RESERVED_K_CODE_N
646

Monitor Checks

Check ID
Violation
Description
SAS_RESERVED_
NOTIFY_PRIMITIVE_P
Reserved NOTIFY
detected.
Reserved NOTIFY primitives should not

be detected. This check fires if reserved
NOTIFY primitives are detected on the
SAS interface.
Reserved OPEN_REJECT
detected.
Reserved OPEN_REJ primitives should

not be detected. This check fires if
reserved OPEN_REJ primitives are
Speed negotiation window

violation occurred.
SAS devices should transmit ALIGN

primitives only within windows like
SNTT window. This check fires if an
ALIGN(0) or ALIGN(1) is detected
outside the specified Speed Negotiation
Transmit Time (SNTT).
SAS_RESERVED_
NOTIFY_PRIMITIVE_N
SAS_RESERVED_OPEN_REJ_
PRIMITIVE_P
SAS_RESERVED_OPEN_REJ_
PRIMITIVE_N
SAS_SPD_NEG_WINDOW_
VIOLATION_P
SAS_SPD_NEG_WINDOW_
VIOLATION_N
Transport Layer Checks

Table 15-6 shows the transport layer checks performed by SAS monitor.
Table 15-6. SAS Monitor Transport Layer Checks
Check ID
Violation
Description
SAS_ACK_NAK_RECEIVED_
WITHOUT_FRAME_
TRANSMISSION_P
Device should not send ACK or

NAK without receiving frame.
ACK or NAK primitives are

transmitted to acknowledge receipt
of frames. SAS device should not
transmit acknowledgement
(ACK/NAK) without receiving any
frame. This check fires if ACK or
NAK primitives are detected
without any frames.
Frames should be acknowledged

within the time specified by the
parameter
ACK_NAK_TIMEOUT.
Every frame should be

acknowledged within the time
specified in the parameter
ACK_NAK_TIMEOUT. This
check fires if an ACK/NAK timeout
occurs.
ALIGN(0) primitive expected.
A SAS device can insert ALIGNs

within frames and the sequence of
rotation should be maintained.
ALIGN3 should be followed by
ALIGN0. This check fires if
ALIGN(0) is not detected after
ALIGN(3).
SAS_ACK_NAK_RECEIVED_
WITHOUT_FRAME_
TRANSMISSION_N
SAS_ACK_NAK_TIMEOUT_
VIOLATION_P
SAS_ACK_NAK_TIMEOUT_
VIOLATION_N
SAS_ALIGN0_PRIMITIVE_
EXPECTED_P
EXPECTED_N
647

Monitor Checks
Table 15-6. SAS Monitor Transport Layer Checks (cont.)

Check ID
Violation
Description
EXPECTED_P

within frames, and the sequence of
ALIGN(0).

ALIGN(1).

ALIGN(3).
BREAK primitive should be

detected 6 times.
BREAK primitive is a redundant

primitive and it should be detected
six times. This check fires if six
consecutive BREAK primitives are
not detected, and the
parameter is set.
Break timeout occurred.
BREAK primitives should be

exchanged by devices to indicate
breaking the connection. A BREAK
primitive should be responded with
a BREAK primitive within the
specified BREAK_TIMEOUT
value.
BROADCAST primitive should

be detected 6 times.
BROADCAST primitive is a
redundant primitive, and it should
be detected six times. This check
fires if six consecutive
BROADCAST primitives are not
detected, and the
parameter is set.
When detected, three consecutive

CLOSE_AFFILIATION
primitives must be detected.
CLOSE_AFFILIATION primitive
is a triple primitive and should be
detected 3 times. This check fires if
three consecutive
CLOSE_AFFILIATION primitives
are not detected and the
parameter is set.
EXPECTED_N
EXPECTED_P
EXPECTED_N
EXPECTED_P
EXPECTED_N
SAS_BREAK_PRIMITIVE_
VIOLATION_P
SAS_BREAK_PRIMITIVE_
VIOLATION_N
SAS_BREAK_TIMEOUT_
VIOLATION_P
SAS_BREAK_TIMEOUT_
VIOLATION_N
SAS_BROADCAST_PRIMITIVE_
VIOLATION_P
SAS_BROADCAST_PRIMITIVE_
VIOLATION_N
SAS_CLOSE_AFFILIATION_
PRIM_VIOLATION_P
SAS_CLOSE_AFFILIATION_
PRIM_VIOLATION_N
648

Monitor Checks

Check ID
Violation
Description
SAS_CLOSE_PRIMITIVE_
VIOLATION_P
CLOSE primitive should be

detected 3 times.
CLOSE primitive is a triple

primitive. This check fires if 3
consecutive CLOSE primitives are
not detected, and the
parameter is set.
CLOSE timeout occurred.
CLOSE primitives should be

exchanged by devices to indicate
end of connection. A CLOSE
primitive should be responded with
a CLOSE primitive within the
specified CLOSE_TIMEOUT
value.
Device transmitting COMSAS

sequence should receive a
COMSAS sequence within the
specified time out period.
Device transmitting a COMSAS

sequence should receive COMSAS
sequence from the other end device.
A COMSAS sequence from the
other end device should be detected
within the specified
COMSAS_TIMEOUT value.
Invalid CRC detected.
Data integrity of the frames is

achieved through a 32-bit CRC field
in the SAS frame. The received
CRC should match the computed
CRC. This check fires if the
computed CRC and the received
CRC mismatch.
SAS_CREDIT_TIMEOUT_
VIOLATION_N
Port which accepts an OPEN

address frame should send at least
one RRDY primitive within the
time specified by the parameter
CREDIT_TIMEOUT.
A port that accepts an OPEN

address frame should send at least
one RRDY primitive within the
time specified in the parameter
CREDIT_TIMEOUT. This check
fires if credit timeout occurs.
SAS_DATA_FRAME_FROM_
INITIATOR_WITHOUT_
XFERRDY_FRAME_P
Initiator device should not send

DATA frame without receiving
XFERRDY frame.
An Initiator device should transmit

a DATA frame only after receiving
a XFER_RDY frame. This check
fires if DATA frames are detected
without corresponding
XFER_RDY.
DATA frame not receiving ACK

or NAK should be closed by
DONE (ACK/NAK TIMEOUT)
primitive.
If the transmitted DATA frame is

not acknowledged, then the device
should close the connection within a
DONE (ACK/NAK timeout)
primitive. The ACK/NAK timeout
is specified using the parameter
check fires if the connection is not
closed using DONE (ACK/NAK
timeout).
SAS_CLOSE_PRIMITIVE_
VIOLATION_N
SAS_CLOSE_TIMEOUT_
VIOLATION_P
SAS_CLOSE_TIMEOUT_
VIOLATION_N
SAS_COMSAS_TIMEOUT_
VIOLATION_P
SAS_COMSAS_TIMEOUT_
VIOLATION_N
SAS_CRC_VIOLATION_P
SAS_CRC_VIOLATION_N
SAS_CREDIT_TIMEOUT_
VIOLATION_P
SAS_DATA_FRAME_FROM_
INITIATOR_WITHOUT_
XFERRDY_FRAME_N
SAS_DATA_RECEIVED_
WITHOUT_ACK_NAK_
WITHOUT_DONE_ACK_NAK_P
SAS_DATA_RECEIVED_
WITHOUT_ACK_NAK_
WITHOUT_DONE_ACK_NAK_N
649

Monitor Checks

Check ID
Violation
Description
SAS_DONE_PRIMITIVE_IN_
SMP_OR_STP_P
DONE primitive should not be

detected in SMP or STP
transactions.
The DONE primitive should be

used only in SSP protocol
transactions. This check fires if a
DONE primitive is detected in a
SMP or STP transaction.
Done timeout occurred.
DONE primitives should be

exchanged by devices to indicate no
frames are pending to transmit. A
DONE primitive should be
responded with a DONE primitive
within the specified
DONE_TIMEOUT value.
EOF occurred without SOF.
SAS devices transmit EOF

primitive to indicate the end of the
frame being transmitted. An EOF
primitive should be transmitted only
after a SOF primitive. This check
fires if an EOF is detected without a
corresponding SOF.
Nonexpander device should not

transmit an AIP primitive.
An Expander device can perform

arbitration. When arbitration is in
progress, AIP primitives are
transmitted by the expander device.
An end device should not perform
arbitration. This check fires if AIP
is transmitted by a nonexpander
device (i.e., parameter
Nonexpander device should not

transmit an ERROR primitive.
ERROR is sent by an expander

device when it is forwarding dwords
from a SAS physical link to a SAS
physical link, if it receives an
invalid dword. This check fires if
ERROR is transmitted by a
nonexpander device (i.e., parameter
SAS_DEVICE_TYPE is set to
zero).
FIS transmitted without exchange

of XRDY and RRDY.
STP device should not transmit

before transmitting XRDY and
receiving RRDY frame.
SAS_DONE_PRIMITIVE_IN_
SMP_OR_STP_N
SAS_DONE_TIMEOUT_
VIOLATION_P
SAS_DONE_TIMEOUT_
VIOLATION_N
SAS_EOF_DETECTED_
WITHOUT_SOF_P
SAS_EOF_DETECTED_
WITHOUT_SOF_N
SAS_EXPANDER_AIP_
VIOLATION_P
SAS_EXPANDER_AIP_
VIOLATION_N
SAS_EXPANDER_ERROR_
VIOLATION_P
SAS_EXPANDER_ERROR_
VIOLATION_N
SAS_FIS_TRANSMITTED_
WITHOUT_EXCHANGING_
XRDY_AND_RRDY_P
SAS_FIS_TRANSMITTED_
WITHOUT_EXCHANGING_
XRDY_AND_RRDY_N
SAS_FIS_TYPE_VIOLATION_P
SAS_FIS_TYPE_VIOLATION_N
SAS_FOUR_BYTE_ALIGN_
VIOLATION_P
SAS_FOUR_BYTE_ALIGN_
VIOLATION_N
650
FIS type field in the REPORT

The FIS type field in a report PHY
PHY SATA response should have SATA response should have the
the value 34h.
value 34h. This check fires if the
FIS type field is not set to 34h.
All frames should contain integral Frames should contain integral
number of dwords.
numbers of dwords. This check fires
if the frame does not contain an
integral number of dwords.

Monitor Checks

Check ID
Violation
Description
SAS_FRAME_RECEIVED_
WITHOUT_CREDIT_P
Frame received without credit.
Credits are used for flow control.

All SSP frames should be
transmitted only if credit is
sufficient. This check fires if a
frame is transmitted without
sufficient credit.
Frames with CRC error should be

acknowledged with a NAK
primitive to indicate CRC error.
If the frame has a CRC error, then

the frame should be acknowledged
with a NAK (CRC ERROR)
primitive. This check fires if a NAK
(CRC ERROR) primitive is not
detected.
After detecting hard reset, no data

should be transmitted within the
time specified by the parameter
HARD_RESET_PERIOD.
After detecting HARD RESET, a

device should not transmit any valid
primitive within the time specified
by the parameter
HARD_RESET_PERIOD. The
device should wait for the specified
time period before transmitting any
primitive.
The device should not transmit

another INIT sequence while
waiting for cominit sequence.
A port waiting for COMINIT

should not send another INIT
sequence within the HOTPLUG
timeout period.
Device transmitting identification

address frame should receive the
same within the specified time
out period.
Identification address frames should

be exchanged by devices to indicate
the link reset sequence is
completed. A device that transmits
an identification address frame
should detect an identification
address frames within the
IDENT_FRAME_TIMEOUT
value.
Illegal primitive detected in a

SMP connection.
Only primitives specific to the SMP

connection should be detected
within an SMP connection. Any
other primitive detected is illegal.
This check fires if illegal primitives
are detected.
SAS_FRAME_RECEIVED_
WITHOUT_CREDIT_N
SAS_FRAME_WITH_CRC_ERR_
WITHOUT_NAK_P
SAS_FRAME_WITH_CRC_ERR_
WITHOUT_NAK_N
SAS_HARD_RESET_
VIOLATION_P
SAS_HARD_RESET_
VIOLATION_N
SAS_HOTPLUG_TIMEOUT_
VIOLATION_P
SAS_HOTPLUG_TIMEOUT_
VIOLATION_N
SAS_IDENT_FRAME_TIMEOUT_
VIOLATION_P
SAS_IDENT_FRAME_TIMEOUT_
VIOLATION_N
INSIDE_SMP_CONNECTION_P
INSIDE_SMP_CONNECTION_N
INSIDE_SSP_CONNECTION_P
INSIDE_SSP_CONNECTION_N
INSIDE_STP_CONNECTION_P
Illegal primitive detected in a SSP Only primitives specific to the SSP

connection.
within a SSP connection. Any other
primitive detected is illegal.
Illegal primitive detected in a
STP connection.
INSIDE_STP_CONNECTION_N
Only primitives specific to the STP

within a STP connection. Any other
primitive detected is illegal. This
check fires if illegal primitives are
detected.
651

Monitor Checks

Check ID
Violation
Description
SAS_INTERLOCKED_FRAME_
WITHOUT_ACK_NAK_P
Inter-locked frames should not be

transmitted again without getting
an ACK or NAK.
An Inter-locked frame should be

acknowledged with an ACK or
NAK before transmitting another
inter-locked frame. This check fires
when an inter-locked frame is
transmitted before the previous
inter-locked frame is
acknowledged.
SAS_INTERLOCKED_FRAME_
WITHOUT_ACK_NAK_N
SAS_NO_FRAME_AFTER_
DONE_PRIMITIVE_P
SAS_NO_FRAME_AFTER_
DONE_PRIMITIVE_N
Frames should not be transmitted DONE primitives are transmitted to

after DONE primitive is detected. close a connection. Within an SSP
connection, a SAS device should
not transmit frames after
transmission of a DONE primitive.
This check fires if frames are
detected after transmission of a
DONE primitive.
SAS_OPEN_ADDR_RESPOSNE_
TIMEOUT_VIOLATION_P
Response to open address request

should be received within 1 ms.
Device transmits an open address

request to open the connection. An
open address request should be
acknowledged within the specified
OPEN_ADDR_RES_TIMEOUT
value.
Phy identifier value should be

less than or equal to 80h.
The PHY identifier value should be

less than 80h. This check fires if the
PHY identifier field is not less than
or equal to 80h.
Reserved CLOSE primitives

Reserved CLOSE primitives should

not be detected. This check fires if a
reserved CLOSE primitive is
Reserved DONE primitives

detected.
Reserved DONE primitives should

reserved DONE primitive is
Reserved NAK primitive

detected.
Reserved NAK primitives should

not be detected.This check fires if a
reserved NAK primitive is detected
on the SAS interface.
Reserved RRDY primitives

Reserved RRDY primitives should

reserved RRDY primitive is on the
SAS interface.
Response data list length should

be set to zero if the DATAPRES
field is set to no data.
The response data list length should

be set to zero if the DATAPRES
field is set to no data. This check
fires if the response data list length
is set to a nonzero value.
SAS_OPEN_ADDR_RESPOSNE_
TIMEOUT_VIOLATION_N
SAS_PHY_IDENTIFIER_
VIOLATION_P
SAS_PHY_IDENTIFIER_
VIOLATION_N
SAS_RESERVED_CLOSE_
PRIMITIVE_P
SAS_RESERVED_CLOSE_
PRIMITIVE_N
SAS_RESERVED_DONE_
PRIMITIVE_P
SAS_RESERVED_DONE_
PRIMITIVE_N
SAS_RESERVED_NAK_
PRIMITIVE_P
SAS_RESERVED_NAK_
PRIMITIVE_N
SAS_RESERVED_RRDY_
PRIMITIVE_P
SAS_RESERVED_RRDY_
PRIMITIVE_N
SAS_RESPONSE_LENGTH_
VIOLATION_P
SAS_RESPONSE_LENGTH_
VIOLATION_N
652

Monitor Checks

Check ID
Violation
Description
SAS_RESPONSE_LIST_
LENGTH_VIOLATION_P
Response data list length should

be set to four if the DATAPRES
field is set to 1h.
The response data list length should

be set to four if the DATAPRES
field is set to 1h. This check fires if
this field is not set to four.
Retransmit bit should be set to

zero in COMMAND, TASK, or
XFERRDY frames.
Retransmit bit should be set to zero

for COMMAND, TASK, and
XFERRDY frames. This check fires
if the retransmit bit is not zero in a
COMMAND, TASK, or
XFERRDY frame.
R_OK/R_ERR primitive should

be transmitted only after
receiving WTRM primitive.
STP device should transmit a

R_OK/R_ERR primitive only after
receiving a WTRM primitive. The
check fires if a R_OK/R_ERR
primitive is transmitted without
receiving a WTRM primitive.
Receive D (rx_data_minus) is
not driven to a valid level.
Receive D always should be driven

to a valid level.
Receive D+ (rx_data_plus) is not

Receive D+ always should be

SAS_RESPONSE_LIST_
LENGTH_VIOLATION_N
SAS_RETRANSMIT_BIT_
VIOLATION_P
SAS_RETRANSMIT_BIT_
VIOLATION_N
SAS_ROK_OR_RERR_
DETECTED_BEFORE_WTRM_P
SAS_ROK_OR_RERR_
DETECTED_BEFORE_WTRM_N
SAS_RX_DN_UNKN_P
SAS_RX_DN_UNKN_N
SAS_RX_DP_UNKN_P
SAS_RX_DP_UNKN_N
SAS_SATA_HOLD_PRIMITIVE_
VIOLATION_P
SAS_SATA_HOLD_PRIMITIVE_
VIOLATION_N
SAS_SATA_HOLDA_PRIMITIVE_
VIOLATION_P
SATA HOLD primitive should be The SATA HOLD primitive is a

detected 2 times.
repeated primitive and should be
two consecutive SATA HOLD
primitives are not detected, and the
parameter is set.
SATA HOLDA primitive should
The SATA HOLDA primitive is a

two consecutive SATA HOLDA
parameter is set.
SATA RERR primitive should be

detected 2 times.
The SATA RERR primitive is a

two consecutive SATA RERR
parameter is set.
SATA RIP primitive should be

detected 2 times.
SATA RIP primitive is a repeated

primitive and should be detected 2
times. This check fires if two
consecutive SATA RIP primitives
are not detected, and the
parameter is set.
SAS_SATA_HOLDA_PRIMITIVE_
VIOLATION_N
SAS_SATA_RERR_PRIMITIVE_
VIOLATION_P
SAS_SATA_RERR_PRIMITIVE_
VIOLATION_N
SAS_SATA_RIP_PRIMITIVE_
VIOLATION_P
SAS_SATA_RIP_PRIMITIVE_
VIOLATION_N
653

Monitor Checks

Check ID
Violation
Description
SAS_SATA_ROK_PRIMITIVE_
VIOLATION_P
SATA ROK primitive should be

detected 2 times.
The SATA ROK primitive is a

two consecutive SATA ROK
parameter is set.
SAS_SATA_ROK_PRIMITIVE_
VIOLATION_N
SAS_SATA_RRDY_PRIMITIVE_
VIOLATION_P
SAS_SATA_RRDY_PRIMITIVE_
VIOLATION_N
SAS_SATA_SYNC_PRIMITIVE_
VIOLATION_P
SATA RRDY primitive should be The SATA RRDY primitive is a

detected 2 times.
two consecutive SATA RRDY
parameter is set.
SATA SYNC primitive should be
detected 2 times.
The SATA SYNC primitive is a

two consecutive SATA SYNC
parameter is set.
SATA WTRM primitive should

The SATA WTRM primitive is a

two consecutive SATA WTRM
parameter is set.
SATA XRDY primitive should

The SATA XRDY primitive is a

two consecutive SATA XRDY
parameter is set.
Sense data list length should be

set to a nonzero value, if the
DATAPRES field is set to 2h.
The sense data list length should be

set to a nonzero value if the
DATAPRES field is set to 2h. This
check fires if the sense data list
length is set to zero.
Sense data list length should be

set to zero if the DATAPRES
field is set to no data.
The sense data list length should be

set to zero if the DATAPRES field
is set to NO DATA. This check fires
if the sense data list length is set to a
nonzero value.
SAS_SATA_SYNC_PRIMITIVE_
VIOLATION_N
SAS_SATA_WTRM_PRIMITIVE_
VIOLATION_P
SAS_SATA_WTRM_PRIMITIVE_
VIOLATION_N
SAS_SATA_XRDY_PRIMITIVE_
VIOLATION_P
SAS_SATA_XRDY_PRIMITIVE_
VIOLATION_N
SAS_SENSE_DATA_LIST_
LENGTH_VIOLATION_P
SAS_SENSE_DATA_LIST_
LENGTH_VIOLATION_N
SAS_SENSE_LENGTH_
VIOLATION_P
SAS_SENSE_LENGTH_
VIOLATION_N
SAS_SMP_REQ_FRAME_TYPE_
VIOLATION_P
SAS_SMP_REQ_FRAME_TYPE_
VIOLATION_N
654
The Information Unit Type field In a SMP request, the information

in the SMP request should be 40h. unit type should be set to 40h. This
check fires if the information unit
type is not 40h, and the

Monitor Checks

Check ID
Violation
Description
SAS_SMP_REQ_FUNCTION_
VIOLATION_P
Illegal function field.
The function field in a SMP request

should be one of the following:
REPORT GENERAL (00h),
REPORT SATA CAPABILITIES
(01h), REPORT
MANUFACTURER
INFORMATION (02h), REPORT
ROUTE INFORMATION (14h),
DISCOVER (10h), REPORT PHY
ERROR LOG (11h), REPORT
PHY SATA (12h), REPORT PHY
MARGIN SETTINGS (13h),
CONFIGURE ROUTE
INFORMATION (80h), PHY
CONTROL (90h), or PHY
MARGIN CONTROL (91h). This
check fires if the function field is
not set to one of the above values,
and the
Illegal phy operation field.
The PHY operation field in a SMP

request should be one of the
following: NOP (00h), LINK
RESET (01h), HARD RESET
(02h), ENABLE (03h), DISBALE
(04h), NEA LOOPBACK (05h), or
CLEAR ERROR LOG (06h). This
check fires if the PHY operation
field is not set to any of the above
values, and the
Program maximum phy rate field

in the SMP request should have
the values 0h, 8h, or 9h.
The programmed maximum

physical link rate field should be 0h,
8h, or 9h. This check fires if the
programmed maximum physical
link rate field does not contain one
of these values, and the
Program minimum phy rate field

in the SMP request should have
the values 0h, 8h, or 9h.
The programmed minimum

physical link rate field should be 0h,
8h, or 9h. This check fires if the
programmed minimum physical
link rate field does not contain one
of these values, and the
Function field in the SMP request

and response should be equal.
The function value set in a SMP

request should be the same as the
function value set in the SMP
response. This check fires if the
function values of request and
response are not same.
SAS_SMP_REQ_FUNCTION_
VIOLATION_N
SAS_SMP_REQ_PHY_
OPERATION_VIOLATION_P
SAS_SMP_REQ_PHY_
OPERATION_VIOLATION_N
SAS_SMP_REQ_PROG_MAX_
PHY_RATE_VIOLATION_P
SAS_SMP_REQ_PROG_MAX_
PHY_RATE_VIOLATION_N
SAS_SMP_REQ_PROG_MIN_
PHY_RATE_VIOLATION_P
SAS_SMP_REQ_PROG_MIN_
PHY_RATE_VIOLATION_N
SAS_SMP_REQ_RES_FN_
VIOLATION_P
SAS_SMP_REQ_RES_FN_
VIOLATION_N
655

Monitor Checks

Check ID
Violation
Description
SAS_SMP_RES_ATTACHED_
DEV_TYPE_VIOLATION_P
Attached device type field in

SMP response should have the
values of 0h,1h, 2h, or 3h.
Attached device type field in SMP

response frame should only have
values of 0h,1h, 2h, or 3h. This
check fires for other values, and the
Current physical link rate field in

the SMP DISCOVER response
should have the values 0h, 1h, 2h,
3h, 8h, or 9h.
The current physical link rate field

in a SMP response should be one of
the following: UNKNOWN
PHYSICAL LINK RATE (0h),
PHY IS DISABLED (1h), PHY IS
ENABLED (2h), DETECTS SATA
DEVICE (3h), 1.5 Gbps (8h), or 3.0
Gbps (9h). This check fires if the
current physical link rate field does
not contain any of these values, and
the RESERVED_FIELD_CHECK_
The information unit type field in

the SMP response should be 41h.
In a SMP response, the information

unit type should be set to 41h. This
check fires if the information unit
type is not 41h, and the
Illegal Function Result field in

the SMP response.
The function result field in a SMP

response should be set to 00h or
01h. This check fires if none of the
specified values are set in the
function result field, and the
Illegal function field.
The function field in a SMP

response should be one of the
following: REPORT GENERAL
(00h), REPORT SATA
CAPABILITIES (01h), REPORT
MANUFACTURER
INFORMATION (02h), REPORT
ROUTE INFORMATION (14h),
DISCOVER (10h), REPORT PHY
ERROR LOG (11h), REPORT
PHY SATA (12h), REPORT PHY
MARGIN SETTINGS (13h),
CONFIGURE ROUTE
INFORMATION (80h), PHY
CONTROL (90h). or PHY
MARGIN CONTROL (91h). This
check fires if the function field does
not contain one of the above values,
and the
SAS_SMP_RES_ATTACHED_
DEV_TYPE_VIOLATION_N
SAS_SMP_RES_CUR_PHY_
RATE_VIOLATION_P
SAS_SMP_RES_CUR_PHY_
RATE_VIOLATION_N
SAS_SMP_RES_FRAME_TYPE_
VIOLATION_P
SAS_SMP_RES_FRAME_TYPE_
VIOLATION_P
SAS_SMP_RES_FUNCTION_
RESULT_VIOLATION_P
RESULT_VIOLATION_N
VIOLATION_P
VIOLATION_N
656

Monitor Checks

Check ID
Violation
Description
SAS_SMP_RES_ROUTE_
ATTRIBUTE_VIOLATION_P
Routing attribute filed in the SMP

DISCOVER response should
have the values 0h, 1h, or 2h.
The routing attribute field in a SMP

DISCOVER response should be one
of the following: DIRECT
ROUTING (0h), SUBTRACTIVE
ROUTING (1h), or TABLE
ROUTING (2h). This check fires if
the routing attribute field does not
contain one of the above routing
attributes, and the
SOAF primitive is detected

without an EOAF.
The address frame should start with

a SOAF primitive and end with a
EOAF primitive. There should not
be another SOAF primitive before
an EOAF primitive.
SOF occurred without EOF.
SOF primitive should always be

followed by a corresponding EOF
primitive. This check fires if two
SOFs are detected without an
intermediate EOF.
Task Attribute field in the

command frame should have the
values 0h, 1h, 2h, or 4h.
The task attribute field in a SSP

command frame should be one of
the following: SIMPLE (0h),
HEAD OF QUEUE (1h),
ORDERED (2h), or ACA(4h). This
check fires if the task attribute field
contains none of the above values,
and the
DATAPRES field in the response

frame should have the values 0h,
1h, or 2h.
The DATAPRES field in a SSP

response frame should be one of the
following: NO DATA (0h),
RESPONSE DATA (1h), or SENSE
DATA (2h). This check fires if the
DATAPRES field does not contain
one of the above mentioned values,
and the
Illegal SSP frame type detected.
Frame type field in the SSP frame

should be one of the following:
DATA (01h), XFERRDY (05h),
COMMAND (06h), RESPONSE
(07h), or TASK (16h). This check
fires if the frame type field does not
contain one of these values, and the
SAS_SMP_RES_ROUTE_
ATTRIBUTE_VIOLATION_N
SAS_SOAF_WITHOUT_EOAF_P
SAS_SOAF_WITHOUT_EOAF_N
SAS_SOF_DETECTED_
WITHOUT_EOF_P
SAS_SOF_DETECTED_
WITHOUT_SOF_N
SAS_SSP_COM_TASK_
ATTRIBUTE_VIOLATION_P
SAS_SSP_COM_TASK_
ATTRIBUTE_VIOLATION_N
SAS_SSP_DATA_PRES_
VIOLATION_P
SAS_SSP_DATA_PRES_
VIOLATION_N
SAS_SSP_INVALID_FRAME_
TYPE_P
SAS_SSP_INVALID_FRAME_
TYPE_N
657

Monitor Checks

Check ID
Violation
Description
SAS_SSP_MAX_FRAME_SIZE_
VIOLATION_P
Observed frame size for the

current frame type is greater than
the expected maximum frame
size.
The maximum size of DATA,

XFERRDY, COMMAND,
RESPONSE and TASK frames are
1052 bytes, 40 bytes, 312 bytes,
1052 bytes and 56 bytes
respectively. This check fires if any
of these frames violate the
corresponding maximum size
requirement.
Observed frame size for the

current frame type is less than the
expected minimum frame size.
The minimum size of DATA,

XFERRDY, COMMAND,
RESPONSE, and TASK frames are
32 bytes, 40 bytes, 56 bytes, 52
bytes, and 56 bytes, respectively.
This check fires if any of these
frames violate the corresponding
minimum size requirement.
Response code field in

RESPONSE frame should have
the values 8'h0, 8'h02, 8'h04,
8'h05, 8'h08, or 8'h09.
Response code field in the

RESPONSE frame should have any
of the legal encodings (8h0, 8h02,
8h04, 8h05, 8h08, or 8h09) and
not reserved encodings. This check
fires if reserved values are detected.
Illegal status field.
STATUS field in a SSP response

frame should be one of the
following: GOOD (00h), CHECK
CONDITION (02h), CONDITION
MET (04h), BUSY (08h),
INTERMEDIATE (10h),
INTERMEDIATE CONDITION
MET (14h), RESERVED
CONFLICT (18h), OBSOLETE
(22h), TASK SET FULL (28h),
ACA ACTIVE (30h), or TASK
ABORTED (40h). This check fires
if the STATUS field does not
contain any of these values, and the
Illegal task management function

field.
The task management function field

in a SSP task frame should be one
of the following: ABORT TASK
(01h), ABORT TASK SET (02h),
CLEAR TASK SET (04h),
LOGICAL UNIT RESET (08h),
CLEAR ACA (40h), or QUERY
TASK (80h). This check fires if the
task management function field
does not contain one of the above
values, and the
SAS_SSP_MAX_FRAME_SIZE_
VIOLATION_N
SAS_SSP_MIN_FRAME_SIZE_
VIOLATION_P
SAS_SSP_MIN_FRAME_SIZE_
VIOLATION_N
SAS_SSP_RESPONSE_CODE_
VIOLATION_P
SAS_SSP_RESPONSE_CODE_
VIOLATION_N
SAS_SSP_RESPONSE_STATUS_
VIOLATION_P
SAS_SSP_RESPONSE_STATUS_
VIOLATION_N
SAS_SSP_TASK_
MANAGEMENT_FN_
VIOLATION_P
SAS_SSP_TASK_
MANAGEMENT_FN_
VIOLATION_N
658

Monitor Checks

Check ID
Violation
Description
SAS_STP_ALIGN_DWORD_
COUNT_VIOLATION_P
Two consecutive ALIGN

primitives should be detected
once every 256 dwords in a STP
initiator port device.
No more than 256 dwords shall be

sent without two consecutive
ALIGNs in the STP initiator port.
This check fires if more than 256
dwords are detected without two
consecutive ALIGNs.
HOLD should be acknowledged

with HOLDA primitive within 20
dwords.
In a STP transaction, the port that

transmits a HOLD primitive should
receive a HOLDA primitive within
20 dwords. This check fires if the
HOLDA primitive is not detected
within 20 dwords.
SSP initiator port should set the

target port transfer tag field to
16'hFFFF for all the SSP frames
except DATA frame.
An Initiator device should set the

Target Port Transfer Tag field in a
SSP frame to 16'hFFFF for all
frames except for DATA frames.
Transmit D (tx_data_minus) is
Transmit D always should be

SAS_STP_ALIGN_DWORD_
COUNT_VIOLATION_N
SAS_STP_HOLD_HOLDA_
DWORD_VIOLATION_P
SAS_STP_HOLD_HOLDA_
DWORD_VIOLATION_N
SAS_TARGET_PORT_XFER_
TAG_VIOLATION_P
SAS_TARGET_PORT_XFER_
TAG_VIOLATION_N
SAS_TX_DN_UNKN_P
SAS_TX_DN_UNKN_N
SAS_TX_DP_UNKN_P
Transmit D+ (tx_data_plus) is not Transmit D+ always should be

SAS_TX_DP_UNKN_N
SAS_XFER_RDY_RECEIVED_
WITHOUT_ACK_NAK_
WITHOUT_DONE_ACK_NAK_P
XFER_RDY frame not receiving

ACK or NAK should be closed
by DONE(ACK/NAK
TIMEOUT) primitive.
SAS_XFER_RDY_RECEIVED_
WITHOUT_ACK_NAK_
WITHOUT_DONE_ACK_NAK_N
XFER_RDY frame is sent by an

SSP target port to request write data
from an initiator port. If the
transmitted XFER_RDY frame is
not acknowledged, then the device
should close the connection in a
DONE (ACK/NAK timeout)
primitive. The ACK/NAK timeout
is specified using the parameter
check fires if the connection is not
closed using DONE (ACK/NAK
timeout).
SMP, SSP and STP Checks

Table 15-7, Table 15-8, and Table 15-9 show the SAS transport layer checks that are applicable
to SMP, SSP, and STP transactions.
Table 15-7. SMP Transport Layer Checks
SMP Transaction
SAS_SMP_REQ_FRAME_TYPE_VIOLATION
SAS_SMP_REQ_FUNCTION_VIOLATION
SAS_SMP_REQ_PHY_OPERATION_VIOLATION
659

Monitor Checks
Table 15-7. SMP Transport Layer Checks (cont.)

SMP Transaction
SAS_SMP_RES_FRAME_TYPE_VIOLATION
SAS_SMP_RES_FUNCTION_VIOLATION
SAS_SMP_RES_FUNCTION_RESULT_VIOLATION
SAS_SMP_ROUTING_ATTRIBUTE_VIOLATION
SAS_SMP_RES_CUR_PHY_RATE_VIOLATION
SAS_SMP_REQ_PROG_MIN_PHY_RATE_VIOLATION
SAS_SMP_REQ_PROG_MAX_PHY_RATE_VIOLATION
SAS_SMP_RES_REPORT_ROUTE_FN_RESULT_VIOLATION
SAS_SMP_RES_DISCOVER_FN_RESULT_VIOLATION
SAS_SMP_RES_REP_PHY_ERR_LOG_FN_RESULT_VIOLATION
SAS_SMP_RES_REP_PHY_SATA_FN_RESULT_VIOLATION
SAS_SMP_RES_REP_PHY_MAR_FN_RESULT_VIOLATION
SAS_SMP_RES_REP_CON_FN_RESULT_VIOLATION
SAS_SMP_RES_REP_PHY_MAR_CON_FN_RESULT_VIOLATION
SAS_SMP_REQ_RES_FN_VIOLATION
SAS_PHY_IDENTIFIER_VIOLATION
SAS_FIS_TYPE_VIOLATION
SAS_ILLEGAL_PRIMITIVE_INSIDE_SMP_CONNECTION
SAS_SMP_RES_ATTACHED_DEV_TYPE_VIOLATION
Table 15-8. SSP Transport Layer Checks

SSP Transaction
SAS_SSP_COM_TASK_ATRIBUTE_VIOLATION
SAS_SSP_TASK_MANAGEMENT_FN_VIOLATION
SAS_SSP_DATA_PRES_VIOLATION
SAS_SSP_STATUS_VIOLATION
SAS_FRAME_WITH_CRC_ERR_WITHOUT_NAK
SAS_ACK_NAK_TIMEOUT_VIOLATION
SAS_CREDIT_TIMEOUT_VIOLATION
SAS_SSP_MIN_FRAME_SIZE_VIOLATION
SAS_SSP_MAX_FRAME_SIZE_VIOLATION
660

Monitor Checks
Table 15-8. SSP Transport Layer Checks (cont.)

SSP Transaction
SAS_SENSE_LENGTH_VIOLATION
SAS_RESPONSE_LENGTH_VIOLATION
SAS_RESPONSE_LIST_LENGTH_VIOLATION
SAS_SENSE_DATA_LIST_LENGTH_VIOLATION
SAS_NO_FRAME_AFTER_DONE_PRIMITIVE
SAS_BREAK_TIMEOUT_P
SAS_INTERLOCKED_FRAME_WITHOUT_ACK_NAK
SAS_FRAME_RECEIVED_WITHOUT_CREDIT
SAS_XFRRDY_RECEIVED_WITHOUT_ACK_NAK_WITHOUT_DONE_ACK_NAK
SAS_DATA_RECEIVED_WITHOUT_ACK_NAK_WITHOUT_DONE_ACK_NAK
SAS_ACK_NAK_RECEIVED_WITHOUT_FRAME_TRANSMISSION
SAS_DATA_FRAME_FROM_INITIATOR_WITHOUT_XFERRDY_FRAME
SAS_TARGET_PORT_XFER_TAG_VIOLATION
SAS_ILLEGAL_PRIMITIVE_INSIDE_SSP_CONNECTION
SAS_SSP_RESPONSE_CODE_VIOLATION
SAS_RESERVED_DONE_PRIMITIVE
SAS_RESERVED_NAK_PRIMITIVE
SAS_RESERVED_RRDY_PRIMITIVE
SAS_RESERVED_CLOSE_PRIMITIVE
SAS_RETRANSMIT_BIT_VIOLATION
SAS_DONE_TIMEOUT_P
Table 15-9. STP Transport Layer Checks

STP Transaction
SAS_SATA_XRDY_PRIMITIVE_VIOLATION
SAS_SATA_WTRM_PRIMITIVE_VIOLATION
SAS_SATA_SYNC_PRIMITIVE_VIOLATION
SAS_SATA_RRDY_PRIMITIVE_VIOLATION
SAS_SATA_RIP_PRIMITIVE_VIOLATION
SAS_SATA_ROK_PRIMITIVE_VIOLATION
SAS_SATA_RERR_PRIMITIVE_VIOLATION
661

Table 15-9. STP Transport Layer Checks (cont.)

STP Transaction
SAS_SATA_HOLD_PRIMITIVE_VIOLATION
SAS_SATA_HOLDA_PRIMITIVE_VIOLATION
SAS_STP_HOLD_HOLDA_DWORD_VIOLATION
SAS_STP_ALIGN_DWORD_COUNT_VIOLATION
SAS_CLOSE_AFFLIATION_PRIM_VIOLATION
SAS_ROK_OR_RERR_DETECTED_BEFORE_WTRM
SAS_FIS_TRANSMITTED_WITHOUT_EXCHANGING_XRDY_AND_RRDY
SAS_ILLEGAL_PRIMITIVE_INSIDE_STP_CONNECTION

Table 15-10 shows the corner cases maintained by the SAS monitor. These corner cases are
collected for the transmit and the receive interfaces.
Table 15-10. SAS Monitor Corner Cases
Corner Cases
Description
PHY reset sequences
Number of PHY reset sequences.
Link reset sequences
Number of Link reset sequences.
Transactions completed
Number of transactions completed without a CRC error.
ACK received
Number of Acknowledgements received.
NAK received with CRC error
Number of Negative Acknowledgements with CRC error.
Connection requests accepted
Number of connection requests accepted.
Connection requests rejected with NO

DESTINATION
Number of connection requests rejected with NO

DESTINATION.
Connection requests rejected with BAD

DESTINATION
Number of connection requests rejected with BAD

DESTINATION.
Connection requests rejected with WRONG

DESTINATION
Number of connection requests rejected with WRONG

DESTINATION.
Connection requests rejected with LINK

RATE NOT SUPPORTED
Number of connection requests rejected with LINK RATE NOT

SUPPORTED.
Connection requests rejected with RETRY
Number of connection requests rejected with RETRY.
Connection requests rejected with

PROTOCOL NOT SUPPORTED
Number of connection requests rejected with PROTOCOL NOT

SUPPORTED.

PATHWAY BLOCKED
Number of connection requests rejected with PATHWAY

BLOCKED.
662

Monitor Statistics
Table 15-10. SAS Monitor Corner Cases (cont.)

Corner Cases
Description

RESOURCE BUSY
Number of connection requests rejected with RESOURCE

BUSY.
SSP transactions
Number of SSP transactions.
SMP transactions
Number of SMP transactions.
STP transactions
Number of STP transactions.
Time outs
Number of timeouts.
ACK/NAK timeouts
Number of ACK/NAK timeouts detected.
Credit timeouts
Number of Credit timeouts detected.
Connection requests waiting on partial
Number of times a connection request was waiting on partial.
Connection requests waiting on device
Number of times a connection request was waiting on device.
Connection requests waiting on connection
Number of times connection request was waiting on connection.
Monitor Statistics
Table 15-11 shows the statistics maintained by the SAS monitor. These statistics are collected
for the transmit and the receive interfaces.
Table 15-11. SAS Monitor Statistics
Statistics
Description
Transactions
Number of transactions.
Frames with CRC error
Number of frames with a CRC error.
Disparity errors
Number of disparity errors detected.
Data frames
Number of data frames.
Command frames
Number of command frames.
Xferrdy frames
Number of Xferrdy frames.
Response frames
Number of Response frames.
Task frames
Number of task frames.
Open address frames
Number of open address frames.
Identification address frames
Number of identification address frames.
Align burst with non-ALIGN0 primitive
Number of align bursts with non-ALIGN0 primitive.
Times outs
Number of timeouts.
663

Monitor FAQ
Monitor FAQ
Following are answers to frequently asked questions (FAQ) about the QVL SAS monitor.
What types of devices are tracked by the SAS monitor?
SAS monitor can track SAS end devices and SAS expander devices. Use the
SAS_DEVICE_TYPE parameter to configure the device tracked. The SAS monitor does
not track SATA devices.
How is the SAS monitor instantiated in a multi-PHY core?
Each SAS monitor tracks only one PHY. Multiple SAS monitor instances are required to
track multiple PHYs of a device (see Figure 15-6).
Figure 15-6. Examples of Single- and Multi-PHY Devices
1-PHY Device
SAS Device B
SAS Device A
SAS Monitor
PHY
PHY
3-PHY Device
SAS Device A
SAS Device B
SAS Monitor
PHY
PHY
SAS Monitor
PHY
PHY
SAS Monitor
PHY
664
PHY

Monitor FAQ
How is the SAS monitor instantiated on a parallel interface?

The SAS monitor tracks serial or parallel interfaces. To track a 10-bit or 20-bit parallel
interface, do the following:
10-bit parallel interface

Configure the monitor for a parallel interface by setting the INTERFACE_TYPE
parameter to 1. Leave tx_data_minus and rx_data_minus unconnected. Connect the
tx_data_plus and rx_data_plus ports with 10b encoded values from the transmit
and receive interfaces, respectively. The bit order of the 10b encoded parallel data
should be as follows: {j,h,g,f,i,e,d,c,b,a}. Bit names are taken from the standard 8b/10b
encoding/decoding schemes.
20-bit parallel interface

parameter to 1. Leave tx_data_minus and rx_data_minus unconnected. Connect the
tx_data_plus and rx_data_plus ports with 10b encoded values from the transmit
and receive interfaces, respectively. The bit order of the 10b encoded parallel data
should be as follows: {j,h,g,f,i,e,d,c,b,a}. Bit names are taken from the standard 8b/10b
Configure the monitor to track a 20-bit interface by setting the INTERFACE_TYPE
parameter to 2 and the DOUBLE_DATA_RATE parameter to 0 (see the notes following
Table 15-3 on page 633). In the SAS interface, 10-bit encoded data is transmitted in the
following order (first to last): a b c d e i f g h j. The SAS monitor assumes in a 20-bit
chunk, that the first K-code sits in bits [19:10] of the 20 bit data. Use the following bit
order (for both TX and RX interfaces) as shown in Table 15-12:
Table 15-12. Bit Order for TX and RX Interfaces
bit
19
18
17
16
15
14
13
12
11
10
encoding
-------------------------K28.5--------------------------
An SAS interface does not have a clock signal, but the SAS monitor has a clock
input. How are an SAS monitors clock signals connected?
If recovered clocks are available from the design, then connect the recovered clocks to
the SAS monitor clock inputs. The SAS monitor uses these clocks to sample data. If
recovered clocks are not available from the design, use the clock recovery module (see
Clock Recovery Module on page 640) to recover the clocks and connect the recovered
clocks to the monitor.
For example, the following instantiations recover the Tx and Rx clocks:
qvl_clock_recovery TX_CLOCK_RECOVERY (
665

Monitor FAQ
.pos_data
.neg_data
.clock
(tx_data_plus),
(tx_data_minus),
(tx_recovered_clk)
);
qvl_clock_recovery RX_CLOCK_RECOVERY (
.pos_data
(rx_data_plus),
.neg_data
(rx_data_minus),
.clock
(rx_recovered_clk)
);
The following instantiations connect the recovered clocks:

qvl_sas_monitor U0 (
.reset
(reset),
.areset
(areset),
// -------------------- Tx Interface Signals -------------------.tx_clk
(tx_recovered_clk),
.tx_data_plus
(tx_data_plus),
.tx_data_minus
(tx_data_minus),
.tx_idle_signal
(),
// -------------------- Rx Interface Signals -------------------.rx_clk
(rx_recovered_clk),
.rx_data_plus
(rx_data_plus),
.rx_data_minus
(rx_data_minus),
.rx_idle_signal
(),
// ---------------- Configuration-specific Signals -------------.bypass_reset_sequence (1'b0),
.start_speed_negotiation (1'b0)
);
qvl_sas_dynamic_timer_values_monitor U0 (
.reset
(reset),
.areset
(areset),
// -------------------- Tx Interface Signals -------------------.tx_clk
(tx_recovered_clk),
.tx_data_plus
(tx_data_plus),
.tx_data_minus
(tx_data_minus),
.tx_idle_signal
(),
// -------------------- Rx Interface Signals -------------------.rx_clk
(rx_recovered_clk),
.rx_data_plus
(rx_data_plus),
.rx_data_minus
(rx_data_minus),
.rx_idle_signal
(),
// ---------------- Configuration-specific Signals -------------.bypass_reset_sequence
(1'b0),
(1'b0)
// ---------------- Timer Values -------------------------------.tx_cominit_idle_time
(tx_cominit_idle_time),
(tx_comsas_idle_time),
.rx_cominit_idle_time_min (rx_cominit_idle_time_min),
.rx_cominit_idle_time_max (rx_cominit_idle_time_max),
(rx_comsas_idle_time_min),
(rx_comsas_idle_time_max),
(tx_cominit_neg_time),
.tx_comsas_neg_time
(tx_comsas_neg_time),
(rx_cominit_neg_time),
666

Monitor FAQ
.rx_comsas_neg_time
.rate_change_delay
.spd_neg_lock_time
.hotplug_timeout
.comsas_timeout
.hard_reset_timeout
.break_timeout
.credit_timeout
.ack_nak_timeout
.close_timeout
.done_timeout
(rx_comsas_neg_time),
(hotplug_timeout),
(comsas_timeout),
(break_timeout),
(credit_timeout),
(ack_nak_timeout),
(close_timeout),
(done_timeout)
);
How can the monitor skip reset sequences?

The SAS reset sequence includes an initialization sequence and a speed negotiation
sequence. SAS monitor can track both sequences. To skip tracking reset sequences,
connect the bypass_reset_sequence port to 1'b1.
What is the start_speed_negotiation port? How is it connected?
The SAS monitor tracks the speed negotiation sequence. The beginning of every speed
negotiation window is marked by an electrical idle period called the RCD (Rate Change
Delay). Asserting start_speed_negotiation indicates the start of the RCD period
for the speed negotiation window. The SAS monitor requires a rising edge to indicate
the start of a RATE CHANGE DELAY period (i.e., the start of a speed negotiation
sequence). A pulse driven for one clock period is sufficient; but driving the port for
longer than one clock period is OK.
This input is required only if bypass_reset_sequence is set to 1'b0 and the interface
is parallel. This port is not needed if bypass_reset_sequence is set to 1'b1 or the
interface is in the serial mode.
How can transport layer checks be disabled?
Set the TRANSPORT_LAYER_CHECKS_ENABLE parameter to 0.
What are tx_idle_signal and rx_idle_signal? How do they differ from the
ELECTRICAL_IDLE_TIME_BIT_PATTERN parameter?
An electrical idle period on the SAS serial interface is indicated by driving both
tx_data_plus and tx_data_minus lines to the same value. In a parallel interface, the
10b encoded value during electrical idle is implementation-specific. The
tx_idle_signal and rx_idle_signal inputs are provided to determine the electrical
idle condition on the bus. If these signals are not provided by the design, then the
ELECTRICAL_IDLE_TIME_BIT_PATTERN parameter specifies the bit pattern on
tx_data_plus or rx_data_plus during electrical idle. When this pattern is detected,
667

Monitor FAQ
an electrical idle condition is assumed. By default, a bit pattern of 10'h3FF on the 10b
encoded data reflects an electrical idle condition on the bus.
Applicable only in parallel mode. In serial mode, all of these inputs are not applicable.
What value should the ELECTRICAL_IDLE_TIME_BIT_PATTERN parameter be in
serial mode?
In serial mode, the value of the ELECTRICAL_IDLE_TIME_BIT_PATTERN parameter is
redundant. In this mode, the SAS monitor looks for equal data_plus and
data_minus signals to infer electrical idle periods.
The designs clocks are active on both edges. How is the SAS monitor connected?
Set the DOUBLE_DATA_RATE parameter to 1. Monitor cannot be configured for
DOUBLE_DATA_RATE mode for a 20 bit interface.
How does the monitor track the speed negotiation sequence?
SAS monitor configures the speed negotiation timers (RCDT, SNLT, and SNTT)
through the following parameters:
o
RATE_CHANGE_DELAY
SPEED_NEGOTIATION_LOCK_TIME
SPEED_NEGOTIATION_TRANSMIT_TIME
The values passed to these parameters correspond to OOBIs (One UI of G1). Therefore,
the length of each speed negotiation window is RCDT + SNTT. Parameter
TX_MAX_SUPPORTED_RATE configures the length of the entire speed negotiation
sequence by configuring the total number of speed negotiation windows in the speed
negotiation sequence.
During each window of the speed negotiation sequence, the RCD timer will expire first,
and start the SNLT and SNTT timers. If ALIGN0 to ALIGN1 transition is detected by
the monitor before the expiry of the SNLT timer, then the monitor assumes the device
supports this particular rate and waits for the expiry of the SNTT timer.
If ALIGN0 to ALIGN1 transition is not detected within the expiry of the SNLT timer in
a speed negotiation window, then that window is considered as failed. The monitor
assumes that the speed corresponding to this window is not supported.
What should the clock frequency be during G1, G2 and G3 windows of the speed
negotiation sequence?
The frequency of the clock should match the data rate of the speed negotiation window.
For example, if the speed negotiation sequence is in a G2 window, then the clock
frequency should correspond to 3 Gbps.
How does the SAS monitor detect dword synchronization?
668

Monitor FAQ
Detection of ALIGN0 to ALIGN1 transitions within SNLT period indicates dword

synchronization.
How does the SAS monitor configure the receive side COMINIT/COMSAS sequence idle
time ranges?
The monitor configures these idle time ranges through the following parameters:
o
RX_COMINIT_IDLE_TIME_MIN and RX_COMINIT_IDE_TIME_MAX
RX_COMSAS_IDLE_TIME_MIN and RX_COMSAS_IDLE_TIME_MAX
If not specified, then the monitor takes the default range specified in the SAS
specification.
669

Monitor FAQ
670
Chapter 16
SERIAL ATA (SATA)
Introduction
Serial ATA is a high-speed serial link replacement for the parallel ATA attachment of mass
storage devices. The serial link employed is a high-speed differential layer that utilizes Gigabit
technology and 8b/10b encoding. Serial ATA II specification defines enhancements to the
Serial ATA 1.0a specification that provide additional capabilities while retaining Serial ATA
1.0a compatibility and desktop cost structure.
The QVL SATA monitor is designed for checking the Serial ATA and Serial ATA II interfaces.
This SATA monitor is modeled from the requirements provided in the following documents:
Serial ATA Revision 2.5, 27-October-2005
Serial ATA: High Speed Serialized AT Attachment Revision 1.0a, 7-January-2003.
Serial ATA II: Extensions to Serial ATA 1.0a Revision 1.2, 27-August-2004
SATA PHY Interface Specification (SAPIS) Draft Rev 0.90, February 8, 2002
Supported Features
Implementations
Host ports
Device ports
Port multiplier ports
Port selector ports
Interfaces
Serial Interface
Parallel 10b interface (10b/20b/40b parallel data)
SAPIS interface
671
SERIAL ATA (SATA)

Phy Layer
Phy reset sequence
Speed negotiation
Power management
Gen1 and Gen2 speeds
Link Layer
Data integrity (32-bit CRC)
Framing
All types of SATA primitives
8b/10b encoding for data
Link flow control
Transport / Command Layer
All types of SATA FISe.
FIS sequencing
PIO, DMA, Legacy queued DMA and FPDMA modes of transfer
Auto-activate DMA
Asynchronous notification
Native Command queuing

The QVL SATA monitor can be instantiated on the host or device. It can also be instantiated on
the host side of the port multiplier, device side of the port multiplier, host side of the port
selector or device side of the port selector. The monitor can be instantiated on either serial
interface, or on parallel 10b interface, or on a SAPIS interface. If the implementation under test
does not include a serializer/deserializer block, then the SATA monitor must be instantiated in
parallel mode. If the implementation under test includes a serializer/deserializer block, then the
monitor must be instantiated in serial mode. In either mode, input to the monitor should be 10b
encoded values. A typical SATA setup is shown in Figure 16-1.
672
SERIAL ATA (SATA)

Figure 16-1. SATA implementation

Phy Layer
SAPIS
SAPIS
MW
SATA
SAPIS
MW
SATA
MW
SATA
MW
Host Side
SATA
SATA
SATA
MW
SATA
MW
Host B
SATA
SATA
Host
Host A
SATA
MW
SATA
MW
SAPIS
MW
Device Side
Port Multiplier
SATA
MW
SAPIS
SAPIS
MW
Link Layer
Link Layer
Phy Layer
SATA
Port Selector
SATA
SATA
MW
SATA
SATA
MW
Device A
SATA
MW
Device B
SATA
MW
Device C
SATA
MW
Device
SATA
MW
Connect the SATA monitor as specified in the pin-out Table 16-1 and Table 16-2 and illustrated
in Figure 16-2.
673
SERIAL ATA (SATA)

RECEIVE
TRANSMIT
RECEIVE
TRANSMIT
Figure 16-2. SATA Monitor Pin Diagram

areset
reset
tx_clk
tx_data_plus
tx_data_minus
rx_clk
rx_data_plus
rx_data_minus
SERIAL ATA
(Serial/Parallel10b interface)
Monitor
scrambling_off
bypass_power_on_seq
SERIAL ATA
(SAPIS Interface)
Monitor
scrambling_off
bypass_power_on_seq
areset
reset
tx_data[n:0]
tx_enable
tbc
rx_data[n:0]
rx_data_valid
rbc
rx_locked
k28.5_detect
comwake_detect
comreset_detect
cominit_detect
partial
slumber
Table 16-1. SATA - Serial and parallel 10B Interface Monitor Pins
674
Port
Description
areset
Asynchronous reset signal, active high (not part of standard I/F signals).
bypass_power_on_seq
When this signal is active high the monitor does not track power on
sequence. See note 1 on page 676.
reset
Synchronous reset signal, active high (not part of standard I/F signals).
rx_clk
Receive clock. Monitor uses this clock to sample rx_data_plus and

rx_data_minus.
RX_data_plus
RX_data_minus
Input to the Phy. The differential data input to the serial interface when
the INTERFACE_TYPE parameter is set to 0. Connect parallel 10b
outputs from the serializer to this port when the INTERFACE_TYPE
scrambling_off
When this signal is active high, the incoming data will not be
descrambled.
SERIAL ATA (SATA)

Table 16-1. SATA - Serial and parallel 10B Interface Monitor Pins (cont.)
Port
Description
tx_clk
Transmit clock. Monitor uses this clock to sample tx_data_plus and

tx_data_minus.
TX_data_plus
TX_data_minus
Output from the Phy. The differential data output from the serial
interface when the INTERFACE_TYPE parameter is set to 0. Connect
parallel 10b data input of the de-serializer to this port when the
INTERFACE_TYPE parameter is set to 1.
Table 16-2. SAPIS Monitor Pins

Port
Description
areset
bypass_power_on_seq
When this signal is active high the monitor does not track power on sequence.
See note 1 on page 676.
comreset_detect
cominit_detect
Output from the Phy. This output goes high while the criteria for detecting
COMINIT_DETECT and/or COMRESET_DETECT have been met.
comwake_detect
Output from the Phy. This output goes high while the criteria for detecting
COM_WAKE are met.
k28.5_detect
Output from the Phy. K28.5_DETECT goes high while the K28.5 control
character is present (with either disparity) on the RX_DATA pins. Note that the
RX block is allowed to drop any instance of the Align character (as long as it is
dropped in its four byte entirety).
partial
Input to the Phy. When driven high, PARTIAL places the PHY in its Partial
power state as defined by the SATA specification.
rbc
Output from the Phy. RBC is the clock used by the PHY to transfer recovered
data to the link layer. The rbc[1] clock signal of the implementation under test
must be connected to this input.
reset
rx_data[n:0]
Output from the Phy. This delivers the recovered 10b or 20b or 40b data. The
RX block byte aligns the data. Note that RX_DATA bit 0 is the earliest bit
received at the RX inputs, and bit n is the latest received.
rx_data_valid
Output from the Phy. RX_DATA_VALID signal is used for flow control. A
high indicates that the concurrent RX_DATA outputs are valid; a low indicates
that they should be ignored.
rx_locked
Output from the Phy. RX_LOCKED goes high when the following three
conditions are met:
1. The differential input signal exceeds the Squelch Detector threshold
as defined by the SATA specification
2. The receiver is locked to the incoming signal
3. The RX byte alignment is correctly established
scrambling_off
When this signal is active high, the incoming data will not be descrambled.
slumber
Input to the Phy. When driven high, SLUMBER places the PHY in its Slumber
power state as defined by the SATA specification.
675
SERIAL ATA (SATA)

Table 16-2. SAPIS Monitor Pins (cont.)

Port
Description
tbc
Input to the Phy. TBC is the transmit byte clock used to clock data into the PHY
on the TX_DATA bus. TX data transitions occur concurrently with both edges
of TBC. Thus, TBC will nominally operate at 75MHz for Gen 1, and 150 MHz
for Gen2 signaling.
tx_data[n:0]
Input to the Phy. Encoded 10b or 20b or 40b parallel data sent from the Link
layer to the Phy layer for serialization and transmission. Note that TX_DATA
bit 0 is transmitted first, and bit n is transmitted last.
tx_enable
Input to the Phy. TX_ENABLE enables the SATA cable drivers in the
transmitter portion of the PHY. When this signal is high, the drivers generate
normal drive levels. When low, the PHY outputs are idle and maintain common
mode bias as specified in the SATA specification.

1. When the power on sequence is to be bypassed, the bypass_power_on_seq input must
be set to 1 and after the removal of reset, transmit two or more ALIGNp primitives
followed by three or more non-align primitives. These ALIGNp primitives are required
to obtain locking.
2. When the incoming data is not scrambled, set the scrambling_off input to 1. This
disables the descrambler in the monitor.
3. In the parallel mode, connect the encoded 10B symbols as below:
t x _ d a t a _ p l u s [ 9 : 0 ] = { j , h , g , f , i , e , d ,
c , b , a }
where bit a is the LSB of the 10B data and bit j is the MSB of the 10B data.
Monitor Parameters
The parameters shown in Table 16-3 and Table 16-4 on page 678 configure the SATA monitor.
Table 16-3. SATA Monitor Parameters - Serial / Parallel10B Interfaces
Order Parameter
Default Description
1.
Constraints_Mode

2.
INTERFACE_TYPE
This parameter configures the interface.

0 - SATA - Serial interface
1 - SATA - Parallel 10B interface after serializer /
deserializer.
3.
DEVICE_TYPE
This parameter configures the device type on

which the monitor is instantiated.
0 - Host
1 - Device
676
SERIAL ATA (SATA)

Table 16-3. SATA Monitor Parameters - Serial / Parallel10B Interfaces (cont.)

Order Parameter
Default Description
4.
PARALLEL_DATA_WIDTH
10
This parameter configures the width of the data bus

when connected to the parallel 10B interface.
10 - 10 bits
20 - 20 bits
40 - 40 bits
5.
DOUBLE_DATA_RATE
This parameter configures whether data is

available on both clock edges or on single edge of
the clock.
0 - Double data rate disabled.
1 - Double data rate enabled.
6.
MAX_DEV_SPEED
This parameter configures the maximum speed

supported by the SATA device on which the
monitor is instantiated.
0 - GEN1 speed.
1 - GEN2 speed.
7.
NCQ_COMMAND_ENABLE
This parameter configures the monitor to track

native queued commands.
0 - Native command queueing disabled.
1 - Native command queueing enabled.
8.
LEGACY_QUEUED_
COMMAND_ENABLE

legacy queued commands.
0 - Legacy queued command disabled.
1 - Legacy queued command enabled.
9.
PORT_SELECTOR_ENABLE
This parameter configures whether the monitor sits

on an interface connected to a port selector or not.
0 - Port selector disabled.
1 - Port selector enabled.
10.
PORT_MULTIPLIER_ENABLE
This parameter configures whether the monitor sits

on an interface connected to a port multiplier or
not.
0 - Port multiplier disabled.
1 - Port multiplier enabled.
11.
PACKET_COMMAND_ENABLE

packet commands.
0 - Non-Packet command feature set support.
1 - Packet command feature set support.
12.
RESERVED_VALUE_
CHECKING_ENABLE
Set this to 0 to disable checking of reserved fields.

By default, monitor checks for reserved values.
13.
POWER_MGMT_ENABLE

power management mode.
0 - Power management mode disabled.
1 - Power management mode enabled.
14.
MAX_QUEUE_DEPTH
This parameter configures the maximum number

of commands that can be outstanding.
15.
ASYNC_SIGNAL_RECOVERY
This parameter enables asynchronous signal

recovery feature when set to 1. By default, the
asynchronous signal recovery is not supported.
677
SERIAL ATA (SATA)

Table 16-3. SATA Monitor Parameters - Serial / Parallel10B Interfaces (cont.)

Order Parameter
Default Description
16.
RETRY_INTERVAL
14999250 This parameter configures the retry interval time

when asynchronous recovery is enabled. Refer to
the note below this table.
17.
RESERVED_FIS_TYPE_
ENABLE
This parameter enables the reception of reserved

FIS types when set to 1.
18.
VENDOR_FIS_TYPE_ENABLE
This parameter enables the reception of vendor

specific FIS types when set to 1.
19.
ELECTRICAL_IDLE_
PATTERN
This parameter configures the value on the parallel

10b data when an electrical idle is detected on the
serial bus. This parameter is applicable only on a
parallel 10B interface.
Example: When this parameter has a value of 0,
the monitor assumes that a bit pattern of 10'b0 on
the parallel 10b interface indicates electrical idle
on the serial bus.
Note that the RETRY_INTERVAL parameter is by default configured to 14999250 GEN serial
clock - 1UI (unit interval - 1bit time). When the monitor is configured in parallel 10B mode, the
default value of this parameter is set to 1499925 GEN1 parallel 10B clocks (10 UIs).
Table 16-4. SATA Monitor Parameters - SAPIS Interface

Order Parameter
Default
Description
1.
Constraints_Mode

2.
LINK_SIDE
This parameter indicates whether the monitor is

instantiated on the link or on the phy side of the
SAPIS interface.
0-Link side
1-Phy side
3.
DEVICE_TYPE
This parameter configures the device type on

which the monitor is instantiated.
0 - Host
1 - Device
4.
PARALLEL_DATA_WIDTH
10
This parameter configures the width of the data

bus when connected to the parallel 10B interface.
10 - 10 bits
20 - 20 bits
40 - 40 bits
5.
DOUBLE_DATA_RATE
This parameter configures whether data is

available on both clock edges or on a single edge
of the clock.
0 - Double data rate disabled.
1 - Double data rate enabled.
678
SERIAL ATA (SATA)

Table 16-4. SATA Monitor Parameters - SAPIS Interface (cont.)

Order Parameter
Default
Description
6.
MAX_DEV_SPEED
This parameter configures the maximum speed

supported by the SATA device on which the
monitor is instantiated.
0 - GEN1 speed.
1 - GEN2 speed.
7.
NCQ_COMMAND_ENABLE

native queued commands.
0 - Native command queueing disabled.
1 - Native command queueing enabled.
8.
LEGACY_QUEUED_COMMAND_
ENABLE

legacy queued commands.
0 - Legacy queued command disabled.
1 - Legacy queued command enabled.
9.
PORT_SELECTOR_ENABLE
This parameter configures whether the monitor

sits on an interface connected to a port selector or
not.
0 - Port selector disabled.
1 - Port selector enabled.
10.
This parameter configures whether the monitor

sits on an interface connected to a port multiplier
or not.
0 - Port multiplier disabled.
1 - Port multiplier enabled.
11.

packet commands.
0 - Non-Packet command feature set support.
1 - Packet command feature set support.
12.
RESERVED_VALUE_CHECKING_ 1
ENABLE
Set this to 0 to disable checking of reserved fields.

By default, the monitor checks for reserved values.
13.
POWER_MGMT_ENABLE

power management mode.
0 - Power management mode disabled.
1 - Power management mode enabled.
14.
MAX_QUEUE_DEPTH
This parameter configures the maximum number

of commands that can be outstanding.
15.
ASYNC_SIGNAL_RECOVERY
This parameter enables asynchronous signal

recovery feature when set to 1.
16.
RETRY_INTERVAL
14999250
This parameter configures the retry interval time

when asynchronous recovery is enabled. Refer to
the note below this table.
17.
RESERVED_FIS_TYPE_ENABLE
This parameter enables the reception of reserved

FIS types when set to 1.
18.
VENDOR_FIS_TYPE_ENABLE
This parameter enables the reception of vendor

specific FIS types when set to 1.
679
SERIAL ATA (SATA)

Note that the RETRY_INTERVAL parameter is by default configured to 14999250 GEN serial
clock - 1UI (unit interval - 1bit time). When the monitor is configured in parallel 10B mode, the
default value of this parameter is set to 1499925 GEN1 parallel 10B clocks (10 UIs).
Example 1
Example 16-1 instantiates a SATA monitor on a Host serial interface with maximum speed of
GEN1, power management mode, legacy queued commands and reserved field checking
enabled and double data rate, packet command, NCQ commands, asynchronous signal
recovery, reserved FIS and vendor specific FIS disabled.
Example 16-1. SATA Monitor Instantiation
qvl_sata_monitor #(
0, /* Constraints_Mode */
0, /* INTERFACE_TYPE */
0, /* DEVICE_TYPE */
0, /* PARALLEL_DATA_WIDTH */
0, /* DOUBLE_DATA_RATE */
0, /* MAX_DEV_SPEED */
0, /* NCQ_COMMAND_ENABLE */
1, /* LEGACY_QUEUED_COMMAND_ENABLE */
0, /* PORT_SELECTOR_ENABLE */
0, /* PORT_MULTIPLIER_ENABLE */
0, /* PACKET_COMMAND_ENABLE */
1, /* RESERVED_VALUE_CHECKING_ENABLE */
1, /* POWER_MGMT_ENABLE */
32,/* MAX_QUEUE_DEPTH */
0, /* ASYNC_SIGNAL_RECOVERY */
0, /* RETRY_INTERVAL */
0, /* RESERVED_FIS_TYPE_ENABLE */
0, /* VENDOR_FIS_TYPE_ENABLE */
0 /* ELECTRICAL_IDLE_PATTERN */
)
SATA_MONITOR
(.areset(areset),
.reset(reset),
.tx_clk(tx_clk),
.tx_data_plus(tx_data_plus),
.tx_data_minus(tx_data_minus),
.rx_clk(rx_clk),
.rx_data_plus(rx_data_plus),
.rx_data_minus(rx_data_minus),
.scrambling_off(scrambling_off),
.bypass_power_on_seq(bypass_power_on_seq));
680
SERIAL ATA (SATA)

Example 2
Example 16-2 instantiates a SATA monitor on a Device 10B interface with maximum
supported speed of GEN2, double data rate, power management mode, NCQ commands with
max queue depth of 16 and reserved field checking enabled and packet command, legacy
queued commands, asynchronous signal recovery, reserved FIS and vendor specific FIS
disabled.
qvl_sata_monitor #(
10,/* PARALLEL_DATA_WIDTH */
)
SATA_MONITOR
(.areset(areset),
.reset(reset),
.tx_clk(tx_clk),
.rx_clk(rx_clk),
.bypass_power_on_seq(bypass_power_on_seq)
);
Example 3
Example 16-3 instantiates a SATA monitor on a 40B interface in the host side of the port
multiplier with maximum supported speed of GEN1, double data rate, power management
mode, NCQ commands with max queue depth of 16 and reserved field checking enabled and
packet command, legacy queued commands, asynchronous signal recovery, reserved FIS and
vendor specific FIS disabled.
681
SERIAL ATA (SATA)

Example 16-3. SATA Monitor Instantiation for Example 3

qvl_sata_monitor #(
)
SATA_MONITOR
(.areset(areset),
.reset(reset),
.tx_clk(tx_clk),
.rx_clk(rx_clk),
);
Example 4
Example 16-4 instantiates a SATA monitor on a 20B SAPIS interface on the link side of the
device with maximum supported speed of GEN2, double data rate, packet command,
asynchronous signal recovery, reserved FIS and vendor specific FIS enabled and power
management mode, NCQ commands, legacy queued commands and reserved field checking
disabled.
qvl_sata_sapis_monitor #(
1, /* LINK_SIDE */
682
SERIAL ATA (SATA)

Monitor Checks
0, /* MAX_QUEUE_DEPTH */
80,/* RETRY_INTERVAL */
1 /* VENDOR_FIS_TYPE_ENABLE */
)
SAPIS_MONITOR
(.areset(areset),
.reset(reset),
.tbc(tbc),
.tx_data(tx_data),
.tx_enable(tx_enable),
.rbc(rbc),
.rx_data(rx_data),
.rx_data_valid(rx_data_valid),
.k28_5_detect(k28_5_detect),
.rx_locked(rx_locked),
.comwake_detect(comwake_detect),
.comreset_cominit_detect(comreset_cominit_detect),
.partial(partial),
.slumber(slumber),
);
Monitor Checks
The checks performed by the SATA monitor are listed in the following subsections.
Power on Sequence Checks

Table 16-5. Power on Sequence Checks
Check ID
Violation
Description
SATA_ALIGNP_D24_3_
VIOLATION_P
The COMRESET or COMINIT

or COMWAKE bursts must not
have any characters other than
ALINGp or D24.3 characters.
The COMRESET, COMINIT or

COMWAKE signaling consists of a
sequence of bursts separated by idle
bus condition. The data bursts must
comprise of either ALIGNp
primitives or D24.3 characters. This
check fires when a dword other than
ALIGNp primitive or four D24.3
characters are seeing in the data
bursts.
SATA_ALIGNP_D24_3_
VIOLATION_N
683
SERIAL ATA (SATA)

Monitor Checks
Table 16-5. Power on Sequence Checks (cont.)

Check ID
Violation
Description
SATA_COMINIT_BURST_
TIME_VIOLATION_P
Burst time of each burst in

COMINIT signalling must be
106.7ns.
Each burst of the COMINIT signaling

must span 106.7ns. (i.e., 4 dwords or
106.7ns/0.666ns = 160GEN1 clock
cycles). This check fires when the
burst time of the COMINIT signaling
is more or less than 160 GEN1 clocks.
This check is active when
DEVICE_TYPE parameter is set to
1.
COMINIT OOB signaling must

consist of at least 6 bursts.
COMINIT signaling must consist of

at least 6 bursts separated by inter
burst idles. This check fires when the
number of bursts in COMINIT
signaling is less than 6. This check is
active when DEVICE_TYPE is set to
1.
The inter-burst spacing in

COMINIT signaling must be
320ns.
Inter burst spacing of the COMINIT

signaling must span 320ns. (i.e.,
320ns/0.666ns = 480GEN1 clock
cycles). This check fires when the
inter burst spacing of the COMINIT is
more or less than 480 GEN1 clocks.
This check is active when the
DEVICE_TYPE parameter is set to
1.
COMRESET OOB signaling

must consist of at least 6 bursts.
COMRESET signaling must consist

of at least 6 bursts separated by inter
number of bursts in COMRESET
active when DEVICE_TYPE

COMRESET signaling must be
106.7ns.
Each burst of the COMRESET

signaling must span for 106.7ns. (i.e.,
4 dwords or 106.7ns/0.666ns =
160GEN1 clock cycles). This check
fires when the burst time of the
COMRESET signaling is more or less
than 160 GEN1 clocks. This check is
The inter-burst spacing in

COMRESET signaling must be
320ns.
Inter burst spacing of the

COMRESET signaling must span
320ns. (i.e. 320ns/0.666ns =
fires when the inter burst spacing of
the COMRESET is more or less than
480 GEN1 clocks. This check is
SATA_COMINIT_BURST_
TIME_VIOLATION_N
SATA_COMINIT_BURST_
VIOLATION_P
SATA_COMINIT_BURST_
VIOLATION_N
SATA_COMINIT_INTER_
BURST_TIME_VIOLATION_P
SATA_COMINIT_INTER_
BURST_TIME_VIOLATION_N
SATA_COMRESET_BURST_
VIOLATION_P
VIOLATION_N
TIME_VIOLATION_P
TIME_VIOLATION_N
SATA_COMRESET_INTER_
SATA_COMRESET_INTER_
684
SERIAL ATA (SATA)

Monitor Checks
Table 16-5. Power on Sequence Checks (cont.)

Check ID
Violation
Description
SATA_COMWAKE_BURST_
TIME_VIOLATION_P

COMWAKE signalling must be
106.7ns.
Each burst of the COMWAKE

signaling must be 106.7ns. (i.e., 4
dwords or 106.7ns/0.666ns =
fires when the burst time of the
COMWAKE signaling is more or less
than 160 GEN1 clocks. This check is
active on the tx lines.
COMWAKE OOB signaling

must consist of at least 6 bursts.
COMWAKE signaling must consist

of at least 6 bursts separated by inter
number of bursts in COMWAKE
performed on the tx interface.
The inter-burst spacing in the

COMWAKE signaling must be
106.7ns.
Inter burst spacing of the

COMWAKE signaling must be
320ns. (i.e., 106.7ns/0.666ns =
fires when the inter burst spacing of
the COMWAKE is more or less than
480 GEN1 clocks. This check is
active on the tx lines.
The bus should not be idle for

more than 228.3ns after the deassertion of COMWAKE.
Following the COMWAKE from the

device, it shall start transmitting the
ALIGNp primitives within 228.3ns.
This check fires if the device doesnt
transmit the first ALIGNp primitive
with 228.3ns from the de-assertion of
COMWAKE.
Host must not start the

transmission of D10.2 characters
without the reception of
COMWAKE from the device.

device, the host must issues D10.2
characters during the power on
sequence. This check fires when the
host issues D10.2 characters without
the device transmitting COMWAKE.
Device must not transmit

COMWAKE without the
reception of COMWAKE from
the host.

host, the device must issues
COMWAKE during the power on
sequence. This check fires when the
device issues COMWAKE without
receiving COMWAKE from the host.
Host must not transmit

COMWAKE without the
reception of COMINIT from the
device.
The host shall transmit COMWAKE

only after the reception of COMINIT
from the device during the power on
reset sequence. This check fires when
the host issues COMWAKE before
the reception of COMINIT from the
device.
SATA_COMWAKE_BURST_
TIME_VIOLATION_N
SATA_COMWAKE_BURST_
VIOLATION_P
SATA_COMWAKE_BURST_
VIOLATION_N
SATA_COMWAKE_INTER_
SATA_COMWAKE_INTER_
SATA_COMWAKE_LAST_
IDLE_VIOLATION_P
SATA_COMWAKE_LAST_
IDLE_VIOLATION_N
SATA_D10_2_BEFORE_D_
COMWAKE_VIOLATION_P
SATA_D10_2_BEFORE_D_
COMWAKE_VIOLATION_N
SATA_D_COMWAKE_WO_
H_COMWAKE_VIOLATION_P
SATA_D_COMWAKE_WO_
H_COMWAKE_VIOLATION_N
SATA_H_COMWAKE_WO_
COMINIT_VIOLATION_P
SATA_H_COMWAKE_WO_
COMINIT_VIOLATION_N
685
SERIAL ATA (SATA)

Monitor Checks
Phy Layer Checks

Table 16-6. Phy Layer Checks
Check ID
Violation
Description
SATA_RX_D_COMWAKE_TO_
D10_2_VIOLATION_P
Host must transmit D10.2

characters within 533ns from
the de-assertion of
COMWAKE by the device.
On detection of COMWAKE from the

device, the host must transmit D10.2
characters until it locks with the ALIGNp
primitives from the device within 533ns
from the de-assertion of COMWAKE from
the device. This check fires when D10.2
from the host is not seen within 533ns after
the de-assertion of COMWAKE from the
device. This check is active only when the
DEVICE_TYPE parameter is set to 1.

ALIGNp primitives before
receiving ALIGNp
primitives from the device.
Following the COMWAKE signaling by

the device, host transmits D10.2 characters
and waits for ALIGNp primitives from the
device to lock. This check fires when the
host transmits ALIGNp primitives before
receiving ALIGNp primitives from the
device. This check is active only when
DEVICE_TYPE is set to 1.
Host must see the first

ALIGNp from the device
within 880us after the deassertion of COMWAKE by
the host.
During the power on sequence, the device

is required to transmit ALIGNp primitives
within 880us after the de-assertion of
COMWAKE from the host. This check
fires when the latency between the deassertion of COMWAKE from the host to
the first ALIGNp after the device
COMWAKE is more than 880us. This
check is active only when the
After receiving
COMWAKE, the host must
receive at least 2048
ALIGNp primitives.
Following the COMWAKE signaling, the

host is required to receive at least 2048
ALIGNp primitives. This check fires when
the host receives less than 2048 ALIGNp
primitives. This check is active only when
the DEVICE_TYPE parameter is set to
0.
SATA_RX_D_COMWAKE_TO_
D10_2_VIOLATION_N
SATA_RX_H_ALIGN_BEFORE_
D_ALIGN_VIOLATION_P
SATA_RX_H_ALIGN_BEFORE_
D_ALIGN_VIOLATION_N
SATA_RX_H_COMWAKE_TO_
D_ALIGNP_VIOLATION_P
SATA_RX_H_COMWAKE_TO_
D_ALIGNP_VIOLATION_N
SATA_RX_NO_2048_ALIGNP_
VIOLATION_P
SATA_RX_NO_2048_ALIGNP_
VIOLATION_N
SATA_RX_RETRY_INTERVAL_ When Asynchronous signal

VIOLATION_P
recovery is enabled,
COMRESET must not be
SATA_RX_RETRY_INTERVAL_ transmitted by the host
VIOLATION_N
before the expiry of RETRY
interval.
686
The host while waiting for COMINIT or

COMWAKE from the device, is allowed to
retry the power on reset sequence only
after the retry interval has elapsed. This
check fires when the host issues
COMRESET signaling when the retry
interval has not elapsed. This check is
active only when the parameter
ASYNCHRONOUS_SIGNAL_
RECOVERY_ENABLE is set and
SERIAL ATA (SATA)

Monitor Checks
Table 16-6. Phy Layer Checks (cont.)

Check ID
Violation
Description
SATA_TX_D_COMWAKE_TO_
D10_2_VIOLATION_P
Host must transmit D10.2

characters within 533ns from
the de-assertion of
COMWAKE by the device.
On detection of COMWAKE from the

device, the host must transmit D10.2
characters until it locks with the ALIGNp
primitives from the device within 533ns
from the de-assertion of COMWAKE from
the device. This check fires when D10.2
from the host is not seen within 533ns after
the de-assertion of COMWAKE from the
device. This check is active only when the

ALIGNp primitives before
receiving ALIGNp
primitives from the device.
Following the COMWAKE signaling by

the device, host transmits D10.2 characters
and waits for ALIGNp primitives from the
device to lock. This check fires when the
host transmits ALIGNp primitives before
receiving ALIGNp primitives from the
device. This check is active only when
Device must transmit the

first ALIGNp within 880us
after the de-assertion of
COMWAKE by the host.
During the power on sequence, the device

is required to transmit ALIGNp primitives
within 880us after the de-assertion of
COMWAKE from the host. This check
fires when the latency between the deassertion of COMWAKE from the host to
the ALIGNp after the device COMWAKE
is more than 880us. This check is active
only when the DEVICE_TYPE parameter
is set to 1.
After transmitting
COMWAKE, the device
must transmit at least 2048
ALIGNp primitives.
Following the COMWAKE signaling, the

device is required to transmit at least 2048
ALIGNp primitives. This check fires when
the device sends less than 2048 ALIGNp
primitives. This check is active only when
the DEVICE_TYPE parameter is set to
1.
When Asynchronous signal

recovery is enabled,
COMRESET must not be
transmitted by the host
before the expiry of RETRY
interval.
The host while waiting for COMINIT or

COMWAKE from the device, is allowed to
retry the power on reset sequence only
after the retry interval has elapsed. This
check fires when the host issues
COMRESET signaling when the retry
interval has not elapsed. This check is
active only when the
ASYNCHRONOUS_SIGNAL_
RECOVERY_ENABLE is set and
SATA_TX_D_COMWAKE_TO_
D10_2_VIOLATION_N
SATA_TX_H_ALIGN_BEFORE_
D_ALIGN_VIOLATION_P
SATA_TX_H_ALIGN_BEFORE_
D_ALIGN_VIOLATION_N
SATA_TX_H_COMWAKE_TO_
D_ALIGNP_VIOLATION_P
SATA_TX_H_COMWAKE_TO_
D_ALIGNP_VIOLATION_N
SATA_TX_NO_2048_ALIGNP_
VIOLATION_P
SATA_TX_NO_2048_ALIGNP_
VIOLATION_N
SATA_TX_RETRY_INTERVAL_
VIOLATION_P
SATA_TX_RETRY_INTERVAL_
VIOLATION_N
687
SERIAL ATA (SATA)

Monitor Checks
Link Layer Checks

Table 16-7. Link Layer Checks
Check ID
Violation
Description
SATA_ALIGN_P_PAIR_
VIOLATION_P
ALIGNp primitive must be

detected in pairs.
The serial ATA specification

requires that the ALIGNp
primitives must always be
transmitted in pairs. This check
fires when a single ALIGNp
primitive is detected.
Invalid 10B code detected.
This check fires when a code

error was detected during
decoding of the incoming 10b
data.
SATA_CONT_P_VIOLATION_N
Primitives other than HOLDp,

HOLDAp, PMREQ_Pp,
PMREQ_Sp, R_ERRp, R_OKp,
R_RDYp, SYNCp, WTRMp, and
X_RDYp must not be followed
by CONTp primitive.
Any repetitive primitive may be

implied to continue repeating
through the use of the CONTp
primitive. The following
primitives may be followed by a
CONTp: HOLDp, HOLDAp,
PMREQ_Pp, PMREQ_Sp,
R_ERRp, R_IPp, R_OKp,
R_RDYp, SYNCp, WTRMp, and
X_RDYp. This check fires if a
primitive other than the ones
specified above are followed by
CONTp.
SATA_CRC_ERROR_
VIOLATION_P
Crc error encountered in the fis

frame.
This check fires when a crc error

was detected in the fis frame.
The data dword must be

transmitted within the SOFp and
EOFp.
Any data dword must be

transmitted within the SOFp and
EOFp primitives. This check fires
when a data dword is detected
before transmission of SOFp or
after the transmission of EOFp
primitives during a frame
transmission.
Disparity error encountered while

decoding the 10B data.
This check fires when a disparity

error was detected during 8B10B
decoding of the incoming data.
SATA_ALIGN_P_PAIR_
VIOLATION_N
SATA_CODE_ERR_
VIOLATION_P
SATA_CODE_ERR_
VIOLATION_N
SATA_CONT_P_VIOLATION_P
SATA_CRC_ERRORCODE_ERR_
VIOLATION_N
SATA_DATA_OUTSIDE_SOF_
EOF_VIOLATION_P
SATA_DATA_OUTSIDE_SOF_
EOF_VIOLATION_N
SATA_DISPARITY_
VIOLATION_P
SATA_DISPARITY_
VIOLATION_N
688
SERIAL ATA (SATA)

Monitor Checks
Table 16-7. Link Layer Checks (cont.)

Check ID
Violation
Description
SATA_DMAT_BY_
TRANSMITTER_VIOLATION_P
DMATp primitive must not be

transmitted by the data FIS
transmitter.
The DMA Terminate (DMATp)

primitive may be sent on the back
channel during transmission of a
Data FIS to signal the transmitter
to terminate the transfer in
progress. It may be used for both
host to device transfers and for
device to host transfers.
Reception of the DMATp shall
cause the recipient to close the
current frame by inserting the
CRC and EOF, and return to the
idle state. This check fires when
DMATp is transmitted by the
host or device that is transmitting
data FIS.
SATA_DMAT_BY_
TRANSMITTER_VIOLATION_N
SATA_DMAT_P_RIP_P_
VIOLATION_P
SATA_DMAT_P_RIP_P_
VIOLATION_N
SATA_EOF_P_MORE_THAN_
ONCE_VIOLATION_P
DMATp must always be followed The DMA Terminate (DMATp)

by R_IPp primitive.
primitive may be sent on the back
channel during transmission of a
Data FIS to signal the transmitter
to terminate the transfer in
progress. The transmission of
DMAT must be followed by
R_IPp primitive. This check fires
if a primitive other than R_IPp or
SYNCp follows DMATp
EOFp primitive must not be
transmitted more than once in a
frame.
Transmission of any frames starts

with the SOFp primitive and ends
with the EOFp primitive. The end
of frame primitive (EOFp) shall
be transmitted not more than
once. This check fires when more
than one EOFp is detected
without an intervening SOFp
primitive.
EOFp must always be followed

by WTRMp primitive.
Transmission of any frame is

completed with an EOFp
primitive. While waiting for the
good or bad status response, i.e.,
R_OKp or R_ERRp primitive,
EOFp must be followed by the
WTRM primitive. This check
fires if a primitive other than
WTRMp or SYNCp follows
EOFp.
SATA_EOF_P_MORE_THAN_
ONCE_VIOLATION_N
SATA_EOF_P_WTRM_P_
VIOLATION_P
SATA_EOF_P_WTRM_P_
VIOLATION_N
689
SERIAL ATA (SATA)

Monitor Checks

Check ID
Violation
Description
SATA_INVALID_K_CODE_
VIOLATION_P
Control characters other than

K28.5 and K28.3 are invalid
K-codes.
In Serial ATA, only K28.3 and

K28.5 control characters are valid
and are always used as the first
byte in a four-byte primitive. The
K28.3 control character is used to
prefix all primitives other than the
ALIGNp primitive, while the
prefix the ALIGNp primitive.
This check fires when a control
character other than K28.3 and
K28.5 is detected.
Invalid primitive detected.
Any dword other than the ones

specified in the primitive
encoding table is considered to be
invalid primitive. This check fires
when a primitive other than the
ones specified in the table are
detected.
K28.5 or K28.3 characters must

be the first byte of any primitive.
In Serial ATA, only K28.3 and

K28.5 control characters are valid
and are always used as the first
byte in a four-byte primitive. The
prefix all primitives other than the
ALIGNp primitive, while the
prefix the ALIGNp primitive.
This check fires when a control
character is not the first byte in
the primitive.
A pair of ALIGNp primitives

must be detected once every 254
non-ALIGNp dwords.
At any point the host or device

must not transmit more than 254
consecutive non-align dwords.
This check fires when more than
254 consecutive non-align
primitives are detected.
PMACKp primitive must be

transmitted at least four times as
an acknowledgement to
PMREQp.
The host or device shall transmit

PMREQ_Pp or PMREQ_Sp
primitive to initiate partial or
slumber power down modes. In
response, the host or device must
transmit at least four PMACKp
primitives. This check fires on
reception of less than four
PMACKp primitives in response
to PMREQp primitives.
SATA_INVALID_K_CODE_
VIOLATION_N
SATA_INVALID_PRIMITIVE_P
SATA_INVALID_PRIMITIVE_N
SATA_K_CODE_NOT_BYTE0_
VIOLATION_P
SATA_K_CODE_NOT_BYTE0_
VIOLATION_N
SATA_NON_ALIGN_DWORD_
VIOLATION_P
SATA_NON_ALIGN_DWORD_
VIOLATION_N
SATA_PMACK_P_LESS_
THAN_4_VIOLATION_P
SATA_PMACK_P_LESS_
THAN_4_VIOLATION_N
690
SERIAL ATA (SATA)

Monitor Checks

Check ID
Violation
Description
SATA_PMACK_P_MORE_
THAN_16_VIOLATION_P
PMACKp primitive must be

transmitted not more than sixteen
times as an acknowledgement to
PMREQp.
The host or device shall transmit

primitive to initiate partial or
slumber power down modes. In
response, the host or device must
transmit at least four and not
more than 16 PMACKp
primitives. More than sixteen
PMACKp primitives must not be
transmitted. This check fires on
receipt of more than 16 PMACKp
primitives.
R_OKp primitive must not be

transmitted when crc error is
encountered.
On encountering crc error during

a frame reception, the frame is
required to be negatively
acknowledged by sending
R_ERRp primitive. This check
fires when R_OKp is detected
when the frame was received with
crc error.
Sub-block containing 000111 was

generated when the running
disparity at the beginning of the
sub-block was negative.
The 8B10B encoding requires

that a sub-block containing
000111 must be generated only
beginning of the sub-block was
positive. This check fires when
the running disparity at the
000111 was negative.

sub-block was negative.

that a sub-block containing 0011
must be generated only when the
running disparity at the beginning
of the sub-block was positive.
This check fires when the running
sub-block 0011 was negative.

sub-block was positive.

that a sub-block containing 1100
must be generated only when the
running disparity at the beginning
of the sub-block was negative.
This check fires when the running
sub-block 1100 was positive.

sub-block was positive.

that a sub-block containing
111000 must be generated only
beginning of the sub-block was
negative. This check fires when
the running disparity at the
111000 was positive.
SATA_PMACK_P_MORE_
THAN_16_VIOLATION_N
SATA_R_OK_P_WHEN_
CRC_ERR_VIOLATION_P
SATA_R_OK_P_WHEN_
CRC_ERR_VIOLATION_N
SATA_RD_000111_SUB_BLK_
VIOLATION_P
VIOLATION_N
VIOLATION_P
VIOLATION_N
VIOLATION_P
VIOLATION_N
VIOLATION_P
VIOLATION_N
691
SERIAL ATA (SATA)

Monitor Checks

Check ID
Violation
SATA_REPEAT_PRIMITIVE_
VIOLATION_P
CONTp primitive must not be

Any repetitive primitive may be
detected until the primitive to be implied to continue repeating
repeated is detected at least twice. through the use of the CONTp
primitive. The recipient of the
CONTp primitive shall ignore all
data received after the CONTp
primitive until the reception of
any primitive, excluding
ALIGNp. All repeated primitives
shall be transmitted a minimum
of twice before a CONTp
primitive is transmitted. This
check fires if the primitive to be
repeated is not transmitted a
minimum of twice before
CONTp.
SATA_REPEAT_PRIMITIVE_
VIOLATION_N
SATA_ROK_FOR_10B_
DISPERR_VIOLATION_P
SATA_ROK_FOR_10B_
DISPERR_VIOLATION_N
SATA_ROK_FOR_INVALID_
FIS_VIOLATION_P
SATA_ROK_FOR_INVALID_
FIS_VIOLATION_N
SATA_ROK_FOR_MALF_FIS_
VIOLATION_P
SATA_ROK_FOR_MALF_FIS_
VIOLATION_N
SATA_RX_DMAT_OUTSIDE_
EOF_SOF_VIOLATION_P
SATA_RX_DMAT_OUTSIDE_
EOF_SOF_VIOLATION_N
692
Description
On detection of 10B or disparity

error during a frame reception,
the frame must be negatively
acknowledged with R_ERRp
primitive.
On detection of a disparity error

or 8b/10b coding violation during
the receipt of a frame, the
received frame must be
negatively acknowledged
(R_ERRp as the frame
handshake). This check fires
when a frame is acknowledged
with R_OKp primitive when
there is 8B10B code error or
disparity error.
On detection of unrecognized FIS

type during a frame reception, the
frame must be negatively
primitive.
On reception of an FIS with

unrecognized type, the host or
device must negatively
acknowledge the frame reception
by issuing R_ERRp during the
frame acknowledgement
handshake. This check fires when
the frame is acknowledged by
R_OKp primitive.
On detection of malformed FIS

during a frame reception, the
primitive.
On reception of a malformed
frame, such as a frame with
incorrect length, the host or
device must negatively
acknowledge by issuing R_ERRp
during the frame
acknowledgement handshake.
This check fires when the frame
is acknowledged by R_OKp
primitive.
DMATp primitive must be

detected within the SOFp and
EOFp primitives.
DMATp must be detected within

the SOFp and EOFp primitives.
This check fires when a DMATp
is received before transmission of
SOFp or after the transmission of
EOFp primitives during a frame
transmission on the tx lines.
SERIAL ATA (SATA)

Monitor Checks

Check ID
Violation
Description
SATA_RX_DPMREQ_WHILE_
HPMREQ_VIOLATION_P
On receipt of PMREQ_Pp or
PMREQ_Sp from the device
while transmitting PMREQ_Pp or
PMREQ_Sp, the host must start
transmitting SYNCp without
entering power down mode.
Host while transmitting

PMREQ_Pp or PMREQ_Sp, on
receipt of PMREQ_Pp or
PMREQ_Sp device must not
enter power management mode.
This check fires when the above
condition is violated. This check
is active only when
DEVICE_TYPE parameter is set
to 1.
HOLDp primitive must be

EOFp primitives.
HOLDp must be detected within

This check fires when a HOLDp
is received on the rx lines before
detection of SOFp or after the
detection of EOFp primitives.
The latency between the detection

of first HOLDp to the detection of
first HOLDAp must not be more
than 20 dwords.
The maximum allowed latency

from the time the MSB of the
HOLDp primitive is on the wire,
to the MSB of the HOLDAp is on
the wire shall not be more than 20
Dword symbol times. This check
fires when the first HOLDAp
primitive on the rx lines in
response to HOLDp is not seen
within 20 dwords.
SATA_RX_DPMREQ_WHILE_
HPMREQ_VIOLATION_N
SATA_RX_HOLD_OUTSIDE_
EOF_SOF_VIOLATION_P
SATA_RX_HOLD_OUTSIDE_
EOF_SOF_VIOLATION_N
SATA_RX_HOLDA_P_
LATENCY_VIOLATION_P
SATA_RX_HOLDA_P_
LATENCY_VIOLATION_N
SATA_RX_HOLDA_UNTIL_
HOLD_VIOLATION_P
SATA_RX_HOLDA_UNTIL_
HOLD_VIOLATION_N
HOLDAp must be received as

HOLDAp must be received as
long as HOLDp primitive is being long as HOLDp is transmitted.
transmitted.
This check fires when any
primitive other than HOLDAp or
SYNCp or CONTp are detected
on the rx lines when HOLDp is
being transmitted on the tx lines.
SATA_RX_HOLDA_WO_
HOLD_VIOLATION_P
HOLDAp primitive must not be

received without transmitting
HOLDp primitive.
Host or Device must not detect

HOLDAp on the rx lines without
transmitting HOLDp. This check
fires when HOLDAp is detected
on the rx lines without
transmitting HOLDp on the tx
lines.
The host transmitting X_RDYp

must back off and start
transmitting R_RDYp on
receiving X_RDYp from the
device.
On receipt of X_RDYp from the

device while transmitting
X_RDYp, the host shall back off
and start transmitting R_RDYp.
This check fires when SOFp is
detected on the rx lines when the
to 1 or when R_RDYp is
detected on the rx lines when the
to 0.
SATA_RX_HOLDA_WO_
HOLD_VIOLATION_N
SATA_RX_HOST_BACK_OFF_
VIOLATION_P
SATA_RX_HOST_BACK_OFF_
VIOLATION_N
693
SERIAL ATA (SATA)

Monitor Checks

Check ID
Violation
Description
SATA_RX_HPMREQ_WHILE_
DPMREQ_VIOLATION_P
PMREQ_Sp from the host, the
device must continue transmitting
PMREQ and enter power down
mode.
Device while transmitting

PMREQ_Sp, on receipt of
PMREQ_Pp or PMREQ_Sp it
must continue transmitting
PMREQ_Pp and the host must
respond with PMACKp or
PMNACKp. This check fires
when the above condition is
violated. This check is active only
when DEVICE_TYPE parameter
is set to 1.
PMACK must not be received

without transmitting PMREQ_Pp
or PMREQ_Sp.
PMACKp primitive must not be

received on the rx lines, without
transmitting PMREQ_Pp or
PMREQ_Sp primitives. This
check fires when PMACKp
primitive was detected without
primitives.
PMNACK must not be received

without transmitting PMREQ_Pp
or PMREQ_Sp.
PMNACKp primitive must not be

received on the rx lines, without
PMREQ_Sp primitives. This
check fires when PMNACKp
primitive was detected without
primitives.
R_RDYp must not be received

without transmitting X_RDYp.
Host or Device must not transmit

R_RDYp on the rx lines without
transmitting X_RDYp. This
check fires when R_RDYp
primitive is detected on the rx
lines without the transmitting
X_RDYp
R_ERRp primitive must be

received until the transmission of
SYNCp.
R_ERRp must be detected on the

rx lines until SYNCp is
transmitted on the tx lines. This
check fires when any primitive
other than R_ERRp is detected on
the rx lines before the
transmission of SYNCp on the tx
lines.
While receiving HOLDp or

HOLDAp or DMATp, R_IPp
must be received after
transmitting EOFp.
While receiving HOLDp or

must be detected after detection
of EOFp on tx lines. This check
fires when any primitive other
than R_IPp or the one that was
being transmitted is detected on
rx lines before detecting EOFp on
the tx lines is detected.
SATA_RX_HPMREQ_WHILE_
DPMREQ_VIOLATION_N
SATA_RX_PMACK_WO_
PMREQ_VIOLATION_P
SATA_RX_PMACK_WO_
PMREQ_VIOLATION_N
SATA_RX_PMNACK_WO_
PMREQ_VIOLATION_P
SATA_RX_PMNACK_WO_
PMREQ_VIOLATION_N
SATA_RX_R_RDY_WO_
X_RDY_VIOLATION_P
SATA_RX_R_RDY_WO_
X_RDY_VIOLATION_N
SATA_RX_RERR_UNTIL_
SYNC_VIOLATION_P
SATA_RX_RERR_UNTIL_
SYNC_VIOLATION_N
SATA_RX_RIP_AFTER_EOF_
VIOLATION_P
SATA_RX_RIP_AFTER_EOF_
VIOLATION_N
694
SERIAL ATA (SATA)

Monitor Checks

Check ID
Violation
Description
SATA_RX_ROK_FOR_
TX_CNT_ERR_VIOLATION_P
SATA_RX_ROK_FOR_
TX_CNT_ERR_VIOLATION_N
On detection of transfer count

mismatch between the count
specified in the PIO setup and the
bytes received in a frame, the
primitive.

primitive. This check fires when
R_OKp is detected on the rx lines
when the frame was transmitted
with transfer count mismatch.
SATA_RX_ROK_UNTIL_SYNC_
VIOLATION_P
R_OKp primitive must be

SYNCp.
R_OKp must be detected on the

rx lines until SYNCp is
transmitted on the tx lines. This
other than R_OKp is detected on
the rx lines before the
transmission of SYNCp on the tx
lines.
SOFp must not be received

without transmitting R_RDYp.
Host or Device must not detect

SOFp on the rx lines without
transmitting R_RDYp. This
check fires when SOFp is
detected on the rx lines without
the detecting R_RDYp on the tx
lines.
On receipt of SYNCp, the

SYNCp primitive must be
transmitted.
Host or device on transmission of

SYNCp on tx interface must start
receiving SYNCp on the rx lines.
This check fires when any
primitive other than SYNCp or
the primitive that was being
transmitted is detected on the rx
lines.
On detection of SOFp without

receiving R_RDY, any primitive
other than SYNCp must not be
detected until transmission of
SYNCp.
On detection of SOFp without

receiving R_RDY, any primitive
other than SYNCp must not be
detected until transmission of
SYNCp. This check fires on
detection of any primitive other
than SYNCp on rx lines when
SOFp was detected without
R_RDYp.
WTRMp primitive must be

R_OKp or R_ERRp or SYNCp.
WTRMp must be received on the

rx lines until R_OKp or R_ERRp
is transmitted on the tx lines. This
other than WTRMp or SYNCp
are detected on the rx lines before
the transmission of R_OKp or
R_ERRp or SYNCp on the tx
lines.
SATA_RX_ROK_UNTIL_SYNC_
VIOLATION_N
SATA_RX_SOF_WO_RRDY_
VIOLATION_P
SATA_RX_SOF_WO_RRDY_
VIOLATION_N
SATA_RX_SYNC_AFTER_
TX_SYNC_VIOLATION_P
SATA_RX_SYNC_AFTER_
TX_SYNC_VIOLATION_N
SATA_RX_SYNC_UNTIL_
SYNC_VIOLATION_P
SATA_RX_SYNC_UNTIL_
SYNC_VIOLATION_N
SATA_RX_WTRM_UNTIL_
S_VIOLATION_P
SATA_RX_WTRM_UNTIL_
STS_VIOLATION_N
695
SERIAL ATA (SATA)

Monitor Checks

Check ID
Violation
Description
SATA_RX_XRDY_DURING_
PMREQ_VIOLATION_P
On receipt of X_RDYp while

PMREQ_Sp primitives, the
device shall not enter power
down mode.
Host or device while transmitting

receipt of X_RDYp it must not
SOFp primitive must not be

transmitted more than once in a
frame.
Transmission of any frame starts

with the SOFp primitive and ends
with the EOFp primitive. The
start of frame primitive (SOFp)
shall be transmitted not more than
once. This check fires when more
than one SOFp is detected
without an intervening EOFp
primitive.
PMREQ_Pp primitives must

always be preceded by SYNCp
primitive.
The device or host shall initiate

partial or slumber mode by
transmitting PMREQ_Pp
primitive. The PMREQ_Pp
primitive must always be
preceded by SYNCp primitives.
This check fires when the
PMREQ_Pp primitive is not
preceded by SYNCp primitive.
PMREQ_Sp primitives must

always be preceded by SYNCp
primitive.
The device or host shall initiate

partial or slumber mode by
transmitting PMREQ_Sp
primitive. The PMREQ_Sp
primitive must always be
preceded by SYNCp primitives.
PMREQ_Sp primitive is not
preceded by SYNCp primitive.
DMATp primitive must be

EOFp primitives.
DMATp must be detected within

This check fires when a DMATp
is transmitted before reception of
SOFp or after the reception of
EOFp primitives during a frame
reception on the rx lines.
PMREQ_Sp from the device
while transmitting PMREQ_Pp or
PMREQ_Sp, the host must start
transmitting SYNCp without
entering power down mode.
Host while transmitting

receipt of PMREQ_Pp or
PMREQ_Sp device must not
condition is violated. This check
is active only when
to 0.
SATA_RX_XRDY_DURING_
PMREQ_VIOLATION_N
SATA_SOF_P_MORE_THAN_
ONCE_VIOLATION_P
SATA_SOF_P_MORE_THAN_
ONCE_VIOLATION_N
SATA_SYNC_P_BEFORE_
PMREQP_P_VIOLATION_P
SATA_SYNC_P_BEFORE_
PMREQP_P_VIOLATION_N
SATA_SYNC_P_BEFORE_
PMREQS_P_VIOLATION_P
SATA_SYNC_P_BEFORE_
PMREQS_P_VIOLATION_N
SATA_TX_DMAT_OUTSIDE_
EOF_SOF_VIOLATION_P
SATA_TX_DMAT_OUTSIDE_
EOF_SOF_VIOLATION_N
SATA_TX_DPMREQ_WHILE_
HPMREQ_VIOLATION_P
SATA_TX_DPMREQ_WHILE_
HPMREQ_VIOLATION_N
696
SERIAL ATA (SATA)

Monitor Checks

Check ID
Violation
Description
SATA_TX_HOLD_OUTSIDE_
EOF_SOF_VIOLATION_P
HOLDp primitive must be

EOFp primitive.
HOLDp must be detected within

This check fires when a HOLDp
is transmitted on the tx lines
before detection of SOFp or after
the detection of EOFp primitives.
The latency between the detection

of first HOLDp to the detection of
first HOLDAp must not be more
than 20 dwords.
The maximum allowed latency

from the time the MSB of the
HOLDp primitive is on the wire,
to the MSB of the HOLDAp is on
the wire shall not be more than 20
Dword symbol times. This check
fires when the first HOLDAp
primitive on the tx lines in
response to HOLDp is not seen
within 20 dwords.
SATA_TX_HOLD_OUTSIDE_
EOF_SOF_VIOLATION_N
SATA_TX_HOLDA_P_
LATENCY_VIOLATION_P
SATA_TX_HOLDA_P_
LATENCY_VIOLATION_N
SATA_TX_HOLDA_UNTIL_
HOLD_VIOLATION_P
SATA_TX_HOLDA_UNTIL_
HOLD_VIOLATION_N
HOLDAp must be transmitted as HOLDAp must be transmitted as

long as HOLDp primitive is being long as HOLDp is received. This
received.
other than HOLDAp or SYNCp
or CONTp are detected on the tx
lines when HOLDp is being
received on the rx lines.
SATA_TX_HOLDA_WO_
HOLD_VIOLATION_P
HOLDAp primitive must not be

transmitted without receiving
HOLDp primitive.

HOLDAp on the tx lines without
receiving HOLDp. This check
fires when HOLDAp is detected
on the tx lines without receiving
HOLDp on the rx lines.
The host transmitting X_RDYp

must back off and start
transmitting R_RDYp on
device.
When host is transmitting

X_RDYp, it must back off and
start transmitting R_RDYp on
device. This check fires when
SOFp is detected on the tx lines
when the DEVICE_TYPE
parameter is set to 0 or when
R_RDYp is detected on the tx
lines when the DEVICE_TYPE
PMREQ_Sp from the host while
PMREQ_Sp, the device must
continue transmitting PMREQ
and enter power down mode.
Device while transmitting

PMREQ_Sp, on receipt of
PMREQ_Pp or PMREQ_Sp it
must continue transmitting
PMREQ_Pp and the host must
respond with PMACKp or
PMNACKp. This check fires
when the above condition is
violated. This check is active only
when DEVICE_TYPE parameter
is set to 0.
SATA_TX_HOLDA_WO_
HOLD_VIOLATION_N
SATA_TX_HOST_BACK_OFF_
VIOLATION_P
SATA_TX_HOST_BACK_OFF_
VIOLATION_N
SATA_TX_HPMREQ_WHILE_
DPMREQ_VIOLATION_P
SATA_TX_HPMREQ_WHILE_
DPMREQ_VIOLATION_N
697
SERIAL ATA (SATA)

Monitor Checks

Check ID
Violation
Description
SATA_TX_PMACK_WO_
PMREQ_VIOLATION_P
PMACK must not be transmitted

without the receipt of
PMREQ_Pp or PMREQ_Sp.
PMACKp primitive must not be

transmitted on the tx lines,
primitives. This check fires when
PMACKp primitive was detected
without PMREQ_Pp or
PMREQ_Sp primitives.
PMNACK must not be

transmitted without the receipt of
PMREQ_Pp or PMREQ_Sp.
PMNACKp primitive must not be

transmitted on the tx lines,
primitives. This check fires when
PMNACKp primitive was
detected without PMREQ_Pp or
PMREQ_Sp primitives.
R_RDYp must not be transmitted

without receiving X_RDYp.

R_RDYp on the tx lines without
the receipt of X_RDYp. This
check fires when R_RDYp
primitive is detected on the tx
lines without the receipt of
X_RDYp
R_ERRp primitive must be

transmitted until the reception of
SYNCp.
R_ERRp must be transmitted on

tx lines until the reception of
SYNCp on the rx lines. This
other than R_ERRp is detected on
the tx lines before the reception of
SYNCp on the rx lines.
While transmitting HOLDp or

must be transmitted after
receiving EOFp.
While transmitting HOLDp or

must be transmitted after
receiving EOFp. This check fires
when any primitive other than
R_IPp or the one that was being
transmitted is transmitted on tx
lines before receiving EOFp on
the rx lines is detected.

primitive.

primitive. This check fires when
R_OKp is detected on the tx lines
when the frame was received with
transfer count mismatch.
SATA_TX_PMACK_WO_
PMREQ_VIOLATION_N
SATA_TX_PMNACK_WO_
PMREQ_VIOLATION_P
SATA_TX_PMNACK_WO_
PMREQ_VIOLATION_N
SATA_TX_R_RDY_WO_
X_RDY_VIOLATION_P
SATA_TX_R_RDY_WO_
X_RDY_VIOLATION_N
SATA_TX_RERR_UNTIL_
SYNC_VIOLATION_P
SATA_TX_RERR_UNTIL_
SYNC_VIOLATION_N
SATA_TX_RIP_AFTER_EOF_
VIOLATION_P
SATA_TX_RIP_AFTER_EOF_
VIOLATION_N
SATA_TX_ROK_FOR_
TX_CNT_ERR_VIOLATION_P
SATA_TX_ROK_FOR_
TX_CNT_ERR_VIOLATION_N
698
SERIAL ATA (SATA)

Monitor Checks

Check ID
Violation
Description
SATA_TX_ROK_UNTIL_SYNC_
VIOLATION_P
R_OKp primitive must be

SYNCp.
R_OKp must be transmitted on tx

lines until the reception of
SYNCp on the rx lines. This
other than R_OKp is detected on
the tx lines before the reception of
SYNCp on the rx lines.
SOFp must not be transmitted

without receiving R_RDYp.

SOFp on the tx lines without
receiving R_RDYp. This check
fires when SOFp is detected on
the tx lines without the receipt of
R_RDYp on the rx lines.
On receipt of SYNCp, the

SYNCp primitive must be
transmitted.
Host or device on reception of

SYNCp must start transmitting
SYNCp on the tx lines. This
other than SYNCp or the
primitive that was being detected
is detected on the tx lines.
On detection of SOFp without the

transmission of R_RDY, any
primitive other than SYNCp must
not be transmitted until the
reception of SYNCp.
On detection of SOFp without the

transmission of R_RDY, any
primitive other than SYNCp must
not be transmitted on tx lines until
the reception of SYNCp on the rx
lines. This check fires on
detection of any primitive other
than SYNCp on tx lines when
SOFp was detected without
R_RDYp.
WTRMp primitive must be

R_OKp or R_ERRp or SYNCp.
WTRMp must be transmitted on

the tx lines until the reception of
R_OKp or R_ERRp on the rx
lines. This check fires when any
primitive other than WTRMp or
SYNCp are detected on the tx
lines before the receipt of R_OKp
or R_ERRp or SYNCp on the rx
lines.
On receipt of X_RDYp while

PMREQ_Sp primitives the host
shall not enter power down mode.
Host or device while transmitting

receipt of X_RDYp it must not
SATA_TX_ROK_UNTIL_SYNC_
VIOLATION_N
SATA_TX_SOF_WO_RRDY_
VIOLATION_P
SATA_TX_SOF_WO_RRDY_
VIOLATION_N
SATA_TX_SYNC_AFTER_
RX_SYNC_VIOLATION_P
SATA_TX_SYNC_AFTER_
RX_SYNC_VIOLATION_N
SATA_TX_SYNC_UNTIL_
SYNC_VIOLATION_P
SATA_TX_SYNC_UNTIL_
SYNC_VIOLATION_N
SATA_TX_WTRM_UNTIL_
STS_VIOLATION_P
SATA_TX_WTRM_UNTIL_
STS_VIOLATION_N
SATA_TX_XRDY_DURING_
PMREQ_VIOLATION_P
SATA_TX_XRDY_DURING_
PMREQ_VIOLATION_N
699
SERIAL ATA (SATA)

Monitor Checks
Transport Layer Checks

Table 16-8. Transport Layer Checks
Check ID
Violation
Description
SATA_AN_IN_SET_DEV_BIT_
VIOLATION_P
In a Set device FIS with

asynchronous notification bit
set to 1, the I bit must be set
to 1 and the status and error
fields must be set to 0.
When device issues asynchronous

notification, the set device bits FIS must
have Interrupt I bit set to one, the
notification N bit set to one, current
status and error field values, and all
reserved fields set to 0. This check
fires when the set device bits with
notification bit is set and violates the
above condition.
Device must not send a Set

device bits FIS with
asynchronous notification bit
set to 1 when the previous
notification was pending.
Device must not send a Set device bits

FIS with Asynchronous notification bit
set to 1 if the host has not
acknowledged the reception of previous
set device bits FIS with Asynchronous
notification bit set to 1. This check
fires when the previous asynchronous
notification was pending and Set device
bits FIS is detected with notification bit
set.
Auto activate bit must be set

to 0 in the DMA setup FIS
sent for a host to device
transfer.
When a DMA setup FIS is transmitted

for a device to host data transfer the auto
activate bit must be set to 0. This
check fires when the auto activate bit is
set in DMA setup FIS for a device to
host data transfer.
BIST activate FIS must have 3

dwords.
When a BIST activate FIS (58h) is

being transmitted, there shall be 3
Dwords transmitted including the FIS
type. This check fires when a BIST
activate FIS with more or less than 3
dwords is issued.
The number of dwords in a

data FIS must not exceed
2048.
When a Data FIS (46h) is being

transmitted, there shall be maximum of
2048 Dwords transmitted excluding the
FIS type and CRC dword. This check
fires when the data payload exceeds
2048 dwords.
Data FIS must not be followed

by another data FIS during
PIO commands.
In PIO IN/OUT transfers, one data FIS

must not be followed by another data
FIS. This check fires when two
consecutive data FISes are detected in
PIO IN/OUT transfers.
SATA_AN_IN_SET_DEV_BIT_
VIOLATION_N
SATA_AN_WHEN_NOTF_
PEND_VIOLATION_P
SATA_AN_WHEN_NOTF_
PEND_VIOLATION_N
SATA_AUTO_ACT_IN_
RD_TX_VIOLATION_P
SATA_AUTO_ACT_IN_
RD_TX_VIOLATION_N
SATA_BIST_ACT_FIS_
COUNT_VIOLATION_P
SATA_BIST_ACT_FIS_
COUNT_VIOLATION_N
SATA_DATA_COUNT_
VIOLATION_P
SATA_DATA_COUNT_
VIOLATION_N
SATA_DATA_FIS_IN_
PIO_CMD_VIOLATION_P
SATA_DATA_FIS_IN_
PIO_CMD_VIOLATION_N
SATA_DATA_NOT_DWORD_
ALIGNED_VIOLATION_P
SATA_DATA_NOT_DWORD_
ALIGNED_VIOLATION_N
700
The data is not dword aligned. The SATA protocol requires that the
data transferred to be dword aligned.
This check fires when data is not dword
aligned.
SERIAL ATA (SATA)

Monitor Checks
Table 16-8. Transport Layer Checks (cont.)

Check ID
Violation
Description
SATA_DEV_RST_CMD_IN_
PM_VIOLATION_P
DEVICE RESET command

must not be issued when port
multiplier is enabled.
Device-reset protocol is not supported

when the monitor is instantiated on a
port multiplier interface. This check
fires when device reset command is
detected. This check is active only when
Good status format violation

for Device Reset command.
On reception of DEVICE_RESET cmd

from the host, the device must transmit
REG device to host FIS to the host with
good status update as in page: 248. This
check fires when the good status format
is violated.
DMA activate FIS must

always be followed by one
data FIS.
In DMA OUT transfers, DMA activate

FIS from the device must always be
followed by data FIS. This check fires
when a FIS other than data FIS follows
DMA activate FIS in case of DMA dataout transfer.
DMA activate FIS must have

1 dword.
When a DMA activate FIS (39h)

(Device to host) is being transmitted,
there shall be 1 Dword transmitted
including the FIS type. This check fires
when a DMA activate FIS with more
than 1 dword is issued.
When auto activate bit is set to

1, for a device to host
transfer, DMA setup FIS must
be followed by Data FIS and
not DMA activate FIS.
When auto activate bit in the DMA

setup FIS, issued for a device to host
transfer is set to 1, it shall not be
followed by DMA activate FIS but must
be followed by data FIS. This check
fires when a FIS other than data FIS
follows a DMA setup FIS with auto
activate bit set.
On receipt of DMA-IN
command from the host, the
device shall transmit either
REG device to host FIS or
data FIS.
A REG host to device FIS with DMAIN command from the host must be
followed by either REG device to host
fis or data FIS. This check fires when a
FIS other than REG device to host or
data FIS follows REG host to device
FIS with DMA IN command.
SATA_DMA_OUT_CMD_
VIOLATION_N
On receipt of DMA-OUT
command from the host, the
device must not transmit any
other FIS other than DMA
activate FIS.
A REG host to device FIS with DMA

OUT command from the host must
always be followed by DMA activate
FIS from the device. This check fires
when a FIS other than DMA activate
FIS follows REG host to device FIS
with DMA OUT command.
SATA_DMA_SETUP_FIS_
COUNT_VIOLATION_P
DMA setup FIS must have 7

dwords.
When a DMA setup FIS (41h) is being

transmitted, there shall be 7Dwords
transmitted including the FIS type. This
check fires when DMA setup FIS with
more or less than 7 dwords is issued.
SATA_DEV_RST_CMD_IN_
PM_VIOLATION_N
SATA_DEV_RST_GS_
VIOLATION_P
SATA_DEV_RST_GS_
VIOLATION_N
SATA_DMA_ACT_CMD_
VIOLATION_P
SATA_DMA_ACT_CMD_
VIOLATION_N
SATA_DMA_ACT_FIS_COUNT_
VIOLATION_P
SATA_DMA_ACT_FIS_COUNT_
VIOLATION_N
SATA_DMA_ACT_WHEN_
AUTO_ACT_VIOLATION_P
SATA_DMA_ACT_WHEN_
AUTO_ACT_VIOLATION_N
SATA_DMA_IN_CMD_
VIOLATION_P
SATA_DMA_IN_CMD_
VIOLATION_N
SATA_DMA_OUT_CMD_
VIOLATION_P
SATA_DMA_SETUP_FIS_
COUNT_VIOLATION_N
701
SERIAL ATA (SATA)

Monitor Checks

Check ID
Violation
SATA_DMA_TRANSFER_
COUNT_VIOLATION_P
In DMA setup FIS, the

In the DMA Setup FIS, the transfer
transfer count register must
count field must be nonzero. It is also
not be set zero except for bit0. required that the low order bit be equal
to zero (indicates even number of bytes
transferred). This check fires when the
transfer count field in the DMA setup
FIS is 0 or when the lower order bit is
nonzero.
SATA_DMA_TRANSFER_
COUNT_VIOLATION_N
SATA_EX_DIAG_BS_NP_
VIOLATION_P
SATA_EX_DIAG_BS_NP_
VIOLATION_N
SATA_EX_DIAG_BS_P_
VIOLATION_P
SATA_EX_DIAG_BS_P_
VIOLATION_N
SATA_EX_DIAG_GS_NP_
VIOLATION_P
SATA_EX_DIAG_GS_NP_
VIOLATION_N
SATA_EX_DIAG_GS_P_
VIOLATION_P
SATA_EX_DIAG_GS_P_
VIOLATION_N
SATA_FIS_WHEN_SRST_
VIOLATION_P
SATA_FIS_WHEN_SRST_
VIOLATION_N
SATA_LEGACY_QUEUED_
CMD_VIOLATION_P
SATA_LEGACY_QUEUED_
CMD_VIOLATION_N
702
Description
Bad status format violation for

Execute device diagnostics
command of non-packet
feature set.
On execution of EXECUTE_DEVICE_
DIAGNOSTIC command from the host,
the device must transmit REG device to
host FIS with bad status as in page: 247
for the non-packet command feature set.
This check fires when the bad status
format is violated.

Execute device diagnostics
command of packet feature
set.
host FIS with bad status as in page: 247
for the packet command feature set.
This check fires when the bad status
format is violated.

for Execute device diagnostics
command of non-packet
feature set.
On execution of the
EXECUTE_DEVICE_DIAGNOSTIC
command from the host, the device must
transmit REG device to host FIS with
good status to the host as in page: 246
for non-packet command feature set.
This check fires when the good status
format is violated.

for Execute device diagnostics
command of packet feature
set.
host FIS with good status to the host as
in page: 246 for the packet command
feature set.This check fires when the
good status format is violated.
Device must not perform any

operation when SRST bit is
set
When the device is put into soft reset

through the SRST bit in the REG host to
device FIS, the device shall not perform
any operation until a FIS from the host
with SRST bit cleared is received. This
check fires when any FIS other than
REG host to device FIS with SRST bit
cleared, is received or transmitted when
the device is subjected to soft reset.
READ or WRITE queued

Legacy queued commands must not be
commands must not be issued. issued when the LEGACY_QUEUED_
COMMAND_ENABLE parameter is
cleared. This check fires when a legacy
queued command is detected when the
LEGACY_QUEUED_COMMAND_
ENABLE parameter is set to 0.
SERIAL ATA (SATA)

Monitor Checks

Check ID
Violation
Description
SATA_NCQ_CMD_
VIOLATION_P
NCQ command must not be

issued.
Native queued commands must not be

issued when the NCQ_COMMAND_
ENABLE parameter is cleared. This
check fires when a native queued
command is detected when the
NCQ_COMMAND_ENABLE
The command tag in the

native queued command must
not be greater than the
maximum queue depth.
Every native queued command will

have a command tag value. By default,
Serial ATA requires the tag value to be
in the range of 0 to 31 when the queue
depth is 32. This check fires when the
tag value is greater than or equal to the
MAX_QUEUE_DEPTH parameter.
This check is active only when
NCQ_COMMAND_ENABLE
Reg FIS transmitted in

response to the NCQ
command from the host must
have I bit set to 0.
Reg FIS transmitted by the device in

response to the NCQ commands must
have the Interrupt bit I set to 0. This
check fires when the REG device to host
FIS transmitted in response to native
queued command has the interrupt bit
I set.
Response for a NCQ

command must not be sent
without the NCQ command
being outstanding.
DMADma setup FIS must not be sent in

response to NCQ commands with a tag
number for which the NCQ command
was not outstanding. This check fires
when a DMA setup FIS with a tag
number for which there was no NCQ
command pending is detected. This
check is active only when
NCQ_COMMAND_ENABLE
parameter is set.
Status for a NCQ command

must not be sent without the
NCQ command being
outstanding.
Set device bits FIS must not be sent with

the sactive field set, when NCQ
command for the respective tag number
was not outstanding. This check fires
when the sactive field is set and its
respective NCQ command was not
pending. This check is active only when
NCQ_COMMAND_ENABLE
parameter is set.
Status for a NCQ command

must not be sent without the
response for the same.
Status for NCQ command should be

sent only after detecting a response for
the commands. This check is active only
when NCQ_COMMAND_ENABLE
parameter is set.
PIO setup FIS must always be

followed by one data FIS.
When the device sends PIO setup FIS, it

must be followed by data FIS
irrespective of whether it is PIO-IN or
PIO-OUT transfers. This check fires
when the PIO setup FIS is followed by a
FIS other than data FIS.
SATA_NCQ_CMD_
VIOLATION_N
SATA_NCQ_QUEUE_DEPTH_
VIOLATION_P
SATA_NCQ_QUEUE_DEPTH_
VIOLATION_N
SATA_NCQ_REG_D2H_STS_
VIOLATION_P
SATA_NCQ_REG_D2H_STS_
VIOLATION_N
SATA_NCQ_RESP_WO_CMD_
VIOLATION_P
SATA_NCQ_RESP_WO_CMD_
VIOLATION_N
SATA_NCQ_STS_WO_CMD_
VIOLATION_P
SATA_NCQ_STS_WO_CMD_
VIOLATION_N
SATA_NCQ_STS_WO_RESP_
VIOLATION_P
SATA_NCQ_STS_WO_RESP_
VIOLATION_N
SATA_NO_DATA_AFTER_
PIO_SETUP_VIOLATION_P
SATA_NO_DATA_AFTER_
PIO_SETUP_VIOLATION_N
703
SERIAL ATA (SATA)

Monitor Checks

Check ID
Violation
Description
SATA_NON_NCQ_CMD_STS_
VIOLATION_P
SATA_NON_NCQ_CMD_STS_
VIOLATION_N
On reception of legacy
command when NCQ
command is pending the REG
FIS sent by the device in
response must have ERR and
ABRT bits set to 1 and BSY
bit cleared.
Upon receiving a legacy ATA command

while a native queued command is
outstanding, the device shall signal the
error condition to the host by
transmitting a REG FIS with the ERR
and ABRT bits set to one and the BSY
bit cleared to zero in the status field of
the FIS. This check fires when REG
device to host FIS is detected in
response to a legacy command when
native queued command was pending
violating the above conditions. This
check is active only when
NCQ_COMMAND_ENABLE
parameter is set.
SATA_NON_NCQ_WHEN_NCQ_
PENDING_VIOLATION_P
Legacy command must not be

issued when NCQ command
is still pending.
The host shall not issue a non-ncq

command while a native queued
command is outstanding. This check
fires on detection of legacy command
when a native queued command is
outstanding. This check is active only
when NCQ_COMMAND_ENABLE
parameter is set.

commands other than Execute
device diagnostics, device
reset, and soft reset
commands.
On reception of NON DATA or PIO or

DMA commands from host, the device
shall transmit REG device to host FIS
with bad status as described in the
command description in ATA/ATAP-5
(T13/d1321R2) clause 8 and I bit must
be set to 1. This check fires when the
bad status format is violated.
SATA_OTHER_CMD_GS_
VIOLATION_N

for commands other than
Execute device diagnostics,
device reset, and soft reset
commands.
On reception of NON DATA or PIO or

DMA commands from host, the device
shall transmit REG device to host FIS
with good status as described in the
command description in ATA/ATAP-5
(T13/d1321R2) clause 8 and I bit must
be set to 1. This check fires when the
SATA_PACKET_CMD_
VIOLATION_P
Packet queued command must

not be issued.
Packet command must not be issued

when the PACKET_COMMAND_
ENABLE parameter is set to 0. This
check fires when a packet command is
detected when the
PIO setup FIS must have 5

dwords.
When a PIO setup FIS (5Fh) is being

transmitted, there shall be 5Dwords
transmitted including the FIS type. This
check fires when a PIO setup FIS with
more or less than 5 dwords is issued.
SATA_NON_NCQ_WHEN_NCQ_
PENDING_VIOLATION_N
SATA_OTHER_CMD_BS_
VIOLATION_P
SATA_OTHER_CMD_BS_
VIOLATION_N
SATA_OTHER_CMD_GS_
VIOLATION_P
SATA_PACKET_CMD_
VIOLATION_N
SATA_PIO_SETUP_FIS_
COUNT_VIOLATION_P
SATA_PIO_SETUP_FIS_
COUNT_VIOLATION_N
704
SERIAL ATA (SATA)

Monitor Checks

Check ID
Violation
Description
SATA_PIO_SETUP_STS_
VIOLATION_P
The PIO setup FIS transmitted

during PIO-IN or PIO-OUT
command must have I bit set
to 1 and ERR bit set to 0.
PIO setup FIS transmitted in response to

the PIO IN/OUT command must have I
bit set to 1 and ERR bit set to 0.
In PIO setup FIS the transfer

count register must not be set
zero except for bit0.
In the PIO setup FIS, the Transfer Count

value must be nonzero. It is also
required that the low order bit be equal
to zero (indicates even number of bytes
transferred). This check fires when the
transfer count field in the PIO setup FIS
is 0 or when the lower order bit is
nonzero.
On receipt of packet command

from the host, the device must
transmit PIO setup FIS with I
bit set to 1.
Reception of packet command should

always be followed by transmission of
PIO setup FIS by the device with I bit
set to 1. The check fires when a FIS
other than PIO setup FIS follows REG
host to device FIS with packet
command.
On receipt of READ LOG

EXT command from the host,
the device must send Set
device FIS with ERR=0,
ERROR REG =0, SActive
field = 0xffffffff and I=0.
When the host has responded to an error

FIS with a READ LOG EXT command
with log page = 0x10, the device must
transmit a Set device bits FIS with ERR
in the status field = 0, ERROR = 0,
SActive field = 0xFFFFFFFF, and
Interrupt bit I = 0. This check fire when
the above condition is violated.
Reg device to host FIS must

have 5 dwords.
When a Reg FIS (34h), (Device to host)

is being transmitted, there shall be 5
type. This check fires when a REG
device to host FIS with more or less
than 5 dwords is issued.
The Reg FIS transmitted in

response PIO-IN command
must have I bit set to 1 and
ERR bit set to 1.
Reg FIS transmitted in response to the

PIO-IN command must have I bit set to
1 and ERR bit set to 1. This check
fires when the above condition is
violated.
Reg host to device FIS must

have 5 dwords.
When a Reg FIS (27h), (Host to device)

is being transmitted, there shall be 5
type. This check fires when a REG host
to device FIS with more or less than 5
dwords is issued.
SATA_PIO_SETUP_STS_
VIOLATION_N
SATA_PIO_TRANSFER_
COUNT_VIOLATION_P
SATA_PIO_TRANSFER_
COUNT_VIOLATION_N
SATA_PKT_CMD_PIO_SETUP_
VIOLATION_P
SATA_PKT_CMD_PIO_SETUP_
VIOLATION_N
SATA_RD_LOG_CMD_STS_
VIOLATION_P
SATA_RD_LOG_CMD_STS_
VIOLATION_N
SATA_REG_D2H_FIS_COUNT_
VIOLATION_P
SATA_REG_D2H_FIS_COUNT_
VIOLATION_N
SATA_REG_D2H_STS_
VIOLATION_P
SATA_REG_D2H_STS_
VIOLATION_N
SATA_REG_H2D_FIS_COUNT_
VIOLATION_P
SATA_REG_H2D_FIS_COUNT_
VIOLATION_N
705
SERIAL ATA (SATA)

Monitor Checks

Check ID
Violation
Description
SATA_REL_BIT_IN_CMD_
VIOLATION_P
Reg FIS with REL bit set to

1 must be sent to the host
immediately after the receipt
of legacy queued command or
packet command and not in
between data.
A REG device to host FIS with the REL

bit set to 1 shall be issued only in
response to a READ DMA QUEUED or
WRITE DMA QUEUED command
from the host. This check fires when a
REG host to device FIS with REL bit set
is not preceded by READ DMA
QUEUED or WRITE DMA QUEUED
commands.
The reserved bits in dword of

the REG_H2D_FIS must be
set to zero.
Reserved fields in the fises are required

to be set to zero during frame
transmission. This check fires when the
reserved field in the transmitted FIS are
not set to 0. This check is active only
when RESERVED_VALUE_
CHECKING_ENABLE parameter is set
to 1.
Reg device to host FIS must

not be transmitted with SERV
bit set to 1 in the status
register.
The Reg device to host FIS should not

be transmitted with the SERV bit set to
1 in the Status Register when BSY or
DRQ bits are not set. This check fires
when a REG device to host FIS is issued
with SERV bit set when BSY and DRQ
bits are cleared.
Service command must not be

issued.
Service command must not be issued

when LEGACY_QUEUED_
COMMAND_ENABLE and
parameters are cleared. This check fires
when a service command is detected
when the LEGACY_QUEUED_
COMMAND_ENABLE and
parameters are set to 0.
Set device bits FIS must have

2 dwords.
When a Set device bits FIS (A1h) is

being transmitted, there shall be 2
type. This check fires when a Set device
bits FIS with more or less than 2
Dwords is issued.
SATA_REL_BIT_IN_CMD_
VIOLATION_N
SATA_RESERVED_FIELD_
VIOLATION_P
SATA_RESERVED_FIELD_
VIOLATION_N
SATA_SERV_IN_REG_D2H_
FIS_VIOLATION_P
SATA_SERV_IN_REG_D2H_
FIS_VIOLATION_N
SATA_SERVICE_CMD_
VIOLATION_P
SATA_SERVICE_CMD_
VIOLATION_N
SATA_SET_DEV_FIS_COUNT_
VIOLATION_P
SATA_SET_DEV_FIS_COUNT_
VIOLATION_N
SATA_SRST_BS_NP_
VIOLATION_P
SATA_SRST_BS_NP_
VIOLATION_N
SATA_SRST_BS_P_
VIOLATION_P
SATA_SRST_BS_P_
VIOLATION_N
706
Bad status format violation for On reception of REG device to host FIS
Soft reset protocol of nonwith SRST bit cleared, the device must
packet feature set.
bad status as in page 244 for the nonpacket command feature set.This check
fires when the bad status format is
violated.
Bad status format violation for On reception of REG device to host FIS
Soft reset protocol of packet
with SRST bit cleared, the device must
feature set.
bad status as in page 244 for the packet
command feature set.This check fires
when the bad status format is violated.
SERIAL ATA (SATA)

Monitor Checks

Check ID
Violation
Description
SATA_SRST_GS_NP_
VIOLATION_P

for Soft reset protocol of nonpacket feature set.
On reception of REG device to host FIS

transmit REG FIS with good status as in
page 244 for the non-packet command
feature set. This check fires when the

for Soft reset protocol of
packet feature set.
On reception of REG device to host FIS

good status as in page 244 for the packet
command feature set.This check fires
when the good status format is violated.
SATA_SRST_GS_NP_
VIOLATION_N
SATA_SRST_GS_P_
VIOLATION_P
SATA_SRST_GS_P_
VIOLATION_N
SAPIS Checks
Table 16-9. SAPIS Checks
Check ID
Violation
SATA_COMWAKE_IN_
PARTIAL_VIOLATION_P
COMWAKE must not be asserted While in partial power down mode,

when partial signal is asserted.
the host or device shall come out of
power down state by transmitting
COMWAKE only after the partial
signal from the link is de-asserted.
COMWAKE is transmitted by the
device or host when the partial signal
remains asserted. This check is
applicable only for SAPIS interface.
SATA_COMWAKE_IN_
PARTIAL_VIOLATION_N
SATA_COMWAKE_IN_
SLUMBER_VIOLATION_P
SATA_COMWAKE_IN_
SLUMBER_VIOLATION_N
SATA_CR_CI_AND_CW_
ACTIVE_VIOLATION_P
SATA_CR_CI_AND_CW_
ACTIVE_VIOLATION_N
Description
COMWAKE must not be asserted While in slumber power down mode,

when partial signal is asserted.
the host or device shall come out of
power down by transmitting
COMWAKE only after the slumber
signal from the link is de-asserted.
COMWAKE is transmitted by the
device or host when the slumber
signal remains asserted. This check is
applicable only for SAPIS interface.
The comreset_cominit_detect and The comreset_cominit_detect and
comwake inputs should not be
comwake_detect input signals of the
asserted high at the same instant. SAPIS interface must not be asserted
at the same instant. This check fires
when both comreset_cominit_detect
and comwake_detect signals are
equal to 1.
707
SERIAL ATA (SATA)

Link Layer Normal and Corner Cases
Table 16-9. SAPIS Checks (cont.)

Check ID
Violation
Description
SATA_PARTIAL_SLUMBER_
ACTIVE_VIOLATION_P
The partial and slumber inputs

should not be asserted at the same
instant.
The partial and slumber input signals

of the SAPIS interface must not be
asserted at the same instant. This
check fires when both partial and
slumber signals are equal to 1.
SATA_PARTIAL_SLUMBER_
ACTIVE_VIOLATION_N
SATA_SAPIS_COMRESET_
COMINIT_DETECT_UNKN_
PSATA_SAPIS_COMRESET_
COMINIT_DETECT_UNKN_N
Signal COMRESET_DETECT or Signal COMRESET_DETECT or

COMINIT_DETECT is not
COMINIT_DETECT must always
be driven to a valid level.
SATA_SAPIS_COMWAKE_
DETECT_UNKN_PSATA_SAPIS
COMWAKE_DETECT_UNKN_N
Signal COMWAKE_DETECT is
Signal COMWAKE_DETECT must

always be driven to a valid level.
SATA_SAPIS_K28_5_DETECT_
UNKN_PSATA_SAPIS_K28_5_
DETECT_UNKN_N
Signal K28.5_DETECT is not

Signal K28.5_DETECT must always

SATA_SAPIS_PARTIAL_
UNKN_PSATA_SAPIS_
PARTIAL_UNKN_N
Signal PARTIAL is not driven to

a valid level.
Signal PARTIAL must always be

SATA_SAPIS_RX_DATA_
UNKN_PSATA_SAPIS_RX_
DATA_UNKN_N
Receive data (RX_DATA) is not

Receive data (RX_DATA) must

SATA_SAPIS_RX_DATA_
VALID_UNKN_PSATA_SAPIS_
RX_DATA_VALID_UNKN_N
Signal RX_DATA_VALID is not

Signal RX_DATA_VALID must

SATA_SAPIS_RX_LOCKED_
UNKN_PSATA_SAPIS_RX_
LOCKED_UNKN_N
Signal RX_LOCKED is not

Signal RX_LOCKED must always

SATA_SAPIS_SLUMBER_
UNKN_PSATA_SAPIS_
SLUMBER_UNKN_N
Signal SLUMBER is not driven

to a valid level.
Signal SLUMBER must always be

SATA_SAPIS_TX_DATA_
UNKN_PSATA_SAPIS_TX_
DATA_UNKN_N
Transmit data (TX_DATA) is not

Transmit data (TX_DATA) must

SATA_SAPIS_TX_ENABLE_
UNKN_PSATA_SAPIS_TX_
ENABLE_UNKN_N
Signal TX_ENABLE is not

Signal TX_ENABLE must always be


Figure 16-10 shows the link layer normal cases.
Table 16-10. Link Layer Normal Cases
708
Normal Case
Description
Total number of primitives
This gives the total number of primitives detected.
SERIAL ATA (SATA)

Table 16-10. Link Layer Normal Cases (cont.)

Normal Case
Description
Total number of malformed frames.
Number of FISes that were malformed i.e. FIS dword

count was violated.
Total number of transactions that exceeded the

transfer count.
Number of transactions whose data payload exceeded the

transfer count specified in the PIO setup FIS.
Total number of transactions that had less transfer

count.
Number of transactions whose data payload was less than

the transfer count specified in the PIO setup FIS.
Total number of frames with CRC error.
Number of frames that were transmitted with CRC error.
Maximum bus idle time.
Maximum time for which the bus was idle.
Minimum bus idle time.
Minimum time for which the bus was idle.
Maximum number of bytes in DATA FIS.
Maximum number of bytes in DATA FIS.
Minimum number of bytes in DATA FIS.
Minimum number of bytes in DATA FIS.
Maximum number of DATA FISes in one PIO

transfer.
Maximum number of DATA FISes in one PIO transfer.
Minimum number of DATA FISes in one PIO

transfer.
Minimum number of DATA FISes in one PIO transfer.
Maximum number of DATA FISes in one DMA

transfer.
Maximum number of DATA FISes in one DMA transfer.
Minimum number of DATA FISes in one DMA

transfer.
Minimum number of DATA FISes in one DMA transfer.
Maximum time after which HOLDAp was

received in response to HOLDp.
Maximum time after which HOLDAp was received in

response to HOLDp.
Minimum time after which HOLDAp was

received in response to HOLDp.
Minimum time after which HOLDAp was received in

response to HOLDp.
Maximum time after which EOFp was received in

response to DMATp.
Maximum time after which EOFp was received in

response to DMATp.
Minimum time after which EOFp was received in

response to DMATp.
Minimum time after which EOFp was received in

response to DMATp.
Maximum time after which R_OKp or R_ERRp

was received in response to EOFp.
Maximum time after which R_OKp or R_ERRp was

received in response to EOFp.
Minimum time after which R_OKp or R_ERRp

was received in response to EOFp.
Minimum time after which R_OKp or R_ERRp was

received in response to EOFp.
Figure 16-11 shows the link layer corner cases.

Table 16-11. Link Layer Corner Cases
Corner Case
Description
Total number of times COMWAKE detected
This statistics gives the total number of COMWAKEs

detected.
709
SERIAL ATA (SATA)

Table 16-11. Link Layer Corner Cases (cont.)
710
Corner Case
Description
Total number of times Partial initiated
This gives the total number times partial power down mode
was initiated by the transmission of PMREQp.
Total number of times Slumber initiated
This gives the total number times slumber power down mode
was initiated by the transmission of PMREQp.
Total number of times Partial entered
This gives the total number times partial power down mode
was entered by the transmission of PMACKp.
Total number of times Slumber entered
This gives the total number times slumber power down mode
was entered by the transmission of PMACKp.
Total number of ALIGNp
This gives the total number of ALIGNp primitives detected.
Total number of CONTp
This gives the total number of CONTp primitives detected.
Total number of DMATp
This gives the total number of DMATp primitives detected.
Total number of EOFp
This gives the total number of EOFp primitives detected.
Total number of HOLDp
This gives the total number of HOLDp primitives detected.
Total number of HOLDAp
This gives the total number of HOLDAp primitives detected.
Total number of PMACKp
This gives the total number of PMACKp primitives detected.
Total number of PMNACKp
This gives the total number of PMNACKp primitives

detected.
Total number of PMREQ_Pp (Partial)
This gives the total number of PMREQ_Pp primitives

detected.
Total number of PMREQ_Sp (Slumber)
This gives the total number of PMREQ_Sp primitives

detected.
Total number of R_ERRp
This gives the total number of R_ERRp primitives detected.
Total number of R_IPp
This gives the total number of R_IPp primitives detected.
Total number of R_OKp
This gives the total number of R_OKp primitives detected.
Total number of R_RDYp
This gives the total number of R_RDYp primitives detected.
Total number of SOFp
This gives the total number of SOFp primitives detected.
Total number of SYNCp
This gives the total number of SYNCp primitives detected.
Total number of X_RDYp
This gives the total number of X_RDYp primitives detected.
Total number of WTRMp
This gives the total number of WTRMp primitives detected.
Total number of frame transfers that were put

on hold by HOLDp
This gives the total number of frame transfers that were put
on hold (one statistic for each interface).
Total number of DMA setup FIS
This gives the total number of DMA set-up FIS.
Total number of BIST Activate FIS
This gives the total number of BIST set-up FIS.
Total number of DATA FIS
This gives the total number of DATA FIS.
SERIAL ATA (SATA)

Transport Layer Normal and Corner Cases

Figure 16-12 shows the transport layer normal cases.
Table 16-12. Transport Layer Normal Cases
Normal Cases
Description
Total number of times COMRESET detected
This statistics gives the total number of COMRESET

detected.
Total number of good statuses sent through REG FIS. Number of good statuses send through REG FIS
device to host.
Total number of bad statuses sent through REG FIS.
Number of bad statuses send through REG FIS

device to host.
Maximum number of NCQ commands outstanding.
Maximum number of NCQ commands outstanding.
Bitmap of the tags taken by the NCQs
Bitmap of the tags taken by the NCQs.
Figure 16-13 shows the transport layer corner cases.

Table 16-13. Transport Layer Corner Cases
Corner Cases
Description
Total number of times COMINIT detected
This statistics gives the total number of COMINIT

detected.
Total number of unsolicited COMINITs detected
This statistic gives the total number of unsolicited

COMINITs detected.
Total number of aborted transaction
This gives the total number of transactions which was

aborted by setting the ABORT bit in the error register.
Total number of times SRST bit was set to "1"
This gives the total number of times SRST bit was set in
the Reg host to device FIS.
Total number of REG device to host FIS
This gives the total number of REG device to host FISes.
Total number of REG host to device FIS
This gives the total number of REG host to device FISes.
Total number of PIO setup FIS
This gives the total number of PIO set-up FIS.
Total number of DMA Activate FIS
This gives the total number of DMA Activate FIS.
Total number of SET Device bits FIS
This gives the total number of SET Device bits FIS.
Total number of DEVICE RESET command
This gives the total number of DEVICE RESET

command.
Total number of SET FEATURE command
This gives the total number of SET FEATURE

command.
Total number of IDENTIFY DEVICE command
This gives the total number of IDENTIFY DEVICE

command.
Total number of READ LOG EXT command
This gives the total number of READ LOG EXT

command.
711
SERIAL ATA (SATA)

Table 16-13. Transport Layer Corner Cases (cont.)

Corner Cases
Description
Total number of NON-DATA commands
This gives the total number of NON-DATA commands.
Total number of PIO data-in command
This gives the total number of PIO data-in command.
Total number of PIO data-out command
This gives the total number of PIO data-out command.
Total number of DMA data-in command
This gives the total number of DMA data-in command.
Total number of DMA data-out command
This gives the total number of DMA data-out command.
Total number of PACKET command
This gives the total number of PACKET command.
Total number of READ DMA QUEUED command
This gives the total number of READ DMA QUEUED

command.
Total number of WRITE DMA QUEUED command
This gives the total number of WRITE DMA QUEUED

command.
Total number of READ FPDMA command
This gives the total number of READ FPDMA

command.
Total number of WRITE FPDMA command
This gives the total number of WRITE FPDMA

command.
Total number of REG device to host FIS with ERR

bit set
This gives the total number of REG FIS with ERR bit
set.
Total number of SET Device bits FIS with ERR bit

set
This gives the total number of SET Device bits FIS with
ERR bit set.
Total number of PIO setup FIS with ERR bit set
This gives the total number of PIO setup FIS with ERR
bit set.
Total number of DMA setup FIS with Auto activate

bit set.
This gives the total number of DMA set-up FIS with

Auto activate bit set.
Total number of times Asynchronous notification

requested by the device and serviced with REG FIS.
This gives the total number of times Asynchronous

notification requested by the device and serviced with
REG FIS.
Total number of SET device bits FISes with SERV

bit set.
This gives the total number of times SERV bit in the

SET device bits FIS was set.
Total number REG device to host FISes with REL bit

set to "1".
This gives the total number of times REL bit in the REG
FIS set to "1".
Total number of successful PIO data-in transfers
Successful PIO data-in transfers. Transfers for which a

REG device to host FIS with err bit set to 0 and error
register with all bits set to 0.
Successful PIO data-out transfers
Successful PIO data-out transfers. Transfers for which a

Successful DMA data-in transfers
Successful DMA data-in transfers. Transfers for which a

Successful DMA data-out transfers
Successful DMA data-out transfers. Transfers for which

a REG device to host FIS with err bit set to 0 and error
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SERIAL ATA (SATA)

Table 16-13. Transport Layer Corner Cases (cont.)

Corner Cases
Description
Successful READ DMA QUEUED transfers
Successful READ DMA QUEUED transfers. Transfers

for which a REG device to host FIS with err bit set to
0 and error register with all bits set to 0.
Successful WRITE DMA QUEUED transfers
Successful WRITE DMA QUEUED transfers. Transfers

for which a REG device to host FIS with err bit set to
0 and error register with all bits set to 0.
Successful READ FPDMA transfers
Successful READ FPDMA transfers. Transfers for

which a Set device bits FIS with Sactive bit for the
corresponding command tag set to 1.
Successful WRITE FPDMA transfers
Successful WRITE FPDMA transfers. Transfers for

corresponding command tag set to 1.
Unsuccessful PIO data-in transfers
Unsuccessful PIO data-in transfers. Transfers for which

a REG device to host FIS with err bit set to 1 or error
register with one of its bits set to 1.
Unsuccessful PIO data-out transfers
Unsuccessful PIO data-out transfers. Transfers for which

a REG device to host FIS with err bit set to 1 or error
register with one of its bits set to 1.
Unsuccessful DMA data-in transfers
Unsuccessful DMA data-in transfers. Transfers for

which a REG device to host FIS with err bit set to 1 or
error register with one of its bits set to 1.
Unsuccessful DMA data-out transfers
Unsuccessful DMA data-out transfers. Transfers for

which a REG device to host FIS with err bit set to 1 or
error register with one of its bits set to 1.
Unsuccessful READ DMA QUEUED transfers
Unsuccessful READ DMA QUEUED transfers.

Transfers for which a REG device to host FIS with err
bit set to 1 or error register with one of its bits set to
1.
Unsuccessful WRITE DMA QUEUED transfers
Unsuccessful WRITE DMA QUEUED transfers.

Transfers for which a REG device to host FIS with err
bit set to 1 or error register with one of its bits set to
1.
Unsuccessful READ FPDMA transfers
Unsuccessful READ FPDMA transfers. Transfers for

corresponding command tag was set to 0 and err bit
was set to 1.
Unsuccessful WRITE FPDMA transfers
Unsuccessful WRITE FPDMA transfers. Transfers for

corresponding command tag was set to 0 and err bit
was set to 1.
ALL ncq tags covered
This corner case is set to 1 when all the bits in

ncq_tags_bitmap statistic is set to 1.
713
SERIAL ATA (SATA)

Monitor FAQ
Monitor FAQ
Following are answers to frequently asked questions (FAQ) about the QVL SATA monitor.
1. What are the various interfaces supported by the monitor?
The QVL SATA monitor supports the following interfaces:
o
Serial interface (instantiate the SATA monitor).
10B parallel interface (instantiate the SATA monitor).
SAPIS interface (instantiate the SATA_SAPIS monitor).
2. What are the various devices supported by the monitor?

The SATA monitor can be instantiated on a SATA compliant host or device design
under test. The DEVICE_TYPE parameter, when set to "0," indicates that the monitor is
instantiated in a SATA compliant host. If the parameter is set to "1", then it indicates
that the monitor is instantiated in a SATA compliant device.
3. What do the tx_ and rx_ prefixes signify?
The tx_ prefix indicates the transmit signals of the design under test, and rx_ prefix
indicates the receive signals of the design under test.
4. Is there an option to skip power on and speed negotiation sequence?
The monitor provides an option to skip power on and speed negotiation sequence. The
bypass_power_on_seq input port is used to skip power on and speed negotiation
sequence when tied to "1." However, the monitor expects the device under test to
transmit and receive a minimum of two ALIGNp primitives followed by three SYNCp
primitives to obtain locking.
5. How do I disable scrambling?
The monitor provides a port named scrambling_off. When the incoming data is not
scrambled, set the scrambling_off input to 1. This disables the descrambler in the
monitor.
6. Why is the DOUBLE_DATA_RATE parameter provided?
The DOUBLE_DATA_RATE parameter configures the active edges of the SATA clock. By
default, the clocks are active only on the rising edge. The monitor can be configured
such that the clock is active on the rising edge as well as on the falling edge. This
parameter is required to be set to "1" when the design under test is active on both the
clock edges.
7. Is it possible to disable scrambling for the TX lanes only?
No, scrambling and de-scrambling is disabled only for the test mode of operation and
only can be disabled for the device as a whole.
714
SERIAL ATA (SATA)

Monitor FAQ
8. How does the monitor perform symbol lock?

The monitor uses the ALIGNp primitive or D24.3 character to perform symbol lock. The
monitor samples the serial bits and waits until a proper ALIGNp primitive or D24.3
character is detected. The monitor considers detection of an ALIGNp primitive or D24.3
character as symbol lock.
9. How is the SATA monitor instantiated on a parallel interface?
The SATA monitor tracks serial as well as parallel interfaces. To track a 10-bit or 20-bit
or 40-bit parallel interface, do the following:
10-bit parallel interface:
parameter to 1 and the PARALLEL_DATA_WIDTH parameter to 10. Leave
tx_data_minus and rx_data_minus unconnected. Connect the tx_data_plus
and rx_data_plus ports with 10b encoded values from the transmit and receive
interfaces, respectively. The bit order of the 10b encoded parallel data should be as
follows: {j,h,g,f,i,e,d,c,b,a}. Bit names are taken from the standard 8b/10b
20-bit parallel interface:
parameter to 1 and the PARALLEL_DATA_WIDTH parameter to 20. Leave
tx_data_minus and rx_data_minus unconnected. Connect the tx_data_plus
and rx_data_plus ports with 10b encoded values from the transmit and receive
interfaces respectively. The bit order of the 10b encoded parallel data should be as
follows: {j,h,g,f,i,e,d,c,b,a}. Bit names are taken from the standard 8b/10b
encoding/decoding schemes. The SATA monitor assumes the first K-code sits on the
least significant byte of the 20B interface.
10. On the SATA Serial interface, why does the SATA monitor have clock signals,
when the SATA Serial Interface does not specify clock signals?
On the SATA Serial Interface, the clock is embedded in the data streams. Usually
the SATA PHY implementation should have a clock recovery logic. This recovered
clock could be accessed through hierarchical referencing.
The SATA monitor does not have clock recovery logic internally. Therefore,
connect the recovered clock from the PHY model to the SATA monitor.
11. What is the significance of the MAX_DEV_SPEED parameter?
This parameter configures the monitor for the maximum speed support by the design
under test. For instance, if the design under test supports both GEN1 and GEN2 speeds,
then this parameter must be set to "1."
12. Does the monitor support the Packet command feature set?
715
SERIAL ATA (SATA)

Monitor FAQ
Yes, the PACKET_COMMAND_ENABLE parameter must be set to "1" to enable the tracking
of the packet command feature set.
13. Does the monitor support the Legacy queued command feature?
Yes, the LEGACY_QUEUED_COMMAND_ENABLE parameter must be set to "1" to enable the
tracking of the legacy queued commands.
14. Does the monitor support the Native command queuing?
Yes, the NCQ_COMMAND_ENABLE parameter must be set to "1" to enable the tracking of
the NCQ commands.
15. What is the significance of the PORT_MULTIPLIER_ENABLE parameter?
When the monitor is instantiated in a design under test with a SATA compliant port
multiplier device or host interface, this parameter must be set to "1" to indicate the
monitor is instantiated on the port multiplier interface.
16. What is the significance of PORT_SELECTOR_ENABLE parameter?
When the monitor is instantiated in a design under test with a SATA compliant port
selector device or host interface, this parameter must be set to "1" to indicate the monitor
is instantiated on the port selector interface.
17. When is it required to set the ASYNCHRONOUS_SIGNAL_RECOVERY
parameter?
When the monitor is instantiated in a DUT that supports Asynchronous signal recovery
and the monitor is required to track ASR, this parameter has to be set to "1".
18. What is the purpose of the RETRY_INTERVAL parameter?
The default value of this parameter is set to 14999250 (GEN1 clocks = 10ms). In case
the user wants to reconfigure this value, this parameter is provided to override the
default value set in the monitor. This is used for debugging purpose.
19. What are the parameters that need to be configured in the monitor to enable
tracking of the NCQ commands?
The NCQ_COMMAND_ENABLE parameter must be set to "1". Also, configure the
MAX_QUEUE_DEPTH parameter to the maximum allowed. NCQ commands can be
outstanding at a particular instant. If the design under test allows a maximum of 16 NCQ
commands to be outstanding, then set this parameter to 16.
20. What is the significance of the LINK_SIDE parameter in SAPIS monitor?
This parameter indicates whether the monitor is instantiated on the LINK side or the
PHY side of the SAPIS interface. Set this to "0" if the monitor is instantiated on the
PHY side of the SAPIS interface. By default, the monitor is instantiated on the LINK
side of the SAPIS interface.
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SERIAL ATA (SATA)

Monitor FAQ
21. The design under test is compliant to the SATA I specification. How do I configure
the monitor?
The parameters NCQ_COMMAND_ENABLE and ASYNC_SIGNAL_RECOVERY must be set to
"0".
717
SERIAL ATA (SATA)

Monitor FAQ
718
Chapter 17
Serial Parallel Interface (SPI) Monitor
Introduction
The Serial Parallel Interface (SPI) module allows a duplex, synchronous, serial communication
between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI
operation can be interrupt driven. The QVL SPI monitor is designed for checking the SPI
interface.
This QVL SPI monitor is modeled from the requirements provided in the following documents:
SPI Block Guide, V03.06, February 04, 2003
Supported Features
SPI supports the following features:
Master Mode and Slave Mode
Multiple Slave
SPI Clock Polarity Bit
SPI Clock Phase Bit
LSB-First Enable
SPI Baud Rate Divisor

The QVL SPI monitor can be placed on the master or slave side to provide interface checks. The
checks in the SPI monitor can also be used as search targets and check constraints while running
formal analysis on the SPI master or slave devices. A typical SPI setup is shown in Figure 17-1.
719

Figure 17-1. SPI Monitor Implementation
SPI
Master
SPI
Slave
SPI Interface
QVL
QVL
Connect the SPI Master or Slave monitor pins to internal signals as specified in the pin-out
Table 17-1 and illustrated in Figure 17-2.
Figure 17-2. SPI Monitor Pins Diagram
clk
reset
areset
sck
mosi
ss
miso
active_slave_count
baudrate_divisor
lsbfe
cpol
cpha
SPI Monitor
Table 17-1. SPI Monitor Pins Description
720
Pins
Description
clk
Reference clock
reset
Synchronous reset, active high
areset
Asynchronous reset, active high
sck
Serial Clock
mosi
Master Output, Slave Input
ss
Slave Select, active low
miso
Master Input, Slave Output
active_slave_count
Number of slave count

Table 17-1. SPI Monitor Pins Description (cont.)

Pins
Description
baudrate_divisor
Baudrate divisor. Sets the baud rate divisor for the externally
generated clock (SCK) from the system clock.
lsbfe
LSB-First Enable. If lsbfe == 1, then data is transferred, least

significant bit first.
cpol
Clock Polarity Bit. If cpol == 1, then active low clock is

selected and SCK is high in idle state.
cpha
Clock Phase Bit. If cpha == 1, then sampling of data occurs at

even edges of SCK clock.
Monitor Parameters
SPI monitor to track the SPI Master and SPI Slave devices.
Table 17-2. SPI Monitor Parameters
Order Parameters
Default Description
1.
Constraints_Mode
This parameter configures the checks in the monitor as

constraints during formal analysis.
2.
SS_WIDTH
This parameter configures the number of slaves connected.
3.
MASTER_MODE
This parameter configures QVL in Master Mode.
SPI Monitor Instantiation Example

Example 17-1 instantiates an SPI monitor on an SPI master interface. The number of slave
connected is 1.
Example 17-1. SPI Monitor Master Interface
qvl_spi_monitor #(
.SS_WIDTH(1),
.MASTER_MODE(1)
)
spi_monitor (
.clk(dut_clk),
.reset(dut_reset),
.areset(dut_areset),
.sck(dut_sck),
.mosi(dut_mosi),
.ss(dut_ss),
721

Monitor Checks
.miso(dut_miso),
.active_slave_count(dut_active_slave_count),
.baudrate_divisor(dut_baudrate_divisor),
.lsbfe(dut_lsbfe),
.cpol(dut_cpol),
.cpha(dut_cpha)
);
Monitor Checks
Table 17-3 shows the monitor checks performed by the SPI monitor.
Table 17-3. SPI Master Checks
Check ID
Violation
Description
SPI_CPHA_CHANGE_DURING_
TRANSFER_P
Transmission abort due to

change in CPHA during
transfer.
When transfer is in progress, then CPHA

should not be changed and changing of
CPHA will lead into idle state.
Transmission abort due to

change in CPOL during
transfer.
When transfer is in progress, then CPOL

should not be changed and changing of
CPOL will lead into idle state.
SPI_CPHA_CHANGE_DURING_
TRANSFER_N
SPI_CPOL_CHANGE_DURING_
TRANSFER_P
SPI_CPOL_CHANGE_DURING_
TRANSFER_N
SPI_LSBFE_CHANGE_DURING_ Transmission abort due to
TRANSFER_P
change in LSBFE during
transfer.
SPI_LSBFE_CHANGE_DURING_
TRANSFER_N
When transfer is in progress, then

LSBFE should not be changed and
changing of LSBFE will lead into idle
state.
SPI_INVALID_SS_DURING_
TRANSFER_P
When transfer is in progress, SS should

be low for a slave.
SS should be low during

transfer.
SPI_INVALID_SS_DURING_
TRANSFER_N
722
Chapter 18
System Packet Interface Level 4 Phase 2
(SPI4-2)
Introduction
System Packet Interface Level 4 Phase 2 (SPI4-2) is an interface for packet and cell transfer
between a physical layer (PHY) device and a Link layer device for aggregate bandwidths of
OC-192 ATM and Packet over SONET/SDH (POS), as well as 10Gb/s Ethernet applications.
SPI4-2 is the system packet interface for data transfer between the Link layer and the PHY
device. Transmit and Receive refer, respectively, to data flow and associated control/status
information from the Link Layer to PHY, and from the PHY to Link layer devices.
Mentor Graphics (0-In) provides the following two QVL monitors designed for checking SPI42 interface implementations:
SPI4-2 Receive monitor

This monitor checks the Receive Interface of SPI4-2 protocol.
SPI4-2 Transmit monitor

This monitor checks the Transmit Interface of SPI4-2 protocol.
In addition to the main specification, the SPI4-2 monitors support the following extensions:
Control Word Extension
Narrow Interface Applications
Hit-Less Bandwidth Reprovisioning
The SPI-4.2 monitors can also be configured to verify POS-PHY L4 interface implementations.
Please refer to the later sections of this chapter for information on configuring the SPI-4.2
monitors for these implementations.
System Packet Interface Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical
and Link Layer Devices; January 2001
723
System Packet Interface Level 4 Phase 2 (SPI4-2)

Receive Monitor
Receive Monitor
The SPI4-2 Receive interface monitor supports data path and FIFO status interfaces. It provides
programmability for the following:
Enable/disable of FIFO status interface.
LVTTL_IO (Single edge clocking) or LVDS_IO_P (Double edge clocking) mode.
Enable/disable of Control Word Extension (Appendix E of the reference document).
Enable/disable of Narrow Band Interface OC-48 implementation (Appendix F of the

reference document).
Enable/disable of Hit-less Bandwidth Reprovisioning (Appendix G of the reference

document).

To use the 0-In SPI4-2 Receive monitor, place an instance of the monitor inside the PHY layer
device or the Link layer device as shown in Figure 18-1.
Figure 18-1. SPI4-2 Receive Monitor Implementation
rdclk
rdat
rctl
LINK Layer
rstat
rsclk
PHY Layer
SPI4-2
Receive
Monitor
or
LINK Layer
SPI4-2
Receive
Monitor
rdclk
rdat
rctl
PHY Layer
rstat
rsclk
Connect the SPI4-2 Receive monitor pins to internal signals as specified in the pin out
724

Receive Monitor
Figure 18-2. SPI4-2 Receive Monitor Pin Diagram

rdclk
rdat
rctl
rsclk
rstat
areset
reset
port_addresses
max_burst_1_x
max_burst_2_x
data_max_t_x
calendar_len_x
calendar_m_x
calendar_sequence_x
l_max_x
data_training_sequences_cnt_x
fifo_max_t_x
max_packet_len_x
min_packet_len_x
max_burst_1_y
max_burst_2_y
data_max_t_y
calendar_len_y
calendar_m_y
calendar_sequence_y
l_max_y
data_training_sequences_cnt_y
fifo_max_t_y
max_packet_len_y
min_packet_len_y
ports_count
lvds_io
fifo_valid_sync_or_training_delay
control_word_extension_enable
bandwidth_reprovisioning_enable
enable_fifo_status_if
SPI4-2
Receive Monitor
Table 18-1. SPI4-2 Receive Monitor Pins

Pin
Description
areset
Enables (1) and disables (0) the Hit-less Bandwidth Reprovisioning

feature discussed in Appendix G of the reference document. If this pin is
set to 1'b0, then only signals that belong to parameter set X are used by
the monitor. Use this pin only when ports are used to configure the
monitor (i.e., when USE_PORTS_TO_CONFIGURE_P is set to 1).
calendar_len_x
calendar_len_y
Length of the FIFO status sequence.
725

Receive Monitor
Table 18-1. SPI4-2 Receive Monitor Pins (cont.)
726
Pin
Description
calendar_m_x
calendar_m_y
Number of times the FIFO status sequence is repeated within the

synchronous pattern (RSTAT = 2'b11) boundary.
calendar_sequence_x
calendar_sequence_y
Port address sequence in which the FIFO status for all the ports is sent on
the FIFO status interface. The number of slots in a FIFO status sequence
is equal to the number of slots in the calendar sequence.
The order in which port addresses are wired to calendar_sequence_x
(calendar_sequence_y) configures the order in which status information is
sent on the FIFO status interface in a calendar length sequence. That is,
there is an exact one-to-one mapping between calendar_sequence_x order
and the status sequence order. For example, suppose there are four ports,
the calendar length is 6, and the port addresses sequence in which the
FIFO status is sent is 0, 1, 2, 3, 0, 1. Configure these signals as follows:
Status of port addresses 0 and 1 are sent twice on the FIFO status
sequence.
Status of port addresses 2 and 3 are sent only once.
The calendar_sequence_x/ calendar_sequence_y in the monitor
instantiation should be connected as follows:
.calendar_sequence_x (
{32'd0,32'd1,32'd2, 32'd3,32'd0,32'd1}),
.calendar_sequence_y (
{32'd0,32'd1,32'd2, 32'd3,32'd0,32'd1}),
Note that the port address should always be 32-bits wide when it is
connected to the monitor.
Enables (1) and disables (0) the Payload control word extension feature
discussed in the Appendix E of the reference document. Use this pin only
when ports are used to configure the monitor (i.e., when
USE_PORTS_TO_CONFIGURE_P is set to 1).
Note that when the control word extension feature is enabled, the port
address is derived only from the normal control word and the first
extension control word. Subsequent extension control words are userdefined or application-specific, and therefore, are not processed by
the monitor.
data_max_t_x
data_max_t_y
Maximum interval (in RDCLK half clock cycles) within which at least
data_training_sequences_cnt_x number of Training sequences are
expected. Set these parameters to 0 to disable Training sequence on the
data path interface.
Number of Training sequences expected on the data path interface for

every data_max_t_x (data_max_t_y) clock edges.
Enables(1) and disables (0) the FIFO status interface. By default, tracking
of the FIFO status interface is enabled. Use this pin only when ports are
used to configure the monitor (i.e., when
fifo_max_t_x
fifo_max_t_y
Maximum interval (in RSCLK half clock cycles for LVDS_IO_P mode,
or in RSCLK cycles for LVTTL_IO mode) within which at least one
Training sequence is expected on the FIFO status interface. Set these
parameters to 0 to disable the Training sequence on the FIFO interface.

Receive Monitor
Table 18-1. SPI4-2 Receive Monitor Pins (cont.)

Pin
Description
Maximum time (in RSCLK half clock cycles) for the start of the Training
sequence on the FIFO interface when LVDS_IO_P mode is enabled. For
LVTTL mode, fifo_valid_sync_or_training_delay is the maximum time
(in RSCLK cycles) for the start of SYNC pattern on FIFO interface. Use
this pin only when ports are used to configure the monitor (i.e., when
l_max_x
l_max_y
Maximum response time (in RDCLK half clock cycles) of the Data path
interface logic to respond to change in FIFO status. Note: l_max_x
(l_max_y) corresponds to the worst case response time after the FIFO
status becomes SATISFIED. Response time is defined as the interval
from reception of status update on the FIFO status channel for a port to its
reflection in the data path interface when payload transfer from that port
is in progress.
lvds_io
Clocking mode for the FIFO status interface. Set to 1'b1 if the FIFO status
is to be updated on both positive and negative edges of RSCLK
(LVDS_IO_P mode). Set to 1'b0 to update status only on the positive
edge of RSCLK (LVTTL_IO mode). Use this pin only when ports are
max_burst_1_x
max_burst_1_y
Maximum number of 16 byte blocks data that the FIFO can accept when
FIFO status channel indicates STARVING.
max_burst_2_x
max_burst_2_y
FIFO status channel indicates HUNGRY. Parameter of set X.
max_packet_len_x
max_packet_len_y
Maximum size of a packet on the data path interface.
min_packet_len_x
min_packet_len_y
Minimum size of a packet on the data path interface.
port_addresses
Concatenated input of all the port addresses that are to be tracked. Every
port address should be 32-bits wide. Note that all port addresses used in
the design should be connected.
ports_count
Number of ports tracked by the monitor. Use this pin only when ports are
rctl
Receive control, high indicates Control word and low indicates Payload
(Data burst).
rdat
Receive data bus.
rdclk
Receive data clock, both edges active.
reset
rsclk
Receive status clock, rising edge or both edges active depending on

LVTTL or LVDS mode of operation.
rstat
Receive FIFO status.
Port signals with _x and _y suffixes are configurable parameter signals. These signals
are required to support the Hit-less Bandwidth reprovisioning feature specified in
727

Receive Monitor
Appendix G of the SPI4-2 specification. Signals with _x belong to parameter set X, and
signals with _y belong to parameter set Y. Parameter set X is selected if the Calendar
Selection Word (sent on the FIFO status interface) value is 2'b01. Parameter set Y is
selected if the Calendar Selection Word value is 2'b10. If your implementation does not
support the bandwidth reprovisioning feature, then use parameter set X to configure the
monitor. You can leave signals of parameter set Y unconnected.
When the USE_PORTS_TO_CONFIGURE_P parameter is set to 1, then the values

connected to the following ports are used in the monitor:
o
ports_count
lvds_io
The values on these ports can change only during reset and must remain constant until
the next reset.
When the USE_PORTS_TO_CONFIGURE_P parameter is set to 0, then the Verilog
parameters listed in Table 18-2 are used to configure the monitor.
Monitor Parameters
The parameters in Table 18-2 configure the SPI4-2 Receive monitor.
Table 18-2. SPI4-2 Receive Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode

2.
LINK_SIDE_P

instantiated within the LINK layer or PHY device.
By default, the monitor is configured to reside within
the LINK layer. Set this parameter to 0 if it is
instantiated in the PHY device.
3.
PORTS_COUNT_P
This parameter indicates the number of ports that

exist in the design. The monitor tracks all the ports in
the design.
Note that when parameter USE_PORTS_TO_
CONFIGURE_P is set to 0, the monitor tracks all
of the ports in the design. When parameter
USE_PORTS_TO_CONFIGURE_P is set to 1,
parameter PORTS_COUNT_P should indicate
the total number of ports in the design. The port
ports_count indicates the number of ports tracked
by the monitor.
728

Receive Monitor
Table 18-2. SPI4-2 Receive Monitor Parameters (cont.)

Order Parameter
Default Description
4.
ENABLE_FIFO_STATUS_IF_P
To enable/disable the FIFO status interface. By

default, tracking of the FIFO status interface is
enabled. Set it to 0 to disable tracking.
5.
LVDS_IO_P
Selects the clocking mode for the FIFO status

interface. Set it to 1 if the FIFO status is to be updated
on both the positive and negative edges of RSCLK
(LVDS_IO_P mode). Set it to 0 to update status only
on the positive edge of RSCLK(LVTTL_IO mode).
6.
FIFO_VALID_SYNC_OR_
TRAINING_DELAY_P
Maximum time (in RSCLK half clock cycles) for the

start of Training sequence on FIFO interface when
LVDS_IO_P mode is enabled. For LVTTL mode, it
is the maximum time (in RSCLK cycles) for the start
of SYNC pattern on FIFO interface.
7.
MAX_CALENDAR_LEN_P
256
Maximum length of the FIFO status sequence. This

parameter intakes the value of the maximum possible
calendar length for the design. The calendar length
can be dynamically changed using calendar_len_x &
calendar_len_y.
8.
CONTROL_WORD_
EXTENSION_ENABLE_P
Enables or disables the Payload control word

extension feature discussed in Appendix E of the
reference document. Default is disabled.
Note that when the control word extension
feature is enabled, the port address is derived
only from the normal control word and the first
extension control word. Subsequent extension
control words are user-defined or applicationspecific, and therefore, are not processed by the
monitor.
9.
BANDWIDTH_
0
REPROVISIONING_ENABLE_P
Enables or disables the Hit-less Bandwidth

Reprovisioning feature discussed in Appendix G of
the reference document. If this parameter is set to 0,
then only signals that belong to parameter set X are
used by the monitor. Default is disabled.
10.
NARROW_BAND_
INTERFACE_ENABLE_P
Enables or disables the Narrow band interface feature

discussed in Appendix F of the reference document.
Default is disabled.
11.
USE_PORTS_TO_
CONFIGURE_P
When set to 1, the input ports ports_count, lvds_io,

enable_fifo_status_if,
fifo_valid_sync_or_training_delay,
control_word_extension_enable, and
bandwidth_reprovisioning_enable configure the
monitor. By default, parameters PORTS_COUNT_P,
LVDS_IO_P, ENABLE_FIFO_STATUS_IF_P,
FIFO_VALID_SYNC_OR_TRAINING_DELAY_P,
CONTROL_WORD_EXTENSION_ENABLE_P,
and BANDWIDTH_REPROVISIONING_
ENABLE_P configure the monitor.
729

Receive Monitor
Note that the monitor tracks only the first ports_count number of ports out of
PORTS_COUNT_P number of ports. When you connect the port port_addresses, you must
connect all of the ports in the design. For example, consider a design with four ports (i.e.,
PORTS_COUNT_P is 4). The port_addresses port should be connected as follows:
.port_addresses (addr_1, addr_2, addr_3, addr_4),
If the ports_count port has a value of 2, then the monitor tracks ports with addresses addr_1
and addr_2.
POS-PHY L4 Interface Support

The SPI4-2 transmit monitor can be configured to track POS-PHY L4 implementations. To use
the SPI4-2 transmit monitor as POS-PHY L4 transmit monitor, do the following:
1. Set data_training_sequences_cnt_x signal to 1.
2. Set fifo_max_t_x signal to 0.
3. Set the CONTROL_WORD_EXTENSION_ENABLE_P parameter to 0.
4. Set the BANDWIDTH_REPROVISIONING_ENABLE_P parameter to 0.
5. Set the NARROW_BAND_INTERFACE_ENABLE_P parameter to 0.
Example 1
Example 18-1 instantiates an SPI4-2 Receive monitor within a Link layer device with the
following configuration:
730
Number of ports in the design is 10.
Hit-less Bandwidth Reprovisioning is enabled.
Narrow band interface is disabled.
Number of status slots for this port in a FIFO status sequence is 12.
The max_burst_2_x (for HUNGRY status) is set to 5 and max_burst_1_x (for

STARVING status) is set to 7. The max_burst_2_y (for HUNGRY status) is set to 7
and max_burst_1_y (for STARVING status) is set to 9.
The data path interface response time (L_MAX) is 16 RDCLK half clock cycles. This is the
same for both values of the calendar selection word.
Number of RDCLK half clock cycles for receiving at least three Training sequences is
1000 (DATA_MAX_T). This is the same for both values of the calendar selection word.

Receive Monitor
Length of the FIFO status (CALENDAR_LEN) is set to 12 and the number of FIFO status
sequences within sync (RSTAT = 2'b11) pattern boundary (CALENDAR_M) is set to two.
This is the same for both values of the calendar selection word.
Example 18-1. SPI4-2 Receive Monitor Instantiation
qvl_spi4_2_rx_monitor #(
0,
/* Constraints_Mode*/
1,
/* LINK_SIDE_P */
10,
/* PORTS_COUNT_P */
1,
/* ENABLE_FIFO_STATUS_IF_P */
0,
/* LVDS_IO_P */
5,
/* FIFO_VALID_SYNC_OR_TRAINING_DELAY_P */
12,
/* MAX_CALENDAR_LEN_P */
0,
/* CONTROL_WORD_EXTENSION_ENABLE_P */
1,
/* BANDWIDTH_REPROVISIONING_ENABLE_P */
0 )
/* NARROW_BAND_INTERFACE_ENABLE_P */
SPI4_2_RX_MON(
.rdclk
(rdclk),
.rsclk
(rsclk),
.areset
(areset),
.reset
(reset),
.rdat
(rdat),
.rctl
(rctl),
.rstat
(rstat),
.port_addresses
({32'd0, 32'd1, 32'd2, 32'd3, 32'd4,
32'd5, 32'd6, 32'd7, 32'd8, 32'd9}),
.max_burst_1_x
(7),
.max_burst_2_x
(5),
.data_max_t_x
(1000),
.calendar_len_x
(12),
.calendar_m_x
(2),
.calendar_sequence_x
({32'd0, 32'd1, 32'd2, 32'd3, 32'd4,
32'd5, 32'd0, 32'd1, 32'd6, 32'd7,
32'd8, 32'd9}),
.l_max_x
(16),
.data_training_sequences_cnt_x(3),
.fifo_max_t_x
(500),
.max_packet_len_x
(1000),
.min_packet_len_x
(50),
.max_burst_1_y
(9),
.max_burst_2_y
(7),
.data_max_t_y
(1000),
.calendar_len_y
(12),
.calendar_m_y
(2),
.calendar_sequence_y
({32'd0, 32'd1, 32'd2, 32'd3, 32'd4,
32'd5, 32'd6, 32'd7, 32'd8, 32'd9,
32'd4, 32'd5),
.l_max_y
(16),
.data_training_sequences_cnt_y(3),
.fifo_max_t_y
(500),
.max_packet_len_y
(1000),
.min_packet_len_y
(50) );
731

Receive Monitor
Example 2
Hit-less Bandwidth Reprovisioning is disabled. Therefore, signals that belong to

parameter set Y are left unconnected.
The max_burst_2_x (for HUNGRY status) is set to five and max_burst_1_x (for
STARVING status) is set to seven.
The data path interface response time (L_MAX) is 16 RDCLK half clock cycles.
1000 (DATA_MAX_T).
Length of the FIFO status (CALENDAR_LEN) is set to 12, and the number of FIFO status
sequences within sync (RSTAT = 2'b11) pattern boundary (CALENDAR_M) is set to 2.
0,
1,
/* LINK_SIDE_P */
10,
/* PORTS_COUNT_P */
1,
0,
/* LVDS_IO_P */
5,
12,
0,
0,
0 )
SPI4_2_RX_MON(
.rdclk
(rdclk),
.rsclk
(rsclk),
.areset
(areset),
.reset
(reset),
.rdat
(rdat),
.rctl
(rctl),
.rstat
(rstat),
.port_addresses
({32'd0, 32'd1, 32'd2,
32'd5, 32'd6, 32'd7,
.max_burst_1_x
(7),
.max_burst_2_x
(5),
.data_max_t_x
(1000),
.calendar_len_x
(12),
.calendar_m_x
(2),
({32'd0, 32'd1, 32'd2,
32'd5, 32'd0, 32'd1,
32'd8, 32'd9}),
.l_max_x
(16),
732
32'd3, 32'd4,
32'd8, 32'd9}),
32'd3, 32'd4,
32'd6, 32'd7,

Receive Monitor
.fifo_max_t_x
(500),
.max_packet_len_x
(1000),
.min_packet_len_x
(50)),
Example 3
Maximum number of ports in the design is 10.

The max_burst_2_x (for HUNGRY status) is set to five, and max_burst_1_x (for
The data path interface response time (L_MAX) is 16 RDCLK half clock cycles.
1000 (DATA_MAX_T).
sequences within the sync (RSTAT = 2'b11) pattern boundary (CALENDAR_M) is set to 2.
LVDS_IO_P, CONTROL_WORD_EXTENSION_ENABLE_P,
BANDWIDTH_REPROVISIONING_ENABLE_P, and ENABLE_FIFO_STATUS_IF_P
are
configured through ports.

0,
1,
/* LINK_SIDE_P */
10,
/* PORTS_COUNT_P */
1,
0,
/* LVDS_IO_P */
5,
12,
0,
0,
0,
1 )
/* USE_PORTS_TO_CONFIGURE_P */
SPI4_2_RX_MON(
.rdclk
(rdclk),
.rsclk
(rsclk),
.areset
(areset),
.reset
(reset),
.rdat
(rdat),
.rctl
(rctl),
733

Receive Monitor
.rstat
.port_addresses
(rstat),
({32'd0, 32'd1, 32'd2,
32'd4, 32'd5, 32'd6,
32'd8, 32'd9}),
.max_burst_1_x
(7),
.max_burst_2_x
(5),
.data_max_t_x
(1000),
.calendar_len_x
(12),
.calendar_m_x
(2),
({32'd0, 32'd1, 32'd2,
32'd4, 32'd5, 32'd0,
32'd6, 32'd7, 32'd8,
.l_max_x
(16),
.data_training_sequences_cnt_x
(3),
.fifo_max_t_x
(500),
.max_packet_len_x
(1000),
.min_packet_len_x
(50),
.ports_count
(32'd5),
.lvds_io
(1'b0),
.fifo_valid_sync_or_training_delay(32'd5),
.control_word_extension_enable
(1'b0),
.bandwidth_reprovisioning_enable (1'b0),
.enable_fifo_status_if
(1'b1));
32'd3,
32'd7,
32'd3,
32'd1,
32'd9}),
Monitor Checks
Table 18-3 shows the checks performed by the SPI4-2 Receive monitor.
Table 18-3. SPI4-2 Receive Checks
Check ID
Violation
SPI4_2_RX_00_P
A control word other than Idle

Constraints formal analysis to exercise
Control/Payload Control/Training the pins as per the specification. Failure
Control should not be issued.
to do so can cause the design to
malfunction when formal analysis
controls the pins.
SPI4_2_RX_00_N
SPI4_2_RX_01_P
SPI4_2_RX_01_N
SPI4_2_RX_02_P
SPI4_2_RX_02_N
SPI4_2_RX_03_P
SPI4_2_RX_03_N
734
Description
A Payload Control word should

not be immediately followed by
an Idle Control word.
When the Type field of the control

word indicates Payload, then the
Payload transfer should immediately
follow the control word. This check
fires if Payload Control is followed by

not be immediately followed by a
Training Control word.

follow the control word. This check
fires if Payload Control is followed by
A Training Control word should

During a training sequence, the

Training Control word sequence
should be immediately followed by a
Training Data word. This check fires if
a Training Control word sequence is
followed by an Idle Control word.

Receive Monitor
Table 18-3. SPI4-2 Receive Checks (cont.)

Check ID
Violation
Description
SPI4_2_RX_04_P

Payload Control word.
During a training sequence, the

Training Control word sequence
should be immediately followed by a
Training Data word. This check fires if
a Training Control word sequence is
followed by a Payload Control word.
An Idle Control word should not

be followed by Payload transfer.
An Idle Control word should always be

followed by a Payload Control, or
Training Control, or another Idle
Control word. This check fires if an
Idle Control word is followed by
Payload transfer.
Payload transfer should not be

followed by a Training Control
word.
Payload transfer can terminate only

with an Idle Control or another Payload
Control word. This check fires if the
Payload transfer is terminated by a

not be followed by another

follow the Payload Control word. This
check fires if Payload Control is
followed by another Payload Control
word.
Length of the Training sequence

on the data path should not be
greater than 21 half clock cycles.
Length of the Training sequence is 21

(comprised of 1 Idle Control word, 10
Training Control words, and 10
Training Data words). This check fires
if Training Control or Training Data
words count is greater than 10 half
clock cycles.

on the data path should not be less
than 21 half clock cycles.

Training Control words, and 10
Training Data words). This check fires
if the Training Control or Training
Data words count is less than 10 half
clock cycles.
Payload transfer should end with

an EOP or pause at a 16 byte
block boundary.
Payload transfer to a port can either

end with an EOP or pause at a 16 byte
block boundary. Violation of this
condition causes the check to fire.
DIP4 parity error occurred on the

The monitor calculates DIP4 parity for

various types of transfer as detailed in
the specification. This check fires if a
DIP4 parity is detected on the data path
interface.
At least DATA_TRAINING_
SEQUENCES_CNT number of
Training sequences should occur
on the data path interface for
every DATA_MAX_T half clock
cycles.
There should be at least DATA_

TRAINING_SEQUENCES_CNT
number of training sequence
transmitted for every DATA_MAX_T
number of half clock cycles. This
check fires if no Training sequence is
transmitted for DATA_MAX_T
number of half clock cycles.
SPI4_2_RX_04_N
SPI4_2_RX_05_P
SPI4_2_RX_05_N
SPI4_2_RX_06_P
SPI4_2_RX_06_N
SPI4_2_RX_07_P
SPI4_2_RX_07_N
SPI4_2_RX_08_P
SPI4_2_RX_08_N
SPI4_2_RX_09_P
SPI4_2_RX_09_N
SPI4_2_RX_10_P
SPI4_2_RX_10_N
SPI4_2_RX_11_P
SPI4_2_RX_11_N
SPI4_2_RX_12_P
SPI4_2_RX_12_N
735

Receive Monitor

Check ID
Violation
Description
SPI4_2_RX_13_P
Successive SOPs should be

separated by 8 half clock cycles.
Successive start of packet indications

(using bit 12 of the control word)
should be separated by 8 half clock
cycles. Violation of this condition
causes the check to fire.
Unused byte of a Payload,

terminated by EOP with one byte
valid, should be 0x00 (hex).
On Payload transfers that do not end on

an even byte boundary, the unused byte
(after the last valid byte) should be set
to zero. This check fires if the unused
byte contains a nonzero bit.
SOP should not be issued to a

port when it is in the paused
status.
When a port is in paused status, SOP

should not be issued to the port until
the remaining data is transferred.
Violation of this condition causes the
check to fire.
All the Training Data of a

Training sequence on the data
path should be identical.
All the Training Data in a Training

sequence should be identical. Violation
of this condition causes the check to
fire.

port when an error condition has
been reported on FIFO status
interface.
A continuous stream of 11 pattern on

RSTAT pins signifies an error
condition. Under such cases,
transmission to all the ports should be
stopped until a nonerror status is
indicated on the RSTAT pins. This
check fires if a SOP is issued to a port
when an error has been reported on the
FIFO status interface.

port beyond L_MAX distance,
after the FIFO status became
SATISFIED.
When the FIFO status of a port

becomes SATISFIED, SOP should not
be issued to the port after the L_MAX
response time has elapsed. Violation of
this condition causes the check to fire.
Payload should not be transferred

to a port beyond L_MAX
distance, after the FIFO status
became SATISFIED.

becomes SATISFIED, Payload should
not be transferred to the port after the
L_MAX response time has elapsed.
check to fire.
Size of the Payload transferred to

a port should not exceed the
MAX_BURST_2 limit when its
FIFO is in the HUNGRY
condition.

becomes HUNGRY, the number of 16
byte blocks transferred to it should not
exceed the MAX_BURST_2 limit.
check to fire.

FIFO is in the STARVING
condition.

becomes STARVING, the number of
16 byte blocks transferred to it should
not exceed the MAX_BURST_1 limit.
check to fire.
SPI4_2_RX_13_N
SPI4_2_RX_14_P
SPI4_2_RX_14_N
SPI4_2_RX_15_P
SPI4_2_RX_15_N
SPI4_2_RX_17_P
SPI4_2_RX_17_N
SPI4_2_RX_18_P
SPI4_2_RX_18_N
SPI4_2_RX_19_P
SPI4_2_RX_19_N
SPI4_2_RX_20_P
SPI4_2_RX_20_N
SPI4_2_RX_21_P
SPI4_2_RX_21_N
SPI4_2_RX_22_P
SPI4_2_RX_22_N
736

Receive Monitor

Check ID
Violation
Description
SPI4_2_RX_23_P
Length of the FIFO status

sequence should not be less than
the value of CALENDAR_LEN
multiplied by CALENDAR_M.
The length of the FIFO status sequence

is determined by CALENDAR_LEN
multiplied by CALENDAR_M. This
check fires if a synchronous pattern
(2'b11) occurs before the calculated
number of status slots elapse.

Two bit diagonal interleaved parity

(DIP2) is transmitted at the end of
FIFO status sequence. This check fires
if a DIP2 parity error is detected on the

sequence should not be greater
than the value of
CALENDAR_LEN multiplied by
CALENDAR_M.

(2'b11) does not occur after the
calculated number of status slots have
elapsed.
The value of calendar selection

word should be either 2'b01 or
2'b10.
When Hit-less Bandwidth

reprovisioning feature is enabled, the
calendar selection word that selects one
of two set of parameters X and Y
should be either 2'b01 or 2'b10. This
check fires if the calendar selection
word is either 2'b00 or 2'b11.
When LVDS_IO_P mode is

enabled, training sequences
should be transmitted on FIFO
status interface after reset.
When LVDS_IO_P mode is enabled,

Training sequence should be
transmitted on the FIFO interface after
reset went inactive. This check fires if
there is no start of Training sequence
even after the FIFO_VALID_SYNC_
OR_TRAINING_DELAY number of
RSCLK half clocks have elapsed.
When LVTTL_IO mode is

enabled, framing pattern (2'b11)
should be transmitted on the
FIFO status interface after reset.
When LVTTL_IO mode is enabled,

framing pattern (2'b11) should be
transmitted on FIFO status interface
after reset went inactive. This check
fires if there is no framing pattern even
after the FIFO_VALID_SYNC_
OR_TRAINING_DELAY number of
RSCLK clocks have elapsed.

on the FIFO interface should not
be greater than 20.
The length of the Training sequence on

FIFO status interface is 20 RSCLK half
clock cycles if LVDS_IO_P mode is
enabled, and it is 20 RSCLK cycles if
LVTTL_IO mode is enabled. This
check fires if the length of Training
sequence is greater than 20.
SPI4_2_RX_23_N
SPI4_2_RX_24_P
SPI4_2_RX_24_N
SPI4_2_RX_25_P
SPI4_2_RX_25_N
SPI4_2_RX_27_P
SPI4_2_RX_27_N
SPI4_2_RX_28_P
SPI4_2_RX_28_N
SPI4_2_RX_29_P
SPI4_2_RX_29_N
SPI4_2_RX_30_P
SPI4_2_RX_30_N
737

Receive Monitor

Check ID
Violation
Description
SPI4_2_RX_31_P

be less than 20.

FIFO status interface is 20 RSCLK half
clock cycles if LVDS_IO_ P mode is
enabled, and it is 20 RSCLK cycles if
LVTTL_IO mode is enabled. This
check fires if the length of Training
sequence is less than 20.
At least one Training sequence

should occur on the FIFO
interface for every
FIFO_MAX_T cycles.
At least one Training sequence should

occur on the FIFO interface for every
FIFO_MAX_T RSCLK half clock
cycles if LVDS_IO_P mode is enabled,
or every FIFO_MAX_T RSCLK
cycles if LVTTL_IO mode is enabled.
Violation of this condition causes this
check to fire.
Size of a packet should not be less

than the specified minimum
packet size.
The size of the received packet should

not be less than the value specified by
min_packet_len_x or
min_packet_len_y. Note that
min_packet_len_y is relevant only if
the bandwidth reprovisioning is
enabled.
Size of a packet should not be

greater than the specified
maximum packet size.

not be greater than the value specified
by max_packet_len_x or
max_packet_len_y. Note that
max_packet_len_y is relevant only if
the bandwidth reprovisioning is
enabled.
Reserved encoding should not be

transmitted as part of control
word.
Bits [15:12] of a control word should

not be driven to 4'b0001, 4'b0011,
4'b0001, and 4'b0111. This check fires
if reserved bit values are transmitted.
Note that if control word extension is
enabled, then 4'b0001 and 4'b0111 are
treated as valid combination. In this
case, this checker will not fire.
A Payload control word should

not be issued to a port without
SOP information, when the port is
inactive.
When the port is in the inactive

condition, a payload transfer to the port
should start with an SOP. This check
fires if a payload control is issued to an
inactive port with port address address
without SOP information.
A control word is not transmitted

after indicating the control word
extension.
If there is an extended control word in

the next RDCLK edge, then the current
control word bit combination [15:12]
value equals 4'b0001. This check fires
if the current control word signals an
extended control word, and there is no
control word in the next RDCLK edge.
SPI4_2_RX_31_N
SPI4_2_RX_32_P
SPI4_2_RX_32_N
SPI4_2_RX_33_P
SPI4_2_RX_33_N
SPI4_2_RX_34_P
SPI4_2_RX_34_N
SPI4_2_RX_35_P
SPI4_2_RX_35_N
SPI4_2_RX_36_P
SPI4_2_RX_36_N
SPI4_2_RX_37_P
SPI4_2_RX_37_N
738

Receive Monitor

Check ID
Violation
Description
SPI4_2_RX_38_P
Only Training sequence should

be transmitted on the data path
interface after reset until a valid
FIFO status is received.
After reset, only Training sequence

should be transmitted on the data path
interface until a valid FIFO status is
received. This check fires if a
data/control word other than Training
sequence is transmitted over the data
path interface after reset.
Another SOP should not be

issued to an active port without
completing the previous transfer.
When the port is in active condition,

the current payload transfer can be
terminated with a 16 byte blocks data
boundary (port becomes paused), or an
EOP/EOP abort (port becomes
inactive), or an EOP/EOP abort, and
SOP (port continues to be active). This
check fires if a payload control is
issued to an active port with port
address, address only with SOP.
EOP should not be issued to a

port without a preceding SOP.
Every packet should start with a SOP,

and it should end with an EOP. This
check ensures that every EOP for the
port with port address address is
preceded by a SOP. This check fires
when an EOP is received without a
preceding SOP.
SPI4_2_RX_PARAM_01_P
CALENDAR_LEN should not be

The value of CALENDAR_LEN

less than 1.
CALENDAR_M should not be

The value of CALENDAR_M

less than 1.
MAX_BURST_2 should not be

The value of MAX_BURST_2

less than 1.

MAX_BURST_2.
MAX_BURST_1 value should not be

less than the value of MAX_BURST_2
as per definition of these parameters.
This check fires if MAX_BURST_1 is
specified to be less than
MAX_BURST_2.
DATA_MAX_T should not be

less than the minimum limit of 21
half clock cycles (Training
sequence length).
DATA_MAX_T value should not be

less than the length of the Training
sequence. This check is disabled if
data_max_t_x (data_max_t_y) is set to
0.
FIFO_MAX_T should not be less

FIFO_MAX_T value should not be

fifo_max_t_x (fifo_max_t_y) is set to
0.
SPI4_2_RX_38_N
SPI4_2_RX_39_P
SPI4_2_RX_39_N
SPI4_2_RX_40_P
SPI4_2_RX_40_N
739

Receive Monitor

Check ID
Violation
Description
DATA_TRAINING_
SEQUENCES_CNT should not
be less than the minimum limit of
1.
The value of the DATA_TRAINING_

SEQUENCES_CNT parameter should
not be specified to be less than 1.
Product of CALENDAR_LEN
and CALENDAR_M should not
be less than 16 when
LVDS_IO_P mode is selected.

the product of CALENDAR_LEN and
CALENDAR_M should not be less
than 16. This is required to differentiate
the Training sequence and FIFO status
sequence.
Minimum packet size should not

1.
The min_packet_len_x or
min_packet_len_y parameter should
Maximum packet size should not

be specified to be less than the
minimum packet size.
The max_packet_len_x or
max_packet_len_y parameter value
should not be less than the value of the
respective min_packet_len_x or
min_packet_len_y parameter.
740
The active clock edge for checks SPI4_2_RX_00_P to SPI4_2_RX_22_P and

SPI4_2_RX_33_P to SPI4_2_RX_40_P, which is the positive edge of RDCLK.
The active clock edge for checks SPI4_2_RX_00_N to SPI4_2_RX_22_N, and

SPI4_2_RX_33_N to SPI4_2_RX_40_N, which is the negative edge of RDCLK.
The active clock edge for checks SPI4_2_RX_PARAM_01_P to SPI4_2_RX_PARAM_13_P

is the positive edge of RDCLK. These checks are on parameters and therefore, are coded
to fire only on the first clock edge when both reset and areset are sampled inactive.
Checks SPI4_2_RX_38_P, SPI4_2_RX_18_P to SPI4_2_RX_22_P, and

SPI4_2_RX_38_N, SPI4_2_RX_18_N to SPI4_2_RX_22_N are active only if the
ENABLE_FIFO_STATUS_IF_P parameter is set to 1.
The active clock edge for checks SPI4_2_RX_23_P to SPI4_2_RX_32_P, which is the
positive edge of RSCLK. These checks are active only if the
ENABLE_FIFO_STATUS_IF_P parameter is set to 1.
The active clock edge for checks SPI4_2_RX_23_N to SPI4_2_RX_32_P, which is the
negative edge of RSCLK. These checks are active only if the
ENABLE_FIFO_STATUS_IF_P parameter and the LVDS_IO_P parameter are set to 1.

Receive Monitor

Table 18-4 shows the corner cases captured by the SPI4-2 Receive monitor.
Table 18-4. SPI4-2 Receive Monitor Corner Cases
Corner Case
Description
Number of Packets with Application

Error
Total number of packets transferred with application specific error.
Number of EOPs with one byte valid
Total number of End of Packets (EOPs) issued with only one byte of
the last word being valid.
Number of EOPs with two bytes valid
Total number of End of Packets (EOPs) issued with both the bytes of
Number of Unpaused Packet transfers
Total number of times an entire packet (SOP, data, EOP) is

transferred without interruption. Note that if all packets are transferred
without interruption, then this statistic is equal to the Payload Controls
statistic.
FIFO Status Error Count
Total number of times an error condition (stream of 11 pattern on

RSTAT pins) is reported on the FIFO status interface. This statistic is
zero if the ENABLE_FIFO_STATUS_IF_P parameter is set to 0.
Number of DIP4 Parity Errors
Total number of packets transferred with DIP4 parity error.
Total number of FIFO status sequences transferred with DIP2 parity

error. This statistic is zero if the ENABLE_FIFO_STATUS_IF_P
Number of Idle Controls
Total number of idle control words transferred.
Number of Payload Controls
Total number of payload control words transferred.
Number of Data Path Training

sequences
Total number of training sequences transferred on the data path

interface.
Number of FIFO interface Training

sequences
Total number of training sequences transferred on the FIFO interface.
STARVING FIFO Status Count
Number of times the FIFO status is reported as STARVING on the

FIFO status interface (RSTAT).
HUNGRY FIFO Status Count
Number of times the FIFO status is reported as HUNGRY on the

SATISFIED FIFO Status Count
Number of times the FIFO status is reported as SATISFIED on the

Monitor Statistics
Table 18-5 shows the statistics collected by the SPI4-2 Receive monitor.
Table 18-5. SPI4-2 Receive Monitor Statistics
Statistic
Description
Number of Packets transferred
Total number of Packets transferred between the PHY device and the
Link layer device.
741

Receive Monitor
Table 18-5. SPI4-2 Receive Monitor Statistics (cont.)
742
Statistic
Description
Number of bytes transferred
Total number of bytes transferred between the PHY device and the
Link layer device.
Maximum Packet size
Maximum number of bytes transferred in a single packet.
Maximum number of Idle Controls

between transactions
Maximum number of Idle control words issued between transactions.
Number of Ports that never received

a Packet.
Total number of ports that did not receive any packets.

Transmit Monitor
Transmit Monitor
The SPI4-2 Transmit interface monitor supports data path and FIFO status interfaces. It
provides programmability for the following:
LVTTL_IO (Single edge clocking) or LVDS_IO_P (Double edge clocking) mode.
Enable/disable of Control Word Extension (Appendix E of the reference document).
Enable/disable of Narrow Band Interface OC-48 implementation (Appendix F of the

reference document).
Enable/disable of Hit-less Bandwidth Reprovisioning (Appendix G of the reference

document).

To use the 0-In SPI4-2 Transmit monitor, place an instance of the monitor inside the PHY layer
device or the Link layer device as shown in Figure 18-3.
Figure 18-3. SPI4-2 Transmit Monitor Implementation
tdclk
tdat
tctl
LINK Layer
tstat
tsclk
PHY Layer
SPI4-2
Transmit
Monitor
or
LINK Layer
SPI4-2
Transmit
Monitor
tdclk
tdat
tctl
PHY Layer
tstat
tsclk
Connect the SPI4-2 Transmit monitor pins to internal signals as specified in the pin out
743

Transmit Monitor
Figure 18-4. SPI4-2 Transmit Monitor Pin Diagram

tdclk
tdat
tctl
tsclk
tstat
areset
reset
port_addresses
max_burst_1_x
max_burst_2_x
data_max_t_x
calendar_len_x
calendar_m_x
calendar_sequence_x
l_max_x
fifo_max_t_x
max_packet_len_x
min_packet_len_x
max_burst_1_y
max_burst_2_y
data_max_t_y
calendar_len_y
calendar_m_y
calendar_sequence_y
l_max_y
fifo_max_t_y
max_packet_len_y
min_packet_len_y
ports_count
lvds_io
SPI4-2
Transmit Monitor
Table 18-6. SPI4-2 Transmit Monitor Pins

Pin
Description
areset
bandwidth_reprovisioning_
enable
Enables (1) and disables (0) the Hit-less Bandwidth Reprovisioning feature
discussed in Appendix G of the reference document. If this pin is set to 1'b0,
then only signals that belong to parameter set X are used by the monitor.
Use this pin only when ports are used to configure the monitor (i.e., when
calendar_len_x
calendar_len_y
Length of the FIFO status sequence.
calendar_m_x
calendar_m_y
Number of times the FIFO status sequence is repeated within the

synchronous pattern (TSTAT = 2'b11) boundary.
744

Transmit Monitor
Table 18-6. SPI4-2 Transmit Monitor Pins (cont.)

Pin
Description
calendar_sequence_x
calendar_sequence_y
Port address sequence in which the FIFO status for all the ports is sent on
the FIFO status interface. The number of slots in a FIFO status sequence is
equal to the number of slots in the calendar sequence.
The order in which port addresses are wired to calendar_sequence_x
(calendar_sequence_y) configures the order in which status information is
sent on the FIFO status interface in a calendar length sequence. That is,
there is an exact one-to-one mapping between calendar_sequence_x order
and the status sequence order.
For example, suppose there are four ports, the calendar length is 6, and the
port addresses sequence in which the FIFO status is sent is 0, 1, 2, 3, 0, 1. To
configure these signals:
Status of port addresses 0 and 1 are sent twice on the FIFO status
sequence.
Status of port addresses 2 and 3 are sent only once.
The calendar_sequence_x/calendar_sequence_y in the monitor
instantiation should be connected as follows:
.calendar_sequence_x (
{32'd0,32'd1,32'd2, 32'd3,32'd0,32'd1}),
.calendar_sequence_y (
{32'd0,32'd1,32'd2, 32'd3,32'd0,32'd1}),
Note that the port address should always be 32-bits wide when it is
connected to the monitor.
Enables (1) and disables (0) the Payload control word extension feature
discussed in the Appendix E of the reference document. Use this pin only
when ports are used to configure the monitor (i.e., when
Note that when the control word extension feature is enabled, the port
address is derived only from the normal control word and the first
extension control word. Subsequent extension control words are userdefined or application-specific, and therefore, are not processed by the
monitor.
data_max_t_x
data_max_t_y
Maximum interval (in TDCLK half clock cycles) within which at least
data_training_sequences_cnt_x number of Training sequences are expected.
Set these parameters to 0 to disable Training sequence on the data path
interface.
Number of Training sequences expected on the data path interface for every
data_max_t_x (data_max_t_y) clock edges.
fifo_max_t_x
fifo_max_t_y
Maximum interval (in TSCLK half clock cycles for LVDS_IO_P mode, or
in TSCLK cycles for LVTTL_IO mode) within which at least one Training
sequence is expected on the FIFO status interface. Set these parameters to 0
to disable Training sequence on FIFO interface.
fifo_valid_sync_or_training_
delay
Maximum time (in RSCLK half clock cycles) for the start of the Training
sequence on the FIFO interface when LVDS_IO_P mode is enabled. For
LVTTL mode, fifo_valid_sync_or_training_delay is the maximum time (in
RSCLK cycles) for the start of SYNC pattern on the FIFO interface. Use
this pin only when ports are used to configure the monitor (i.e., when
745

Transmit Monitor
Table 18-6. SPI4-2 Transmit Monitor Pins (cont.)

Pin
Description
l_max_x
l_max_y
Maximum response time (in TDCLK half clock cycles) of the Data path
interface logic to respond to change in FIFO status.
Note that the l_max_x (l_max_y) corresponds to the worst case
response time after the FIFO status becomes SATISFIED. Response
time is defined as the interval from reception of status update on the
FIFO status channel for a port to its reflection in the data path interface
when payload transfer from that port is in progress.
lvds_io
Clocking mode for the FIFO status interface. Set to 1'b1 if the FIFO status is
to be updated on both positive and negative edges of RSCLK (LVDS_IO_P
mode). Set to 1'b0 to update status only on the positive edge of RSCLK
(LVTTL_IO mode). Use this pin only when ports are used to configure the
monitor (i.e., when USE_PORTS_TO_CONFIGURE_P is set to 1).
max_burst_1_x
max_burst_1_y
FIFO status channel indicates STARVING.
max_burst_2_x
max_burst_2_y
FIFO status channel indicates HUNGRY. Parameter of set X.
max_packet_len_x
max_packet_len_y
Maximum size of a packet on the data path interface.
min_packet_len_x
min_packet_len_y
Minimum size of a packet on the data path interface.
port_addresses
Concatenated input of all the port addresses that are to be tracked. Every
port address should be 32-bits wide. Note that all the port addresses that are
used in the design should be connected.
ports_count
Number of ports tracked by the monitor. Use this pin only when ports are
reset
tctl
Transmit control, high indicates Control word and low indicates Payload
(Data burst).
tdat
Transmit data bus.
tdclk
Transmit data clock, both edges active.
tsclk
Transmit status clock, rising edge or both edges active depending on

LVTTL or LVDS mode of operation.
tstat
Transmit FIFO status.
746
Port signals with _x and _y suffixes are configurable parameter signals. These signals
are required to support the Hit-less Bandwidth reprovisioning feature specified in
Appendix G of the SPI4-2 specification. Signals with _x belong to parameter set X, and
signals with _y belong to parameter set Y. Parameter set X is selected if the Calendar
Selection Word (sent on the FIFO status interface) value is 2'b01. Parameter set Y is
selected if the Calendar Selection Word value is 2'b10. If your implementation does not

Transmit Monitor
support the bandwidth reprovisioning feature, use parameter set X to configure the
monitor. You can leave signals of parameter set Y unconnected.
When the USE_PORTS_TO_CONFIGURE_P parameter is set to 1, then the values

connected to the following ports are used in the monitor:
o
ports_count
lvds_io
The values on these ports can change only during reset and must remain constant until
the next reset.
When the USE_PORTS_TO_CONFIGURE_P parameter is set to 0, then the Verilog
parameters listed in Table 18-7 are used to configure the monitor.
Monitor Parameters
The parameters in Table 18-7 configure the SPI4-2 Transmit monitor.
Table 18-7. SPI4-2 Transmit Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode

2.
LINK_SIDE_P

instantiated within the LINK layer or PHY device. By
default, the monitor is configured to reside within the
LINK layer. Set this parameter to 0 if it is instantiated
in the PHY device.
3.
PORTS_COUNT_P
This parameter indicates the number of ports that exist

in the design. The monitor tracks all the ports in the
design.
Note that when parameter USE_PORTS_TO_
CONFIGURE_P is set to 0, the monitor tracks all
of the ports in the design. When parameter
USE_PORTS_TO_CONFIGURE_P is set to 1,
parameter PORTS_COUNT_P should indicate the
total number of ports in the design. The port
ports_count indicates the number of ports tracked
by the monitor.
4.
LVDS_IO_P
Selects the clocking mode for the FIFO status interface.

Set it to 1 if the FIFO status is to be updated on both the
positive and negative edges of TSCLK (LVDS_IO_P
mode). Set it to 0 to update status only on the positive
edge of TSCLK(LVTTL_IO mode).
747

Transmit Monitor
Table 18-7. SPI4-2 Transmit Monitor Parameters (cont.)

Order Parameter
Default Description
5.
FIFO_VALID_SYNC_OR_
TRAINING_DELAY_P
6.
MAX_CALENDAR_LEN_P 256
Maximum length of the FIFO status sequence. This

parameter intakes the value of maximum possible
calendar length for the design. The calendar length can
be dynamically changed using calendar_len_x &
calendar_len_y.
7.
CONTROL_WORD_
EXTENSION_ENABLE_P
To enable/disable the Payload control word extension

feature discussed in the Appendix E of the reference
document.
Note that when control word extension feature is
enabled, port address is derived only from the
normal control word and the first extension control
word. Subsequent extension control words are user
defined or application specific, and therefore, are
not processed by the monitor.
8.
BANDWIDTH_
REPROVISIONING_
ENABLE_P
To enable/disable the Hit-less Bandwidth

Reprovisioning feature discussed in Appendix G of the
reference document. If this parameter is set to 0, then
only signals that belong to parameter set X are used by
the monitor.
9.
NARROW_BAND_
INTERFACE_ENABLE_P
To enable/disable the Narrow band interface feature

discussed in Appendix F of the reference document.
10.
USE_PORTS_TO_
CONFIGURE_P
When set to 1, the input ports ports_count, lvds_io,

enable_fifo_status_if,
fifo_valid_sync_or_training_delay,
control_word_extension_enable, and
bandwidth_reprovisioning_enable configure the
monitor. By default, the parameters
PORTS_COUNT_P, LVDS_IO_P,
ENABLE_FIFO_STATUS_IF_P,
FIFO_VALID_SYNC_OR_TRAINING_DELAY_P,
CONTROL_WORD_EXTENSION_ENABLE_P, and
BANDWIDTH_REPROVISIONING_ENABLE_P
configure the monitor.
Maximum time (in TSCLK half clock cycles) for the

start of Training sequence on FIFO interface when
LVDS_IO_P mode is enabled. For LVTTL mode, it is
the maximum time (in TSCLK cycles) for the start of
SYNC pattern on FIFO interface.
Note that the monitor tracks only the first ports_count number of ports out of
PORTS_COUNT_P number of ports. When you connect the port port_addresses, you must
connect all of the ports in the design. For example, consider a design with four ports (i.e.,
PORTS_COUNT_P is 4). The port_addresses port should be connected as follows:
port_addresses (addr_1, addr_2, addr_3, addr_4),
If the ports_count port has a value of 2, then the monitor tracks ports with addresses addr_1
and addr_2.
748

Transmit Monitor
POS-PHY L4 Interface Support

The SPI4-2 transmit monitor can be configured to track POS-PHY L4 implementations. To use
the SPI4-2 transmit monitor as POS-PHY L4 transmit monitor, do the following:
1. Set data_training_sequences_cnt_x signal to 1.
2. Set fifo_max_t_x signal to 0.
3. Set the CONTROL_WORD_EXTENSION_ENABLE_P parameter to 0.
4. Set the BANDWIDTH_REPROVISIONING_ENABLE_P parameter to 0.
5. Set the NARROW_BAND_INTERFACE_ENABLE_P parameter to 0.
Example 1
Example 18-4 instantiates an SPI4-2 Transmit monitor within a Link layer device with the
Hit-less Bandwidth Reprovisioning is enabled.
Number of status slot for this port in a FIFO status sequence is 12.
STARVING status) is set to seven. The max_burst_2_y (for HUNGRY status) is set to
seven and max_burst_1_y (for STARVING status) is set to nine.
The data path interface response time (L_MAX) is 16 TDCLK half clock cycles. This is the
same for both values of the calendar selection word.
Number of TDCLK half clock cycles for receiving at least three Training sequences is
1000 (DATA_MAX_T). This is the same for both values of the calendar selection word.
sequences within synchronous (TSTAT = 2'b11) pattern boundary (CALENDAR_M) is set
to 2. This is the same for both values of the calendar selection word.
Example 18-4. SPI4-2 Transmit Monitor Instantiation
qvl_spi4_2_tx_monitor #(
0,
1,
/* LINK_SIDE_P */
10,
/* PORTS_COUNT_P */
0,
/* LVDS_IO_P */
5,
749

Transmit Monitor
12,
0,
1,
0 )
SPI4_2_TX_MON(
.tdclk
(tdclk),
.tsclk
(tsclk),
.areset
(areset),
.reset
(reset),
.tdat
(tdat),
.tctl
(tctl),
.tstat
(tstat),
.port_addresses
({32'd0, 32'd1, 32'd2,
32'd5, 32'd6, 32'd7,
.max_burst_1_x
(7),
.max_burst_2_x
(5),
.data_max_t_x
(1000),
.calendar_len_x
(12),
.calendar_m_x
(2),
({32'd0, 32'd1, 32'd2,
32'd5, 32'd0, 32'd1,
32'd8, 32'd9}),
.l_max_x
(16),
.fifo_max_t_x
(500),
.max_packet_len_x
(1000),
.min_packet_len_x
(50),
.max_burst_1_y
(9),
.max_burst_2_y
(7),
.data_max_t_y
(1000),
.calendar_len_y
(12),
.calendar_m_y
(2),
.calendar_sequence_y
({32'd0, 32'd1, 32'd2,
32'd5, 32'd6, 32'd7,
32'd4, 32'd5),
.l_max_y
(16),
.data_training_sequences_cnt_y(3),
.fifo_max_t_y
(500),
.max_packet_len_y
(1000),
.min_packet_len_y
(50) );
32'd3, 32'd4,
32'd8, 32'd9})
32'd3, 32'd4,
32'd6, 32'd7,
32'd3, 32'd4,
32'd8, 32'd9,
Example 2
750


Transmit Monitor
The max_burst_2_x (for HUNGRY status) is set to five, and max_burst_1_x (for
The data path interface response time (L_MAX) is 16 TDCLK half clock cycles.
1000 (DATA_MAX_T).
sequences within synchronous (RSTAT = 2'b11) pattern boundary (CALENDAR_M) is set
to 2.
0,
1,
/* LINK_SIDE_P */
10,
/* PORTS_COUNT_P */
0,
/* LVDS_IO_P */
5,
12,
0,
0,
0 )
SPI4_2_TX_MON(
.tdclk
(tdclk),
.tsclk
(tsclk),
.areset
(areset),
.reset
(reset),
.tdat
(tdat),
.tctl
(tctl),
.tstat
(tstat),
.port_addresses
({32'd0, 32'd1, 32'd2,
32'd5, 32'd6, 32'd7,
.max_burst_1_x
(7),
.max_burst_2_x
(5),
.data_max_t_x
(1000),
.calendar_len_x
(12),
.calendar_m_x
(2),
({32'd0, 32'd1, 32'd2,
32'd5, 32'd0, 32'd1,
32'd8, 32'd9}),
.l_max_x
(16),
.fifo_max_t_x
(500),
.max_packet_len_x
(1000),
.min_packet_len_x
(50)),
32'd3, 32'd4,
32'd8, 32'd9}),
32'd3, 32'd4,
32'd6, 32'd7,
Example 3
751

Transmit Monitor
Maximum number of ports in the design is 10.

The data path interface response time (L_MAX) is 16 TDCLK half clock cycles.
1000 (DATA_MAX_T).
sequences within the synchronous (RSTAT = 2'b11) pattern boundary (CALENDAR_M) is
set to 2.
LVDS_IO_P, CONTROL_WORD_EXTENSION_ENABLE_P, and

BANDWIDTH_REPROVISIONING_ENABLE_P are configured
through ports.

0,
1,
/* LINK_SIDE_P */
10,
/* PORTS_COUNT_P */
0,
/* LVDS_IO_P */
5,
12,
0,
0,
0,
1 )
/* USE_PORTS_TO_CONFIGURE_P */
SPI4_2_TX_MON(
.tdclk
(tdclk),
.tsclk
(tsclk),
.areset
(areset),
.reset
(reset),
.tdat
(tdat),
.tctl
(tctl),
.tstat
(tstat),
.port_addresses
({32'd0, 32'd1, 32'd2,
32'd4, 32'd5, 32'd6,
32'd8, 32'd9}),
.max_burst_1_x
(7),
.max_burst_2_x
(5),
.data_max_t_x
(1000),
.calendar_len_x
(12),
.calendar_m_x
(2),
({32'd0, 32'd1, 32'd2,
32'd4, 32'd5, 32'd0,
32'd6, 32'd7, 32'd8,
.l_max_x
(16),
752
32'd3,
32'd7,
32'd3,
32'd1,
32'd9}),

Transmit Monitor
.data_training_sequences_cnt_x
(3),
.fifo_max_t_x
(500),
.max_packet_len_x
(1000),
.min_packet_len_x
(50),
.ports_count
(32'd5),
.lvds_io
(1'b0),
.fifo_valid_sync_or_training_delay(32'd5),
.control_word_extension_enable
(1'b0),
.bandwidth_reprovisioning_enable (1'b0));
Monitor Checks
Table 18-8 shows the checks performed by the SPI4-2 Transmit monitor.
Table 18-8. SPI4-2 Transmit Checks
Check ID
Violation
SPI4_2_TX_00_P
SPI4_2_TX_00_N
A control word other than Idle

Constraints formal analysis to exercise
Control/Payload Control/Training the pins as per the specification. Failure
Control should not be issued.
to do so can cause the design to
malfunction when formal analysis
controls the pins.
SPI4_2_TX_01_P
SPI4_2_TX_01_N


follow the control word. This check fires
if Payload Control is followed by an Idle
Control word.
SPI4_2_TX_02_P
SPI4_2_TX_02_N


follow the control word. This check fires
if Payload Control is followed by
SPI4_2_TX_03_P
SPI4_2_TX_03_N

During a training sequence, the Training

Control word sequence should be
immediately followed by a Training
Data word. This check fires if a Training
Control word sequence is followed by
SPI4_2_TX_04_P
SPI4_2_TX_04_N

During a training sequence, the Training

Control word sequence should be
immediately followed by a Training
Data word. This check fires if a Training
Control word sequence is followed by a
SPI4_2_TX_05_P
SPI4_2_TX_05_N
An Idle Control word should not

be followed by Payload transfer.
An Idle Control word should always be

followed by a Payload Control, or
Training Control, or another Idle
Control word. This check fires if an Idle
Control word is followed by Payload
transfer.
Description
753

Transmit Monitor
Table 18-8. SPI4-2 Transmit Checks (cont.)

Check ID
Violation
Description
SPI4_2_TX_06_P
SPI4_2_TX_06_N
Payload transfer should not be

followed by a Training Control
word.
Payload transfer can terminate only with

an Idle Control or another Payload
Control word. This check fires if the
Payload transfer is terminated by a
SPI4_2_TX_07_P
SPI4_2_TX_07_N

not be followed by another

follow the Payload Control word. This
check fires if Payload Control is
followed by another Payload Control
word.
SPI4_2_TX_08_P
SPI4_2_TX_08_N

on data path should not be greater

Training Control words, and 10 Training
Data words). This check fires if Training
Control or Training Data words count is
greater than 10 half clock cycles.
SPI4_2_TX_09_P
SPI4_2_TX_09_N

on data path should not be less

Training Control words, and 10 Training
Data words). This check fires if the
Training Control or Training Data words
count is less than 10 half clock cycles.
SPI4_2_TX_10_P
SPI4_2_TX_10_N
Payload transfer should end with

an EOP or pause at a 16 byte
block boundary.
Payload transfer to a port can either end

with an EOP or pause at a 16 byte block
boundary. Violation of this condition
causes the check to fire.
SPI4_2_TX_11_P
SPI4_2_TX_11_N

The monitor calculates DIP4 parity for

various types of transfer as detailed in
the specification. This check fires if a
DIP4 parity is detected on the data path
interface.
SPI4_2_TX_12_P
SPI4_2_TX_12_N
At least DATA_TRAINING_
SEQUENCES_CNT number of
Training sequences should occur
on the data path interface for
every DATA_MAX_T half clock
cycles.
There should be at least DATA_

TRAINING_SEQUENCES_CNT
number of training sequence transmitted
for every DATA_MAX_T number of
half clock cycles. This check fires if no
Training sequence is transmitted for
DATA_MAX_T number of half clock
cycles.
SPI4_2_TX_13_P
SPI4_2_TX_13_N
Successive SOPs should be

separated by 8 half clock cycles.
Successive start of packet indications

(using bit 12 of the control word) should
be separated by 8 half clock cycles.
check to fire.
SPI4_2_TX_14_P
SPI4_2_TX_14_N
Unused byte of a Payload,

terminated by EOP with one byte
valid, should be 0x00 (hex).
On Payload transfers that do not end on

an even byte boundary, the unused byte
(after the last valid byte) should be set to
zero. This check fires if the unused byte
contains a nonzero bit.
754

Transmit Monitor

Check ID
Violation
Description
SPI4_2_TX_15_P
SPI4_2_TX_15_N

port when it is in paused status.
When a port is in paused status, SOP

should not be issued to the port until the
remaining data is transferred. Violation
of this condition causes the check to fire.
SPI4_2_TX_17_P
SPI4_2_TX_17_N
All the Training Data of a

Training sequence on the data
path should be identical.
All the Training Data in a Training

sequence should be identical. Violation
of this condition causes the check to fire.
SPI4_2_TX_18_P
SPI4_2_TX_18_N

port when an error condition has
been reported on FIFO status
interface.
A continuous stream of 11 pattern on

TSTAT pins signifies an error condition.
Under such cases, transmission to all the
ports should be stopped until a nonerror
status is indicated on the TSTAT pins.
This check fires if a SOP is issued to a
port when an error has been reported on
the FIFO status interface.
SPI4_2_TX_19_P
SPI4_2_TX_19_N

port beyond L_MAX distance,
after the FIFO status became
SATISFIED.
When the FIFO status of a port becomes

SATISFIED, SOP should not be issued
to the port after the L_MAX response
time has elapsed. Violation of this
condition causes the check to fire.
SPI4_2_TX_20_P
SPI4_2_TX_20_N
Payload should not be transferred

to a port beyond L_MAX
distance, after the FIFO status
became SATISFIED.

SATISFIED, then the Payload should
not be transferred to the port after the
L_MAX response time has elapsed.
check to fire.
SPI4_2_TX_21_P
SPI4_2_TX_21_N

FIFO is in the HUNGRY
condition.

HUNGRY, the number of 16 byte
blocks transferred to it should not
check to fire.
SPI4_2_TX_22_P
SPI4_2_TX_22_N

FIFO is in the STARVING
condition.

STARVING, the number of 16 byte
blocks transferred to it should not
check to fire.
SPI4_2_TX_23_P
SPI4_2_TX_23_N

sequence should not be less than
the value of CALENDAR_LEN
multiplied by CALENDAR_M.

(2'b11) occurs before the calculated
number of status slots elapse.
SPI4_2_TX_24_P
SPI4_2_TX_24_N

Two bit diagonal interleaved parity

(DIP2) is transmitted at the end of FIFO
status sequence. This check fires if a
DIP2 parity error is detected on the
755

Transmit Monitor

Check ID
Violation
Description
SPI4_2_TX_25_P
SPI4_2_TX_25_N

sequence should not be greater
than the value of
CALENDAR_LEN multiplied by
CALENDAR_M.

(2'b11) does not occur after the
calculated number of status slots have
elapsed.
SPI4_2_TX_27_P
SPI4_2_TX_27_N
The value of calendar selection

word should be either 2'b01 or
2'b10.
When Hit-less Bandwidth

reprovisioning feature is enabled, the
calendar selection word that selects one
of two sets of parameters X and Y
should be either 2'b01 or 2'b10. This
check fires if the calendar selection
word is either 2'b00 or 2'b11.
SPI4_2_TX_28_P
SPI4_2_TX_28_N
When LVDS_IO_P mode is

enabled, training sequences

Training sequence should be transmitted
on the FIFO interface after reset went
inactive. This check fires if there is no
start of Training sequence even after the
FIFO_VALID_SYNC_OR_
TRAINING_DELAY_P number of
TSCLK half clocks have elapsed.
SPI4_2_TX_29_P
SPI4_2_TX_29_N
When LVTTL_IO mode is

enabled, framing pattern (2'b11)
When LVTTL_IO mode is enabled,

framing pattern (2'b11) should be
transmitted on the FIFO status interface
after reset went inactive. This check
fires if there is no framing pattern even
after the FIFO_VALID_SYNC_OR_
TRAINING_DELAY_P number of
TSCLK clocks have elapsed.
SPI4_2_TX_30_P
SPI4_2_TX_30_N

be greater than 20.

the FIFO status interface is 20 TSCLK
half clock cycles if LVDS_IO_P mode
is enabled, and it is 20 TSCLK cycles if
LVTTL_IO mode is enabled. This check
fires if the length of Training sequence
is greater than 20.
SPI4_2_TX_31_P
SPI4_2_TX_31_N

be less than 20.

the FIFO status interface is 20 TSCLK
half clock cycles if LVDS_IO_P mode
is enabled, and it is 20 TSCLK cycles if
LVTTL_IO mode is enabled. This check
fires if the length of Training sequence
is less than 20.
SPI4_2_TX_32_P
SPI4_2_TX_32_N
At least one Training sequence

should occur on the FIFO
interface for every
FIFO_MAX_T cycles.
At least one Training sequence should

occur on the FIFO interface for every
FIFO_MAX_T TSCLK half clock
cycles if LVDS_IO_P mode is enabled,
or every FIFO_MAX_T TSCLK cycles
if LVTTL_IO mode is enabled.
Violation of this condition causes this
check to fire.
756

Transmit Monitor

Check ID
Violation
Description
SPI4_2_TX_33_P
SPI4_2_TX_33_N
Size of a packet should not be less

than the specified minimum
packet size.

not be less than the value specified by
min_packet_len_x or
min_packet_len_y. Note that
min_packet_len_y is relevant only if
bandwidth reprovisioning is enabled.
SPI4_2_TX_34_P
SPI4_2_TX_34_N
Size of a packet should not be

greater than the specified
maximum packet size.

not be greater than the value specified
by max_packet_len_x or
max_packet_len_y. Note that
max_packet_len_y is relevant only if
bandwidth reprovisioning is enabled.
SPI4_2_TX_35_P
SPI4_2_TX_35_N
Reserved encoding should not be

transmitted as part of control
word.
Bits [15:12] of a control word should not

be driven to 4'b0001, 4'b0011, 4'b0001,
and 4'b0111. This check fires if reserved
bit values are transmitted. Note that if
the control word extension is enabled,
then 4'b0001 and 4'b0111 are treated as
valid combination. In this case, this
checker will not fire.
SPI4_2_TX_36_P
SPI4_2_TX_36_N
A Payload control word should

not be issued to a port without
SOP information, when the port is
inactive.
When the port is in inactive condition, a

payload transfer to the port should start
with an SOP. This check fires if a
payload control is issued to an inactive
port with port address, address without
SOP information.
SPI4_2_TX_37_P
SPI4_2_TX_37_N
A control word is not transmitted

after indicating control word
extension.
If there is an extended control word in

next TDCLK edge, then the current
control word bit combination [15:12]
value equals 4'b0001. This check fires if
the current control word signals an
extended control word, and there is no
control word in the next TDCLK edge.
SPI4_2_TX_38_P
SPI4_2_TX_38_N
Only Training sequence should

be transmitted on the data path
interface after reset until a valid
FIFO status is received.
After reset, only the Training sequence

should be transmitted on the data path
interface until a valid FIFO status is
received. This check fires if a
data/control word other than Training
sequence is transmitted over the data
path interface after reset.
SPI4_2_TX_39_P
SPI4_2_TX_39_N
SOP should not be issued to an

active port without completing
the previous transfer.
When the port is in active condition, the

current payload transfer can be
terminated with a 16 byte blocks data
boundary (port becomes paused), or an
EOP/EOP abort (port becomes inactive),
or an EOP/EOP abort, and SOP (port
continues to be active). This check fires
if a payload control is issued to an active
port with port address, address only with
SOP.
757

Transmit Monitor

Check ID
Violation
Description
SPI4_2_TX_40_P
SPI4_2_TX_40_N
EOP should not be issued to a

port without a preceding SOP.
Every packet should start with a SOP,

and it should end with an EOP. This
check ensures that every EOP for the
port with port address, address is
preceded by a SOP. This check fires
when an EOP is received without a
preceding SOP.
SPI4_2_TX_PARAM_01_P
CALENDAR_LEN should not be

The value of CALENDAR_LEN

less than 1.
CALENDAR_M should not be

The value of CALENDAR_M

less than 1.

The value of MAX_BURST_2

less than 1.

MAX_BURST_2.
MAX_BURST_1 value should not be

less than the value of MAX_BURST_2
as per definition of these parameters.
This check fires if MAX_BURST_1 is
specified to be less than
MAX_BURST_2.
DATA_MAX_T should not be

less than the minimum limit of 21
half clock cycles (Training
sequence length).
DATA_MAX_T value should not be

data_max_t_x (data_max_t_y) is set to
0.
FIFO_MAX_T should not be less

FIFO_MAX_T value should not be less

than the length of the Training sequence.
This check is disabled if fifo_max_t_x
(fifo_max_t_y) is set to 0.
DATA_TRAINING_
SEQUENCES_CNT should not
1.
The value of DATA_TRAINING_

SEQUENCES_CNT parameter should
Product of CALENDAR_LEN
and CALENDAR_M should not
be less than 16 when
LVDS_IO_P mode is selected.
When LVDS_IO_P mode is enabled, the

product of CALENDAR_LEN and
CALENDAR_M should not be less than
16. This is required to differentiate the
Training sequence and the FIFO status
sequence.
Minimum packet size should not

1.
The min_packet_len_x or
min_packet_len_y parameter should not
be specified to be less than 1.
Maximum packet size should not

be specified to be less than the
minimum packet size.
The max_packet_len_x or
max_packet_len_y parameter value
should not be less than the value of the
respective min_packet_len_x or
min_packet_len_y parameter.

758

Transmit Monitor
The active clock edge for checks SPI4_2_TX_00_P to SPI4_2_TX_22_P, and

SPI4_2_TX_33_P to SPI4_2_TX_40_P, which is the positive edge of TDCLK.
The active clock edge for checks SPI4_2_TX_00_N to SPI4_2_TX_22_N and

SPI4_2_TX_33_N to SPI4_2_TX_40_N, which is the negative edge of TDCLK.
The active clock edge for checks SPI4_2_TX_PARAM_01_P to SPI4_2_TX_PARAM_13_P

is the positive edge of TDCLK. These checks are on parameters and therefore, are coded
to fire only on the first clock edge when both reset and areset are sampled inactive.
The active clock edge for checks SPI4_2_TX_23_P to SPI4_2_TX_32_P, which is the
positive edge of TSCLK.
The active clock edge for checks SPI4_2_TX_23_N to SPI4_2_TX_32_P, which is the
negative edge of TSCLK.

Table 18-9 shows the corner cases captured by the SPI4-2 Transmit monitor.
Table 18-9. SPI4-2 Transmit Monitor Corner Cases
Corner Case
Description
Number of Packets with Application

Error
Total number of packets transferred with application specific error.
Number of EOPs with one byte valid
Total number of End of Packets (EOPs) issued with only one byte of
Number of EOPs with two bytes valid
Total number of End of Packets (EOPs) issued with both the bytes of
Number of Unpaused Packet transfers
Total number of times an entire packet (SOP, data, EOP) is

transferred without interruption. Note that if all packets are
transferred without interruption, then this statistic is equal to the
Payload Controls statistic.
FIFO Status Error Count
Total number of times an error condition (stream of 11 pattern on

TSTAT pins) is reported on the FIFO status interface. This statistic
is zero if the ENABLE_FIFO_STATUS_IF_P parameter is set to 0.
Total number of packets transferred with DIP4 parity error.
Total number of FIFO status sequences transferred with DIP2 parity

error. This statistic is zero if the ENABLE_FIFO_STATUS_IF_P
Number of Idle Controls
Total number of idle control words transferred.
Number of Payload Controls
Total number of payload control words transferred.
Number of Data Path Training sequences Total number of training sequences transferred on the data path
interface.
Number of FIFO interface Training
sequences
Total number of training sequences transferred on the FIFO

interface.
STARVING FIFO Status Count
Number of times the FIFO status is reported as STARVING on the

FIFO status interface (TSTAT).
759

Transmit Monitor
Table 18-9. SPI4-2 Transmit Monitor Corner Cases (cont.)

Corner Case
Description
HUNGRY FIFO Status Count
Number of times the FIFO status is reported as HUNGRY on the

SATISFIED FIFO Status Count
Number of times the FIFO status is reported as SATISFIED on the

Monitor Statistics
Table 18-10 shows the statistics collected by the SPI4-2 Transmit monitor.
Table 18-10. SPI4-2 Transmit Monitor Statistics
760
Statistic
Description
Number of Packets transferred
Total number of Packets transferred between the PHY device and the
Link layer device.
Number of bytes transferred
Total number of bytes transferred between the PHY device and the
Link layer device.
Maximum Packet Size
Maximum number of bytes transferred in a single packet.
Maximum number of Idle Controls

between transactions
Maximum number of Idle control words issued between transactions.
Number of ports that never received a

Packet
Total number of ports that did not receive any packets.
Chapter 19
Universal Serial Bus 2.0 (USB)
Introduction
The Universal Serial Bus (USB) is specified to be an industry standard extension to the PC
architecture, with a focus on computer telephony, consumer and productivity appliances. USB
is a cable bus that supports data exchange between a host computer and a wide range of
peripherals. The attached peripherals share USB bandwidth through a host-scheduled, tokenbased protocol. The QVL Universal Serial Bus monitor is designed for checking the USB
protocol implementations.
USB 2.0 monitors are compliant with the specifications provided in the following documents:
Universal Serial Bus Specification. Revision 2.0, April 27, 2000.
Errata for USB 2.0 Specification - May 28, 2002.
Errata for USB 2.0 Specification - December 7, 2000.
Engineering Change Notice, Link Power Management Addendum to USB2.0

Specification.
The USB 2.0 UTMI monitor is compliant with the specifications provided in the following
document:
USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.05 - March
29, 2001.
UTMI+ Specification, Revision 1.0, February 25, 2004
OTG Interface (On-The-Go Supplement to the USB 2.0 Specification, Revision 1.3,
December 5, 2006)
The USB 2.0 ULPI monitor is compliant with the specifications provided in the following
document:
UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1, October 20, 2004
OTG Interface (On-The-Go Supplement to the USB 2.0 Specification, Revision 1.3,
December 5,2006)*
761

Supported Features
Supported Features
The following features are supported by the USB 2.0 monitors:
Tracks packet size.
Tracks Token, Extended Token, and Data CRC errors.
Maximum packet size supported by transfer types and end points.
Inter-packet delay violations.
Data packet ID sequences.
Tracks all the transfer types supported by USB.

o
Control transfers.
Interrupt transfers.
Bulk transfers.
Isochronous transfers.
Validates the SETUP data (requests, commands).
Start-of-Frame (SOF) Jitter.
The USB monitor can be instantiated on the downstream port of the host (root hub), upstream
port of the hub, downstream port of the hub, and upstream port of the device.
Additional features supported by the USB 2.0 UTMI monitor are as follows:
Tracks SPLIT transactions.
Supports Level 0, 1, 2, 3.
HS/FS, FS Only, LS Only modes of operations.
Supports 8-bit and 16-bit UTMI.
Supports bidirectional UTM interface.
Supports on-the-go devices.
Additional features supported by the USB 2.0 ULPI monitor are as follows:
762
HS, FS, LS modes of operation.
Supports 4-bits and 8-bits wide ULPI data bus.
Supports on-the-go devices.

USB 2.0 Monitor Instantiated on the Host or Hub
USB 2.0 Monitor Instantiated on the Host or Hub

The USB monitor tracks all transactions initiated by the host. It tracks the transaction
sequences, CRC errors, packet size, packet ID, standard device requests, and hub class requests.
The monitor tracks the various transfer types, packet sizes supported by the transfer types,
control transfer sequence, and sequence bits of the device for which address is specified during
monitor instantiation.
If this monitor is instantiated on Host or Hub (between Host and Hub), then this monitor
instance will not check the assertions for the traffic targeted to a device connected to Hub. For
checking these, a different Monitor instance should be connected between the Hub and device.
The monitors track the packet ID, standard device requests, and CRC errors for packets
addressed to any other device.
Features not supported by the USB 2.0 monitors are as follows:
Does not follow the process of bus enumeration.
Does not follow the process of device configuration (i.e., the monitors do not identify
the addresses assigned to the devices or device configurations).
Monitor does not support vendor control signals and test modes.

To use the USB 2.0 monitor, place an instance of the monitor inside the USB hub, USB device,
or USB host as shown in Figure 19-1.
The standard USB 2.0 monitor must be instantiated at the serial interface between the USB
Devices. The USB 2.0 UTMI monitor must be instantiated at the UTMI interface, between the
USB UTMI transceiver and the USB core logic (USB device controller, hub controller, or host
controller logic). The USB 2.0 ULPI monitor must be instantiated at the ULPI interface,
between ULPI transceiver (PHY) and OTG/Host/Peripheral Core (LINK).
You can include instantiations of the USB 2.0 monitor in a checker control file.
763

USB 2.0 (Standard) Monitor
Figure 19-1. USB 2.0 Monitor Implementation
USB Host
USB Bus
USB
Monitor
USB Hub
or
USB Hub
USB Bus
USB Host
USB
Monitor
USB Hub
USB Bus
USB
Monitor
USB Device
or
USB Device
USB Hub
USB Bus
USB
Monitor

Connectivity
Connect the standard USB 2.0 monitor pins to internal signals as specified in the pin out
Table 19-1 and illustrated in Figure 19-2. The monitor should be connected at the interface
between a USB controller and USB transceiver as shown in Figure 19-2. This transceiver is
only an analog transceiver.
764

Figure 19-2. USB 2.0 (standard) Monitor Pin Diagram

clock
areset
reset
dp
dm
oe_n
speed
address
end_point_config
number_of_active_endpoints
USB 2.0
Monitor
dp
dm
USB Wire
Serial Interface
oe_n
speed
USB Controller
USB
Monitor
Table 19-1. USB 2.0 (standard) Monitor Pin

Pin
Description
address
Address of the device or function. Connect to the address register (register that
holds the assigned address) if the monitor is instantiated on the upstream port
of the device.
areset
clock
Clock input. This clock is used to sample the data on the USB bus. Refer to the
connectivity note 1 at the end of this table.
dm
Negative data input/output of the transceiver.
dp
Positive data input/output of the transceiver.
end_point_config
End point configuration input.
This signal configures the number of active endpoints tracked currently by the
monitor. The value must not be greater than NUMBER_OF_ENDPOINTS
parameter.
oe_n
Output enable signal, active low.
reset
speed
Speed indicator signals. A value of 00 indicates a low speed link, 01 indicates

a full speed link, and 11 indicates a high speed link.
Connectivity Notes
1. The clock is not a USB interface signal. This signal must be provided from the users
design. The monitor does not perform clock recovery.
765

2. Input address should be connected to the address register of the device if the monitor
is instantiated on the upstream port of the device. If the monitor is instantiated on the
downstream port of the host, hub, or upstream port of the hub, then tie this input to the
address of the device for which transactions needs to be tracked.
3. Input oe_n is an active low input signal. This signal indicates whether host is driving or
device is driving the bus. For example, if the monitor is instantiated on the downstream
port of the host, then a logic low sampled on this signal indicates that the host is driving
the bus. (Ports dp and dm act as the input ports of the transceiver.) A logic high
sampled on this signal indicates that the device is driving the bus. (Ports dp and dm act
as the output ports of the transceiver.)
4. Input end_point_config configures the end points to be tracked. This input follows
the encoding scheme as explained below. For configuring the end points end point
address, transfer type supported by the end point, direction of the end point (IN or
OUT), and maximum packet size supported by the end point need to be specified. Each
end point needs 21-bits for the configuration. The order in which these bits are used is as
follows:
Assuming a 21-bit register for each end point configuration information, various fields
of the register are defined as shown below:
A3 A2 A1 A0 D T2 T1 T0 O1 O0 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
o
In this register, the A3 bit is the most significant bit and S0 is the least
significant bit.
A3 A2 A1 A0
The D bit specifies the direction of the end point. When set to 1, the end point
supports only IN transactions. When set to 0, the end point supports only OUT
transactions. This bit should be set to 0 if the end point supports control
transfers.
T2 T1 T0
specifies the transfer type supported by the end point. Allowed values
for these bits are as follows:
0
0
0
1
766
0
1
1
0
1
0
1
0
Control transfer
Interrupt transfer
Bulk transfer
Isochronous transfer
Bits O1 and O0 specify the additional transaction opportunity per microframe

as follows:
0
0
1
1
specifies the address of the end point.
0
1
0
1
None (1 Transaction per microframe)

1 Additional (2 Transactions per microframe)
Reserved.
Bits S10 to S0 specify the maximum packet size supported by the end point.
This field represents wMaxPacketSize of configuration information.

If there are multiple end points to be tracked by the monitor, then the above specified
encoding information should be provided for each end point. The encoded value of the
end points should be concatenated and wired to the end_point_config input.
For example, suppose the monitor needs to track two end points whose configuration
information is as follows:
end_point_1 = 21'b 0000_0_001_00_0000010000
Control end point with address 0000 and wMaxPacketSize of 16.

end_point_2 = 21'b 0001_1_010_00_0000001000
Interrupt end point with address 0001, IN only, and wMaxPacketSize of 8.

Then the end_point_config input should be as follows:
{end_point_1, end_point_2}
or
Monitor Parameters
Parameters shown in Table 19-2 configures a standard USB 2.0 monitor.
Table 19-2. USB 2.0 Monitor Parameters
Order
Parameter
Default Description
1.
Constraints_Mode

2.
PORT_TYPE
This parameter configures the port type tracked by the

monitor. Set this parameter to the following:
0 if the monitor is instantiated on the downstream
port of the host.
1 if the monitor is instantiated on the upstream
port of the Hub.
port of the Hub.
port of the device.
3.
NUMBER_OF_
ENDPOINTS
This parameter configures the maximum number of end

points that can be tracked by the monitor. Maximum
number of end points supported by the monitor is 31.
Maximum number of control end points supported by
the monitor is 16.
767

Table 19-2. USB 2.0 Monitor Parameters (cont.)

Order
Parameter
Default Description
4.
FRAME_INTERVAL_
COUNT
60000
This parameter configures the USB bit (clock) count for

a frame in case of Full speed device, microframe in case
of High speed device, and is redundant in case of Low
speed devices. This count is the number of clock cycles
between two consecutive SOF frames, from end-ofpacket of the SOF packet to the end-of-packet of the
next SOF packet. The default value tracks a standard
USB frame/microframe interval.
5.
SOF_JITTER_INTERVAL_
COUNT
30
This parameter indicates the jitter in SOF packets.

According to specification, for HIGH speed this is
+/-62.5 ns and for FULL speed it is +/-500 ns. So count
for high speed is 30.
6.
SEQUENCE_BIT_
TRACKING_ENABLE
This parameter enables sequence-bit tracking in the

monitor. Set this parameter to 0 to disable sequence-bit
tracking.
7.
PACKET_ISSUE_
CHECK_ENABLE
This parameter configures the monitor to fire for the

illegal issue of token requests. By default, the monitor
fires for these conditions.
Example 1: If IN token is issued to OUT only end point,
then the monitor check fires when this parameter is 1.
Example 2: If undefined requests other than standard
device class requests are issued, then the monitor
checks fire when this parameter is 1.
Set this parameter to 0 to discard the checks.
8.
OTG_DEVICE
This parameter configures the monitor to support USB

on-the-go devices. Set this parameter to 1 to support
USB on-the-go devices. By default, USB on-the-go
device is not supported.
9.
HUB_SETUP_INTERVAL
This parameter configures the hub setup interval. By

default, this parameter is set to 4.
Example 19-1 and Example 19-2 show instantiating the USB 2.0 monitors.
Example 1
This example instantiates a USB monitor on the downstream port of the host.
Example 19-1. USB Monitor on the Downstream Port
qvl_usb_2_0_monitor
#( 0,
0,
/* PORT_TYPE */
768

1,
/* NUMBER_OF_ENDPOINTS */
60000,
/* FRAME_INTERVAL_COUNT */
30,
/* SOF_JITTER_INTERVAL_COUNT */
1,
/* SEQUENCE_BIT_TRACKING_ENABLE */
1)
/* PACKET_ISSUE_CHECK_ENABLE */
USB_MON (
.clock
(clock),
.areset
(areset),
.reset
(reset),
.dp
(dp),
.dm
(dm),
.oe_n
(oe_n),
.speed
(2'b11),
.address
(address),
.end_point_config (end_point_config),
.number_of_active_endpoints (5'b1) );
Example 2
This example instantiates a USB monitor on the upstream port of the high-speed device to track
transactions of four end points. The address of the device is specified through the address input.
Example 19-2. USB Monitor on the Upstream Port
qvl_usb_2_0_monitor
#( 0,
3,
/* PORT_TYPE */
4,
60000,
30,
1,
1)
USB_MON (
.clock
(clock),
.areset
(areset),
.reset
(reset),
.dp
(dp),
.dm
(dm),
.oe_n
(oe_n),
.speed
(2'b11),
.address
(address),
769

USB 2.0 UTMI Monitor

Connect the USB 2.0 UTMI monitor pins to internal signals as specified in the pin out
between a USB controller and USB transceiver as shown in Figure 19-3.
Figure 19-3. USB 2.0 UTMI Monitor Pin Diagram
xcvr_select[0]
xcvr_select[1]
term_select
op_mode[1:0]
suspendm
clock
areset
reset
tx_valid
tx_valid_h
tx_ready
data_in_low[7:0]
data_in_high[7:0]
address[6:0]
end_point_config
rx_valid
rx_valid_h
rx_active
rx_error
data_out_low[7:0]
data_out_high[7:0]
data_low
data_high
valid_h
USB 2.0
UTMI
Monitor
host_disconnect
dp_pulldown
dm_pulldown
id_pullup
id_dig
a_valid
b_valid
vbus_valid
sess_end
drv_vbus
dischrg_vbus
chrg_vbus
databus16_8
line_state[1:0]
Table 19-3. USB 2.0 UTMI Monitor Pins

Pin
Description
address [6:0]
Address of the device or function. If the monitor is instantiated on the upstream port of
the device, then connect to the address register (register that holds the assigned
address).
areset
clock
Clock input. This clock is used to sample data on the USB bus.
data_in_high [7:0]
8-bit parallel USB data input that transfers the high byte of 16-bit transmit data. This
input is applicable only when databus18_8 is 1. This input is not applicable for fullspeed only and low-speed only devices.
770

Table 19-3. USB 2.0 UTMI Monitor Pins (cont.)

Pin
Description
data_in_low [7:0]
8-bit parallel USB data input bus. When databus16_8 is 1, this bus transfers the low
byte of the 16-bit transmit data.
data_out_high [7:0]
8-bit parallel USB data output that transfers the high byte of 16-bit receive data. This
input is applicable only when databus16_8 is 1. This input is not applicable for fullspeed only and low-speed only devices.
data_out_low [7:0]
8-bit parallel USB data output bus. When databus16_8 is 1, this bus transfers the low
byte of the 16-bit receive data.
databus16_8
Selects between 8-bit and 16-bit data transfers. This input is not applicable for fullspeed only and low-speed only devices.
end_point_config
line_state [1:0]
Current state of the USB bus.
number_of_active_
endpoints
monitor. The value must not be greater than NUMBER_OF_ENDPOINTS parameter.
reset
rx_active
Receive active signal. Indicates that the receive state machine is active.
rx_error
Receive error signal. When asserted, indicates that a receive error is detected.
rx_valid
Receive data valid signal. This signal indicates when the data_out bus is valid.
rx_valid_h
Receive data valid high signal. When databus16_8 input is 1, this signal indicates that
the data_out [15:8] bus has valid data. This input is not applicable for full-speed only
and low-speed only devices.
term_select
This signal selects between full-speed and high-speed terminations. A 0 indicates

that the high-speed termination is selected. A 1 indicates full-speed termination is
selected. This input is not applicable for full-speed only and low-speed only devices.
op_mode [1:0]
This signal is the UTM operational mode input signal. The value of 0 means normal
operation, and a value of 2 means that NRZI encoding and bit stuffing is disabled. This
mode is used during device chirping sequence done during speed negotiation protocol.
suspendm
This signal places the macrocell in low power mode. The value of 0 means low power
mode and a value of 1 means normal operation.
tx_ready
Transmit data ready signal. This signal indicates when the transmit data are loaded into
the transmit holding shift register.
tx_valid
Transmit data valid signal.
tx_valid_h
Transmit data valid high signal. When databus16_8 is 1, this signal indicates that
data_in [15:8] contains valid transmit data. This input is not applicable for full-speed
only and low-speed only devices.
xcvr_select[0]
Selects between full-speed and high-speed transceivers. A 0 indicates that the highspeed transceiver is selected. A 1 indicates full-speed transceiver is selected. This
input is not applicable for FS only and LS only devices.
Bidirectional Signals of the Design

data_high [7:0]
Bidirectional high order 8-bit data of the 16-bit interface.
data_low [7:0]
Bidirectional low order 8-bit data.
771

Table 19-3. USB 2.0 UTMI Monitor Pins (cont.)

Pin
Description
valid_h
Valid transfer. Only applicable for the 16-bit bidirectional interface (databus16_8 = 1).
If TxValid is high, then this signal is equivalent to TxValidH. If TxValid is low, then
this signal is equivalent to RxValidH.
Level 1 Signals of the Design

id_pullup
Signal that enables the sampling of the analog Id line.
id_dig
Indicates whether the connected plug is a mini-A or mini-B.The value of 0 indicates

mini-A and a value of 1 indicates mini-B.
a_valid
Indicates if the session for an A-peripheral is valid.
b_valid
Indicates if the session for a B-peripheral is valid.
vbus_valid
Indicates if the voltage on Vbus is at a valid level for operation.
sess_end
Indicates if the voltage on Vbus is below B-Device Session End threshold.
drv_vbus
This signal enables to drive 5V on Vbus.
dischrg_vbus
The signal enables discharging Vbus.
chrg_vbus
The signal enables charging Vbus.
host_disconnect
This signal is used for all types of peripherals connected to it. It is only valid when
DpPulldown and DmPulldown are 1. The value of 1 indicates that there is no
peripheral connected and a value of 0 means that a peripheral is connected.
dp_pulldown
This signal enables the 15k Ohm pull-down resistor on the DP line. The value of 0
means the Pull-down resistor is not connected to DP and a value of 1 means the Pulldown resistor is connected to DP.
dm_pulldown
This signal enables the 15k Ohm pull-down resistor on the DM line. The value of 0
means the Pull-down resistor is not connected to DM and a value of 1 means the Pulldown resistor is connected to DM.
Level 2 and 3 Signals of the Design

xcvr_select[1]
This signal is used with xcvr_select[0] from level 2 and above. xcvr_select[1:0] selects
between the following modes:
00 : HS transceiver
01 : FS transceiver
10 : LS transceiver (Valid in level 2 and above)
11 : Send a LS packet on a FS bus or receive a LS packet. (Valid only in level 3)
Connectivity Notes
1. Input address should be connected to the address register of the device if the monitor
is instantiated on the upstream port of the device. If the monitor is instantiated on the
2. Input end_point_config configures the end points to be tracked. This input follows
the encoding scheme as explained below. For configuring the end points end point
address, transfer type supported by the end point, direction of the end point (IN or
772

OUT), and maximum packet size supported by the end point needs to be specified. Each
end point needs 21-bits for the configuration. The order in which these bits are used is as
follows:
o
In this register, the A3 bit is the most significant bit, and S0 is the least
significant bit.
A3 A2 A1 A0
transfers.
T2 T1 T0
0
0
0
1
0
1
1
0
1
0
1
0
Control transfer
Interrupt transfer
Bulk transfer
Bits O1 and O0 specify the additional transaction opportunity per microframe as

follows:
0
0
1
1
0
1
0
1

Reserve
end_point_1 = 21'b 0000_0_001_00_0000010000

end_point_2 = 21'b 0001_1_010_00_0000001000

773

or
3. Care should be taken in connecting the clock to the UTMI monitor. There are certain
checks which require that the clock frequency connected to the monitor is in accordance
with the UTMI specifications. It is 30 MHz for a 16-bit interface, and 60 MHz for an
8-bit interface. Not connecting the proper clock can result in violations.
Monitor Parameters
Parameters shown in Table 19-4 configures a USB 2.0 UTMI monitor.
Table 19-4. USB 2.0 UTMI Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode
Set this parameter to 1 if the checks in the monitor are to be

used as constraints for formal analysis.
2.
UTMI_LEVEL
Configures the Level of the UTM interface to be tracked

by monitor:
0 if the monitor is instantiated on Level 0 interface.
3.
PORT_TYPE
Configures the port type tracked by the monitor. Set this

parameter to the following:
port of the host.
1 if the monitor is instantiated on the upstream port
of the Hub.
port of the Hub.
3 if the monitor is instantiated on the upstream port
of the device.
4.
UTMI_SIDE
Indicates on which side of the interface the monitor is

instantiated. By default, the monitor is assumed to be
instantiated on the Serial Interface Engine (SIE) side of the
interface. Set it to 1 if the monitor is instantiated on the
Transceiver Macrocell side of the interface.
5.
BI_DIRECTIONAL
Configures the monitor to track a bidirectional interface.

Set this parameter to 1 to track the bidirectional interface.
By default, the monitor is configured to track a
unidirectional interface.
6.
DEVICE_SPEED
Configures the UTM for high-speed/full-speed, full-speed

only, or low-speed only mode of operation. Set this
parameter to 1 if the UTM is full-speed only. Set this
parameter to 2 if the UTM is low-speed only. By default,
the UTM is a high-speed/full-speed device. For full-speed
only and low-speed only devices, only an 8-bit interface is
allowed.
774

Table 19-4. USB 2.0 UTMI Monitor Parameters (cont.)

Order Parameter
Default Description
7.
NUMBER_OF_
ENDPOINTS

Maximum number of control end points supported by the
monitor is 16.
8.
FRAME_INTERVAL_
COUNT
7500
Configures the USB frame interval. This count is the

number of clock cycles between two consecutive SOF
frames, from end-of-packet of the SOF packet to the endof-packet of the next SOF packet. This parameter is
applicable only for a full-speed interface. The default value
tracks a standard USB frame interval.
9.
COUNT

+/-62.5 ns and for FULL speed it is +/-500 ns.
10.
SEQUENCE_BIT_
TRACKING_ENABLE
Enables sequence-bit tracking in the monitor. Set this

parameter to 0 to disable sequence-bit tracking.
11.
PACKET_ISSUE_
CHECK_ENABLE
Configures the monitor to fire for the illegal issue of token

requests. By default, the monitor fires for these conditions.
Example 1: If an IN token is issued to an OUT only end
point, then a monitor check fires when this parameter is 1.
device class requests are issued, then the monitor checks
fire when this parameter is 1.
12.
RX_ACTIVE_DEASSERT_
TO_TX_VALID_ASSERT_
DELAY_MIN
Configures the minimum time (in clock cycles) between

the de-assertion of RxActive and assertion of TxValid.
13.
RX_ACTIVE_DEASSERT_
TO_TX_VALID_ASSERT_
DELAY_MAX
24
Configures the maximum time (in clock cycles) between

the de-assertion of RxActive and assertion of TxValid.
14.
TX_VALID_DEASSERT_
TO_RX_ACTIVE_
ASSERT_DELAY_MIN
Configures the minimum time (in clock cycles) between

the de-assertion of TxValid and assertion of RxActive.
15.
TX_VALID_DEASSERT_
TO_RX_ACTIVE_
ASSERT_DELAY_MAX
37
Configures the maximum time (in clock cycles) between

the de-assertion of TxValid and assertion of RxActive.
16.
TIME_OUT_COUNT
800
Configures the number of clock cycles after which the

device or host is required to time out.
17.
OTG_DEVICE
Configures the monitor to support USB on-the-go devices.

Set this parameter to 1 to support USB on-the-go devices.
By default, USB on-the-go device is not supported.
775


Order Parameter
Default Description
18.
HUB_TURNAR_TIMEOUT_
16BIT
45000
Configures the timeout interval for the response of the host

after the device has done the K-chirp during speed
negotiation protocol in 16-bit UTMI operation at 30 MHz
clock speed.
19.
HUB_TURNAR_TIMEOUT_
8BIT
90000
Configures the timeout interval for the response of the host

after the device has done the K-chirp during speed
negotiation protocol in 8-bit UTMI operation at 60 MHz
clock speed.
20.
HUB_CHIRP_TIMEOUT_
16BIT
1800
Configures the timeout interval for each chirp (K or J)

initiated by the host during speed negotiation protocol
during a 16-bit UTMI operation at 30 MHz clock
frequency.
21.
HUB_CHIRP_TIMEOUT_
8BIT
3600
Configures the timeout interval for each chirp (K or J)

initiated by the host during speed negotiation protocol
during an 8-bit UTMI operation at 60 MHz clock
frequency.
22.
TERM_SEL_DEASS_
AFTER_HS_DETECT_
TIMEOUT_16BIT
15000
Configures the timeout interval for the de-assertion of term

select after the speed has been detected as high-speed in
16-bit UTMI interface at 30 MHz clock frequency.
23.
TERM_SEL_DEASS_
AFTER_HS_DETECT_
TIMEOUT_8BIT
30000
Configures the timeout interval for the de-assertion of term

select after the speed has been detected as high-speed in
24.
SE0_COUNT_MAX_FULL_
SPEED_REVERSE_8BIT
187500
Configures the maximum time 3.125 ms in number of

clocks for which SE0 has to be seen on the bus for reversal
to full-speed mode in 8-bit UTMI interface at 30 MHz
clock frequency.
25.
SE0_COUNT_MAX_FULL_
SPEED_REVERSE_16BIT
93750

clocks for which SE0 has to be seen on the bus for reversal
clock frequency.
26.
SE0_COUNT_MIN_FULL_
SPEED_REVERSE_8BIT
180000
Configures the minimum time 3 ms in number of clocks

for which SE0 has to be seen on the bus for reversal to fullspeed mode in 8-bit UTMI interface at 60 MHz clock
frequency.
27.
SE0_COUNT_MIN_FULL_
SPEED_REVERSE_16BIT
90000
Configures the minimum time 3 ms in number of clocks

for which SE0 has to be seen on the bus for reversal to fullspeed mode in 16-bit UTMI interface at 30 MHz clock
frequency.
28.
FULL_SPEED_SE0_RESET_
TIMEOUT_8BIT
150
Configures the time 2.5 us number of clock in full-speed

mode for which SE0 has to be seen on the bus for detecting
reset in 8-bit UTMI interface at 60 MHz clock frequency.
29.
TIMEOUT_16BIT
75
Configures the time 2.5 us number of clock in full-speed

mode for which SE0 has to be seen on the bus for detecting
30.
FULL_SPEED_J_SUSPEND_
TIMEOUT_8BIT
180000
Configures the number of clock in full-speed mode for

which J has to be seen on the bus for detecting suspend in
776


Order Parameter
Default Description
31.
TIMEOUT_16BIT
90000
Configures the number of clock in full-speed mode for

which J has to be seen on the bus for detecting suspend in
32.
LINE_STATE_DEBOUNCE_
TIMEOUT_8BIT
6000
Configures the time in range of 100 us to 875 us to sample

the LineState for detection of reset/suspend after reversal
clock frequency.
33.
TIMEOUT_16BIT
3000
Configures the time in range of 100 us to 875 us to sample

the LineState for detection of reset/suspend after reversal
clock frequency.
34.
CLK_USABLE_TIMEOUT_
8BIT
336000
Configures the time 5.6 ms in number of clocks for the

clock to be usable after J-SE0 transition is seen on the bus
in 8-bit UTMI interface at 60 MHz clock frequency.
35.
CLK_USABLE_TIMEOUT_
16BIT
168000

clock to be usable after J-SE0 transition is seen on the bus
in 16-bit UTMI interface at 30 MHz clock frequency.
36.
MIN_RESET_INTERVAL_
8BIT
600000
Configures the minimum reset interval of 10ms in 8-bit

UTMI interface at 60 MHz clock frequency.
37.
MIN_RESET_INTERVAL_
16BIT
300000
Configures the minimum reset interval of 10ms in 16-bit

UTMI interface at 30 MHz clock frequency.
38.
CHIRP_KJ_START_
TIMEOUT_8BIT
6000
Configures the time 100 us in number of clocks for ChirpKJ sequence to start after device Chirp-K in 8-bit UTMI
interface at 60 MHz clock frequency.
39.
CHIRP_KJ_START_
TIMEOUT_16BIT
3000
Configures the time 100 us in number of clocks for ChirpKJ sequence to start after device Chirp-K in 16-bit UTMI
40.
DEV_CHIRP_K_TIMEOUT_
8BIT
348000
Configures the maximum time 5.8 ms in number clocks for

assertion of device chirp after detection SE0 on the bus for
41.
DEV_CHIRP_K_TIMEOUT_
16BIT
174000
Configures the maximum time 5.8 ms in number clocks for

assertion of device chirp after detection SE0 on the bus for
42.
DEV_CHIRP_K_DEASS_
TIMEOUT_8BIT
420000
Configures the maximum clocks before which device chirp

has to be de-asserted after it is asserted in 8-bit UTMI
43.
DEV_CHIRP_K_DEASS_
TIMEOUT_16BIT
210000
Configures the maximum clocks before which device chirp

has to be de-asserted after it is asserted in 16-bit UTMI
44.
DEV_CHIRP_K_ASSERT_
TIMEOUT_8BIT
360000
Configures the maximum time 6 ms in clocks before which

device chirp has to be asserted after entering handshake
mode in 8-bit UTMI interface at 60 MHz clock frequency.
45.
DEV_CHIRP_K_ASSERT_
TIMEOUT_16BIT
180000
Configures the maximum time 6 ms in clocks before which

device chirp has to be asserted after entering handshake
mode in 16-bit UTMI interface at 30 MHz clock
frequency.
777


Order Parameter
Default Description
46.
DEV_MIN_REMOTE_
WAKE_UP_COUNT_8BIT
300000
Configures the minimum time 5 ms in clocks before which

a device capable of remote wake up must not initiate
resume in 8-bit UTMI interface at 60 MHz clock
frequency.
47.
DEV_MIN_REMOTE_
WAKE_UP_COUNT_16BIT
150000
Configures the minimum time 5 ms in clocks before which

a device capable of remote wake up must not initiate
resume in 16-bit UTMI interface at 30 MHz clock
frequency.
48.
RESUME_K_MIN_ASSERT_
8BIT
60000
Configures the minimum clocks for which resume K must

be asserted in 8-bit UTMI interface at 60 MHz clock
frequency.
49.
RESUME_K_MIN_ASSERT_
16BIT
30000

frequency.
50.
RESUME_K_MAX_ASSERT_
8BIT
900000
Configures the maximum clocks for which resume K can

frequency.
51.
RESUME_K_MAX_ASSERT_
16BIT
450000
Configures the maximum clocks for which resume K can

frequency.
52.
RESUME_K_DURATION_
LINE_STATE_8BIT
1200000

be found on the LineState in 8-bit UTMI interface at 60
MHz clock frequency.
53.
RESUME_K_DURATION_
LINE_STATE_16BIT
600000

be found on the LineState in 16-bit UTMI interface at 30
MHz clock frequency.
54.
RESUME_NORMAL_OPER_
TIMEOUT_8BIT
75
Configures the maximum clock before which the device

should resume normal operation after coming out of
resume sequence in 8-bit UTMI interface at 60 MHz clock
frequency.
55.
RESUME_NORMAL_OPER_
TIMEOUT_16BIT
38
Configures the maximum clock before which the device

should resume normal operation after coming out of
resume sequence in 16-bit UTMI interface at 30 MHz
clock frequency.
56.
SUSPENDM_DEASSERT_
TO_RESUME_K_ASSERT_
TIMEOUT_8BIT
600000
Configures maximum delay for assertion of FS 'K' on the

bus after suspendm is asserted in 8-bit UTMI interface at
60 MHz clock frequency.
57.
SUSPENDM_DEASSERT_
TO_RESUME_K_ASSERT_
TIMEOUT_16BIT
300000
Configures maximum delay for assertion of FS 'K' on the

bus after suspendm is asserted in 16-bit UTMI interface at
30 MHz clock frequency.
58.
HOST_DISCONNECT_
UPDATE_RECOVERY_
TIMEOUT_8BIT
240000
Configures the recovery time after reversal to full-speed

mode before which host_disconnect signal cannot be
updated in 8-bit UTMI interface at 60 MHz clock
frequency.
778


Order Parameter
Default Description
59.
120000
HOST_DISCONNECT_
UPDATE_RECOVERY_
TIMEOUT_16BIT
Configures the recovery time after reversal to full-speed

mode before which host_disconnect signal cannot be
updated in 16-bit UTMI interface at 30 MHz clock
frequency.
Example 19-3 and Example 19-4 show instantiating the USB 2.0 UTMI monitors.
Example 1
This example instantiates a USB monitor to track an 8-bit UTM Level 0 interface, full-speed
only device.
Example 19-3. USB Monitor to Track an 8-bit UTM Interface
qvl_usb_2_0_utmi_monitor
#( 0,
0,
/* UTMI_LEVEL */
3,
/* PORT_TYPE */
0,
/* UTMI_SIDE */
0,
/* BI_DIRECTIONAL */
1,
/* DEVICE_SPEED */
1,
75000,
4,
1,
1)
USB_UTMI_MON (
.clock
(clock),
.areset
(areset),
.reset
(reset),
.tx_valid
(TxValid),
.tx_ready
(TxReady),
.data_in_low
(Data_In),
.rx_valid
(RxValid),
.rx_active
(RxActive),
.rx_error
(RxError)
.data_out_low
(Data_Out)
.line_state
(LineState)
.address
(address)
779

Example 2
This example instantiates a USB monitor on the upstream port of a high-speed device to track
transactions of four end points. The address of the device is specified through the address input.
The UTM Level 0 interface is a high-speed/full-speed, 16-bit interface.
qvl_usb_2_0_utmi_monitor
#( 0,
0,
/* UTMI_LEVEL */
3,
/* PORT_TYPE */
0,
/* UTMI_SIDE */
0,
/* BI_DIRECTIONAL */
0,
/* DEVICE_SPEED */
4,
7500, /* FRAME_INTERVAL_COUNT */
4,
1,
1)
USB_UTMI_MON (
.clock
(clock),
.areset
(areset),
.reset
(reset),
.tx_valid
(TxValid),
.tx_valid_h
(TxValidH),
.tx_ready
(TxReady),
.data_in_low
(Data_In[7:0]),
.data_in_high
(Data_In[15:8]),
.rx_valid
(RxValid),
.rx_valid_h
(RxValidH),
.rx_active
(RxActive),
.rx_error
(RxError),
.data_out_low
(Data_Out[7:0]),
.data_out_high
(Data_Out[15:8]),
.line_state
(LineState),
.xcvr_select
(XcvrSelect),
.term_select
(TermSelect),
.op_mode
(OpMode),
.suspendm
(SuspendM),
.databus16_8
(DataBus16_8),
.address
(address),
780

USB 2.0 ULPI Monitor

Connect the USB 2.0 ULPI monitor pins to internal signals as specified in the pin out
between a USB controller and USB transceiver as shown in the Figure 19-4.
Figure 19-4. USB 2.0 ULPI Monitor Pin Diagram
clock
data[7:0] or
data[3:0]
address[6:0]
reset
USB 2.0
ULPI Monitor
dir
areset
nxt
end_point_config
stp
Table 19-5. USB 2.0 ULPI Monitor Pins

Pin
Description
address [6:0]
Address of the device or function. If the monitor is instantiated on the upstream

port of the device, then connect to the address register (register that holds the
assigned address).
areset
clock
Clock input. This clock is used to sample data on the ULPI bus.
data[7:0] or data[3:0]
It is bidirectional data bus with option of two bus widths, 8-bits wide and 4-bits
wide. The 8-bit data timed on rising edge of clock. (Optional) 4-bit data timed
on rising and falling edges of clock. In 4-bit data bus, least significant nibble is
transferred first on rising edge of clock. The most significant nibble is
transferred second on the falling edge of clock.
dir
Controls the direction of data bus. A 0 indicates data bus is driven by Link. A
1 indicates data bus is driven by Phy.
end_point_config
monitor. The value must not be greater than the NUMBER_OF_ENDPOINTS
parameter.
781

Table 19-5. USB 2.0 ULPI Monitor Pins (cont.)

Pin
Description
nxt
The Phy asserts nxt to throttle all data types, except register read data and the
RxCMD.
reset
stp
The Link assert stp to signal the end of a USB transmit packet or a register
write operation, and optionally to stop any receive. The stp signal must be
asserted in the cycle after the last data byte is presented on the bus.
Connectivity Notes
1. Input address should be connected to the address register of the device if the monitor is
instantiated on the upstream port of the device. If the monitor is instantiated on the
2. Input end_point_config configures the end points to be tracked. This input follows the
encoding scheme as explained below. For configuring the end points end point address,
transfer type supported by the end point, direction of the end point (IN or OUT), and
maximum packet size supported by the end point needs to be specified. Each end point
needs 21-bits for the configuration. The order in which these bits are used is as follows:
o
In this register, the A3 bit is the most significant bit, and S0 is the least
significant bit.
A3 A2 A1 A0
transfers.
T2 T1 T0
0
0
0
1
0
1
1
0
1
0
1
0
Control transfer
Interrupt transfer
Bulk transfer
Bits O1 and O0 specify the additional transaction opportunity per microframe as

follows:
0
0
782
0
1


1
1
o
0
1

Reserve
end_point_1 = 21'b 0000_0_001_00_0000010000

end_point_2 = 21'b 0001_1_010_00_0000001000

or
Monitor Parameters
Parameters shown in Table 19-6 configures a USB 2.0 ULPI monitor.
Table 19-6. USB2.0 ULPI Monitor Parameters
Order
Parameter
Default
Description
1.
Constraints_Mode

2.
PORT_TYPE
Configures the port type tracked by the monitor. Set

this parameter to the following:
port of the host.
port of the Hub.
port of the Hub.
port of the device.
783

Table 19-6. USB2.0 ULPI Monitor Parameters (cont.)

Order
Parameter
Default
Description
3.
ULPI_SIDE
Indicates on which side of the interface monitor is

instantiated. By default, the monitor is assumed to be
instantiated on the LINK side of the interface. Set it to 1
if the monitor is instantiated on the PHY side of the
interface.
4.
DATA_WIDTH
Indicates the data bus width of ULPI Interface. It can

either be set to 4 or 8. By default, it is set to 4.
5.
DEVICE_SPEED
Configures the monitor for device type in terms of

supported speed. Set this parameter to 0 if the ULP is
dual mode HS/FS. Set this parameter to 1 if the ULP is
FS only. Set this parameter to 2 if the ULP is LS only.
By default, this parameter is set to 0.
6.
NUMBER_OF_ENDPOINTS

Maximum number of control end points supported by
the monitor is 16.
7.
FRAME_INTERVAL_COUNT
7500
Configures the USB frame interval. This count is the

number of clock cycles between two consecutive SOF
frames, from end-of-packet of the SOF packet to the
end-of-packet of the next SOF packet. This parameter is
not applicable for full-speed only device. The default
value tracks a standard USB frame interval.
8.
COUNT

+/-62.5 ns and for FULL speed it is +/-500 ns.
9.
SEQUENCE_BIT_TRACKING_
ENABLE
Enables sequence-bit tracking in the monitor. Set this

parameter to 0 to disable sequence-bit tracking.
10.
PACKET_ISSUE_CHECK_
Configures the monitor to fire for the illegal issue of

token requests. By default, the monitor fires for these
conditions.
ENABLE
Example 1: If an IN token is issued to an OUT only end

point, then a monitor check fires when this parameter is
1.
device class requests are issued, then the monitor
checks fire when this parameter is 1.
11.
STP_ASSERT_TO_NXT_
ASSERT_DELAY_HS_MIN
15
Configures the minimum delay (in clock cycles)

between assertion of stp and assertion of nxt, when
operating in HS.
12.
STP_ASSERT_TO_NXT_
ASSERT_DELAY_FS_MIN

operating in FS.
13.
STP_ASSERT_TO_NXT_
ASSERT_DELAY_LS_MIN
77

operating in LS.
784


Order
Parameter
Default
Description
14.
STP_ASSERT_TO_NXT_
ASSERT_DELAY_HS_MAX
24
Configures the maximum delay (in clock cycles)

operating in HS.
15.
STP_ASSERT_TO_NXT_
ASSERT_DELAY_FS_MAX
18

operating in FS.
16.
STP_ASSERT_TO_NXT_
ASSERT_DELAY_LS_MAX
247

operating in LS.
17.
DIR_DEASSERT_TO_NXT_
ASSERT_DELAY_HS_MIN

between de-assertion of dir and assertion of nxt, when
operating in HS.
18.
ASSERT_DELAY_FS_MIN

operating in FS.
19.
ASSERT_DELAY_LS_MIN
77

operating in LS.
20.
ASSERT_DELAY_HS_MAX
14

operating in HS.
21.
ASSERT_DELAY_FS_MAX
18

operating in FS.
22.
ASSERT_DELAY_LS_MAX
247

operating in LS.
23.
DIR_DEASSERT_TO_DIR_
AND_NXT_ASSERT_DELAY_
HS_MIN

between de-assertion of dir and assertion of both nxt
and dir indicating packet receive, when operating in
HS.
24.
FS_MIN

and dir indicating packet receive, when operating in FS.
25.
LS_MIN

and dir indicating packet receive, when operating in LS.
26.
STP_ASSERT_TO_DIR_AND_
NXT_ASSERT_DELAY_HS_
MAX
92

between assertion of stp and assertion of both nxt and
dir indicating packet receive, when operating in HS.
27.
NXT_ASSERT_DELAY_FS_
MAX
80

dir indicating packet receive, when operating in FS.
785


Order
Parameter
Default
Description
28.
NXT_ASSERT_DELAY_LS_
MAX
718

dir indicating packet receive, when operating in LS.
29.
TIME_OUT_COUNT
800
Configures the number of clock cycles after which the

device or host is required to time out.
30.
OTG_DEVICE
Configures the monitor to support USB on-the-go

devices. Set this parameter to 1 to support USB
on-the-go devices. By default, USB on-the-go device is
not supported.
31.
HUB_TURNAROUND_
TIMEOUT_MIN
60000
Configures the minimum timeout interval for the

response of the host after the device has done the
K-chirp during speed negotiation protocol. After which
the device revert back to FS default state.
32.
HUB_TURNAROUND_
TIMEOUT_MAX
150000
Configures the maximum timeout interval for the

response of the host after the device has done the
K-chirp during speed negotiation protocol. Before
which the device should revert back to FS default state.
33.
HUB_CHIRP_K_TIMEOUT
3600
Configures the timeout interval for each K-chirp

initiated by the host during speed negotiation protocol.
34.
HUB_CHIRP_J_TIMEOUT
3600
Configures the timeout interval for each J-chirp

initiated by the host during speed negotiation protocol.
35.
HUB_CHIRP_K_MIN
2400
Configures the minimum time (in clock cycles) for

which host should drive chirp K during speed
negotiation protocol
36.
HUB_CHIRP_J_MIN
2400
Configures the minimum time (in clock cycles) for

which host should drive chirp J during speed
negotiation protocol.
37.
HUB_CHIRP_KJ_MIN
Configures the minimum number of chirp KJ sequence

host should transmit to acknowledge the reset sequence.
38.
SE0_COUNT_FULL_SPEED_
REVERSE_ MAX
187500
Configures the maximum time in number of clocks for

which SE0 has to be seen on the bus for reversal to full
speed mode.
39.
SE0_COUNT_FULL_SPEED_
REVERSE_MIN
180000
Configures the minimum time (in number of clocks) for

which SE0 has to be seen on the bus for reversal to full
speed mode.
40.
TIMEOUT
150
Configures the maximum time (in number of clocks) in

full speed mode for which SE0 has to be seen on the bus
for detecting reset.
41.
TIMEOUT
180000
Configures the number of clocks in full speed mode for

which J has to be seen on the bus for detecting suspend.
42.
TIMEOUT
6000
Configures the time in range of 100 us to 875 us to

sample the line state for detection of reset/suspend after
reversal to full speed mode.
43.
CLK_USABLE_TIMEOUT
336000

clock to be usable after J-SE0 transition is seen on the
bus.
786


Order
Parameter
Default
Description
44.
MIN_RESET_INTERVAL
600000
Configures the minimum reset interval of 10ms.
45.
CHIRP_KJ_START_TIMEOUT
6000
Configures the time 100 us in number of clocks for

Chirp-KJ sequence to start after device Chirp-K.
46.
TERM_SEL_DEASS_AFTER_
HS_DETECT_TIMEOUT
30000
Configures the number of cycles after which device

should enable HS terminations after it detects minimum
number of chirp-KJ sequence.
47.
DEV_CHIRP_K_ASSERT_
TIMEOUT
360000
Configures the maximum number of cycles to asserts

chirp-K on bus from HS Reset T0.
48.
DEV_CHIRP_K_TIMEOUT
348000

clocks for assertion of device chirp after detecting SE0
on the bus for reset from suspend.
49.
DEV_CHIRP_K_DEASS_
TIMEOUT_MAX
420000
Configures the maximum number of clocks before

which device chirp has to be de-asserted after it is
asserted.
50.
DEV_CHIRP_K_DEASS_
TIMEOUT_MIN
60000
Configures the minimum number of clocks after which

device chirp has to be de-asserted after it is asserted.
51.
DEV_REMOTE_WAKE_UP_
COUNT_MIN
300000
Configures the minimum time 5ms in clock cycles

before which a device capable of remote wake up must
not initiate resume.
52.
MAX_SUSPENDM_ASSERT_
INTERVAL
600000
Configures the maximum number of clock cycles by

which device should be suspended, drawing no more
than suspend current.
53.
SUSPENDM_DEASSERT_TO_
RESUME_K_ASSERT_
TIMEOUT
600000
Configures the maximum number of cycles by which

device should assert resume K, after SuspendM is
pulled high for remote wake-up.
54.
RESUME_K_ASSERT_MIN
60000
Configures the minimum number of clocks for which

resume K from device must be asserted.
55.
RESUME_K_ASSERT_MAX
900000
Configures the maximum number of clocks for which

resume K from device must be asserted.
56.
RESUME_NORMAL_
OPERATION_TIMEOUT
80
Configures the maximum number of clock cycles

before which the device should resume normal
operation after coming out of resume sequence.
57.
RESUME_K_DURATION_
LINE_STATE
1200000
Configures the minimum clocks (20 ms) for which

resume K, driven by host must be found on the
line_state.
58.
5
CLK_DETECT_DIR_
DEASSERTED_SUSPEND_MIN
59.
PRE_PID_LS_SYNC_MIN
20
Configures the number of clock cycles for which PHY

must drive idle between last bit of PRE PID and first bit
of LS SYNC.
60.
INIT_SE0_COUNT_DISCONN_
MIN
120000
Configures the minimum number of cycles for which

SE0 should be seen on linestate to initiate the SRP.
Configures the minimum clock edges to be seen before

exiting the low power mode.
787


Order
Parameter
Default
Description
61.
DATA_LINE_PULSE_
DURATION_MIN
300000
Configures the minimum number of cycles for which

data line pull up resistor is on during data-line pulsing
to initiate SRP.
62.
DATA_LINE_PULSE_
DURATION_MAX
600000
Configures the maximum number of cycles for which

data line pull up resistor is on during data-line pulsing
to initiate SRP.
Example 19-5 and Example 19-6 show instantiating the USB 2.0 ULPI monitors.
Example 1
This example instantiates a USB monitor to track a 4-bit ULP interface, full-speed only device.
Example 19-5. USB Monitor to Track an 4-bit ULP Interface
qvl_usb_2_0_ulpi_monitor
#( 0,
3,
/* PORT_TYPE */
0,
/* ULPI_SIDE */
4,
/* DATA_WIDTH */
1,
/* DEVICE_SPEED */
1,
60000,
30,
1,
1)
USB_ULPI_MON (
.clock
(clock),
.areset
(areset),
.reset
(reset),
.nxt
(nxt),
.stp
(stp),
.dir
(dir),
.data
(data),
.address
(address)
.number_of_active_endpoints (5'd1) );
788

Example 2
This example instantiates a USB monitor on the upstream port of a dual mode high-speed
device to track transactions of four end points. The address of the device is specified through the
address input. The ULP interface is a high-speed, 8-bit interface.
qvl_usb_2_0_ulpi_monitor
#( 0,
3,
/* PORT_TYPE */
0,
/* ULPI_SIDE */
8,
/* DATA_WIDTH */
0,
/* DEVICE_SPEED */
4,
7500, /* FRAME_INTERVAL_COUNT */
4,
1,
1)
USB_ULPI_MON (
.clock
(clock),
.areset
(areset),
.reset
(reset),
.nxt
(nxt),
.stp
(stp),
.dir
(dir),
.data
(data),
.address
(address)
.number_of_active_endpoints (5'd4) );
789

Monitor Checks
Monitor Checks
USB 2.0 Standard Monitor Checks
Table 19-7 lists the checks performed by the USB 2.0 standard monitor.
Table 19-7. USB 2.0 Standard Monitor Checks
Check ID
Violation
Description
USB_2_0_ACK_ISSUED_BY_
DEVICE_DURING_IN_XFR
A device can issue ACK

handshake only during
non-IN transaction.
An ACK handshake is returned only when a

handshake is expected for the data transfer.
The device can issue an ACK handshake
during OUT, SETUP, or PING transaction
after receiving the data packet. This check
fires if an ACK handshake is issued by the
device during an IN transaction. In an IN
transfer, the device can issue ACK for
SPLIT transactions.
HOST_DURING_NON_IN_XFR
A host can issue ACK

handshake only during IN
transaction.
An ACK handshake is returned only when a

The host can issue an ACK handshake
during an IN transaction after receiving the
data. This check fires if an ACK handshake
packet is issued by the host during non-IN
transactions.
USB_2_0_ACK_RECEIVED_
FOR_IN_TKN
Function should not respond

with ACK handshake for IN
token.
When a host issues the IN token, the

function should respond with either
STALL, NAK, or a return DATA packet.
This check fires if an ACK handshake is
returned for an IN token.
USB_2_0_ADDRESS_
KNOWN_DRIVEN
Input address is not driven to

a valid level.
Checks that the address input is both known

USB_2_0_BIT_STUFF_ERR_
HOST
Bit stuff error occurred.
A zero bit should be inserted after every six

consecutive ones. This check fires if seven
consecutive ones are sampled on the bus.
This check is active only on the
full-speed/low-speed buses. In a high-speed
bus, a bit stuff error is considered to be an
end-of-packet.
USB_2_0_BULK_ISO_ON_
LOW_SPD_BUS
Bulk transfers and

Isochronous transfers are not
supported by low-speed
devices.
Bulk and isochronous transfer types are not

supported by low-speed devices. This check
fires if a bulk transfer or an isochronous
transfer is initiated on a low-speed bus.
USB_2_0_BULK_XFR_
DATA_PID_ERR_HOST
A host or device should send

DATA0 PID in the data
packet of the first transaction
of a bulk transfer.
A host or device should always send a

DATA0 packet ID in the first data packet of
a bulk transfer. This check fires if the
DATA0 packet ID is not sent in the first
data packet of the bulk transfer. This check
assumes that the sequence bit is initialized
to zero after the device is configured.
USB_2_0_BIT_STUFF_ERR_
DEVICE
USB_2_0_BULK_XFR_
DATA_PID_ERR_DEVICE
790

Monitor Checks
Table 19-7. USB 2.0 Standard Monitor Checks (cont.)

Check ID
Violation
Description
USB_2_0_BULK_XFR_
SEQ_BIT_ERR_HOST
Sequence bit mismatch

occurred in the bulk transfer.
The packet ID received in the data packet

should match the expected packet ID. This
check fires if there is a mismatch between
the received packet ID and the expected
packet ID. The monitor toggles the
sequence bit (internal to the monitor)
whenever a transaction is completed. This
check is active only if the address received
in the token matches the address input.
USB_2_0_CLEAR_FEATURE_
HUB_REQUEST_ERR
A CLEAR_FEATURE hub
class request should have
windex of zero and wlength
of zero.
A CLEAR FEATURE (clear hub feature)

hub class request should have values of zero
for wlength and windex. This check fires if
any of these conditions are not satisfied.
USB_2_0_CLEAR_
FEATURE_REQUEST_
DEVICE_ERR
A CLEAR FEATURE
request (device as recipient)
should have zero value
windex.
A CLEAR FEATURE request with device

as recipient (bm_request_type[4:0] === 0)
should have zero values for windex. This
check fires if this condition is not met. The
correctness of wLength is checked by
assertion below.
USB_2_0_CLEAR_
FEATURE_REQUEST_ERR
A CLEAR_FEATURE
request should have a value
of zero for wlength.
A CLEAR FEATURE request should have

a zero value for wlength. This check fires if
the wlength field of CLEAR FEATURE
request is not zero.
USB_2_0_CLEAR_PORT_
FEATURE_REQUEST_ERR
A CLEAR_FEATURE (clear
port feature) hub class
request should have wlength
of zero.
A CLEAR FEATURE (clear port feature)

hub class request should have a value of
zero for wlength. This check fires if wlength
is not zero.
USB_2_0_CLEAR_REQUEST_
OTG_ERR
On-The-Go feature selector

cannot be cleared with a
CLEAR_FEATURE
command.
On-The-Go feature selector cannot be

cleared with a CLEAR_FEATURE
command.
USB_2_0_CLEARTT_
REQUEST_ERR
A CLEAR_TT_BUFFER
A CLEAR_TT_BUFFER hub class request
hub class request should have should have wlength of zero. This check
wlength of zero.
fires if the wlength field is not zero.
USB_2_0_BULK_XFR_
SEQ_BIT_ERR_DEVICE
USB_2_0_CSPLIT_TKN_U_BIT_ Illegal u bit in the

Complete-SPLIT token.
ERROR
The U bit in the complete-SPLIT token is

reserved and must be zero.
USB_2_0_CSPLIT_TO_ISO_
END_POINT
Complete SPLIT token

should not be issued for an
isochronous OUT transfer.
No handshaking is involved in isochronous

data transfers. Therefore, a complete-SPLIT
is not required. This check fires if the host
issues a complete-SPLIT token during an
USB_2_0_CTRL_XFR_
DATA_PHASE_DIR_ERR
Direction of data phase of

control transfer should match
the direction specified in the
setup data.
SETUP data specifies the direction of the

data phase of a control transfer. This check
fires if there is a mismatch between the
specified direction and the direction of the
data phase of the control transfer. This
791

Monitor Checks

Check ID
Violation
Description
USB_2_0_CTRL_XFR_DATA_
PHASE_LENGTH_ERR_HOST
A host or device should

transfer only wlength number
of bytes during the data phase
of control transfer.
The wlength field of the SETUP data

specifies the number of bytes to be
transferred by the host and the maximum
number of bytes that can be transferred by
the device during the data phase of a control
transfer. This check fires if the host
transfers more or less bytes than the
specified number of bytes. It also fires if the
device transfers more than the specified
number of bytes during the data phase of the
control transfer. This check is active only if
the address received in the token matches
the address input.

occurred in the control
transfer.

Packet ID MDATA and

DATA2 should be used for
high-speed split, high
bandwidth isochronous end
points only.
Packet IDs (PID) DATA2 and MDATA are

used for high-speed split, high bandwidth
isochronous end points. These PIDs should
not be used for non-split, Bulk, Control,
Interrupt transfer end points. This check
fires if DATA2, MDATA packet IDs are
detected.
Data packet CRC error.
The 16-bit CRC field is specified for data

packets to cover the data field of the data
packet. This check fires if an error is
detected in the CRC.
An isochronous transfer
should always use DATA0
packet id during transmission
of data packets.
A device or host controller should always

send the DATA0 packet ID during
isochronous transfers. A device or host
controller should be able to accept either a
DATA0 or DATA1 packet ID. This check
fires if a DATA1 packet is sent at the source
side. This check is active only when the
address specified in the token field matches
the address input.
Devices should not initiate a

packet transfer when the host
is not waiting.
Devices should always respond to a packet

issued by a host. For example, when the
host issues the IN token, devices should
return a DATA packet. When there is no
data packet or handshake packet due from
the devices, only the host is allowed to
initiate a packet transfer. This check fires if
devices initiate a packet transfer when there
is no packet due from them.
USB_2_0_CTRL_XFR_DATA_
PHASE_LENGTH_ERR_
DEVICE
USB_2_0_CTRL_XFR_SEQ_
BIT_ERR_HOST
USB_2_0_CTRL_XFR_SEQ_
BIT_ERR_DEVICE
USB_2_0_DATA2_MDATA_
FOR_NON_ISO_HOST
FOR_NON_ISO_DEVICE
USB_2_0_DATA_CRC_ERR_
HOST
DEVICE
USB_2_0_DATA_PID_
ERR_ISO_XFR_HOST
USB_2_0_DATA_PID_
ERR_ISO_XFR_DEVICE
USB_2_0_DEVICE_
INITIATED_XFR_WHEN_
HOST_NOT_WAITING
792

Monitor Checks

Check ID
Violation
Description
USB_2_0_DEVICE_ISSUED_
TKN
A device should not issue

token packets.
Only hosts can issue token packets. This

check fires if a token packet is issued by the
device. This check is not applicable if the
device is USB On-The-Go compliant.
USB_2_0_DM_KNOWN_
DRIVEN
Input dm is not driven to a

valid level.
Checks that the dm input is both known (not

only when oe_n is asserted.
USB_2_0_DP_KNOWN_
DRIVEN
Input dp is not driven to a

valid level.
Checks that the dp input is both known (not

only when oe_n is asserted.
USB_2_0_END_POINT_
CONFIG_KNOWN_DRIVEN
Input end_point_config is not Checks that the end_point_config input is

both known (not X) and driven (not Z).
USB_2_0_EXT_TKN_CRC_ERR
Extended Token packet CRC

error.
The five-bit CRC field is specified for

extended token to cover the bmAttributes of
EXT tokens. This check fires if an error is
USB_2_0_EXT_TKN_PKT_
ILLEGAL_bLinkState
Illegal bLinkState field in

Extended token packet.
The only legal value for bLinkState in

bmAttributes field of the extended token
packet is L1 (Sleep). All other values are
reserved.
ILLEGAL_SUBPID
Illegal SubPID field in

SubPID field of extended token packet

contains reserved values. The only legal
value is LPM token.
SIZE_ERR
Extended Token packet

should have 24 bits.
Extended token packet should always be

terminated by an end-of-packet delimiter
after receiving 3 bytes or 24-bits. This
check fires if end-of-packet is not received
after 24-bits, or the end-of-packet is
received before 24-bits.
USB_2_0_FRAME_NUMBER_
ERR
Illegal frame number.
Frame numbers received in two consecutive

frames should be in increasing order, and
they should have a difference of 1.
However, frame numbers detected in the
SOF packets in a microframe should remain
the same. This check fires if the frame
numbers received in two successive frames
do not follow this criterion.
USB_2_0_FUNCTION_MAX_
INTER_PKT_DLY_ERR
A device should start

responding to a packet within
the specified maximum
interpacket delay.
If a device is expected to provide a response

to the host, then the maximum inter-packet
delay is specified to be 6.5-bit times for a
full/low-speed bus and 192-bit times for a
high-speed bus. The monitor assumes 7-bit
times for a full/low-speed bus. This check
fires if the device does not start responding
within the specified maximum inter-packet
delay. This check is active only if the
PORT_TYPE parameter is 1, 2, or 3.
793

Monitor Checks

Check ID
Violation
Description
USB_2_0_FUNCTION_MIN_
INTER_PKT_DLY_ERR
A device should allow the

specified bit times of interpacket delay.
A device (function or hub) must provide a

specified minimum number of bit times of
inter-packet delay. This delay is measured
at the responding device with bit times
measured in terms of the response bit times.
For a high-speed bus, the device must
provide a minimum of 8-bit times of interpacket delay. For a full-speed/low-speed
bus, the device must provide a minimum of
2-bit times of inter-packet delay. This check
fires if this minimum inter-packet delay is
violated by the device. This check is active
only if the PORT_TYPE parameter is 1, 2,
or 3.
USB_2_0_FUNCTION_
RESPONDS_FOR_ERR_PKT

for packets received with an
error.
Devices should not respond for packets

received with an error, they should wait for
a timeout. This check fires if the device
starts responding to a packet received with
an error.
USB_2_0_GET_
CONFIGURATION_
REQUEST_ERR
A GET_CONFIGURATION
request should have a value
of zero for wvalue, windex,
and a value of one for
wlength.
A GET CONFIGURATION request should

have zero values of wvalue, windex and a
value of one for wlength. This check fires if
any of these conditions are not satisfied.
USB_2_0_GET_HUB_
STATUS_REQUEST_ERR
A GET_STATUS (get hub

status) hub class request
should have wvalue, windex
of zero and wlength of four.
A GET STATS (get hub status) hub class

request should have a value of zero for
wvalue, windex and a value of four for
wlength. This check fires if any of these
conditions are not satisfied.
USB_2_0_GET_
INTERFACE_REQUEST_ERR
A GET_INTERFACE
request should have wvalue
of zero and wlength of one.
A GET INTERFACE request should have a

zero value for wvalue and a value of one for
wlength. This check fires if any one of these
USB_2_0_GET_INTERFACE_
REQUEST_TO_HUB
GET_INTERFACE request
should not be issued to the
hub.
A hub response for the GET INTERFACE

request is not defined. This check fires if a
GET INTERFACE request is issued to the
hub. This check is active only if the
PORT_TYPE parameter is 1. This check is
active only if the
PACKET_ISSUE_CHECK_ENABLE
parameter is 1. This check assumes that the
address specified through the address input
is the hub address.
USB_2_0_GET_PORT_
STATUS_REQUEST_ERR
A GET_STATUS (get port

should have wvalue of zero
and wlength of four.
A GET STATUS (get port status) hub class

wvalue and a value of four for wlength. This
check fires if any of these conditions are not
satisfied.
794

Monitor Checks

Check ID
Violation
Description
USB_2_0_GET_STATUS_
REQUEST_DEVICE_ERR
A GET_STATUS request
with device as recipient
should have wvalue of zero,
windex of zero, and wlength
of two.
A GET STATUS request with device as

recipient (bm_request_type[4:0] === 0)
should have values of zero for wvalue,
windex, and a value of two for wlength.
This check fires if any one of these
USB_2_0_GET_STATUS_
REQUEST_NON_DEVICE_ERR
with nondevice as recipient
and wlength of two.
A GET STATUS request with nondevice as

recipient should have a value of zero for
wvalue and a value of two for wlength. This
satisfied.
USB_2_0_HANDSHAKE_PKT_
IN_ISO_XFR
Handshake packets should

not be generated for
isochronous transfers.
Isochronous transactions do not support

handshake packets. This check fires when a
NAK or STALL handshake packet is
returned during an IN transaction. This
check is active only when the address
specified in the token field matches the
address input.
USB_2_0_HANDSHAKE_
PKT_SIZE_ERR_HOST_
A handshake packet should

have only 8-bits.
A handshake packet should always contain

8-bits. This check fires if an end-of-packet
is not received after receiving all the 8-bits
of the handshake packet.
USB_2_0_HIGH_SPEED_
ENDPOINT ISSUED_ERR
A high-speed end point

returned ERR handshake
packet.
ERR is a high-speed only handshake that is

returned to allow a high-speed hub to report
an error on a full-speed/low-speed bus. It is
only returned by a hub as a part of a SPLIT
transaction. This check fires if a device
other than a hub returned an ERR
handshake. This check is enabled only when
parameter is set.
USB_2_0_HOST_ISSUED_
ILLEGAL_HANDSHAKE
Host returned STALL, NAK,

NYET, ERR handshake
packet.
The host is not allowed to return STALL,

NAK, NYET, ERR under any condition.
This check fires if any of the above
handshakes are returned by the host.
USB_2_0_HANDSHAKE_
PKT_SIZE_ERR_DEVICE
USB_2_0_HOST_ISSUED_TKN_ A host should not issue a

token before the completion
BEFORE_XFR_COMPLETE
of the current transaction.
A host should not initiate a transaction

before the current transaction is complete.
This check fires if the host initiates a
transaction by issuing a token before the
completion of the current transaction. This
check is active only if the receive address
address input.
795

Monitor Checks

Check ID
Violation
Description
USB_2_0_HOST_MAX_
INTER_PKT_DLY_ERR
A host should start

responding to a packet within
the specified maximum
interpacket delay.
If a host is expected to provide a response to

a device, then the maximum inter-packet
delay is specified to be 7.5-bit times for a
full-speed/low-speed bus and 192-bits for a
high-speed bus. The monitor assumes 7-bit
times for a full-speed/low-speed bus. This
check fires if the host does not start
responding within the specified maximum
inter-packet delay.
USB_2_0_HOST_MIN_
INTER_PKT_DLY_ERR
A host should allow the

specified bit times of interpacket delay.
A host must provide the specified minimum

number of bit times of inter-packet delay.
For a high-speed bus, the host must provide
a minimum of 88-bit times of inter-packet
delay while transmitting two packets in a
row. While transmitting after receiving a
packet, an inter-packet delay of 8-bit times
should be provided. For a full-speed/lowspeed bus, the host must provide a
minimum of 2-bit times of inter-packet
delay. This check fires if the minimum
inter-packet delay is less than the specified
bit times. This check is active only if the
PORT_TYPE parameter is 0.
USB_2_0_HOST_RESPONDS_
FOR_ERR_PKT
Host should not respond for

packets received with an
error.
A host should not respond for packets

received with an error. The host should wait
for 18-bit times so that devices timeout.
This check fires if the host starts responding
to a packet received with an error.
USB_2_0_HUB_CLASS_
REQUEST_TO_DEVICE
HUB class specific requests

should not be issued to
functions.
Hub class requests should not be issued to

devices. This check fires if a hub class
request is issued to the device when the
device address is configured. This check is
active only if the PORT_TYPE parameter is
3.
USB_2_0_ILLEGAL_BULK_
XFR_WMAX_PACKET_SIZE
Illegal wmaxpacketsize
specified for bulk transfer
end points.
The allowed values for the maximum packet

size supported by bulk transfer end points is
8, 16, 32, or 64 bytes for full-speed devices,
and 512 bytes for high-speed devices. This
check fires if any other value is specified.
USB_2_0_ILLEGAL_CTRL_
specified for control transfer
end points.

size supported for control transfers is 8, 16,
32, or 64 bytes for full-speed devices, 8
bytes for low-speed devices, and 64 bytes
for high-speed devices. This check fires if
any other value is specified.
USB_2_0_ILLEGAL_
HANDSHAKE_LPM_REQ
ACK, NYET, or STALL are

the only legal handshake
response for LPM
transaction.
ACK/NYET/STALL are the only legal

handshake response by device to L1
transition request through extended token
from host.
796

Monitor Checks

Check ID
Violation
Description
USB_2_0_ILLEGAL_
INTERRUPT_XFR_WMAX_
PACKET_SIZE
specified for interrupt
transfer end points.

size supported by interrupt transfer end
points is 64 bytes or less for full-speed
devices, 1024 bytes or less for high-speed
devices, and 8 bytes or less for low-speed
devices. This check fires if any other value
is specified.
USB_2_0_ILLEGAL_
ISOCHRONOUS_XFR_
WMAX_PACKET_SIZE
specified for isochronous

size supported by isochronous transfer end
points is 1023 bytes for full-speed devices
USB_2_0_ILLEGAL_SE0_
SIGNALING_HOST
Illegal SE0 signaling on the

bus.
Any sequence of SE0 that is neither an

end-of-packet nor a reset is treated by the
monitor as an illegal sequence of SE0.
Example: A sequence of three SE0s
followed by a J is treated as an illegal SE0
signaling on bus. This check fires if an
illegal sequence of SE0 is sampled on the
USB bus. Applicable for full-speed/lowspeed signaling only.
USB_2_0_ILLEGAL_
TOKEN_ON_FULL_SPD_LINK
Packet ID SPLIT, MDATA,

DATA2, PING, ERR, NYET
is not allowed on a fullspeed/low-speed link.
Packet IDs SPLIT, NYET, DATA2,

MDATA, PING, ERR should not be
detected on a full-speed/ low-speed link.
This check fires if any of the above PIDs are
detected.
USB_2_0_IN_END_POINT_
RECEIVED_OUT_TKN
Host should not issue OUT

token to IN only end point.
A host should not initiate an OUT

transaction to an IN only end point. This
check fires if the host issues an OUT token
to an IN only end point. This check is active
only when the address input matches the
address received in the tokens. This check is
enabled only if the PACKET_ISSUE_
CHECK_ENABLE parameter is 1.
USB_2_0_INT_XFR_DATA_
PID_ERR_HOST
A host or device should send

of an interrupt transfer.
A host or device should always send a

DATA0 packet ID in the first data packet of
an interrupt transfer. This check fires if the
data packet of the interrupt transfer. This
check assumes that the sequence bit is
initialized to zero after the device is
configured.

occurred in the interrupt
transfer.

USB_2_0_ILLEGAL_SE0_
SIGNALING_DEVICE
PID_ERR_DEVICE
USB_2_0_INT_XFR_SEQ_BIT_
ERR_HOST
USB_2_0_INT_XFR_SEQ_BIT_
ERR_DEVICE
797

Monitor Checks

Check ID
Violation
Description
USB_2_0_INVALID_
SIGNALING_ON_BUS_HOST
Invalid signaling levels on

the USB bus.
A logic high sampled on both dm and dp

inputs is considered as invalid signaling.
This check fires if an invalid signaling level
is sampled on the bus.
USB_2_0_LPM_DATA0_TKN_
WITHOUT_EXT_TKN
Extended token packet

received without EXT token.
EXT token must be transmitted before LPM

token (Extended token packet). Similarly
DATA0 packet should always follow token
packet.
USB_2_0_NO_ACK_
HANDSHAKE_FOR_SETUP
Function should
acknowledge with ACK
handshake when setup data is
received without an error.
If SETUP data is received without error,

then the function should respond with an
ACK handshake. This check fires if a
function does not respond with ACK for a
SETUP data received without error. This
check is active only if the PORT_TYPE
parameter is 1 or 3.
USB_2_0_NO_DATA1_PID_
DURING_STATUS_PHASE_
HOST
STATUS phase of data

transfer should always
contain DATA1 packet id.
The STATUS phase of a control transfer

should always contain the DATA1 packet
ID in the data packet. This check fires if the
DATA1 packet ID is not present in the
status phase of a control transfer. This check
is active only if the receive address
address input.
USB_2_0_NO_RESPONSE_
FOR_PKT_RECEIVED_
WITHOUT_ERR
Device should respond with

proper response packet.
If a device receives a data packet or a token

packet without any error, then it must
respond with a proper handshake. This
check fires if the device does not respond.
USB_2_0_NO_STATUS_
PHASE_AFTER_SETUP_
PHASE
Status phase should follow

the setup phase when
wlength field of the setup
data contains a value of zero.
The wlength field of SETUP data specifies

whether the control transfer has a data phase
or not. This check fires if the value of
wlength is zero, and a data transfer is
initiated during the control transfer. This
check is active only if the received address
specified in the token matches the address
input.
USB_2_0_NON_CONTROL_
ENDPOINT_ZERO
End point zero should always

be a control end point.
End point address zero is reserved for

control transfers. This check fires if any
other type of transfer is defined for end
point zero.
USB_2_0_NON_INTEGRAL_
NUMBER_OF_BYTES_HOST
A data packet should always

contain integral number of
bytes.
Data must always be sent in an integral

number of bytes. This check fires when
there is a nonintegral number of bytes in the
data field of the data packet.
USB_2_0_INVALID_
SIGNAIGNALING_ON_BUS_
DEVICE
DEVICE
USB_2_0_NON_INTEGRAL_
NUMBER_OF_BYTES_DEVICE
798

Monitor Checks

Check ID
Violation
Description
USB_2_0_NUMBER_OF_
ENDPOINTS_ERROR
Maximum number of end

points supported is 31 for
full-speed/high-speed
devices and 3 for low-speed
devices.
A maximum of 31 end points are allowed

for full-speed/high-speed devices. For
low-speed devices, a maximum of 3 end
points are allowed.
USB_2_0_OE_KNOWN_
DRIVEN
Input oe_n is not driven to a

valid level.
Checks that the oe_n input is both known

USB_2_0_OUT_ENDPOINT_
RECEIVED_IN_TKN
Host should not issue IN

A host should not initiate an IN transaction
token to OUT only end point. to an OUT only end point. This check fires
if the host issues an IN token to an OUT
only end point. This check is active only
when the address input matches the address
received in the tokens. This check is
USB_2_0_PING_
HANDSHAKE_ERROR
High-speed end points must

respond with either NAK,
ACK, or STALL handshake.
NAK, ACK, STALL are the only handshake

packets returned in response to a PING
token. This check fires if any other
handshake packet is detected.
USB_2_0_PING_NEXT_
TRANSACTION_ERROR
OUT transaction did not

follow successful PING.
The host should initiate an OUT transfer as

the next transfer to a Control/Bulk OUT end
point if the end point returned an ACK
handshake for the PING token. However,
IN transfers can be initiated as the next
transfer to the end point if the end point is
both IN and OUT. This check fires if the
next transfer initiated is not an OUT
transfer.
USB_2_0_PING_NOT_
INITIATED
Host must issue PING token

to a Control/Bulk OUT end
point.
If the host receives a NAK/NYET

handshake or timeout for an OUT transfer,
then it must issue a PING token to the end
point. The host must continue to issue the
PING token until it receives an ACK
handshake for the PING token. This check
fires if this protocol is violated.
USB_2_0_PKT_ID_CHK_
FIELD_ERR_HOST
Packet ID check field should

be ones complement of the
packet ID field.
Packet ID consists of a four-bit packet type

field and a four-bit check field. The packet
ID check field should be ones complement
of the packet ID field. This check fires if the
packet ID check field is not ones
complement of packet ID field.
PRE packets should not be

issued on low-speed/highspeed interfaces.
Preamble PRE packets are issued to hubs.

When a PRE packet is received, hubs enable
the low-speed downstream ports. This
check fires if PRE packets are issued on a
low-speed/high-speed interface.
USB_2_0_PKT_ID_CHK_
FIELD_ERR_DEVICE
USB_2_0_PRE_PID_ISSUED
799

Monitor Checks

Check ID
Violation
Description
USB_2_0_REQUEST_NOT_
DEFINED
Brequest not defined.
The brequest field of the SETUP data

should be a defined value. This check fires
if brequest specified in the SETUP data is
undefined. This check is active only for
STANDARD requests (i.e., if the type field
of bmrequestfield is 00). This check is
active only if the PACKET_ISSUE_
USB_2_0_REQUEST_
RECIPIENT_NOT_DEFINED
Recipient field of
Recipient field of bmrequesttype specified
bmrequesttype is not defined. in the SETUP data should be a defined
value. This check fires if the values are
undefined. This check is active if the
parameter is 1.
USB_2_0_REQUEST_TYPE_
NOT_DEFINED
Type field in the

Type field of bmrequesttype specified in the
bmrequesttype is not defined. SETUP data should be a defined value. This
check fires if the values are undefined. This
check is active if the PACKET_ISSUE_
USB_2_0_RESET_TT_ERR
A RESET_TT hub class

request should have wvalue,
wlength of zero.
USB_2_0_RESPONSE_
FOR_OUT_SETUP_TOKEN
Device should not respond

A device should not respond to OUT or
with any packets on reception SETUP tokens. Devices are allowed to
of OUT or SETUP tokens.
respond only after receiving the data packet
associated with the OUT or SETUP
responds to an OUT or SETUP token.
USB_2_0_SET_ADDRESS_
REQUEST_ERR
A SET_ADDRESS request
should have wlength and
windex of zero.
A SET ADDRESS request should have

values of zero for wlength and windex. This
satisfied.
USB_2_0_SET_
CONFIGURATION_
REQEST_ERR
A SET_CONFIGURATION
and windex of zero.
A SET CONFIGURATION request should

have values of zero for wlength and windex.
This check fires if any of these conditions
are not satisfied.
USB_2_0_SET_FEATURE_
REQUEST_DEVICE_ERR
A SET FEATURE request

(device as recipient) should
have wlength and windex of
zero.
A SET FEATURE request with device as

recipient should have zero values of
wlength and windex. This check fires if any
of these conditions are not satisfied.
REQUEST_ERR
A SET_FEATURE request
should have wlength of zero.
A SET FEATURE request should have a

zero value for wlength. This check fires if
wlength is not zero.
USB_2_0_SET_HUB_
FEATURE_REQUEST_ERR
A SET_FEATURE (set hub

feature) hub class request
should have windex, wlength
of zero.
A SET FEATURE (set hub feature) hub

class request should have a value of zero for
windex and wlength. This check fires if any
of these conditions are not satisfied.
800
A RESET_TT hub class request should

have wvalue of zero and wlength of zero.
This check fires if a nonzero value is
detected.

Monitor Checks

Check ID
Violation
USB_2_0_SET_
INTERFACE_REQUEST_ERR
A SET_INTERFACE request A SET INTERFACE request should have a

should have wlength of zero. value of zero for wlength. This check fires if
wlength of SET INTERFACE request is not
zero.
USB_2_0_SET_INTERFACE_
REQUEST_TO_HUB
SET INTERFACE request

hub.
A hub response for the SET INTERFACE

request is not defined. This check is active
only if the PORT_TYPE parameter is 1.
This check fires if a SET INTERFACE
request is issued to the hub. This check is
active only if the
is the hub address.
USB_2_0_SET_PORT_
FEATURE_REQUEST_ERR
A SET_FEATURE (set port

A SET FEATURE (set port feature) hub

class request should have a value of zero for
wlength. This check fires if wlength is not
zero.
USB_2_0_SETUP_DATA_PID_
ERR
Setup data should always

A SETUP transaction always uses the

DATA0 packet ID in the data packet. This
check fires if the DATA0 packet ID is not
present in the data packet of a SETUP
transaction.
USB_2_0_SETUP_DATA_
SIZE_ERR
SETUP data should always

contain 8 bytes.
A SETUP data should always contain 8

bytes. This check fires if SETUP data does
not contain 8 bytes.
USB_2_0_SETUP_TKN_TO_
NON_CTRL_ENDPOINT
A host should not issue

SETUP token to noncontrol
endpoints.
A host should not initiate a control transfer

to noncontrol end points. This check fires if
SETUP tokens are issued to noncontrol end
points. This check is active only if the
receive address specified in the token field
matches the address input.
USB_2_0_SOF_PKT_ISSUED_
TO_LOW_SPD_DEVICE
SOF packets should not be

issued to low-speed devices.
SOF packets are to be ignored by the lowspeed devices. However, to defeat illegal
behavior, the monitor tracks whether SOF
packets are issued to low-speed devices.
This check fires if the SOF packets are seen
on the low-speed interface. This check is
Description
801

Monitor Checks

Check ID
Violation
Description
USB_2_0_SOF_PKTS_AT_
IRREGULAR_INTERVALS
SOF packets should be

detected every 1 ms (+/- SOF
jitter range) for a full-speed
bus, and once in every 125 us
(+/-SOF jitter range) for a
high-speed bus.
SOF packets are issued by the host at a

nominal rate of once in every 1 ms for fullspeed buses and once every 125 us for highspeed bus. This time is mapped into the
number of clock cycles and is specified
through FRAME_INTERVAL_COUNT.
This interval is measured from the
end-of-packet of the SOF packet to the
end-of-packet of the next SOF packet. This
check fires if the SOF packets are received
earlier than the frame interval or are not
received at the frame interval. This check is
active only when a high-speed/full-speed
interface is tracked by the monitor. This
assertion does not check correctness of
Frame number.
SOF_JITTER_INTERVAL_COUNT is
used to specify the SOF jitter range.
USB_2_0_SPEED_KNOWN_
DRIVEN
Input speed is not driven to a

valid level.
Checks that the speed input is both known

USB_2_0_SPLIT_PKT_SIZE_
ERR
A SPLIT token should have

32-bits.
SPLIT token is a special token. This should

be terminated by an end-of-packet delimiter
after receiving 32-bits. This check fires if
the end-of-packet is not received after
32-bits, or the end-of-packet is received
before 32-bits.
USB_2_0_SPLIT_TKN_E_BIT_
ERROR
Illegal e bit in the SPLIT

For bulk/control IN/OUT, Interrupt
token. Expected e bits is 1'b0. IN/OUT, and isochronous IN start-splits,
the E field must be zero. This check fires if
the E field is 1.
USB_2_0_SPLIT_TKN_S_BIT_
ERROR
Illegal s bit in the SPLIT

token. Expected s bit is 1'b0.
If the ET field of the SPLIT token specifies

Bulk or Isochronous IN transfer, then S
should be set to 0. This check fires if the S
bit is set to 1.
USB_2_0_SSPLIT_NO_
PAYLOAD_HOST
A Start-SPLIT token issued

to an isochronous end point
with start, middle, or end
encoding must have a
payload.
This check fires if the data packet following

the OUT token does not have a data
payload.

with STALL or NAK
handshake for setup data
during the control transfer.
A function receiving a SETUP must accept

the SETUP data and respond with an ACK.
This check fires if a function returns a
STALL or NAK handshake for a SETUP
transaction.
USB_2_0_SSPLIT_NO_
PAYLOAD_DEVICE
USB_2_0_STALL_NAK_
HANDSHAKE_FOR_SETUP
802

Monitor Checks

Check ID
Violation
Description
USB_2_0_STALL_RECEIVE_
ERR
If STALL handshake is
received during data phase or
status phase of the control
transfer, then successive
access to that control
endpoint should result in the
reception of stall handshake
until the completion of next
setup phase.
Control end points return a STALL

handshake when the device is unable to
complete a command. The function will
continue to return a STALL in response to
any IN or OUT transaction until the next
SETUP transaction is complete. This check
fires if any other handshake packet is
returned by the devices after STALL is
returned. This check is active only when the
address specified in the token field matches
the address input.
USB_2_0_STOP_TT_
REQUEST_ERR
A STOP_TT hub class

and wlength of zero.
A STOP_TT hub class request should have

wvalue and wlength zero. This check fires if
a nonzero value is detected.
USB_2_0_SYNC_FRAME_
REQUEST_ERR
A SYNCH FRAME request

and wlength of two.
A SYNCH FRAME request should have a

value of zero for wvalue and two for
wlength. This check fires if any of the above
condition is not satisfied.
USB_2_0_SYNCH_FRAME_
REQUEST_TO_HUB
SYNCH FRAME request

hub.
A hub response for the SYNCH FRAME

This check fires if a SYNCH FRAME
active only if the
is the hub address.
USB_2_0_TKN_CRC_ERR
Token packet CRC error.

tokens to cover the address, end point
number of IN, OUT, SETUP, SPLIT tokens,
and the frame number of the SOF token.
This check fires if an error is detected in the
CRC.
USB_2_0_TKN_PKT_SIZE_ERR
Token packets should have

24-bits.
Token packet should always be terminated

by an end-of-packet delimiter after
receiving 3 bytes or 24-bits. This check fires
if end-of-packet is not received after
24-bits, or the end-of-packet is received
before 24-bits. This check also covers the
PING special token.
USB_2_0_TOKEN_BEFORE_
TIMEOUT
Host should wait for the

specified number of bit times
to indicate timeout.
If a data packet is corrupted, then the host

should wait for a specified number of bit
times before sending the next token. In
addition, the host should wait for a specified
number of bit times for a response before
sending the next token. For a fullspeed/low-speed bus, the specified number
of bit times is 18. For a high-speed bus, the
specified number of bit times is 816. This
check fires if these conditions are violated.
803

Monitor Checks

Check ID
Violation
Description
USB_2_0_WMAX_PKT_
SIZE_ERR_HOST
A host or device should not

transfer more than the
negotiated maximum number
of bytes in the data packet.
A host or device can transfer only the

negotiated number of bytes in the data
packet of the transfer. This negotiated
maximum number of bytes are specified in
the end point configuration information
(wMaxPacketSize). This check fires if the
host or device transfers more than the
specified maximum number of bytes in the
data packet.
USB_2_0_WMAX_PKT_
SIZE_ERR_DEVICE
USB 2.0 UTMI Monitor Checks

Table 19-8 and Table 19-9 list the checks performed by the USB 2.0 UTMI monitor.
Table 19-8. USB 2.0 UTMI Monitor UTMI Checks
804
Check ID
Violation
Description
USB_2_0_UTMI_DATA_
CHANGE_BEFORE_TX_
READY
Value on DataIn bus must be

held until TxReady is sampled
asserted.
The value driven on the DataIn bus must

be held until the transmit hold shift
register is loaded with the new data. The
value on the DataIn bus is allowed to
change only after the data are loaded.
This check fires if the value on the
DataIn bus changes before data are
loaded.
USB_2_0_UTMI_DATA_
HIGH_KNOWN_DRIVEN
Data[15:8] is not driven to a

valid level.
Checks that Data8_15 is both known and

driven.
USB_2_0_UTMI_DATA_
IN_KNOWN_DRIVEN
DataIn is not driven to a valid

level.
Checks that DataIn is both known and

driven.
USB_2_0_UTMI_DATA_
LOW_KNOWN_DRIVEN
Data[7:0] is not driven to a

valid level.
Checks that Data7_0 is both known and

driven.
USB_2_0_UTMI_DATA_
OUT_KNOWN_DRIVEN
DataOut is not driven to a valid

level.
Checks that DataOut is both known and

driven.
USB_2_0_UTMI_
DATABUS16_8_KNOWN_
DRIVEN
DataBus16_8 is not driven to a

valid level.
Checks that DataBus16_8 is both known

and driven.
USB_2_0_UTMI_ILLEGAL_
RX_VALID
More than one byte transferred

after the negation of the
RxValidH signal.
When a packet has an odd number of

bytes, only one byte transfer is allowed
after the de-assertion of the RxValidH.
This transfer is indicated by asserting
RxValid for one clock per byte time.
This check fires if RxValid is sampled
asserted for more than one clock.

Monitor Checks
Table 19-8. USB 2.0 UTMI Monitor UTMI Checks (cont.)

Check ID
Violation
Description
RX_VALIDH
RxValidH signal should not be

asserted without asserting the
RxValid signal.
RxValidH indicates that the data on

data_out [15:8] is valid. RxValidH
should not be asserted without asserting
RxValid. This check fires if RxValidH is
sampled asserted and RxValid is not
asserted.
TX_READY
More than one byte transferred

after the negation of TxValidH
signal.
When a packet has an odd number of

bytes, only one byte transfer is allowed
after TxValidH de-asserts. This transfer
is indicated by asserting TxValid for one
clock and TxValidH is de-asserted in
that clock cycle. This check fires if
TxValid is sampled asserted for more
than one clock.
TX_VALIDH
TxValidH signal should not be

asserted without asserting the
TxValid signal.
TxValidH indicates that the data on

data_in [15:8] is valid. TxValidH should
not be asserted without asserting
TxValid.
USB_2_0_UTMI_LINE_
STATE_KNOWN_DRIVEN
LineState is not driven to a

valid level.
Checks that LineState is both known and

driven.
USB_2_0_UTMI_NUMBER_
OF_ENDPOINTS_ERROR

points supported is 32 for fullspeed/high-speed devices and
3 for low-speed devices.
A Maximum of 16 OUT and 16 IN end

points are allowed for full-speed/highspeed devices. For low-speed devices, a
maximum of 3 end points are allowed.
USB_2_0_UTMI_INVALID_
CHIRP_SEQUENCE
Chirp sequence for high-speed

detection is invalid.
Checks if at least 6 chirps of alternating

KJ chirps are seen before returning to
normal operation from the disable NRZI
encoding operation.
USB_2_0_UTMI_TIMEOUT_
KJ_CHIRP_DURATION
Chirp duration for K or J

driven by the hub during highspeed detection sequence, has
timed out.
Checks if the chirp duration of K or J

chirp has timed out the maximum
duration of 60 us.
USB_2_0_UTMI_J_STATE_
DURING_DEV_K_CHIRP
LineState has transitioned to J

state while device was sending
K chirp during speed detect
sequence.
Checks if the chirp changed to J state

during the device K chirp during speed
negotiation sequence.
USB_2_0_UTMI_DEV_
INITIATE_WITH_J_DURING_
CHIRP
LineState has transitioned to J

state in order to begin chirping
by the device.
Checks if device initiated the chirp

sequence with J state instead of K state.
USB_2_0_UTMI_TERM_SEL_
DEASSERT_TIMEOUT
The term_select signal did not

change to low level before
500 us after detecting the
device as a high-speed device.
Checks if the term_select changed to low

level within 500 us of detection of highspeed.
USB_2_0_UTMI_RX_
ACTIVE_KNOWN_DRIVEN
RxActive is not driven to a

valid level.
Checks that RxActive is both known and

driven.
805

Monitor Checks
806
Check ID
Violation
Description
USB_2_0_UTMI_RX_
DEASSERT_TO_TX_VALID_
ASSERT_MAX_ERROR
Maximum inter-packet delay

specification is violated while
transmitting a packet after the
reception of a packet.
USB 2.0 specifies the maximum interpacket delay when the USB host/device
is required to respond to the packet. The
host/device should start responding
within the specified maximum delay.
This check fires if the maximum interpacket delay is violated.
USB_2_0_UTMI_RX_
DEASSERT_TO_TX_VALID_
ASSERT_MIN_ERROR
Minimum inter-packet delay

transmitting a packet after the
reception of a packet.
USB 2.0 specifies that there should be a

minimum inter-packet delay when the
USB host/device is required to respond
to a packet. This check fires if the
minimum inter-packet delay is violated.
USB_2_0_UTMI_RX_
ERROR_KNOWN_DRIVEN
RxError is not driven to a valid

level.
Checks that RxError is both known and

driven.
USB_2_0_UTMI_RX_
VALID_ASSERTED_
BEFORE_RX_ACTIVE
RxValid signal should be

asserted after the assertion of
the RxActive signal.
Transceiver asserts RxActive to indicate

that a SYNC pattern is detected on the
USB bus. The transceiver then asserts
RxValid to indicate that it has a byte to
be read. RxValid should not be asserted
before the assertion of the RxActive
signal. This check fires if RxValid is
asserted before the assertion of the
RxActive.
USB_2_0_UTMI_RX_
VALID_KNOWN_DRIVEN
RxValid is not driven to a valid

level.
Checks that RxValid is both known and

driven.
USB_2_0_UTMI_RX_VALID_
MORE_THAN_ONE_CLOCK
RxValid signal should be

asserted for one clock per byte
time.
UTMI specifies that the RxValid signal

should be asserted for one clock cycle
per byte time. Byte time is defined to be
32 clock cycles in full-speed or lowspeed only implementations, and 40
clock cycles in full-speed mode of
high-speed/full-speed implementations.
This check fires if RxValid is asserted
for more than one clock.
USB_2_0_UTMI_RX_
VALID_NOT NEGATED
RxValid signal asserted after

RxValid should be de-asserted once
the negation of RxError signal. RxError is sampled asserted. This check
fires if RxValid is not negated after
detecting RxError.
USB_2_0_UTMI_RX_
VALIDH_KNOWN_DRIVEN
RxValidH is not driven to a

valid level.
Checks that RxValidH is both known

and driven.
USB_2_0_UTMI_
RXERROR_ASSERTED
Illegal RxError signal

assertion.
Transceiver asserts RxError only when

the transceiver is receiving a packet.
Reception of a packet is indicated by
asserting the RxActive signal. This
check fires if RxError is asserted and the
RxActive and RxValid signals are not
asserted.
USB_2_0_UTMI_TERM_
SELECT_KNOWN_DRIVEN
TermSelect is not driven to a

valid level.
Checks that TermSelect is both known

and driven.

Monitor Checks

Check ID
Violation
Description
USB_2_0_UTMI_TX_READY_
ASSERTED_MORE_THAN_
ONE_CLOCK
TxReady signal should be

asserted for one clock per byte
time.
UTMI specifies that TxReady should be

asserted for one clock cycle per byte
time. Byte time is defined to be 32 clock
cycles in full-speed or low-speed only
implementations, and 40 clock cycles in
full-speed mode of high-speed/fullspeed implementations. This check fires
if TxReady is asserted for more than one
clock.
USB_2_0_UTMI_TX_
READY_KNOWN_DRIVEN
TxReady is not driven to a

valid level.
Checks that TxReady is both known and

driven.
USB_2_0_UTMI_TX_VALID_
DEASSERT_TO_RX_ACTIVE_
ASSERT_MAX_ERROR
Maximum inter-packet delay

receiving a packet after the
transmission of a packet.
USB 2.0 specifies the maximum interpacket delay when the USB host/device
is required to respond to the packet. The
host/device should start responding
within the specified maximum delay.
This check fires if the maximum interpacket delay is violated.
ASSERT_MIN_ERROR
Minimum inter-packet delay

receiving a packet after the
transmission of a packet.
USB 2.0 specifies that there should be a

minimum inter-packet delay when the
USB host/device is required to respond
to a packet. This check fires if minimum
the inter-packet delay is violated.
USB_2_0_UTMI_TX_
VALID_KNOWN_DRIVEN
TxValid is not driven to a valid

level.
Checks that TxValid is both known and

driven.
USB_2_0_UTMI_TX_
VALID_RX_ACTIVE_
ASSERTED
TxValid and RxActive signal

should not be asserted
together.
USB is a half duplex bus. Therefore,

data can be either transmitted or
received; TxValid and RxActive should
not be asserted together. This check fires
if TxValid and RxActive are sampled
asserted.
USB_2_0_UTMI_TX_
VALIDH_KNOWN_DRIVEN
TxValidH is not driven to a

valid level.
Checks that TxValidH is both known

and driven.
USB_2_0_UTMI_VALIDH_
KNOWN_DRIVEN
ValidH is not driven to a valid

level.
Checks that ValidH is both known and

driven.
USB_2_0_UTMI_XCVR_
SELECT_KNOWN_DRIVEN
XcvrSelect is not driven to a

valid level.
Checks that XcvrSelect is both known

and driven.
USB_2_0_UTMI_INTER_RX_
VALID_DELAY
Consecutive RXValid does not

occur at legal intervals.
While receiving the Data in 8 bit

interface, Consecutive RXValid should
come at 40th, 45th, or 50th clock cycle
in FS mode; 32nd, 36th, or 40th clock
cycle in 8 LS only and FS only mode.
USB_2_0_UTMI_INTER_TX_
READY_DELAY
Consecutive TXReady does

not occur at legal intervals.
While transmitting the Data in 8 bit

interface, Consecutive TXReady byte
should come at 40th, 45th, or 50th clock
cycle; the 32nd, 36th or 40th clock cycle
in LS only and FS only mode.
807

Monitor Checks
808
Check ID
Violation
Description
USB_2_0_UTMI_RX_ACTIVE_
ASSERT_ERROR
RXActive is not negated for

minimum legal interval
between consecutive received
packets.
RXActive must be negated for at least 1

clock between the consecutive received
Packets in HS mode and 4 Clocks
between consecutive received Packets in
FS mode, FS only mode, and LS only
mode.
USB_2_0_UTMI_SUSPENDM_
TERM_SELECT_FS
While SuspendM is active

TermSelect is not in FullSpeed mode.
While SuspendM is active, the

TermSelect must always be in FullSpeed mode.
DEASSERT_MORE_THAN_
ONE_CLOCK
RXValid goes low for more

than one consecutive clock
cycle while receiving data in
HS mode.
While receiving the Data, RXValid must

not go low for more than one
consecutive clock cycle in HS mode.
DEASSERT_MORE_THAN_
ONE_CLOCK
TXReady goes low for more

While transmitting the Data, TXReady
than one consecutive clock
must not go low for more than one
cycle while transmitting data in consecutive clock cycle in HS mode.
HS mode.
DEASSERT_TO_TX_READY_
DEASSERT_ERROR
TXReady negedge does not

After exactly one clock of the negedge
come exactly after one clock of of TXValid comes the negedge of
TXValid negedge.
TXReady in HS mode.
RX_VALID_ACTIVITY_
WHILE_TX
RXValid and/or RXActive is

While transmission of Data, RXValid
active while data transmission. and/or RXActive must not be active.
TX_VALID_ACTIVITY_
WHILE_RX
TXReady and/or TXValid is

active while data reception.
While reception of Data, TXReady

and/or TXValid must not be active.
ASSERTION_DELAY
RXValid remains low after

legal limit while RXActive is
asserted during data reception.
RXValid must not remain low for more

than 50 consecutive clocks while
RXActive is asserted in FS mode and 40
consecutive clocks in FS only and LS
only mode.
ASSERTION_DELAY
TXReady remains low after

legal limit while TXValid is
asserted during data
transmission.
TXReady must not remain low for more

than 50 consecutive clocks while
TXValid is asserted, and 40 consecutive
clocks in FS only and LS only mode.
USB_2_0_UTMI_FULL_
SPEED_REVERSAL_ERROR
Full-speed reversal timeout.
If the Device in High-Speed mode

detects bus inactivity for more than 3
milliseconds to 3.125 milliseconds, then
the UTM places itself into Full-Speed
mode. (XcvrSelect = 1, TermSelect = 1).
NEGATION_RESET_ERROR
SuspendM is not
When reset is entered from a suspended
combinatorially negated when state SuspendM is combinatorially
reset is entered from suspended negated.
state.
USB_2_0_UTMI_DEV_CHIRP_
ASSERT_MAX_DELAY
Device ChirpK assertion

timeout.
After first reset SE0 has been detected,

the Device has up to 6 milliseconds to
assert Chirp K.

Monitor Checks

Check ID
Violation
Description
USB_2_0_UTMI_REMOTE_
WAKE_UP_MIN_DELAY
Early remote wake-up

signaling.
Device with remote wake-up capability

must wait for at least 5 milliseconds
after the bus is in the Idle state, before
sending remote wake-up resume
signaling.
USB_2_0_UTMI_RESUME_
SIGNAL_ASSERT_MAX_
DURATION_ERROR
Illegally long resume signaling

asserted on the bus.
The Remote wake-up Device must hold

the resume signaling for no more than 15
milliseconds.
DEASSERT_MAX_DELAY
Device chirp on bus after legal

limit.
The device chirp must last no later than

7.0 ms after HS Reset T0 (SE0 asserted
for first time).
USB_2_0_UTMI_CHIRP_KJ_
START_DELAY
ChirpKJ not asserted by

downstream port within legal
limit.
After release of ChirpK, downstream

port must start assertion of ChirpKJ
sequence on the bus no later than 100 us.
USB_2_0_UTMI_ILLEGAL_OP_ Reserved OpMode used at

level0.
MODE
OpMode[0:1] 11b is reserved in level0

mode.
USB_2_0_UTMI_REMOTE_
WAKE_UP_MAX_DELAY
FS K is not asserted within

legal limit after SuspendM is
negated.
Device must assert FS 'K' on the bus no

later than 10 ms after SuspendM is
asserted.
SIGNAL_ASSERT_MIN_
DURATION_ERROR
Illegally short resume

signaling asserted on the bus.
While generation of resume signaling,

the assertion of TXValid and all 0s data
is presented on the DataIn bus for at
least 1 ms.
SUSPEND_ASSERT_MAX_
DELAY

timeout after entering reset
handshake from suspend state.
After the first clock transition ChirpK

must be asserted no later than 5.8 ms
after assert of SuspendM.
USB_2_0_UTMI_RESET_I
NTERVAL_MIN_ERROR
Minimum reset interval

violated.
Minimum Reset interval must be 10 ms.
ASSERT_MAX_DELAY
SuspendM not asserted within

legal limit after detecting
suspend mode.
The latest time device must be

suspended drawing no more than
suspend current.
USB_2_0_UTMI_SPEED_
MISMATCH_AFTER_RESUME
Speed mismatch between

presuspend and post resume.
The device should return to the same

speed after resume as it was before
entering suspend mode.
NORMAL_OPER_MAX_
ERROR
Normal operation timeout after The device should resume normal

resume release.
operation after 1.25 us.
USB_2_0_UTMI_RESUME_K_
DURATION_MIN_ERROR
Resume K not seen on the bus

for minimum legal duration.
Resume K must be on the bus for

minimum of 20 ms.
USB_2_0_UTMI_INVALID_
SIGNALING_ON_LINE_STATE
Invalid LineState.
LineState[1:0] must not be 11b in all

modes and 10b in high-speed mode.
809

Monitor Checks

Check ID
Violation
Description
DEASSERT_TO_RX_VALID_
DEASSERT_ERROR
RXValid negedge does not

occur simultaneously with
RXActive negedge.
If Negedge of RXActive is detected,

then negedge of RXValid must also be
detected on the same clock.
USB_2_0_UTMI_HS_RX_
ACTIVE_ASSERT_TO_RX_
VALID_ASSERT_DELAY
RXActive assert to RXValid

assert delay not in the legal
range in HS mode.
RXValid goes high in the range of 1 to 4

clocks from RxActive goes high in HS
Mode with 8 bit interface and 1 to 2
clocks in 16-bit interface HS mode.
USB_2_0_UTMI_FS_LS_RX_
ACTIVE_ASSERT_TO_RX_
VALID_ASSERT_DELAY
RXActive assert to RXValid

assert delay violated in FS/LS
mode.
RXValid goes high at the 32nd clock

after posedge of RxActive in FS only
and LS only mode with 8 bit interface;
40th clock in FS mode with 8 bit
interface.
USB_2_0_UTMI_RX_VALIDH_
MORE_THAN_ONE_CLOCK
RXValidH signal asserted for

more than one clock cycle per
byte time.
RXValidH signal should not be asserted

for more than one clock cycle per byte
time.
USB_2_0_UTMI_SE0_ASSERT_ SE0 not seen on the bus at

expected time after resume K
TO_END_RESUME_COUNT_
is asserted.
ERROR
810
SE0 must be seen on LineState 20 ms

after the resume K assertion.
PORT_TYPE_LEVEL_0
UTMI level 0 can only operate

in peripheral mode.
PORT_TYPE can be 1 or 3 when

UTMI_LEVEL is set to level 0.
USB_2_0_UTMI_DP_
PULLDOWN_VALUE_ERROR
Illegal DpPulldown value.
DpPulldown signal must be 1b for host

controllers and 0 for peripheral mode.
USB_2_0_UTMI_DM_
Illegal DmPulldown value.
DmPulldown signals must be 1b for host

controllers and 0 in peripheral mode.
USB_2_0_UTMI_HOST_
DISCONNECT_XCVR_
SELECT_ERROR
XcvrSelect not switched to FS

mode when HostDisconnect is
asserted in HS mode.
If in HS mode a HostDisconnect is set to

1b, then at that moment the macrocell
will be switched to FS mode
(XcvrSelect = 01b).
USB_2_0_UTMI_HOST_
DISCONNECT_UPDATE_
ERROR
Early update of
HostDisconnect after reversal
to FS mode.
HostDisconnect signal cannot be

updated for 4 ms from the transition into
full-speed.
COMB_OP_MODE_XCVR_
SELECT
Illegal OpMode and

XcvrSelect combination.
If OpMode is set to 11b and XcvrSelect

not equal to 00b, then the behavior of the
transceiver is undefined.
XCVR_SELECT
Illegal XcvrSelect at level 2.
XcvrSelect cannot be 11b in level 2.
USB_2_0_UTMI_ID_DIG_
KNOWN_DRIVEN
IdDig is not driven to a valid

level.
Checks that IdDig is both known and

driven.
USB_2_0_UTMI_SESS_END_
KNOWN_DRIVEN
SessEnd is not driven to a valid

level.
Checks that SessEnd is both known and

driven.

Monitor Checks

Check ID
Violation
Description
USB_2_0_UTMI_HOST_
DISCONNECT_KNOWN_
DRIVEN
HostDisconnect is not driven

to a valid level.
Checks that HostDisconnect is both

known and driven.
USB_2_0_UTMI_VBUS_
VALID_KNOWN_DRIVEN
VbusValid is not driven to a

valid level.
Checks that VbusValid is both known

and driven.
USB_2_0_UTMI_AVALID_
KNOWN_DRIVEN
AValid is not driven to a valid

level.
Checks that AValid is both known and

driven.
USB_2_0_UTMI_BVALID_
KNOWN_DRIVEN
BValid is not driven to a valid

level.
Checks that BValid is both known and

driven.
USB_2_0_UTMI_DRV_VBUS_
KNOWN_DRIVEN
DrvVbus is not driven to a

valid level.
Checks that DrvVbus is both known and

driven.
USB_2_0_UTMI_DISCHRG_
VBUS_KNOWN_DRIVEN
DischrgVbus is not driven to a

valid level.
Checks that DischrgVbus is both known

and driven.
USB_2_0_UTMI_CHRG_VBUS_ ChrgVbus is not driven to a

valid level.
KNOWN_DRIVEN
Checks that ChrgVbus is both known

and driven.
USB_2_0_UTMI_DP_
PULLDOWN_KNOWN_
DRIVEN
DpPulldown is not driven to a

valid level.
Checks that DpPulldown is both known

and driven.
USB_2_0_UTMI_DM_
PULLDOWN_KNOWN_
DRIVEN
DmPulldown is not driven to a

valid level.
Checks that DmPulldown is both known

and driven.
USB_2_0_UTMI_ID_PULLUP_
KNOWN_DRIVEN
IdPullup is not driven to a

valid level.
Checks that IdPullup is both known and

driven.
ON-THE-GO DEVICE CHECKS

USB_2_0_UTMI_SESS_NOT_
VALID_FOR_NORMAL_OPER
Valid session not in progress

for doing normal operation.
A session must be in progress for doing

normal transactions in On-The-Go
capable devices.
USB_2_0_UTMI_END_PREV_
SESS_BEFORE_NEW_SESS_
REQ_ERROR
Previous session must be over

before requesting new session.
B-Device cannot request a new session

until it has determined the end of
previous session.
USB_2_0_UTMI_DEV_
DISCONN_BEFORE_SRP_
ERROR
Device must be disconnected

before starting session request
protocol.
SE0 must be detected on the LineState

for at-least 2 ms before starting Session
request protocol. This ensures that
A-Device has detected a disconnect
condition from the device.
USB_2_0_UTMI_SRP_AT_
NON_FULL_SPEED
Session request protocol not

initiated at full-speed.
A On-The-Go B-Device is only allowed

to initiate SRP at full-speed.
811

Monitor Checks

Check ID
Violation
Description
USB_2_0_UTMI_VBUS_AND_
DATA_LINE_PULSING_
ORDER_ERROR
VBUS pulsing must always

follow data-line pulsing.
VBUS pulsing must always follow dataline pulsing.
USB_2_0_UTMI_DATA_LINE_
PULSE_DURATION_ERROR
Data-line pulsing duration

violated.
Data-line pulsing duration must be in the

range of 5 to 10 msec.
USB_2_0_UTMI_HOST_
RECEIVED_SOF_WITHOUT_
HNP
SOF cannot be received from

the device before Host
SOF cannot be received from the device

before Host negotiation protocol.
USB_2_0_UTMI_AVALID_
ASSERT_ERROR
AValid signal must be asserted

when VbusValid is asserted.
AValid signal must be asserted when

VbusValid is asserted.
USB_2_0_UTMI_BVALID_
ASSERT_ERROR
BValid signal must be asserted

if a VbusValid is asserted.
BValid signal must be asserted if a

VbusValid is asserted.
USB_2_0_UTMI_ON_THE_GO_ UTM interface at Level 0 does

not support On-The-Go
SUPPORT_ERROR
devices.
UTM interface at Level 0 does not

support On-The-Go devices.
LINE_STATE_WHEN_
SESSION_NOT_VALID
LineState not SE0 when

session not in progress.
LineState must be 00b when a valid

session is not in progress or session
request protocol is not under progress.
Table 19-9. USB 2.0 UTMI Monitor USB 2.0 Checks

Check ID
Violation
Description
A device can issue an ACK

handshake only during the
non-IN transaction.
ACK handshake is returned only when a

Device can issue an ACK handshake
during an OUT, SETUP, or PING
transaction after receiving the data packet.
This check fires if the ACK handshake is
issued by the device during an IN
transaction. In an IN transfer, the device
can issue an ACK for SPLIT transactions.
HOST_DURING_NON_IN_
XFR
A host can issue an ACK

handshake only during the IN
transaction.

data. This check fires if an ACK
handshake packet is issued by the host
during the non-IN transactions.
USB_2_0_ACK_
RECEIVED_FOR_IN_TKN

token.
When a host issues the IN token, function

should respond with either STALL, NAK,
or return DATA packet. This check fires if
an ACK handshake is returned for the IN
token.
812

Monitor Checks
Table 19-9. USB 2.0 UTMI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_BULK_ISO_
ON_LOW_SPD_BUS
Bulk transfers and

devices.
Bulk and isochronous transfer types are

not supported by low-speed devices. This
check fires if a bulk transfer or an
isochronous transfer is initiated on a lowspeed bus.
USB_2_0_BULK_XFR_
DATA_PID_ERR_HOST
A Host or Device should send

of a bulk transfer.
Host or device should always send the

DATA0 packet ID in the first data packet
of a bulk transfer. This check fires if a
data packet of a bulk transfer. This check

Packet ID received in the data packet

HUB_REQUEST_ERR
A CLEAR_FEATURE hub
windex of zero and wlength of
zero.
CLEAR FEATURE (clear hub feature)

hub class request should have values of
zero for wlength and windex. This check
fires if any of these conditions is not
satisfied.
REQUEST_DEVICE_ERR
A CLEAR FEATURE request

have zero value wlength and
windex.
CLEAR FEATURE request with device as

should have zero values for windex and
conditions is not satisfied.
REQUEST_ERR
A CLEAR_FEATURE
request should have a value of
zero for wlength.
CLEAR FEATURE request should have

the wlength field of a CLEAR FEATURE
USB_2_0_CLEAR_PORT_
FEATURE_REQUEST_ERR
port feature) hub class request
CLEAR FEATURE (clear port feature)

zero for wlength. This check fires if
OTG_ERR

CLEAR_FEATURE
command.

command.
USB_2_0_CLEARTT_
REQUEST_ERR
A CLEAR_TT_BUFFER hub
wlength of zero.
CLEAR_TT_BUFFER hub class request

should have wlength of zero. This check
USB_2_0_CSPLIT_TKN_U_
BIT_ERROR
Illegal u bit in the CompleteSPLIT token.

reserved and must be set to zero.
USB_2_0_BULK_XFR_
DATA_PID_ERR_DEVICE
USB_2_0_BULK_XFR_
SEQ_BIT_ERR_HOST
USB_2_0_BULK_XFR_
SEQ_BIT_ERR_DEVICE
813

Monitor Checks
Check ID
Violation
Description
USB_2_0_CSPLIT_TO_
ISO_END_POINT
Complete-SPLIT token should No handshaking is involved in isochronous

not be issued for an
data transfers. Therefore, complete-SPLIT
USB_2_0_CTRL_XFR_
DATA_PHASE_DIR_ERR

with the direction specified in
the setup data.

is active only if the address received in the
token matches the address input.
USB_2_0_CTRL_XFR_
DATA_PHASE_LENGTH_
ERR_HOST
A Host or Device should


the number of bytes to be transferred by
the host and the maximum number of
bytes that can be transferred by the device
during the data phase of a control transfer.
This check fires if the host transfers more
or fewer bytes than the specified number
of bytes. It also fires if the device transfers
more than the specified number of bytes
This check is active only if the address
received in the token matches the address
input.

transfer.

Packet ID MDATA and

points only.
Packet IDs (PIDs) DATA2 and MDATA

are used for high-speed split, high
bandwidth isochronous end points. These
PIDs should not be used for nonsplit, bulk,
control, interrupt transfer end points. This
check fires if DATA2, MDATA packet
IDs are detected.

USB_2_0_CTRL_XFR_
DATA_PHASE_LENGTH_
ERR_DEVICE
USB_2_0_CTRL_XFR_
SEQ_BIT_ERR_HOST
USB_2_0_CTRL_XFR_
SEQ_BIT_ERR_DEVICE
FOR_NON_ISO_HOST
FOR_NON_ISO_DEVICE
HOST
DEVICE
814

Monitor Checks
Check ID
Violation
Description
USB_2_0_DATA_PID_ERR_
ISO_XFR_HOST
of data packets.

send the DATA0 packet ID during the
controller should be able to accept either
DATA0 or DATA1 packet IDs. This check
fires if a DATA1 packet is sent at the
source side. This check is active only when
the address specified in the token field
matches the address input. This check is
active only for a full-speed bus.
USB_2_0_DEVICE_
INITIATED_XFR_WHEN_
HOST_NOT_WAITING

is not waiting.
Devices should always respond to packets

issued by the host. For example, when the
host issues an IN token, devices should
data packet or handshake packet from the
devices, only the host is allowed to initiate
a packet transfer. This check fires if the
device initiates a packet transfer when
there is no packet due.
TKN

token packets.

check fires if a token packet is issued by
the device. This check is not applicable if
the device is USB on-the-go compliant.
USB_2_0_EXT_TKN_CRC_
ERR

error.

extended token to cover the bmAttributes
of EXT tokens. This check fires if an error
is detected in the CRC.
ILLEGAL_bLinkState


reserved.
ILLEGAL_SUBPID


value is LPM token.
SIZE_ERR


ERROR
Frame numbers received in two

consecutive frames should be in the
increasing order, and they should have a
difference of 1. However, frame numbers
detected in the SOF packets in a
microframe should remain the same. This
check fires if the frame numbers received
in two successive frames do not follow
these criteria.
ISO_XFR_DEVICE
815

Monitor Checks
Check ID
Violation
Description
USB_2_0_FUNCTION_

error.

received with an error. Devices should
wait for timeout. This check fires if the
device starts responding to a packet
received with an error.
USB_2_0_GET_
CONFIGURATION_
REQUEST_ERR
A GET_CONFIGURATION
zero for wvalue and windex,
wlength.
GET CONFIGURATION request should

have zero values for wvalue and windex,
and a value of one for wlength. This check
satisfied.
USB_2_0_GET_HUB_
STATUS_REQUEST_ERR

should have wvalue and
of four.
GET STATS (get hub status) hub class

request should have values of zero for
wvalue and windex, and a value of four for
REQUEST_ERR
A GET_INTERFACE request
and wlength of one.
GET INTERFACE request should have

zero value for wvalue, and a value of one
for wlength. This check fires if any of
these conditions is not satisfied.
REQUEST_TO_HUB
should not be issued to hub.
Hub response for a GET INTERFACE

CHECK_ENABLE parameter is 1. This
check assumes that the address specified
through the address input is the hub
address.
USB_2_0_GET_PORT_
STATUS_REQUEST_ERR

GET STATUS (get port status) hub class

wvalue and a value of four for wlength.
is not satisfied.
USB_2_0_GET_STATUS_
REQUEST_DEVICE_ERR
of two.
GET STATUS request with device as

should have values of zero for wvalue and
is not satisfied.
USB_2_0_GET_STATUS_
REQUEST_NON_DEVICE_
ERR
and wlength of two.
GET STATUS request with nondevice as

wvalue, and a value of two for wlength.
is not satisfied.
USB_2_0_HANDSHAKE_
PKT_IN_ISO_XFR
Handshake packets should not

be generated for isochronous
transfers.

handshake packets. This check fires if a
address input.
816

Monitor Checks
Check ID
Violation
Description
USB_2_0_HANDSHAKE_
PKT_SIZE_ERR_HOST

have only 8-bits.

USB_2_0_HIGH_SPEED_
ENDPOINT ISSUED_ERR

packet.
ERR is a high-speed only handshake that

is returned to allow a high-speed hub to
report an error on a full-speed/low-speed
bus. It is only returned by a hub as a part of
a SPLIT transaction. This check fires if a
device other than hub returned an ERR
handshake. This check is enabled only
when the
parameter is 1.
ILLEGAL_HANDSHAKE

NYET, ERR handshake
packet.

NAK, NYET, or ERR under any
condition. This check fires if any of these
handshakes is returned by the host.
TKN_BEFORE_XFR_
COMPLETE
A Host should not issue a

Host should not initiate a transaction
token before the completion of before the current transaction is complete.
the current transaction.
This check fires if the host initiates a
transaction by the issue of a token before
the completion of the current transaction.
This check is active only if the received
address specified in the token field
FOR_ERR_PKT

Host should not respond for packets
packets received with an error. received with an error. The host should
wait for 18-bit times so that devices
timeout. This check fires if the host starts
responding to a packet received with an
error.
USB_2_0_HUB_CLASS_
REQUEST_TO_DEVICE

functions.

request is issued to a device when the
active only if the PORT_TYPE parameter
is 3.
specified for bulk transfer end
points.
Allowed values for maximum packet size

supported by bulk transfer end points is 8,
16, 32, and 64 bytes for full-speed devices,
end points.

supported for control transfers is 8, 16, 32,
and 64 bytes for full-speed devices, 8 bytes
for low-speed devices, and 64 bytes for
high-speed devices. This check fires if any
other value is specified.
USB_2_0_HANDSHAKE_
PKT_SIZE_ERR_DEVICE
817

Monitor Checks
Check ID
Violation
Description
USB_2_0_ILLEGAL_
HANDSHAKE_LPM_REQ

response for LPM transaction. transition request through extended token
from host.
USB_2_0_ILLEGAL_
INTERRUPT_XFR_WMAX_
PACKET_SIZE
specified for interrupt transfer
end points.

supported by interrupt transfer end points
is 64 bytes or less for full-speed devices,
1024 bytes or less for high-speed devices,
and 8 bytes or less for low-speed devices.
This check fires if any other value is
specified.
USB_2_0_ILLEGAL_
ISOCHRONOUS_XFR_
WMAX_PACKET_SIZE

supported by isochronous transfer end
and 1024 bytes for high-speed devices.
specified.
USB_2_0_ILLEGAL_TOKEN_
ON_FULL_SPD_LINK

DATA2, PING, ERR, and
NYET are not allowed on a
full-speed/low-speed link.

MDATA, PING, and ERR should not be
detected on a full-speed/low-speed link.
This check fires if any of these PIDs are
detected.
RECEIVED_OUT_TKN

Host should not initiate an OUT

transaction to an IN only end point. This
check fires if the host issues an OUT token
to an IN only end point. This check is
active only when the address input
matches the address received in the tokens.
This check is enabled only if the
parameter is 1.
USB_2_0_INT_XFR_
DATA_PID_ERR_HOST


of an interrupt transfer. This check fires if
a DATA0 packet ID is not sent in the first
data packet of an interrupt transfer. This
configured.

transfer.


EXT token must be transmitted before

LPM token (Extended token packet).
Similarly DATA0 packet should always
follow token packet.
PID_ERR_DEVICE
USB_2_0_INT_XFR_
SEQ_BIT_ERR_HOST
USB_2_0_INT_XFR_
SEQ_BIT_ERR_DEVICE
WITHOUT_EXT_TKN
818

Monitor Checks
Check ID
Violation
Description
USB_2_0_NO_ACK_
HANDSHAKE_FOR_SETUP
Function should acknowledge

with ACK handshake when
setup data is received without
an error.
If SETUP data is received without an

error, then the function should respond
with an ACK handshake. This check fires
if a function does not respond with ACK
for SETUP data received without an error.
PORT_TYPE parameter is 1 or 3.
HOST

transfer should always contain
DATA1 packet id.
STATUS phase of a control transfer

should always contain the DATA1 packet
ID in the data packet. This check fires if
the DATA1 packet ID is not present in the
status phase of a control transfer. This
address input.
FOR_PKT_RECEIVED_
WITHOUT_ERR

If a device receives a data packet or a

token packet without any error, then it
must respond with a proper handshake.
This check fires if the device does not
respond.
USB_2_0_NO_STATUS_
PHASE_AFTER_SETUP_
PHASE
Status phase should follow the

setup phase when wlength
field of setup data contains a
value of zero.

whether or not the control transfer has a
data phase. This check fires if the value of
wlength is zero and a data transfer is
initiated during a control transfer. This
input.
ENDPOINT_ZERO


point zero.
RECEIVED_IN_TKN
Host should not issue IN token Host should not initiate an IN transaction
to OUT only end point.
to an OUT only end point. This check fires
if the host issues IN token to an OUT only
end point. This check is active only when
the address input matches the address
USB_2_0_PING_
HANDSHAKE_ERROR

ACK or STALL handshake.
DEVICE
NAK, ACK, STALL are the only

handshake packets returned in response to
a PING token. This check fires if any other
819

Monitor Checks
Check ID
Violation
Description
USB_2_0_PING_NEXT_
TRANSACTION_ERROR

Host should initiate an OUT transfer as the

next transfer to a control/bulk OUT end
point, if the end point returned an ACK
transfer to the end point, if the end point is
transfer.
USB_2_0_PING_NOT_
INITIATED

point.

USB_2_0_PKT_ID_CHK_
FIELD_ERR_HOST

packet ID field.

ID check field is ones complement of the
packet ID field. This check fires if the
complement of the packet ID field.


When a PRE packet is received, hubs
enable the low-speed downstream ports.
This check fires if PRE packets are issued
on a low-speed/high-speed interface.
USB_2_0_REQUEST_
NOT_DEFINED
The brequest field of SETUP data should

be a defined value. This check fires if
brequest specified in the SETUP data is
STANDARD requests, (i.e., the type field
USB_2_0_REQUEST_
Recipient field of
bmrequesttype is not defined.

in SETUP data should be a defined value.
This check fires if the value is undefined.
This check is active if the
parameter is 1.
USB_2_0_REQUEST_
TYPE_NOT_DEFINED
Type field in the

The type field of bmrequesttype specified

parameter is 1.
USB_2_0_RESET_TT_
DESCRIPTOR_REQUEST_
ERR

RESET_TT hub class request should have

wvalue of zero and wlength of zero. This
check fires if a nonzero value is detected.
USB_2_0_PKT_ID_CHK_
FIELD_ERR_DEVICE
820

Monitor Checks
Check ID
Violation
Description
USB_2_0_RESPONSE_FOR_
OUT_SETUP_TOKEN

with any packets on reception
A device should not respond for OUT or

SETUP tokens. Devices are allowed to
respond only after receiving the data
packet associated with an OUT or SETUP
REQUEST_ERR
windex of zero.
SET ADDRESS request should have

values of zero for wlength and windex.
is not satisfied.
USB_2_0_SET_
CONFIGURATION_
REQEST_ERR
A SET_CONFIGURATION
and windex of zero.
SET CONFIGURATION request should

have values of zero for wlength and
windex. This check fires if any of these
REQUEST_DEVICE_ERR

zero.
SET FEATURE request with device as

wlength and windex. This check fires if
any of these conditions is not satisfied.
REQUEST_ERR
SET FEATURE request should have zero

value for wlength. This check fires if
USB_2_0_SET_HUB_
FEATURE_REQUEST_ERR

should have windex and
wlength of zero.
SET FEATURE (set hub feature) hub class

windex and wlength. This check fires if
REQUEST_ERR
A SET_INTERFACE request
SET INTERFACE request should have a

value of zero for wlength. This check fires
if the wlength of SET INTERFACE
REQUEST_TO_HUB

Hub response for a SET INTERFACE

address.
USB_2_0_SET_PORT_
FEATURE_REQUEST_ERR

SET FEATURE (set port feature) hub

class request should have a value of zero
for wlength. This check fires if wlength is
not zero.
USB_2_0_SETUP_DATA_
PID_ERR

A SETUP transaction always uses DATA0

packet ID in the data packet. This check
fires if the DATA0 packet ID is not
present in the data packet of a SETUP
transaction.
USB_2_0_SETUP_DATA_
SIZE_ERR

contain 8 bytes.
SETUP data should always contain 8

bytes. This check fires if SETUP data does
not contain 8 bytes.
821

Monitor Checks
Check ID
Violation
Description
NON_CTRL_ENDPOINT
A Host should not issue

SETUP token to the
noncontrol endpoints.
Host should not initiate a control transfer

to the noncontrol end points. This check
fires if SETUP tokens are issued to
noncontrol end points. This check is active
only if the received address specified in the
token field matches the address input.
TO_LOW_SPD_DEVICE

This check fires if the SOF packets are
seen on the low-speed interface. This
check is active only if the PACKET_
ISSUE_CHECK_ENABLE parameter is
1.
IRREGULAR_INTERVALS

high-speed bus.

nominal rate of once in every 1 ms for fullspeed buses and once every 125 us for
high-speed bus. This time is mapped into
the number of clock cycles and is specified
This interval is measured from the end-ofpacket of the SOF packet to end-of-packet
of the next SOF packet. This check fires if
the SOF packets are received earlier than
the frame interval or not received at the
frame interval. This check is active only
when a high-speed/full-speed interface is
tracked by the monitor. This assertion does
not check correctness of Frame number.
ERR

32-bits.
SPLIT token is a special token. This

should be terminated by an end-of-packet
delimiter after receiving 32-bits. This
after 32-bits or end-of-packet is received
before 32-bits.
USB_2_0_SPLIT_TKN_E_
BIT_ERROR

token. Expected e bits is 1'b0.
For bulk/control IN/OUT, interrupt

IN/OUT, and isochronous IN start-splits,
the E field must be set to zero. This check
fires if the E field is set to one.
USB_2_0_SPLIT_TKN_S_
BIT_ERROR

If the ET field of the SPLIT token

specifies bulk or isochronous IN transfer,
then S should be set to 0. This check fires
if the S bit is set to 1.
USB_2_0_SSPLIT_NO_
PAYLOAD_HOST
A Start-SPLIT token issued to

an isochronous end point with
start, middle, or end encoding
must have a payload.
This check fires if the data packet

following the OUT token does not have a
data payload.
USB_2_0_SSPLIT_NO_
PAYLOAD_DEVICE
822

Monitor Checks
Check ID
Violation
Description
USB_2_0_STALL_NAK_
HANDSHAKE_FOR_SETUP

with STALL or NAK
during control transfer.
Function receiving a SETUP must accept

the SETUP data and respond with ACK.
This check fires if the function returns a
transaction.
USB_2_0_STALL_
RECEIVE_ERR
status phase of control
access to that control endpoint
should result in reception of
stall handshake until the
completion of the next setup
phase.

continue to return stall in response to any
IN or OUT transaction until the next
SETUP transaction is completed. This
check fires if any other handshake packet
is returned by the devices after STALL is
returned. This check is active only when
USB_2_0_STOP_TT_
REQUEST_ERR
A STOP_TT hub class request

wlength of zero.
STOP_TT hub class request should have

wvalue and wlength set to zero. This check
fires if a nonzero value is detected.
USB_2_0_SYNC_FRAME_
REQUEST_ERR
A SYNCH_FRAME request
and wlength of two.
SYNCH FRAME request should have a

value of zero for wvalue and wlength of
two. This check fires if any of these
REQUEST_TO_HUB
SYNCH FRAME request

Hub response for a SYNCH FRAME

address.
USB_2_0_TKN_CRC_ERR
Five-bit CRC field is specified for tokens

to cover the address, end point numbers of
IN, OUT, SETUP and SPLIT tokens, and
the frame number of SOF token. This
check fires if an error is detected in the
CRC.
USB_2_0_TKN_PKT_SIZE_
ERR

24-bits.

receiving 3 bytes or 24-bits. This check
fires if end-of-packet is not received after
24-bits or end-of-packet is received before
24-bits. This check also covers PING
special token.
823

Monitor Checks
Check ID
Violation
Description
USB_2_0_TOKEN_
BEFORE_TIMEOUT
Host should wait for specified

number of bit times to indicate
a timeout.

should wait for the specified number of bit
addition, a host should wait for a specified
sending the next token. This check fires if
the above conditions are violated. For a
full-speed/low-speed bus, the specified
number of bit times is 18. For a high-speed
bus, the specified number of bit times is
816
USB_2_0_WMAX_PKT_
SIZE_ERR_HOST
A Host or Device should not

Host or device can transfer only the

maximum number of bytes is specified in
the end point configuration information.
data packet.
USB_2_0_WMAX_PKT_
SIZE_ERR_DEVICE
USB 2.0 ULPI Monitor Checks

Table 19-10 and Table 19-11 list the checks performed by the USB 2.0 ULPI monitor.
Table 19-10. USB 2.0 ULPI Monitor ULPI Checks
Check ID
Violation
Description
ON-THE-GO DEVICE CHECKS

USB_2_0_ULPI_
ACKNOWLEDGE_STP
Phy must ignore stp in the

same cycle that it first asserts
dir.
Whenever stp and dir are asserted

simultaneously, Phy continues the data
transmission ignoring the assertion of stp
and does not exhibit abort behavior. This
assertion fires if Phy de-asserts dir in the
cycle following assertion of stp and dir.
USB_2_0_ULPI_ASSERT_STP_
BEFORE_FIRST_BYTE_
CONSUMED
The Link must not assert stp

before the first byte has been
consumed by the Phy.
While Link is transmitting, Phy asserts nxt

to indicate the acceptance of current byte.
Link can assert stp only after the first byte
has been accepted by Phy. This assertion
fires if Link asserts stp before first byte has
been accepted by Phy.
USB_2_0_ULPI_CHIRP_J_
AFTER_DEVICE_CHIRP
Device chirp K should be

followed by chirp KJKJKJ
sequence.
Upstream chirp K is followed by

Downstream chirp KJ sequence. This
assertion fires if Upstream chirp K is
followed by chirp J.
824

Monitor Checks
Table 19-10. USB 2.0 ULPI Monitor ULPI Checks (cont.)

Check ID
Violation
Description
USB_2_0_ULPI_DATA_LINE_
PULSE_DURATION_
VIOLATION
During data-line pulsing

B-device should pull-up its
D+ for time range of
T(B_DATA_PLS).
Data-line pulsing duration must be in the

range of 5 ms to 10 ms. This assertion fires
if Data-line pulsing duration violates the
mentioned range.
USB_2_0_ULPI_DATA_NOT_
THROTTLED
Link should retain the

During data transmit (Link is
previous value on bus if nxt is transmitting), nxt indicates when current
low while Link is transmitting. byte is accepted by Phy. When Phy deasserts nxt, Link should hold the previous
byte onto the bus until nxt is asserted. This
assertion fires if Link does not hold the
previous byte onto the bus while nxt is
low.
USB_2_0_ULPI_DATA_
UNKNOWN_DRIVEN
Data is not driven to a valid

level.
Checks that data is both known and driven.
USB_2_0_ULPI_DATA_WIDTH_
ERR
Data bus width should be

either 4-bits or 8-bits.
Data bus can be either 4-bits or 8-bits

wide. This assertion fires if parameter
DATA_WIDTH is set to a value other than
these.
USB_2_0_ULPI_DEVICE_
CHIRP_K_TIMEOUT
Device enables HS transceiver

and asserts chirp k on bus
within 6 ms from HS Reset
T0.
The device chirp is asserted no later than

6.0 ms after HS Reset T0 (SE0 asserted for
first time). This assertion fires if device
chirp is asserted later than 6 ms after HS
Reset SE0.
CHIRP_MAX_VIOLATION
For HS Handshake device

should drive chirp K for no
more than 7 ms after HS
RESET T0.
The device chirp lasts no later than 7.0 ms

after HS Reset T0 (SE0 asserted for first
time). This assertion fires if device chirp is
asserted for more than 7 ms after HS Reset
SE0.
CHIRP_MIN_VIOLATION
For HS Handshake device

should drive chirp K for
minimum of 1 ms.
During HS detection handshake, device

drives upstream chirp K for minimum of 1
ms. This assertion fires if chirp K duration
is violated.
CHIRP_SUSPEND_TIMEOUT

After the first clock transition ChirpK must
timeout after entering reset
be asserted no later than 5.8 ms after assert
handshake from suspend state. of SuspendM. This assertion fires if chirp
K is asserted after 5.8 ms.
B-Device must detect SE0 for

DISCONNECT_SE0_VIOLATION minimum of T (B_SE0_SRP)
min, before initiating SRP.
RESUME_INTERVAL_ERR
For remote wake-up, device

should drive chirp K for
minimum of 1 ms to
maximum of 15 ms.
SE0 must be detected on the LineState for

at least 2 ms before starting Session
request protocol. This ensures that
A-Device has detected a disconnect
condition from the device. This assertion
fires if SRP is initiated before 2 ms.
The Remote wake-up Device hold the
resume signaling for minimum of 1 ms but
for no more than 15 ms. This assertion
fires when resume signaling timings are
violated.
825

Monitor Checks

Check ID
Violation
Description
USB_2_0_ULPI_DIR_
DEASSERTED_REG_READ_
DATA
dir should not be de-asserted

prior to reg read data.
For register read operation, in the cycle

after nxt asserts, Phy asserts dir to gain
control of the data bus and keep asserted
during register data cycle. This assertion
fires if Phy de-asserts dir before returning
register read data.
USB_2_0_ULPI_DIR_
UNKNOWN_DRIVEN
dir is not driven to a valid

level.
Checks that dir is both known and driven.
USB_2_0_ULPI_DP_
Illegal DpPulldown value.
DpPulldown signal must be 1b for host

controllers and 0 for peripheral mode. This
assertion fires if DpPulldown violates its
behavior.
USB_2_0_ULPI_FS_REVERT_
BACK_ERR
If device does not detect chirp

KJ sequence in no less than 1
ms and no more than 2.5 ms
after completing its own chirp,
it should revert back to FS.
Device revert to FS if it does not detect

sequence chirp KJ by a time no less than
1.0 ms and no more than 2.5 ms. This
assertion fires if devices does not revert to
FS but to some other speed.
BACK_TIMEOUT
If device does not detect chirp

KJ sequence in no more than
2.5 ms after completing its
chirp, it should revert back to
FS.
Device revert to FS if it does not detect

chirp KJ sequence by a time no less than
1.0 ms and no more than 2.5 ms. This
assertion fires if devices revert to FS
earlier than 1 ms or later than 2.5 ms.
TIMEOUT
In HS, if bus is idle for no less

than 3.0 ms and no more than
3.125 ms, then only it should
revert to FS by register write
operation.
If the Device in High-Speed mode detects

bus inactivity for more than 3 milliseconds
to 3.125 milliseconds, then the Link places
itself into Full-Speed mode. (XcvrSelect =
01, TermSelect = 1). This assertion fires if
Link places itself into Full-Speed mode
before 3 ms or after 3.125 ms.
USB_2_0_ULPI_HOST_CHIRP_
J_DURATION_ERR
Host chirp J should last for no

less than 40 us and no more
than 60 us.
During HS detection handshake, host

drives downstream chirp J for minimum of
40 us and for maximum of 60 us. This
assertion fires if chirp J duration is
violated.
K_DURATION_ERR
Host chirp K should last for no During HS detection handshake, host

less than 40 us and no more
drives downstream chirp K for minimum
than 60 us.
of 40 us and for maximum of 60 us. This
assertion fires if chirp K duration is
violated.
KJ_COUNT_ERR
Host should send minimum of

3 KJ chirp sequence.
During HS detection handshake, host

drives minimum of 3 chirp KJ sequence
before returning to normal operating
mode. This assertion fires if transition to
normal mode occurs before minimum KJ
sequence.
USB_2_0_ULPI_HOST_
DISCONNECT_IN_NON_
SYNCHRONOUS_MODE
Host Disconnect interrupt is

only valid in Synchronous
mode.
Host disconnected is asserted only in

synchronous mode. This assertion fires
when host disconnect is asserted in
non-synchronous mode.
826

Monitor Checks

Check ID
Violation
Description
USB_2_0_ULPI_HOST_
DISCONNECT_READ_ERR
Host Disconnect is only valid

in host mode. Both
dp_pulldown = 0 and
dm_pulldown = 0
Host Disconnect is asserted only in host

mode (dp_pulldown = 0 and dm_pulldown
= 0). This assertion fires if reg read data
has Host Disconnect bit asserted when not
in host mode.
USB_2_0_ULPI_HOST_
DISCONNECT_WRITE_ERR
Host Disconnect is only valid

in host mode. Both
dp_pulldown = 0 and
dm_pulldown = 0.
Host Disconnect is asserted only in host

mode (dp_pulldown = 0 and dm_pulldown
= 0). This assertion fires if reg write data
has Host Disconnect bit asserted when not
in host mode.
USB_2_0_ULPI_HOST_
DISCONNECT_XCVR_SELECT_
ERROR
XcvrSelect not switched to FS

mode when HostDisconnect is
asserted in HS mode.
If in HS mode a HostDisconnect is set to

1b, then at that moment the XcvrSelect is
in FS mode (XcvrSelect = 01b). It fires if
XcvrSelect is in HS and HostDisconnect is
set to 1b.
USB_2_0_ULPI_HOST_
RECEIVED_SOF_WITHOUT_
HNP
SOF cannot be received from

the device before Host
SOF cannot be received from the device

before Host negotiation protocol. This
assertion fires if SOF is received from
device before HNP.
USB_2_0_ULPI_HOST_
RESUME_MIN_ERR
Host should transmit FS K for

at least 20 ms if it wants to
wake-up the peripheral.
Host drives resume K for minimum of 20

ms. This assertion fires if resume K
duration is less than 20 ms.
USB_2_0_ULPI_HS_REVERT_
ERR
If device detects chirp

KJKJKJ, then no more than
500 us after detection, the
device is required to enter HS
default state.
Device enters the HS default state within

500 us after detecting Downstream chirp
KJ sequence. This assertion fires if HS
default state is entered after 500 us.
USB_2_0_ULPI_HUB_CHIRP_
TIMEOUT
HUB must send an alternating

chirp KJ sequence in no more
than 100 us after bus leaves
the chirp K.
After release of chirpK, downstream port

starts assertion of chirp KJ sequence on the
bus no later than 100 us. This assertion
fires downstream chirp KJ is delayed more
than 100 us.
USB_2_0_ULPI_INVALID_
LINE_STATE
Invalid LineState according to

the speed.
LineState must not be 11b in all modes and

10b in high-speed mode. This assertion
fires if LineState is invalid.
USB_2_0_ULPI_INVALID_
LINESTATE_BETWEEN_HOST_
CHIRP
Invalid LineState between

chirp KJKJKJ sequence.
Downstream chirp KJ comes as a predefined sequence. This assertion fires if

this sequence is violated.
USB_2_0_ULPI_INVALID_STP_
ASSERT_FOR_REG_
OPERATION
Invalid stp asserted during

register operation.
Reg operations are initiated by the Link.

Link asserts stp in reg write operation only
after reg data cycle. This assertion fires if
stp is asserted anywhere else in between
operation.
827

Monitor Checks

Check ID
Violation
Description
USB_2_0_ULPI_LINK_
TRANSMIT_ANOTHER_FIRST_
INCOMPLETE
After asserting stp, Link

cannot transmit another packet
until the first packet has
completed on USB bus.
Link terminates data transmission by

asserting stp. Phy send RX CMDs
indicating EOP for each transmitted
packet. Link cannot transmit another
packet until RX CMD indicating EOP for
previous packet is seen. This assertion
fires if link transmits another packet before
EOP of previous packet.
USB_2_0_ULPI_LOW_POWER_
MODE_DIR_ASSERT_ERR
In cycle following Reg write

for SuspendM, dir should be
asserted.
Phy asserts dir immediately after reg write

operation for asserting SuspendM. This
assertion fires if dir is not immediately
asserted.
MODE_DIR_ASSERT_
EXPECTED_ERR
If stp is not asserted during the

cycle dir is de-asserted, then
the Phy must re-assert dir and
return to low power mode.
Phy qualifies the stp assertion for exiting

LPM by checking that stp is active on the
clock edge that the Phy de-asserts dir. If
stp is not asserted during the cycle dir is
de-asserted, Phy re-asserts dir. It fires if
Phy does not re-asserts dir.
MODE_DIR_DE_ASSERTED
Dir should be kept

continuously high throughout
Low power mode.
Phy de-asserts dir only upon valid exit

from LPM. It fires if dir is de-asserted in
between LPM and stp is not asserted for
exiting LPM.
MODE_EXIT_COUNT_ERR
Before exiting low power

mode, minimum of 5 clock
edges should be registered.
In LPM, Phy ensures that minimum of 5

cycles of clock have been driven prior to
de-asserting dir. It fires if dir is de-asserted
prior to 5 clock cycles.
MODE_INVALID_DATA2
Data[2] is reserved and it

should always be driven 0 in
low power mode.
In low power mode, data[2] is reserved

and always driven low. This assertion fires
if this bit is asserted.
MODE_NXT_ASSERTED
nxt should be low throughout

low power mode.
In low power mode, Phy drives nxt to low.

This assertion fires if nxt is asserted during
low power mode.
MODE_STP_ERR
While exiting low power

mode, Link should de-asserts
stp in the cycle following the
de-assertion of dir.
While exiting LPM, stp is de-asserted one

cycle later than de-assertion of stp. It fires
if stp is not asserted even one cycle after
the de-assertion of dir.
USB_2_0_ULPI_NON_ZERO_
ON_BUSS_DURING_IDLE
When the bus is idle, 00h

should be on the data line.
When data bus is Idle, data lines are

having 0 value. This assertion fires if other
than 0 is present on data bus while no
packet is in progress.
USB_2_0_ULPI_NUMBER_OF_
ENDPOINTS_ERROR

points supported is 31 for
full/high-speed devices and 3
for low-speed devices.
A Maximum of 16 OUT and 16 IN end

points are allowed for full-speed/highspeed devices with address 0 necessarily
being both OUT and IN. For low-speed
devices, a maximum of 3 end points are
allowed. It fires if parameter
NUMBER_OF_ENDPOINTS violates the
above criteria.
828

Monitor Checks

Check ID
Violation
Description
USB_2_0_ULPI_NXT_ASSERT_
DURING_READ_DATA
Register read data should

come with nxt low.
Phy does not assert nxt when dir is

asserted during the reg read operation,
even during the cycle that register read
data is returned. This assertion fires if nxt
is asserted in the cycle when register read
data is transmitted.
DURING_RXERROR
If RxError is received during

receive, then nxt should not be
asserted in the following
cycles until dir goes low.
During Receive after RxError is asserted,

Phy does not assert nxt until RxActive is
de-asserted. This assertion fires if nxt is
asserted during RxError and RxActive is
still high.
OUTSIDE_BYTE_BOUNDARY
Nxt is asserted outside byte

boundary
Depending on the number of bits stuffed in

a byte, nxt is asserted either after 39
cycles, or after 44 cycles, or after 49
cycles. It fires if nxt is asserted after 50
cycles.
USB_2_0_ULPI_NXT_
ASSERTED_DURING_IDLE
During idle transmission, nxt

should not be asserted.
The Phy asserts nxt to throttle data types

except reg read and RX CMD. This checks
that nxt signal should not be asserted
during idle. This fires whenever nxt is
asserted while data and dir continue
exhibiting idle behavior.
USB_2_0_ULPI_NXT_
ASSERTED_MORE_THAN_
ONCE_IN_ONE_BYTE
Nxt should not be asserted

more than once in a byte
boundary.
Nxt should be used to throttle data only

once per byte and should not be asserted
more than once per byte. This assertion
fires if nxt is high without a byte boundary.
USB_2_0_ULPI_NXT_BEFORE_
RXACTIVE
If during receive dir was

previously high, then there
should be an RX CMD
indicating RxEvent before
next packet is received.
If dir is high when RxActive is low, then

Phy sends a RX CMD indicating assertion
of RxActive before asserting nxt indicating
packet receive. This assertion fires if nxt is
asserted before sending RX CMD
indicating RxActive asserted.
USB_2_0_ULPI_NXT_
DEASSERT_EXTENDED_
ADDRESS
Nxt should not be de-asserted

during the extended address
byte.
Phy keeps nxt asserted during extended

address byte. It fires if Phy de-asserts nxt
during extended address byte.
USB_2_0_ULPI_NXT_
DEASSERT_REG_WRITE
nxt should be kept asserted for

the duration of reg write
operation.
There is no bit stuffing in reg write

operations and hence nxt should not go
low. It fires when nxt goes low before stp
is asserted at the end of reg write
operation.
For chirp and resume

USB_2_0_ULPI_NXT_
DEASSERTED_DURING_NOPID signaling, nxt must hold high
until stp is asserted.
During data transmit (NOPID), nxt is keep

asserted until stp is seen high. This
assertion fires if nxt is de-asserted in
between transmission before stp is seen
high.
829

Monitor Checks

Check ID
Violation
Description
USB_2_0_ULPI_NXT_
DEASSERTED_FOR_MORE_
THAN_ONE_CYCLE
During normal operation, nxt

should not be negated for two
consecutive cycles.
During normal transmit or receive

operation, nxt is negated either for bitstuffing or RxError. In HS, if RxError is
not asserted, then nxt is not negated for
consecutive cycles. The assertion fires if
nxt is negated for more than one
consecutive cycles. This check is valid
when operating in HS.
USB_2_0_ULPI_NXT_DIR_
DEASSERT_AFTER_STP_
ASSERT
If link aborts Phy by asserting

stp, Phy must de-assert dir and
nxt in the following cycle.
Whenever Link aborts Phy by asserting

stp, Phy de-asserts dir and nxt in the next
cycle. This assertion fires if Phy does not
de-assert either dir or nxt upon assertion of
stp.
USB_2_0_ULPI_NXT_SHOULD_
DEASSERT_AFTER_FIRST_
NOPID
If TX CMD NOPID is
transmitted, then after
indicating nxt high for TX
CMD, nxt should go low for
next byte and then should go
high.
During NOPID transmit, nxt is low on first

byte during TX CMD and again goes low
on first byte of data, then goes high for the
rest of the transaction. This assertion fires
if nxt behavior deviates from this.
USB_2_0_ULPI_NXT_SHOULD_
FOLLOW_DIR
If dir is going low, either nxt

should be low or should be
going low simultaneously.
Phy ends data transmission by de-asserting

dir and nxt (if asserted). This assertion
fires if nxt is high in the cycle, dir is deasserted.
USB_2_0_ULPI_NXT_TXCMD_
MIS_BEHAVIOUR
Between appearance of TX
CMD on data line and
assertion of nxt there should
be exactly one cycle delay.
When Link starts transmitting data by

sending TX CMD, there is exactly one
cycle delay between assertion of nxt and
transmission of TX CMD. This check is
valid when operating in HS. This assertion
fires if the gap between assertion of nxt
and TX CMD byte is not of exactly one
clock cycle.
USB_2_0_ULPI_NXT_
UNKNOWN_DRIVEN
nxt is not driven to a valid

level.
Checks that nxt is both known and driven.
USB_2_0_ULPI_PHY_ABORT_
LINK_PREVIOUSLY_ABORT
If Phy is aborted by Link, then

the subsequent Link
transaction cannot be aborted
by Phy.
If Link aborts Phy by asserting stp, then

Phy must de-assert dir in the next cycle
and keep dir de-asserted until the Link
transaction has completed. This assertion
fires if Phy assert dir in the on going Link
transaction.
USB_2_0_ULPI_PHY_INVALID_ If Link aborts Phy, Phy cannot

re-asserts dir in the cycle
TRANSACTION
following the turn-around
cycle when dir de-asserts.
Phy cannot start a transaction after being

aborted by Link before making sure that
Link has not started a transaction
immediately. It fires if dir goes high in the
immediate next cycle after stp is asserted
for abort.
USB_2_0_ULPI_PHY_
TRANSMIT_BEFORE_
SENDING_EOP
830
Phy must always send a RX

CMD indicating EOP after
transmit.
For all PID packets, Phy sends RxCmd

indicating EOP. Phy starts sending the data
only if it has sent RX CMD indicating
EOP for the previous packet transmitted by
Link. This assertion fires if Phy starts its
own transmission before sending EOP of
the previous PID packet.

Monitor Checks

Check ID
Violation
Description
USB_2_0_ULPI_PREAMBLE_
ERR
In preamble mode, Phy must

ensure a minimum gap of 4 FS
bit times between last bit of
FS PRE PID and first bit of
low speed sync packet.
In preamble mode, Phy ensures a

minimum gap of 4 full-speed bit times
between the last bit of FS PRE PID and
first byte of LS SYNC. This assertion fires
if minimum gap is not maintained.
USB_2_0_ULPI_RECEIVE_TO_
RECEIVE_DELAY
Interpacket gap between two

consecutive received packet
should not be less than 1
cycle.
Minimum Packet gap between a receive

followed by a receive is 1 when operating
in HS, 1 when operating in FS, 1 when
operating in LS. This assertion fires if
interpacket gap is less than these values.
TRANSMIT_MAX
Interpacket gap between a

receive followed by a transmit
packet should not be more
than desired cycles.
Maximum Packet gap between a receive

followed by a transmit is 14 when
operating in HS, 18 when operating in FS,
247 when operating in LS. This assertion
fires if interpacket gap exceeds these
values.
TRANSMIT_MIN

receive followed by a transmit
packet should not be less than
desired cycles.
Minimum Packet gap between a receive

followed by a transmit is 1 when operating
in HS, 7 when operating in FS, 77 when
operating in LS. This assertion fires if
interpacket gap is less than these values.
USB_2_0_ULPI_REG_NOT_
WRITE_PERMISSION
Register for the given address

is not available for writing.
There are certain registers which are only

available for reading. This assertion fires if
trying to do write operation on these
registers.
USB_2_0_ULPI_REG_READ_
DIR_NOT_ASSERT_AFTER_
ADDRESS
In register read, in the cycle

after register address, dir
should be asserted.
In register read operation, after register

address (or extended address) cycle, Phy
asserts dir. It fires if Phy does not asserts
dir.
ILLEGAL_DIR
dir should not be asserted

during TX CMD byte or
extended reg address byte,
unless it is being aborted due
to RxActive.
In register read operation, Phy asserts dir

after address or extended address (if
extended register operation) byte. This
assertion fires if dir is asserted in address
or extended address byte and nxt is driven
low.
RX_ACTIVE
After reg read, either dir

should de-assert or RxActive
should go high.
After register read data cycle, Phy either

de-asserts dir or sends an RX CMD
indicating RxActive. This assertion fires if
Phy does not de-asserts dir after register
read data cycle and did not assert RxActive
bit in RX CMD sent.
USB_2_0_ULPI_REG_
RESERVED_BITS_READ_ERR
Reserved bits of the register

are not 0.
Reserved bits of register always have 0

value. It fires if reg read data has reserved
bits asserted.
USB_2_0_ULPI_REG_
RESERVED_BITS_WRITE_ ERR
Reserved bits of the register

are not 0.
Reserved bits in registers are always

assigned with 0 value. This assertion fires
if these bits are asserted via reg write
operation.
831

Monitor Checks

Check ID
Violation
Description
USB_2_0_ULPI_REG_WRITE_
DIR_ASSERTED
Dir should not be asserted

during reg write, unless it is
being aborted due to
RxActive.
During reg write, dir goes high only when

a receive aborts the operation. It fires if nxt
is not high when dir goes high.
END_WITH_STP
If register write is not aborted,

Link should assert stp in the
cycle following reg data.
Link asserts stp in the cycle following reg

write data, if reg operation is not aborted.
This assertion fires if stp is not asserted.
NXT_MISBEHAVE
In register write operation, nxt

should not be kept asserted
during stp cycle.
During reg write operation, Phy de-asserts

nxt after reg write data. This assertion fires
if nxt is keep asserted during stp cycle of
reg write operation.
USB_2_0_ULPI_REMOTE_
WAKE_UP_ERR
A device with remote wake-up

capability may not generate
resume signaling unless bus
has been idle for 5 ms.
Device with remote wake-up capability

waits for at least 5 milliseconds after the
bus is in the Idle state, before sending
remote wake-up resume signaling. This
assertions checks for early remote wake up
signaling.
USB_2_0_ULPI_REMOTE_
WAKE_UP_TIMEOUT
Device should assert FS K on

the bus to signal resume
request within 10 ms from
de-assertion of SuspendM.
Device asserts FS 'K' on the bus no later

than 10 ms after SuspendM is asserted.
This assertion fires if remote wake-up
upstream chirp K is delayed more than
10 ms.
USB_2_0_ULPI_RESERVED_
REG_ADDRESS
Reserved register address.
Reserved registers are not available for

reading and writing. This assertion fires
whenever trying to access these registers.
USB_2_0_ULPI_RESERVED_
TX_CMD
This TX CMD is reserved.
Certain values of TX CMD are reserved.

This assertion fires if reserved TX CMD is
sent.
USB_2_0_ULPI_RESET_
INTERVAL_ERR
Minimum Reset interval must

be 10 ms.
Minimum Reset interval is 10 ms. This

assertion fires if reset is over before 10 ms.
USB_2_0_ULPI_RESET_SE0_
ERR
If host does not detect device

chirp, it must continue the
assertion of SE0 until the end
of reset.
Host continue the assertion of SE0 on line

state until the end of reset if device chirp K
is not detected. This assertion fires if other
than K or SE0 is detected on linestate.
USB_2_0_ULPI_RESUME_
NORMAL_OPERTAION_
VIOLATION
Within 1.25 us after the

transition to the SE0 state
while resume, device must
enable normal operation.
The device resume normal operation after

1.25 us. This assertion fires if normal
operation is not resumed within 1.25 us.
USB_2_0_ULPI_SE0_AFTER_
RESUME_K_VIOLATION
Downstream port should

assert SE0 within 20 ms from
assertion of resume signal
from the device.
SE0 is seen on LineState 20 ms after the

resume K assertion. This assertion fires if
SE0 is seen after 20 ms.
USB_2_0_ULPI_SESS_VALID_
ASSERT_ERROR
SessValid signal must be

asserted when VbusValid is
asserted.
Whenever VbusValid is high, currently

ongoing session is valid, and SessValid is
high. This assertion fires if SessValid
de-asserts while VbusValid is still
asserted.
832

Monitor Checks

Check ID
Violation
Description
USB_2_0_ULPI_SESS_VALID_
SESS_END_MISMATCH
SessValid and SessEnd must

not be asserted
simultaneously.
SessEnd symbolizes end of current

session. SessValid symbolizes current
session is in progress. These are mutually
exclusive. This assertion fires when these
are asserted simultaneously.
USB_2_0_ULPI_SESSION_END_
LINE_STATE_VIOLATION
When session ends, LineState

should be SE0.
LineState must be 00b when a valid

session is not in progress or session request
protocol is not under progress. This
assertion fires if LineState is other than
SE0 when session ends.
USB_2_0_ULPI_SESSION_
INVALID_NORMAL_
OPERATION_GOING
Session should be in progress,

while some transaction is
happening.
A session must be in progress for doing

normal transactions in On-The-Go capable
devices. This assertion fires if session is
not in progress while normal operation is
ongoing.
USB_2_0_ULPI_SRP_SPEED_
MISMATCH
An OTG device can initiate

SRP only in FS.
A On-The-Go B-Device is allowed to

initiate SRP only at full-speed. This
assertion fires if SRP is initiated at a speed
other than FS.
USB_2_0_ULPI_STP_ASSERT_
NXT_NOT_DEASSERT
If transmit is not immediately

followed by receive, then nxt
should de-asserted along with
stp.
When Link ends its transaction, by

asserting stp, Phy de-asserts nxt in the next
cycle, given receive is not immediately
followed by transmit. This assertion fires
when Phy does not de-asserts nxt.
USB_2_0_ULPI_STP_
ASSERTED_MORE_THAN_
ONCE
stp should not asserted for two

consecutive cycles by Link
under synchronous mode.
stp is asserted by Link to end its data

transmission or to abort the packet Phy is
transmitting. Link asserts stp only for one
cycle in synchronous mode. It fires if stp is
asserted for more than one consecutive
cycles in synchronous mode.
USB_2_0_ULPI_STP_
UNKNOWN_DRIVEN
Stp is not driven to a valid

level.
Checks that stp is both known and driven.
USB_2_0_ULPI_SUSPEND_
ASSERT_MAX_ERR
The latest time that a device

must actually be suspended,
drawing no more than the
suspend current from bus is
10 ms.
Device is suspended drawing no more than

suspended current within 10 ms after the
bus is idle. This assertion fires if device is
suspended later than 10 ms.
USB_2_0_ULPI_SUSPEND_
SPEED_MISMATCH
Device should resume with

same speed as it was in before
going to suspend state.
The device returns to the same speed after

resume as it was before entering suspend
mode. This assertion fires if there is a
speed mismatch.
USB_2_0_ULPI_SUSPENDM_
TERM_SELECT_FS
While SuspendM is active,

TermSelect is not in FullSpeed mode.
Whenever SuspendM (active low signal) is

driven low, TermSelect is in FS
Termination irrespective of the operating
speed. This assertion fires if TermSelect is
not equal to 1 when SuspendM is asserted.
833

Monitor Checks

Check ID
Violation
Description
USB_2_0_ULPI_TRANSMIT_
TO_RECEIVE_DELAY

transmit followed by a receive
Maximum Packet gap between a transmit

values.
TO_TRANSMIT_MAX

consecutive transmitted
Maximum Packet gap between a transmit

values.
TO_TRANSMIT_MIN

consecutive transmitted
packet should not be less than
desired cycles.
Minimum Packet gap between a transmit

fires if interpacket gap is less than these
values.
USB_2_0_ULPI_VALID_FS_LS_
EOP
RX CMD representing EOP

for FS/LS should be at least 1
bit time for SE0 and one bit
for J.
EOP for FS/LS mode of operation is at

least 1 bit time SE0 followed by 1 bit time
J on LineState. This assertion fires
whenever LineState SE0 is not followed
by LineState J.
USB_2_0_ULPI_VBUS_
PULSING_ORDER_MISMATCH
Vbus pulsing can only be

initiated if initial conditions
and data-line pulsing is done.
Vbus pulsing must always follow data-line

pulsing. This assertion fires if Vbus
pulsing is initiated before data-line
pulsing.
USB_2_0_ULPI_WRONG_
DATA_ON_BUSS_DURING_
STP_FS_LS
Data on bus during stp cycle

should be either 00h/FFh for
FS/LS given
OpMode != 2'b11.
For FS/LS mode of operation, data can be

either 00 or FF (txerror) during stp cycle.
This assertion fires if data is other than this
during stp cycle.
USB_2_0_ULPI_WRONG_
STP_HS

should be 00h for HS given
OpMode != 2'b11.
For HS mode of operation, data is 00

during stp cycle. This assertion fires if data
is other than this during stp cycle.
USB_2_0_ULPI_WRONG_
STP_REG_OPERATION

For reg write operation, data is 00 during
for reg write operations should stp cycle. This assertion fires if data is
be 00.
other than this during stp cycle.
834

Monitor Checks
Table 19-11. USB 2.0 ULPI Monitor USB 2.0 Checks

Check ID
Violation
Description
A device can issue an ACK

handshake only during the
non-IN transaction.

Device can issue an ACK handshake
during an OUT, SETUP, or PING
transaction after receiving the data packet.
This check fires if the ACK handshake is
issued by the device during an IN
transaction. In an IN transfer, the device
can issue an ACK for SPLIT transactions.
HOST_DURING_NON_IN_
XFR
A host can issue an ACK

handshake only during the IN
transaction.

data. This check fires if an ACK handshake
packet is issued by the host during the nonIN transactions.
USB_2_0_ACK_
RECEIVED_FOR_IN_TKN

token.
When a host issues the IN token, function

should respond with either STALL, NAK,
or return DATA packet. This check fires if
an ACK handshake is returned for the IN
token.
USB_2_0_BULK_ISO_
ON_LOW_SPD_BUS
Bulk transfers and

devices.
Bulk and isochronous transfer types are not

supported by low-speed devices. This
check fires if a bulk transfer or an
isochronous transfer is initiated on a lowspeed bus.
USB_2_0_BULK_XFR_
DATA_PID_ERR_HOST

of a bulk transfer.

of a bulk transfer. This check fires if a
data packet of a bulk transfer. This check


HUB_REQUEST_ERR
A CLEAR_FEATURE hub
windex of zero and wlength of
zero.
CLEAR FEATURE (clear hub feature) hub

class request should have values of zero for
REQUEST_DEVICE_ERR
A CLEAR FEATURE request

have zero value wlength and
windex.
CLEAR FEATURE request with device as

should have zero values for windex and
USB_2_0_BULK_XFR_
DATA_PID_ERR_DEVICE
USB_2_0_BULK_XFR_
SEQ_BIT_ERR_HOST
USB_2_0_BULK_XFR_
SEQ_BIT_ERR_DEVICE
835

Monitor Checks
Table 19-11. USB 2.0 ULPI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
REQUEST_ERR
A CLEAR_FEATURE
zero for wlength.
CLEAR FEATURE request should have

the wlength field of a CLEAR FEATURE
USB_2_0_CLEAR_PORT_
FEATURE_REQUEST_ERR
port feature) hub class request
CLEAR FEATURE (clear port feature)

zero for wlength. This check fires if
OTG_ERR

CLEAR_FEATURE
command.

command.
USB_2_0_CLEARTT_
REQUEST_ERR
A CLEAR_TT_BUFFER hub
wlength of zero.
CLEAR_TT_BUFFER hub class request

should have wlength of zero. This check
USB_2_0_CSPLIT_TKN_U_
BIT_ERROR
Illegal u bit in the CompleteSPLIT token.

reserved and must be set to zero.
USB_2_0_CSPLIT_TO_
ISO_END_POINT
Complete-SPLIT token should No handshaking is involved in isochronous

not be issued for an
data transfers. Therefore, complete-SPLIT
USB_2_0_CTRL_XFR_
DATA_PHASE_DIR_ERR

with the direction specified in
the setup data.

is active only if the address received in the
token matches the address input.
USB_2_0_CTRL_XFR_
DATA_PHASE_LENGTH_
ERR_HOST
A Host or Device should


the number of bytes to be transferred by the
host and the maximum number of bytes
that can be transferred by the device during
the data phase of a control transfer. This
check fires if the host transfers more or
fewer bytes than the specified number of
bytes. It also fires if the device transfers
more than the specified number of bytes
This check is active only if the address
received in the token matches the address
input.

transfer.

USB_2_0_CTRL_XFR_
DATA_PHASE_LENGTH_
ERR_DEVICE
USB_2_0_CTRL_XFR_
SEQ_BIT_ERR_HOST
USB_2_0_CTRL_XFR_
SEQ_BIT_ERR_DEVICE
836

Monitor Checks
Check ID
Violation
Description
FOR_NON_ISO_HOST
Packet ID MDATA and

points only.
Packet IDs (PIDs) DATA2 and MDATA

are used for high-speed split, high
bandwidth isochronous end points. These
PIDs should not be used for nonsplit, bulk,
control, interrupt transfer end points. This
check fires if DATA2, MDATA packet IDs
are detected.

of data packets.

send the DATA0 packet ID during the
controller should be able to accept either
DATA0 or DATA1 packet IDs. This check
fires if a DATA1 packet is sent at the
source side. This check is active only when
matches the address input. This check is
active only for a full-speed bus.
USB_2_0_DEVICE_
INITIATED_XFR_WHEN_
HOST_NOT_WAITING

is not waiting.
Devices should always respond to packets

issued by the host. For example, when the
host issues an IN token, devices should
data packet or handshake packet from the
devices, only the host is allowed to initiate
a packet transfer. This check fires if the
device initiates a packet transfer when
there is no packet due.
TKN

token packets.

check fires if a token packet is issued by
the device. This check is not applicable if
the device is USB on-the-go compliant.
USB_2_0_EXT_TKN_CRC_
ERR

error.

extended token to cover the bmAttributes
of EXT tokens. This check fires if an error
is detected in the CRC.
ILLEGAL_bLinkState


reserved.
ILLEGAL_SUBPID


value is LPM token.
FOR_NON_ISO_DEVICE
HOST
DEVICE
ISO_XFR_HOST
ISO_XFR_DEVICE
837

Monitor Checks
Check ID
Violation
Description
SIZE_ERR


ERROR
Frame numbers received in two

consecutive frames should be in the
increasing order, and they should have a
difference of 1. However, frame numbers
detected in the SOF packets in a
microframe should remain the same. This
check fires if the frame numbers received
in two successive frames do not follow
these criteria.
USB_2_0_FUNCTION_

error.

received with an error. Devices should wait
for timeout. This check fires if the device
starts responding to a packet received with
an error.
USB_2_0_GET_
CONFIGURATION_
REQUEST_ERR
A GET_CONFIGURATION
zero for wvalue and windex,
wlength.
GET CONFIGURATION request should

have zero values for wvalue and windex,
and a value of one for wlength. This check
satisfied.
USB_2_0_GET_HUB_
STATUS_REQUEST_ERR

of four.
GET STATS (get hub status) hub class

wvalue and windex, and a value of four for
REQUEST_ERR
A GET_INTERFACE request
and wlength of one.
GET INTERFACE request should have

zero value for wvalue, and a value of one
for wlength. This check fires if any of these
REQUEST_TO_HUB
Hub response for a GET INTERFACE

address.
USB_2_0_GET_PORT_
STATUS_REQUEST_ERR

GET STATUS (get port status) hub class

wvalue and a value of four for wlength.
is not satisfied.
838

Monitor Checks
Check ID
Violation
Description
USB_2_0_GET_STATUS_
REQUEST_DEVICE_ERR
of two.
GET STATUS request with device as

should have values of zero for wvalue and
is not satisfied.
USB_2_0_GET_STATUS_
REQUEST_NON_DEVICE_
ERR
and wlength of two.
GET STATUS request with nondevice as

wvalue, and a value of two for wlength.
is not satisfied.
USB_2_0_HANDSHAKE_
PKT_IN_ISO_XFR
Handshake packets should not

be generated for isochronous
transfers.

handshake packets. This check fires if a
address input.
USB_2_0_HANDSHAKE_
PKT_SIZE_ERR_HOST

have only 8-bits.

USB_2_0_HIGH_SPEED_
ENDPOINT ISSUED_ERR

packet.
ERR is a high-speed only handshake that is

returned to allow a high-speed hub to
report an error on a full-speed/low-speed
bus. It is only returned by a hub as a part of
a SPLIT transaction. This check fires if a
device other than hub returned an ERR
handshake. This check is enabled only
when the
parameter is 1.
ILLEGAL_HANDSHAKE

NYET, ERR handshake
packet.

NAK, NYET, or ERR under any condition.
This check fires if any of these handshakes
is returned by the host.
TKN_BEFORE_XFR_
COMPLETE
A Host should not issue a

Host should not initiate a transaction before
token before the completion of the current transaction is complete. This
the current transaction.
check fires if the host initiates a transaction
by the issue of a token before the
completion of the current transaction. This
address input.
FOR_ERR_PKT

Host should not respond for packets
packets received with an error. received with an error. The host should
wait for 18-bit times so that devices
timeout. This check fires if the host starts
responding to a packet received with an
error.
USB_2_0_HANDSHAKE_
PKT_SIZE_ERR_DEVICE
839

Monitor Checks
Check ID
Violation
Description
USB_2_0_HUB_CLASS_
REQUEST_TO_DEVICE

functions.

request is issued to a device when the
active only if the PORT_TYPE parameter
is 3.
specified for bulk transfer end
points.

supported by bulk transfer end points is 8,
16, 32, and 64 bytes for full-speed devices,
end points.

supported for control transfers is 8, 16, 32,
and 64 bytes for full-speed devices, 8 bytes
for low-speed devices, and 64 bytes for
high-speed devices. This check fires if any
other value is specified.
USB_2_0_ILLEGAL_
HANDSHAKE_LPM_REQ

response for LPM transaction. transition request through extended token
from host.
USB_2_0_ILLEGAL_
INTERRUPT_XFR_WMAX_
PACKET_SIZE
specified for interrupt transfer
end points.

supported by interrupt transfer end points is
64 bytes or less for full-speed devices,
1024 bytes or less for high-speed devices,
and 8 bytes or less for low-speed devices.
specified.
USB_2_0_ILLEGAL_
ISOCHRONOUS_XFR_
WMAX_PACKET_SIZE

supported by isochronous transfer end
and 1024 bytes for high-speed devices.
specified.
USB_2_0_ILLEGAL_TOKEN_
ON_FULL_SPD_LINK

DATA2, PING, ERR, and
NYET are not allowed on a
full-speed/low-speed link.

MDATA, PING, and ERR should not be
detected on a full-speed/low-speed link.
This check fires if any of these PIDs are
detected.
RECEIVED_OUT_TKN

Host should not initiate an OUT transaction

to an IN only end point. This check fires if
the host issues an OUT token to an IN only
enabled only if the
parameter is 1.
840

Monitor Checks
Check ID
Violation
Description
USB_2_0_INT_XFR_
DATA_PID_ERR_HOST


of an interrupt transfer. This check fires if a
data packet of an interrupt transfer. This
configured.

transfer.

WITHOUT_EXT_TKN

EXT token must be transmitted before

LPM token (Extended token packet).
Similarly DATA0 packet should always
follow token packet.
USB_2_0_NO_ACK_
HANDSHAKE_FOR_SETUP
Function should acknowledge

with ACK handshake when
setup data is received without
an error.
If SETUP data is received without an error,

then the function should respond with an
ACK handshake. This check fires if a
function does not respond with ACK for
SETUP data received without an error.
PORT_TYPE parameter is 1 or 3.
HOST

transfer should always contain
DATA1 packet id.
STATUS phase of a control transfer should

always contain the DATA1 packet ID in
the data packet. This check fires if the
DATA1 packet ID is not present in the
status phase of a control transfer. This
address input.
FOR_PKT_RECEIVED_
WITHOUT_ERR

If a device receives a data packet or a token

packet without any error, then it must
respond with a proper handshake. This
check fires if the device does not respond.
USB_2_0_NO_STATUS_
PHASE_AFTER_SETUP_
PHASE
Status phase should follow the

setup phase when wlength
field of setup data contains a
value of zero.

whether or not the control transfer has a
data phase. This check fires if the value of
wlength is zero and a data transfer is
initiated during a control transfer. This
input.
ENDPOINT_ZERO


point zero.
PID_ERR_DEVICE
USB_2_0_INT_XFR_
SEQ_BIT_ERR_HOST
USB_2_0_INT_XFR_
SEQ_BIT_ERR_DEVICE
DEVICE
841

Monitor Checks
Check ID
Violation
Description
RECEIVED_IN_TKN
Host should not issue IN token Host should not initiate an IN transaction
to OUT only end point.
to an OUT only end point. This check fires
if the host issues IN token to an OUT only
USB_2_0_PING_
HANDSHAKE_ERROR

ACK or STALL handshake.
NAK, ACK, STALL are the only

handshake packets returned in response to
a PING token. This check fires if any other
USB_2_0_PING_NEXT_
TRANSACTION_ERROR

Host should initiate an OUT transfer as the

next transfer to a control/bulk OUT end
point, if the end point returned an ACK
transfer to the end point, if the end point is
transfer.
USB_2_0_PING_NOT_
INITIATED

point.

USB_2_0_PKT_ID_CHK_
FIELD_ERR_HOST

packet ID field.

ID check field is ones complement of the
packet ID field. This check fires if the
complement of the packet ID field.


When a PRE packet is received, hubs
enable the low-speed downstream ports.
This check fires if PRE packets are issued
on a low-speed/high-speed interface.
USB_2_0_REQUEST_
NOT_DEFINED
The brequest field of SETUP data should

be a defined value. This check fires if
brequest specified in the SETUP data is
STANDARD requests, (i.e., the type field
USB_2_0_REQUEST_
Recipient field of

parameter is 1.
USB_2_0_PKT_ID_CHK_
FIELD_ERR_DEVICE
842

Monitor Checks
Check ID
Violation
Description
USB_2_0_REQUEST_
TYPE_NOT_DEFINED
Type field in the

The type field of bmrequesttype specified

parameter is 1.
USB_2_0_RESET_TT_
DESCRIPTOR_REQUEST_
ERR

RESET_TT hub class request should have

wvalue of zero and wlength of zero. This
check fires if a nonzero value is detected.
USB_2_0_RESPONSE_FOR_
OUT_SETUP_TOKEN

with any packets on reception
A device should not respond for OUT or

SETUP tokens. Devices are allowed to
respond only after receiving the data packet
associated with an OUT or SETUP
REQUEST_ERR
windex of zero.
SET ADDRESS request should have

values of zero for wlength and windex.
is not satisfied.
USB_2_0_SET_
CONFIGURATION_
REQEST_ERR
A SET_CONFIGURATION
and windex of zero.
SET CONFIGURATION request should

have values of zero for wlength and
windex. This check fires if any of these
REQUEST_DEVICE_ERR

zero.
SET FEATURE request with device as

REQUEST_ERR
SET FEATURE request should have zero

value for wlength. This check fires if
USB_2_0_SET_HUB_
FEATURE_REQUEST_ERR

should have windex and
wlength of zero.
SET FEATURE (set hub feature) hub class

windex and wlength. This check fires if
REQUEST_ERR
A SET_INTERFACE request
SET INTERFACE request should have a

value of zero for wlength. This check fires
if the wlength of SET INTERFACE
REQUEST_TO_HUB

Hub response for a SET INTERFACE

address.
843

Monitor Checks
Check ID
Violation
Description
USB_2_0_SET_PORT_
FEATURE_REQUEST_ERR

SET FEATURE (set port feature) hub class

wlength. This check fires if wlength is not
zero.
USB_2_0_SETUP_DATA_
PID_ERR

A SETUP transaction always uses DATA0

packet ID in the data packet. This check
fires if the DATA0 packet ID is not present
in the data packet of a SETUP transaction.
USB_2_0_SETUP_DATA_
SIZE_ERR

contain 8 bytes.
SETUP data should always contain 8 bytes.

This check fires if SETUP data does not
contain 8 bytes.
NON_CTRL_ENDPOINT
A Host should not issue

SETUP token to the
noncontrol endpoints.
Host should not initiate a control transfer to

the noncontrol end points. This check fires
if SETUP tokens are issued to noncontrol
end points. This check is active only if the
received address specified in the token
field matches the address input.
TO_LOW_SPD_DEVICE

This check fires if the SOF packets are
seen on the low-speed interface. This check
is active only if the PACKET_
ISSUE_CHECK_ENABLE parameter is 1.
IRREGULAR_INTERVALS

high-speed bus.

nominal rate of once in every 1 ms for fullspeed buses and once every 125 us for
high-speed bus. This time is mapped into
the number of clock cycles and is specified
This interval is measured from the end-ofpacket of the SOF packet to end-of-packet
of the next SOF packet. This check fires if
the SOF packets are received earlier than
the frame interval or not received at the
frame interval. This check is active only
when a high-speed/full-speed interface is
tracked by the monitor. This assertion does
not check correctness of Frame number.
ERR

32-bits.
SPLIT token is a special token. This should

be terminated by an end-of-packet
delimiter after receiving 32-bits. This
after 32-bits or end-of-packet is received
before 32-bits.
USB_2_0_SPLIT_TKN_E_
BIT_ERROR

token. Expected e bits is 1'b0.
For bulk/control IN/OUT, interrupt

IN/OUT, and isochronous IN start-splits,
the E field must be set to zero. This check
fires if the E field is set to one.
844

Monitor Checks
Check ID
Violation
Description
USB_2_0_SPLIT_TKN_S_
BIT_ERROR

If the ET field of the SPLIT token specifies

bulk or isochronous IN transfer, then S
should be set to 0. This check fires if the S
bit is set to 1.
USB_2_0_SSPLIT_NO_
PAYLOAD_HOST
A Start-SPLIT token issued to

an isochronous end point with
start, middle, or end encoding
must have a payload.
This check fires if the data packet

following the OUT token does not have a
data payload.
USB_2_0_STALL_NAK_
HANDSHAKE_FOR_SETUP

with STALL or NAK
during control transfer.
Function receiving a SETUP must accept

the SETUP data and respond with ACK.
This check fires if the function returns a
transaction.
USB_2_0_STALL_
RECEIVE_ERR
status phase of control
access to that control endpoint
should result in reception of
stall handshake until the
completion of the next setup
phase.

continue to return stall in response to any
IN or OUT transaction until the next
SETUP transaction is completed. This
check fires if any other handshake packet is
returned by the devices after STALL is
returned. This check is active only when
USB_2_0_STOP_TT_
REQUEST_ERR
A STOP_TT hub class request

wlength of zero.
STOP_TT hub class request should have

wvalue and wlength set to zero. This check
fires if a nonzero value is detected.
USB_2_0_SYNC_FRAME_
REQUEST_ERR
A SYNCH_FRAME request
and wlength of two.
SYNCH FRAME request should have a

value of zero for wvalue and wlength of
two. This check fires if any of these
REQUEST_TO_HUB
SYNCH FRAME request

Hub response for a SYNCH FRAME

address.
USB_2_0_TKN_CRC_ERR
Five-bit CRC field is specified for tokens

to cover the address, end point numbers of
IN, OUT, SETUP and SPLIT tokens, and
the frame number of SOF token. This
check fires if an error is detected in the
CRC.
USB_2_0_SSPLIT_NO_
PAYLOAD_DEVICE
845

Check ID
Violation
Description
USB_2_0_TKN_PKT_SIZE_
ERR

24-bits.

receiving 3 bytes or 24-bits. This check
fires if end-of-packet is not received after
24-bits or end-of-packet is received before
24-bits. This check also covers PING
special token.
USB_2_0_TOKEN_
BEFORE_TIMEOUT
Host should wait for specified

number of bit times to indicate
a timeout.

should wait for the specified number of bit
addition, a host should wait for a specified
sending the next token. This check fires if
the above conditions are violated. For a
full-speed/low-speed bus, the specified
number of bit times is 18. For a high-speed
bus, the specified number of bit times is
816
USB_2_0_WMAX_PKT_
SIZE_ERR_HOST
A Host or Device should not

Host or device can transfer only the

maximum number of bytes is specified in
the end point configuration information.
data packet.
USB_2_0_WMAX_PKT_
SIZE_ERR_DEVICE

Table 19-12 shows the corner cases maintained by the USB 2.0 monitor.
Table 19-12. USB 2.0 Monitor Corner Cases
846
Corner Case
Description
ACK packets
Number of ACK handshake packets issued.
Bulk transfers
Number of transfers to Bulk end points. This corner case is applicable only
when the monitor is configured to track transactions of a bulk endpoint.
This corner case gives the number of complete bulk transfers addressed to
the device with the address specified at the address input.
Clear Feature requests
Number of Clear Feature requests issued by the host.
Clear Hub Feature requests
Number of Clear Hub Feature requests issued by the host. This statistic is
not applicable when the monitor is instantiated on the upstream port of the
function.

Table 19-12. USB 2.0 Monitor Corner Cases (cont.)

Corner Case
Description
Clear Port Feature requests
Number of Clear Port Feature requests issued by host. This statistic is not
applicable when the monitor is instantiated on the upstream port of the
function.
Clear TT Buffer requests
Number of ClearTT Buffer requests issued by the host. This statistic is not
function.
Complete SPLIT packets
Number of Complete-SPLIT packets issued. This corner case is applicable

only when the monitor is instantiated on a downstream port of the host and
an upstream port of the hub.
Control transfers
Number of transfers to a control end point. This corner case is applicable

only when the monitor is configured to track transactions of a control end
point. This corner case gives the number of complete control transfers
addressed to the device with the address specified at the address input.
Data packets
Number of Data packet transfers.
ERR packets
Number of ERR handshake packets. This corner case is applicable only

when the monitor is instantiated on a downstream port of the host and an
upstream port of the hub.
Get Configuration requests
Number of Get Configuration requests issued by the host.
Get Descriptor requests
Number of Get Descriptor requests issued by the host.
Get Hub Descriptor requests
Number of Get Hub Descriptor requests issued by host. This statistic is not
function.
Get Hub Status requests
Number of Get Hub Status requests issued by host. This statistic is not
function.
Get Interface requests
Number of Get Interface requests issued by the host.
Get Port Status requests
Number of Get Port Status requests issued by host. This statistic is not
function.
Get Status requests
Number of Get Status requests issued by the host.
Get TT State requests
Number of GetTTState requests issues by the host. This statistic is not

function.
IN transactions
Number of IN transactions. This corner case gives the number of complete

IN transactions addressed to the device with the address specified at the
address input.
Incomplete IN transactions
Number of Incomplete IN transactions. This statistic gives the number of

incomplete IN transactions addressed to the device with the address
specified at the address input.
Incomplete OUT transactions
Number of Incomplete OUT transactions. This statistic gives the number of

incomplete OUT transactions addressed to the device with the address
847

848
Corner Case
Description
Interrupt transfers
Number of transfers to Interrupt end points. This corner case is applicable

only when the monitor is configured to track transactions of an Interrupt
end point. This corner case gives the number of complete interrupt
transfers addressed to the device with the address specified at the address
input.
Isochronous transfers
Number of transfers to Isochronous end points. This corner case is

applicable only when the monitor is configured to track transactions of an
Isochronous end point. This corner case gives the number of complete
Isochronous transfers addressed to the device with the address specified at
the address input.
NAK packets
Number of NAK handshake packets issued.
NYET packets
Number of NYET handshake packets issued.
OUT transactions
Number of OUT transactions. This corner case gives the number of

complete OUT transactions addressed to the device with address specified
at the address input.
PING packets
Number of PING tokens issued.
Pre PIDs issued
Number of PRE PID packets issued. This corner case is applicable only
when the monitor is instantiated on a downstream port of the hub.
Reset TT requests
Number of ResetTT requests issues by the host. This statistic is not

function.
Resets issued
Number of cycles a reset is issued by the host or Hub. This statistic counts
only resets initiated through SE0 signaling.
Set Address requests
Number of Set Address requests issued by the host.
Set Configuration requests
Number of Set Configuration requests issued by the host.
Set Descriptor requests
Number of Set Descriptor requests issued by the host.
Set Feature requests
Number of Set Feature requests issued by the host.
Set Hub Descriptor requests
Number of Set Hub Descriptor requests issued by host. This statistic is not
function.
Set Hub Feature requests
Number of Set Hub Feature requests issued by the host. This statistic is not
function.
Set Interface requests
Number of Set Interface requests issued by the host.
Set Port Feature requests
Number of Set Port Feature requests issued by the host. This statistic is not
function.
Setup tokens
Number of SETUP tokens issued by the host.
SOF packets
Number of SOF packets issued by host.
STALL packets
Number of STALL handshake packets issued.
Start SPLIT packets
Number of Start-SPLIT packets issued. This corner case is applicable only

when the monitor is instantiated on a downstream port of the host and an
upstream port of the hub.

Monitor Statistics

Corner Case
Description
Stop TT requests
Number of StopTT requests issues by the host. This statistic is not

function.
Synch Frame requests
Number of Synch Frame requests issued by the host.
Time outs
Number of times a time out occurred.
Token packets
Number of Token packets issued by host.
Transactions aborted
Number of transactions aborted. This statistic gives the number of

transactions aborted to the device with the address specified at the address
input.
Monitor Statistics
Table 19-13 shows the statistics maintained by the USB 2.0 monitor.
Table 19-13. USB 2.0 Monitor Statistics
Statistic
Description
Transaction count
Number of transactions. This statistic gives the number of completed

transactions addressed to the device with the address specified at the
address input.
Packets with error
Number of packets with an error.
Packets without error
Number of packets without an error.
No response count
Number of times no response is received for a packet received without an

error.
Incomplete transactions
Number of incomplete transactions. A transaction is incomplete if NAK

or STALL is received in a handshake. This statistic gives the number of
incomplete transactions addressed to the device with the address
849

Monitor Statistics
850
Appendix 20
QVL Defines
Global Defines
Type
DEFINE
Description
Function
`QVL_ASSERT_ON
Activates (and Accellera Standard OVL)

assertion logic. Default: not defined.
`QVL_COVER_ON
Activates coverage logic. Default: not defined.
`QVL_SV_
COVERGROUP_OFF
Disables creation of SystemVerilog

covergroup logic. Default: not defined.
`QVL_CW_FINAL_
COVER
Turns on the display of final coverage

information for QVL checkers. Default: final
coverage not displayed.
`QVL_MW_FINAL_
COVER_OFF
Turns off the display of final coverage

information for QVL monitors. Default: final
coverage is displayed.
Synthesizable
Logic
`QVL_SVA_INTERFACE
Instantiates QVL assertion checkers in a

SystemVerilog interface construct. Default:
not defined.
X/Z Values
`QVL_XCHECK_OFF
Turns off all X/Z checks. Default: not defined.
Coverage
Internal Global Defines

The following global variables are for internal use and the user should not redefine them:
`qvlmodule
`qvlendmodule
`QVL_STD_DEFINES_H
851
QVL Defines
Defines Common to All Assertions
Defines Common to All Assertions

Parameter
DEFINE
Description
severity_level
`QVL_FATAL
Runtime fatal error.
`QVL_ERROR
(default) Runtime error.
`QVL_WARNING
Runtime Warning.
`QVL_INFO
Assertion failure has no specific severity.
`QVL_ASSERT
(default) All the assertion checkers checks

are asserts.
`QVL_ASSUME
All the assertion checkers checks are

assumes.
`QVL_IGNORE
All the assertion checkers checks are

ignored.
`QVL_COVER_ALL
(default) Activates coverage logic for the

checker if `QVL_COVER_ON is defined.
`QVL_COVER_NONE,
`QVL_COVER_SANITY,
`QVL_COVER_BASIC,
`QVL_COVER_CORNER,
`QVL_COVER_STATISTIC
Reserved for future use.
property_type
coverage_level
852
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REPLACEMENT OF THE PRODUCTS THAT DO NOT MEET THIS LIMITED WARRANTY, PROVIDED
CUSTOMER HAS OTHERWISE COMPLIED WITH THIS AGREEMENT. MENTOR GRAPHICS MAKES NO
WARRANTIES WITH RESPECT TO: (A) SERVICES; (B) PRODUCTS PROVIDED AT NO CHARGE; OR (C) BETA
CODE; ALL OF WHICH ARE PROVIDED AS IS.
8.2. THE WARRANTIES SET FORTH IN THIS SECTION 8 ARE EXCLUSIVE. NEITHER MENTOR GRAPHICS NOR
ITS LICENSORS MAKE ANY OTHER WARRANTIES EXPRESS, IMPLIED OR STATUTORY, WITH RESPECT TO
PRODUCTS PROVIDED UNDER THIS AGREEMENT. MENTOR GRAPHICS AND ITS LICENSORS
SPECIFICALLY DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY.
9.
LIMITATION OF LIABILITY. EXCEPT WHERE THIS EXCLUSION OR RESTRICTION OF LIABILITY WOULD BE

VOID OR INEFFECTIVE UNDER APPLICABLE LAW, IN NO EVENT SHALL MENTOR GRAPHICS OR ITS
LICENSORS BE LIABLE FOR INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES (INCLUDING
LOST PROFITS OR SAVINGS) WHETHER BASED ON CONTRACT, TORT OR ANY OTHER LEGAL THEORY, EVEN
IF MENTOR GRAPHICS OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN
NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS LIABILITY UNDER THIS AGREEMENT EXCEED
THE AMOUNT RECEIVED FROM CUSTOMER FOR THE HARDWARE, SOFTWARE LICENSE OR SERVICE GIVING
RISE TO THE CLAIM. IN THE CASE WHERE NO AMOUNT WAS PAID, MENTOR GRAPHICS AND ITS LICENSORS
SHALL HAVE NO LIABILITY FOR ANY DAMAGES WHATSOEVER. THE PROVISIONS OF THIS SECTION 9 SHALL
SURVIVE THE TERMINATION OF THIS AGREEMENT.
10. HAZARDOUS APPLICATIONS. CUSTOMER ACKNOWLEDGES IT IS SOLELY RESPONSIBLE FOR TESTING ITS
PRODUCTS USED IN APPLICATIONS WHERE THE FAILURE OR INACCURACY OF ITS PRODUCTS MIGHT
RESULT IN DEATH OR PERSONAL INJURY (HAZARDOUS APPLICATIONS). NEITHER MENTOR GRAPHICS
NOR ITS LICENSORS SHALL BE LIABLE FOR ANY DAMAGES RESULTING FROM OR IN CONNECTION WITH
THE USE OF MENTOR GRAPHICS PRODUCTS IN OR FOR HAZARDOUS APPLICATIONS. THE PROVISIONS OF
THIS SECTION 10 SHALL SURVIVE THE TERMINATION OF THIS AGREEMENT.
11. INDEMNIFICATION. CUSTOMER AGREES TO INDEMNIFY AND HOLD HARMLESS MENTOR GRAPHICS AND
ITS LICENSORS FROM ANY CLAIMS, LOSS, COST, DAMAGE, EXPENSE OR LIABILITY, INCLUDING
ATTORNEYS FEES, ARISING OUT OF OR IN CONNECTION WITH THE USE OF PRODUCTS AS DESCRIBED IN
SECTION 10. THE PROVISIONS OF THIS SECTION 11 SHALL SURVIVE THE TERMINATION OF THIS
AGREEMENT.
12. INFRINGEMENT.
12.1. Mentor Graphics will defend or settle, at its option and expense, any action brought against Customer in the United States,
Canada, Japan, or member state of the European Union which alleges that any standard, generally supported Product
acquired by Customer hereunder infringes a patent or copyright or misappropriates a trade secret in such jurisdiction.
Mentor Graphics will pay costs and damages finally awarded against Customer that are attributable to the action. Customer
understands and agrees that as conditions to Mentor Graphics obligations under this section Customer must: (a) notify
Mentor Graphics promptly in writing of the action; (b) provide Mentor Graphics all reasonable information and assistance
to settle or defend the action; and (c) grant Mentor Graphics sole authority and control of the defense or settlement of the
action.
12.2. If a claim is made under Subsection 12.1 Mentor Graphics may, at its option and expense, (a) replace or modify the Product
so that it becomes noninfringing; (b) procure for Customer the right to continue using the Product; or (c) require the return
of the Product and refund to Customer any purchase price or license fee paid, less a reasonable allowance for use.
12.3. Mentor Graphics has no liability to Customer if the action is based upon: (a) the combination of Software or hardware with
any product not furnished by Mentor Graphics; (b) the modification of the Product other than by Mentor Graphics; (c) the
use of other than a current unaltered release of Software; (d) the use of the Product as part of an infringing process; (e) a
product that Customer makes, uses, or sells; (f) any Beta Code or Product provided at no charge; (g) any software provided
by Mentor Graphics licensors who do not provide such indemnification to Mentor Graphics customers; or
(h) infringement by Customer that is deemed willful. In the case of (h), Customer shall reimburse Mentor Graphics for its
reasonable attorney fees and other costs related to the action.
12.4. THIS SECTION 12 IS SUBJECT TO SECTION 9 ABOVE AND STATES THE ENTIRE LIABILITY OF MENTOR
GRAPHICS AND ITS LICENSORS FOR DEFENSE, SETTLEMENT AND DAMAGES, AND CUSTOMERS SOLE
AND EXCLUSIVE REMEDY, WITH RESPECT TO ANY ALLEGED PATENT OR COPYRIGHT INFRINGEMENT
OR TRADE SECRET MISAPPROPRIATION BY ANY PRODUCT PROVIDED UNDER THIS AGREEMENT.
13. TERMINATION AND EFFECT OF TERMINATION. If a Software license was provided for limited term use, such license
will automatically terminate at the end of the authorized term.
13.1. Mentor Graphics may terminate this Agreement and/or any license granted under this Agreement immediately upon written
notice if Customer: (a) exceeds the scope of the license or otherwise fails to comply with the licensing or confidentiality
provisions of this Agreement, or (b) becomes insolvent, files a bankruptcy petition, institutes proceedings for liquidation or
winding up or enters into an agreement to assign its assets for the benefit of creditors. For any other material breach of any
provision of this Agreement, Mentor Graphics may terminate this Agreement and/or any license granted under this
Agreement upon 30 days written notice if Customer fails to cure the breach within the 30 day notice period. Termination of
this Agreement or any license granted hereunder will not affect Customers obligation to pay for Products shipped or
licenses granted prior to the termination, which amounts shall be payable immediately upon the date of termination.
13.2. Upon termination of this Agreement, the rights and obligations of the parties shall cease except as expressly set forth in this
Agreement. Upon termination, Customer shall ensure that all use of the affected Products ceases, and shall return hardware
and either return to Mentor Graphics or destroy Software in Customers possession, including all copies and
documentation, and certify in writing to Mentor Graphics within ten business days of the termination date that Customer no
longer possesses any of the affected Products or copies of Software in any form.
14. EXPORT. The Products provided hereunder are subject to regulation by local laws and United States government agencies,
which prohibit export or diversion of certain products and information about the products to certain countries and certain
persons. Customer agrees that it will not export Products in any manner without first obtaining all necessary approval from
appropriate local and United States government agencies.
15. U.S. GOVERNMENT LICENSE RIGHTS. Software was developed entirely at private expense. All Software is commercial
computer software within the meaning of the applicable acquisition regulations. Accordingly, pursuant to US FAR 48 CFR
12.212 and DFAR 48 CFR 227.7202, use, duplication and disclosure of the Software by or for the U.S. Government or a U.S.
Government subcontractor is subject solely to the terms and conditions set forth in this Agreement, except for provisions which
are contrary to applicable mandatory federal laws.
16. THIRD PARTY BENEFICIARY. Mentor Graphics Corporation, Mentor Graphics (Ireland) Limited, Microsoft Corporation
and other licensors may be third party beneficiaries of this Agreement with the right to enforce the obligations set forth herein.
17. REVIEW OF LICENSE USAGE. Customer will monitor the access to and use of Software. With prior written notice and
during Customers normal business hours, Mentor Graphics may engage an internationally recognized accounting firm to
review Customers software monitoring system and records deemed relevant by the internationally recognized accounting firm
to confirm Customers compliance with the terms of this Agreement or U.S. or other local export laws. Such review may include
FLEXlm or FLEXnet (or successor product) report log files that Customer shall capture and provide at Mentor Graphics
request. Customer shall make records available in electronic format and shall fully cooperate with data gathering to support the
license review. Mentor Graphics shall bear the expense of any such review unless a material non-compliance is revealed. Mentor
Graphics shall treat as confidential information all information gained as a result of any request or review and shall only use or
disclose such information as required by law or to enforce its rights under this Agreement. The provisions of this Section 17
shall survive the termination of this Agreement.
18. CONTROLLING LAW, JURISDICTION AND DISPUTE RESOLUTION. The owners of certain Mentor Graphics
intellectual property licensed under this Agreement are located in Ireland and the United States. To promote consistency around
the world, disputes shall be resolved as follows: excluding conflict of laws rules, this Agreement shall be governed by and
construed under the laws of the State of Oregon, USA, if Customer is located in North or South America, and the laws of Ireland
if Customer is located outside of North or South America. All disputes arising out of or in relation to this Agreement shall be
submitted to the exclusive jurisdiction of the courts of Portland, Oregon when the laws of Oregon apply, or Dublin, Ireland when
the laws of Ireland apply. Notwithstanding the foregoing, all disputes in Asia arising out of or in relation to this Agreement shall
be resolved by arbitration in Singapore before a single arbitrator to be appointed by the chairman of the Singapore International
Arbitration Centre (SIAC) to be conducted in the English language, in accordance with the Arbitration Rules of the SIAC in
effect at the time of the dispute, which rules are deemed to be incorporated by reference in this section. This section shall not
restrict Mentor Graphics right to bring an action against Customer in the jurisdiction where Customers place of business is
located. The United Nations Convention on Contracts for the International Sale of Goods does not apply to this Agreement.
19. SEVERABILITY. If any provision of this Agreement is held by a court of competent jurisdiction to be void, invalid,
unenforceable or illegal, such provision shall be severed from this Agreement and the remaining provisions will remain in full
force and effect.
20. MISCELLANEOUS. This Agreement contains the parties entire understanding relating to its subject matter and supersedes all
prior or contemporaneous agreements, including but not limited to any purchase order terms and conditions. Some Software
may contain code distributed under a third party license agreement that may provide additional rights to Customer. Please see
the applicable Software documentation for details. This Agreement may only be modified in writing by authorized
representatives of the parties. Waiver of terms or excuse of breach must be in writing and shall not constitute subsequent
consent, waiver or excuse.
Rev. 100615, Part No. 246066

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Questa Verification Library

Monitors Data Book

1991-2010 Mentor Graphics Corporation

Questa Verification Library Monitors Data Book, v2010.2

AHB Target Monitor FAQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Questa Verification Library Monitors Data Book, v2010.2

Questa Verification Library Monitors Data Book, v2010.2

Questa Verification Library Monitors Data Book, v2010.2

HDMI Monitor Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Questa Verification Library Monitors Data Book, v2010.2

Questa Verification Library Monitors Data Book, v2010.2

Instantiation Examples (PIPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Questa Verification Library Monitors Data Book, v2010.2

Questa Verification Library Monitors Data Book, v2010.2

End-User License Agreement

Questa Verification Library Monitors Data Book, v2010.2

Questa Verification Library Monitors Data Book, v2010.2

Questa Verification Library Monitors Data Book, v2010.2

Questa Verification Library Monitors Data Book, v2010.2

Figure 14-4. Gen1 PIPE Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Questa Verification Library Monitors Data Book, v2010.2

Table 6-15. JEDEC Mode Burst Length Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Questa Verification Library Monitors Data Book, v2010.2

Table 8-18. XLGMII/CGMII Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Questa Verification Library Monitors Data Book, v2010.2

Table 11-3. LPC Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Questa Verification Library Monitors Data Book, v2010.2

Questa Verification Library Monitors Data Book, v2010.2

Table 18-7. SPI4-2 Transmit Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Questa Verification Library Monitors Data Book, v2010.2

Questa Verification Library Monitors Data Book, v2010.2

SET COMmand Editing

Square brackets enclose optional arguments. Do

An italic font indicates a user-supplied

ADD LFsrs lfsr_name

Braces enclose arguments to show grouping. Do

ADD LFsrs lfsr_name

The vertical bar indicates an either/or choice

ADD LFsr Connections

An ellipsis follows an argument that may appear

The following examples demonstrate these syntax conventions.

One or more occurrences of signal.

Zero or one occurrences of -var

-var followed by one or more occurrences

Zero or more occurrences of std_option.

Questa Verification Library Monitors Data Book, v2010.2

One or more occurrences of arg1 arg2.

var1 | var2 | var3

One occurrence of var1or var2 or var3.

constant | val1 val2

One occurrence of constant or val1 val2.

Zero or more occurrences of any of var1,

Mentor Graphics Support

Questa Verification Library Monitors Data Book, v2010.2

They warn of violations of the interface protocol through SystemVerilog assertion

QVL Use Model

Questa Verification Library Monitors Data Book, v2010.2

QVL Monitors Basics

7. QVL Monitor Coverage on page 36

Specifying Global Defines

Specify settings in a Verilog file loaded before the libraries.

Enabling Assertion and Coverage Logic