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Short Course for Indonesian Scholars

Digital System Design


Spring in 2015

Presenter by Ying-Shieh Kung


Nguyen Phan Thanh
Risfendra

Content
1. Introduction to digital system design (Mar. 11) (by Ying-Shieh Kung)
Introduction to FPGA
Introduction to VHDL
Case study in controller and filter design using VHDL
2. ModelSim/Simulink co-simulation (Mar. 18) (by Nguyen Phan Thanh )
Introduction to ModelSim Simulation
Introduction to ModelSim/Simulink co-simulation
Case study
3. FPGA implementation (Mar. 25) (by Risfendra)

A. Introduction to Case Study


of ModelSim Simulation
For ModelSim 5.7d

Arranged by Nguyen Phan Thanh

Spring 2015 in STUST, Taiwan

Refer from:
Prof. Ying-Shieh Kung, Teaching Material, 2014.
Volnei A. Pedroni, Circuit Design and Simulation with VHDL,
Second Edition, The MIT Press, 2010.
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1. Open a project

(project file)

testbench file
original VHDL code

1. Create a new project

2. Add vhd file and testbench file

3. Compile

Counter.vhd

library ieee;
use ieee.std_logic_1164.all;
use Ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-----------------------------------------ENTITY counter IS
PORT(
clk, count_ena
: IN
BIT;
clear, load, direction
: IN
BIT;
p
: IN
INTEGER RANGE 0 TO
255;
max_min
: OUT BIT;
qd
: OUT INTEGER RANGE 0 TO
255);
END counter;
-----------------------------------------ARCHITECTURE a OF counter IS
BEGIN
PROCESS (clk, clear, load)
VARIABLE cnt
: INTEGER RANGE 0 TO 255;
BEGIN
IF (clear = '0') THEN
-- Asynchrnous clear
cnt := 0;
ELSIF (load = '1' and clear = '1') THEN -- Asynchronous
load
cnt := p;
ELSE
IF (clk'EVENT AND clk = '1') THEN
IF (count_ena = '1' and direction = '0') THEN
cnt := cnt - 1;
ELSIF (count_ena = '1' and direction = '1') THEN
cnt := cnt + 1;
END IF;
END IF;
END IF;
qd <= cnt;

-- Terminal count decoder


IF (cnt = 0 and direction = '0') THEN
max_min
<= '1';
ELSIF (cnt = 255 and direction = '1') THEN
max_min <= '1';
ELSE
max_min <= '0';
END IF;
END PROCESS;
END a;

Counter_tb.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
----------------------------------ENTITY counter_tb IS
END counter_tb;
----------------------------------------ARCHITECTURE testbench of counter_tb IS
----- counter declaration --------------COMPONENT counter
PORT ( clk, count_ena
: IN
BIT;
clear, load, direction
: IN
BIT;
p
: IN
INTEGER RANGE 0 TO 255;
max_min
: OUT BIT;
qd
: OUT INTEGER RANGE 0 TO 255);
END COMPONENT;

BEGIN
----- counter_1 instantiation --------------Counter_1: counter PORT MAP (clk, counter_ena,
clear, load, direction, P, max_min, qd);
----- Stimuli generation -------------clk <= NOT clk AFTER 40ns;
clear <= '1' AFTER 0ns;
counter_ena <= '1' AFTER 0ns;
load <= '0' AFTER 0ns;
direction <= '1' AFTER 0ns;
P <= 20 AFTER 0ns;
END testbench;

----- signal declaration ----------SIGNAL clk: BIT := '0';


SIGNAL counter_ena: BIT := '0';
SIGNAL clear: BIT := '0';
SIGNAL load: BIT := '0';
SIGNAL direction: BIT := '0';
SIGNAL P : INTEGER :=0;
SIGNAL max_min : BIT;
SIGNAL qd: INTEGER;

4. Simulation

Choose Library tab


Right click counter_tb => Simulate

Compilation result

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5. Add waveform
Choose Sim tab
Right click counter_tb => Add => Add to Wave

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Setting the simulation time

Change the running time (this case : 500 ns)

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6. Running

Simulation results

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7. End Simulation

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B. Introduction to
ModelSim/Simulink Co-simulation
For ModelSim 5.7d
Matlab 8.0

Arranged by Nguyen Phan Thanh

Spring 2015 in STUST, Taiwan

15

Introduction to ModelSim/Simulink Co-simulation


Matlab Simulink

ModelSim

To verify the functionality


of the HDL correctly match the
system specifications

Environment for multidomain


simulation and Model-Based
Design for dynamic and
embedded systems

y=f(x)

Chip design using HDL


(Hardware Description Languages)

High-level tool for designing


high-performance DSP systems
using FPGAs

Co-simulate ModelSim/Simulink

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MATLAB AND MODELSIM LINKING


(For the link to work, Modelsim has to be invoked from the command prompt of MATLAB.
For this purpose, MATLAB needs to know the location of MODELSIM)

>> configuremodelsim

(Step 1)

Identify the ModelSim installation to be configured for MATLAB and Simulink


Do you want configuremodelsim to locate installed ModelSim executables [ y ] / n ? y

(Step 2)

Select a ModelSim installation to be configured:


[1] C:\Modeltech_5.7d\win32
[0] None

ModelSim SE 5.7d

Select ModelSim installation to be configured: 1

(Step 3)

Previous MATLAB startup file found in this installation of ModelSim:


C:\Modeltech_5.7d\win32\..\tcl\ModelSimTclFunctionsForMATLAB.tcl
Do you want to replace this file [y]/n? y
(Step 4)
ModelSim successfully configured to be used with MATLAB and Simulink

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MODELSIM/MATLAB SIMULINK CO-SIMULATION


1. Open ModelSim in Matlab main window to make the communication

>> configuremodelsim
Identify the ModelSim installation to be configured for MATLAB and Simulink
Do you want configuremodelsim to locate installed ModelSim executables [ y ] / n ? y
Select a ModelSim installation to be configured:
[1] C:\Modeltech_5.7d\win32
[0] None

ModelSim SE 5.7d

Select ModelSim installation to be configured: 1


Previous MATLAB startup file found in this installation of ModelSim:
C:\Modeltech_5.7d\win32\..\tcl\ModelSimTclFunctionsForMATLAB.tcl
Do you want to replace this file [y]/n? y
ModelSim successfully configured to be used with MATLAB and Simulink
>> vsim('socketsimulink',4449)

(Open ModelSim)
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2. ModelSim
2.1. Create new project
- File => New => Project
- Type counter (any project name)

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2.2. Add vhd file

(Step 1)

(Step 2: Choose all files)

Co-simulation & Library files


Original VHDL code

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2.3. Add new library


-

File => New => Library


Choose a new library and a logical mapping to it
At the library name, type lpm

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2.4. Setting file properties


-

Choose all files


Right click and choose Properties
Click tab VHDL, choose Use 1993 Language Syntax

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2.4. Setting file properties (cont.)


-

Choose 2 files 220models and 220pack


Right click and choose Properties
At tab VHDL, choose lpm in Compile to library index

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2.5. Compile program


-

Choose all files


Right click and choose Compile => Compile All

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2.6. Simulation
-

At main window, type vsimu work.counter


(Commands structure: vsimu work.name_of_entity1 work. name_of_entity2)

# Reading C:/Modeltech_5.7d/tcl/vsim/pref.tcl
# do {D:/Softwares/MATLAB/R2008a/bin/tp2eb1637e_fa87_4651_9eb1_209b9189e1d8}
# Loading project counter
# Compile of 220model.vhd was successful.
# Compile of 220pack.vhd was successful.
# Compile of counter.vhd was successful.
# 3 compiles, 0 failed with no errors.

ModelSim> vsimu work.counter


# vsim -foreign {simlinkserver
{D:/Softwares/MATLAB/R2008a/toolbox/modelsim/windows32/liblfmhdls_vs05.dll} ; -socket
4449 } work.counter
# Loading C:/Modeltech_5.7d/win32/../std.standard
# Loading C:/Modeltech_5.7d/win32/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_5.7d/win32/../ieee.std_logic_arith(body)
# Loading C:/Modeltech_5.7d/win32/../ieee.std_logic_unsigned(body)
# Loading work.counter(a)
# Loading D:/Softwares/MATLAB/R2008a/toolbox/modelsim/windows32/liblfmhdls_vs05.dll

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3. Matlab
3.1. Create new model
- At main window, type Simulink
- At Simulink Library Browser, choose EDA Simulator Link MQ

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3.2. Setting HDL block parameters


- At tab Ports, add inputs, outputs and their parameters

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3.2. Setting HDL block parameters (cont.)


- At tab Clock, add clock and timing period

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3.2. Setting HDL block parameters (cont.)

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3.2. Setting HDL block parameters (cont.)

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3.3. Create Model and start Co-simulation


bin 1

Display 1

clear
1

qd

Convert

clear

Constant 5

load

qd
0

Convert

(SI) bin 0001 0100

load
Display 3

Constant 1

direction
1

Convert

direction

Convert

count _ena

Constant 2

count _ena
max _min

max _min

Constant 3

bin 0
Display 6

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HDL Cosimulation

int 8

Constant 4
HDL Cosimulation

bin 0001 0100

Display 2

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3.3. Create Model and start Co-simulation (cont.)

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3.3. Create Model and start Co-simulation (cont.)

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3.3. Create Model and start Co-simulation (cont.)

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3.3. Create Model and start Co-simulation (cont.)

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3.3. Create Model and start Co-simulation (cont.)

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ModelSim/Simulink Co-simulation
Case study
- Sum of Product (SoP)
- Filter Design

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38

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Example-1 Sum of Product

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Example-1 Sum of Product

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Example-1 Sum of Product

0.2

Convert

x1
bin 0000 1100 0010 0111

0.3

fixdt(1,16,0)

Convert

x2

-0.1

Convert

x3

0.5

Convert

a1

0.15

Convert

a2

0.5

Convert

a3

0.094940185546875

-K Gain 1

Output

0: unsigned
1: signed

Q format (Q0)

data length (16bits)


Sum of Product

5.9814453125015

x1

Subtract
x2
x3

fcn

e-005

error

0.095

a1

Display 1
a2

function y = fcn(x1,x2,x3,a1,a2,a3)
y=a1*x1+a2*x2+a3*x3

a3

Embedded
MATLAB Function

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Example-1 Sum of Product


0.2

Convert

x1
bin 0000 1100 0010 0111

0.3

-0.1

Convert

Convert

x2

0.094940185546875

x3
y

0.5

Convert

a1

0.15

Convert

a2

0.5

Convert

a3

-K Gain 1

Output

Sum of Product

5.9814453125015

x1

Subtract

error

x2
x3

fcn

e-005

0.095

a1

Display 1
a2
a3

Embedded
MATLAB Function

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Example-2 Filter Design


A second-order low-pass filter is designed with
bandwidth 5Hz and damping ratio 1.0
The continuous transfer function of the second order low
pass filter is:

Its fourth order low pass filter:

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Example-2 Filter Design


After the bilinear transform with sampling time 0.01,
its discrete transfer function is

Difference equation after Q15 format: (y(n)*32768, or x(n)*32768)


Y(n)= 95486*Y(n-1) 104366*Y(n-2) + 50692*Y(n-3) - 9234*Y(n-4) +
11*X(n) + 44*X(n-1) + 67*X(n-2) + 44*X(n-3) + 11*X(n-4)
Where x(n) are inputs and y(n) are outputs

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Example-2 Filter Design


I. Technique description

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Example-2 Filter Design


II. VHDL Code

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Example-2 Filter Design

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Example-2 Filter Design

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Example-2 Filter Design

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Example-2 Filter Design


III. Simulation Result (ModelSim/Simulink Co-simulation)

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Example-2 Filter Design

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Example-2 Filter Design

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Example-2 Filter Design

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Thank you for your attention

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