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The main aim of the design is to use the generated DSBG for memory applications
In this design we utilize the existing designed systems for purpose of specific
application based oriented design as memories.
This design comprises of the TPG unit and also the Memory module i.e. controller as
well as memory units for the correct response of the real time parameters such as
(Speed, Power, Delay etc).
We have proposed a FSM model based Controller design for the memory unit, which
controls the both the test pattern generator as well.
Literature Survey:
Introduction:
Various forms of embedded test are increasingly viewed as essential to reduce test cost.
Among them, scan testing has gained broad acceptance as a reliable solution. However, due
to the high data activity associated with scan-based test operations, a circuit under test can
dissipate much more power than it was designed to function under. With overstressing
devices beyond the mission mode, reductions in the operating power of ICs in a test mode
have been of concern for years. A full-toggle scan pattern may draw several times the typical
functional mode power, and this trend continues to rise, particularly over the mission modes
peak power. This power-induced over-test may result in thermal issues, voltage noise, power
droop, or excessive peak power over multiple cycles which, in turn, cause a yield loss due to
instant device damage, severe decrease in chip reliability, shorter product lifetime, or a device
malfunction because of timing failures following a significant circuit delay increase, for
example. Abnormal switching activity may also cause fully functional chips to fail during
testing because of phenomena such as IR-drop, crosstalk, or di/dt problem. Numerous
schemes for power reduction during scan testing have been devised [8]. Among them there
are solutions specifically proposed for built-in self-test (BIST) to keep the average and peak
power below a given threshold. For example, the test power can be reduced by preventing
transitions at memory elements from propagating to combinational logic during scan shift.
This is achieved by inserting gating logic between scan cell outputs and logic they drive [4],
[9]. During normal operations and capture, this logic remains transparent. Gated scan cells
are also proposed in [2] and [20]. A synergistic test power reduction method of [21] uses
available on-chip clock gating circuitry to selectively block scan chains while employing test
scheduling and planning to further decrease BIST power in the Cell processor. A test vector
inhibiting scheme of [5] masks test patterns generated by an LFSR as not all produced
vectors, often very lengthy, detect faults. Elimination of such tests can reduce switching
activity with no impact on fault coverage. The advent of low-transition test pattern generators
has added a new dimension to power aware BIST solutions [3], [11], [15]. A device presented
in [19] is comprised of an LFSR feeding scan chains through biasing logic and T-type flipflop. Since this flip-flop holds the previous value until its input is asserted, the same value is
repeatedly scanned into scan chains until the value at the output of biasing logic (e.g., a kinput AND gate) becomes 1. Depending on k, one can significantly reduce the number of
transitions occurring at the scan chain inputs. A dual-speed LFSR of [18] consists of two
LFSRs driven by normal and slow clocks, respectively. The switching activity is reduced at
the circuit inputs connected to the slow-speed LFSR, while the whole scheme still ensures
satisfactory fault coverage. Mask patterns are used in [14] to mitigate the switching activity
in LFSRproduced patterns, whereas a bit swapping of [1] achieves the same goal at the
primary inputs of CUT. A gated LFSR clock of [6] allows one to activate only half of LFSR
stages at a time, thus reducing power consumption, as only half of the circuit inputs change
every cycle. A scheme that combines the low transition generator of [19] (handling easytodetect faults) with a 3-weight PRPG (deployed to detect random pattern resistant faults) can
also be used to reduce switching activity during BIST, as demonstrated in [17]. The schemes
of [10], [13], and [16] suppress transitions in LFSR generated sequences by either statistical
monitoring or injecting intermediate and highly correlated patterns. Finally, a random singleinput change generator can produce low power patterns in a parallel BIST environment, as
shown in [7]. As the BIST power consumption can easily exceed the maximum ratings when
testing at speed, scan patterns must be shifted at a programmable low speed, and only the last
few cycles and the capture cycle are applied at the maximum frequency. In the burst-mode
approach presented in [12], typically five consecutive clock cycles are used. The first
four cycles serve shifting purposes, whereas the last one is designated for capture. The
objective is to stabilize the power supply before the last shift and capture pulses are applied,
which are critical for at-speed tests. To reduce the voltage droop related to a higher circuit
activity, a burst clock controller slows down some of the shift cycles. It allows a gradual
increase of the circuit activity, thereby reducing the di/dt effect. The controller can gate the
shift clocks, depending on the needs for gradual warming up of the circuit. In this paper, we
propose a new pseudorandom test pattern generator (PRPG) for low power BIST
applications. The generator is aimed at reducing the switching activity during scan loading
due to its preselected toggling (PRESTO) levels. It can assume a variety of configurations
that allow a given scan chain to be driven either by PRPG itself or by a constant value fixed
for a given period of time. The PRESTO generator allows loading scan chains with patterns
having low transition counts, and thus significantly reduced power dissipation.
Much higher flexibility in forming low-toggling test patterns can be achieved by deploying a
scheme presented in Fig. 2. Essentially, while preserving the operational principles of the
basic solution, this approach splits up a shifting period of every test pattern into a sequence of
alternating hold and toggle intervals. To move the generator back and forth between these two
states, we use a basic T-type flipflop that switches whenever there is a 1 on its data input. If it
is set to 0, the generator enters the hold period with all latches temporarily disabled regardless
of the shift register content. This property can be crucial in SoC designs where only a single
scan chain crosses a given core, and its abnormal toggling may cause locally unacceptable
heat dissipation that can only be reduced due to temporary hold periods. To make it work, it
first requires placing AND gates on the shift register outputs to allow freezing of all phase
shifter inputs. If the T flip-flop is set to 1 (the toggle period), then the latches enabled through
the shift register can pass test data moving from the PRPG to the scan chains. How long it
takes to stay either in the hold mode or in the toggle mode is decided by two additional userdefined parameters kept in 3-bit Hold and Toggle registers, respectively. In order to terminate
either mode, a 1 must occur on the T flip-flop input.
This weighted pseudorandom signal is produced by a module Encoder H/T based on the
content of seven different stages of the original PRPG, as shown in Fig. 3. Depending on the
control code provided by either the Toggle register or the Hold register, the encoder output
can be asserted with the probability ranging from 21 to 27. Moreover, the control code 000
causes the encoder to assume the high output unconditionally. This property can be used to
terminate deterministically a given period (hold or toggle) within a single clock cycle.
Verilog HDL is a hardware description language that can be used to model a digital
system at many levels of abstraction ranging from the algorithmic-level to the gate-level to
the switch-level. The complexity of the digital system being modeled could vary from that of
a simple gate to a complete electronic digital system, or anything in between. The digital
system can be described hierarchically and timing can be explicitly modeled within the same
description.
Verilog capabilities
The Verilog HDL language includes capabilities to describe the behavior-al nature of a
design, the dataflow nature of a design, a design's structural composition, delays and a
The language not only defines the syntax but also defines very clear simulation
semantics for each language construct. Therefore, models written in
verified using a Verilog simulator. The language inherits
constructs from the C programming language. Verilog HDL provides an extensive range of
modeling capabilities, some of which are quite difficult to comprehend initially. However, a
core subset of the language is quite easy to leam and use. This is sufficient to model most
applications. The complete language, however, has sufficient capabilities to capture the
descriptions from the most complex chips to a complete electronic system.
HISTORY
The verilog HDL language was first developed by Gateway Design Automation in
1983 as hardware are modleling language for their simulator product, At that time ,twas a
propnetary language. Because of the popularity of the,simulator product, Verilog HDL gained
acceptance as a usable and practical language by a number of designers. In an effort to
increase the popularity of the language, the language was placed in the public domain in
1990. Open verilog International (OVI) was formed to promote Verilog. In 1992 OVI decided
to pursue standardization of verilog HDL as an IEEE standard. This effort was succeful and
the language became an IEEE standard in 1995. The complete standard is described in the
verilog hardware description language reference manual. The standard is called std 13641995.
MAJOR CAPABILITIES
Listed below are the majort capabilities of the verilog hardware description
Primitive logic gates, such as and, or and nand, are built-in into the language.
Flexibility of creating a user-defined primitive (UDP). Such a primitive could either
be a combinational logic primitive or a sequential logic primitive.
Switch-level modeling primitive gates, such as pmos and nmos, are also built-in into
the language.
Explicit language constructs are provided for specifying pin-to-pin delays, path delays
and timing checks of a design.
A design can be modeled in three different styles or in a mixed style. These styles are:
behavioral style - modeled using procedur-al constructs; dataflow style - modeled
using continuous assign-ments; and structural style - modeled using gate and module
instantiations.
There are two data types in Verilog HDL; the net data type and the register data type.
The net type represents a physical connection between structural elements while a
register type represents an abstract data storage element.
Hierarchical designs can be described, up to any level, using the module instantiation
construct.
A design can be of arbitrary size; the language does not impose a limit.
Verilog HDL is non-proprietary and is an IEEE standard.
A design can be described in a wide range of levels, ranging from switch-level, gatelevel,
register-transfer-level
(RTL)
queuing-level.
A design can be modeled entirely at the switch-level using the built-in switch-level
primitives.
The same single language can be used to generate stimulus for the design and for
specifying test constraints, such as specifying the values of inputs.
Verilog HDL can be used to perform response monitoring of the design under test,
that is, the values of a design under test can be monitored and displayed. These values
can also be compared with expected values, and in case of a mismatch, a report
message can be printed.
At the behavioral-level, Verilog HDL can be used to describe a design not only at the
RTL-level, but also at the architectural-level and its algorithmic-level behavior.
At the structural-level, gate and module instantiations can be used.
Figure 5.1 shows the mixed-level modeling capability of Verilog HDL, that is, in one
design, each module may be modeled at a different level.
Verilog HDL also has built-in logic functions such as & (bitwise-and) and I (bitwiseor).
High-level programming language constructs such as condition- als, case statements,
and loops are available in the language.
ABOUT SYNTHESIS
by wires. In such a case, a second program called the RTL module builder is
necessary. The purpose of this builder is to build, or acquire from a library of predefined
components, each of the required RTL blocks in the user-specified target technology.
Figure 5.2 shows the basic elements of Verilog HDL and the elements used in hardware. A
mapping mechanism or a construction mechanism has to be provided that translates the
Verilog HDL elements into their corresponding hardware elements.
Because of these problems, different synthesis systems support different Verilog HDL
subsets for synthesis. Since there is no single object in Verilog HDL that means a latch or a
flip-flop, each synthesis system may provide different mechanisms to model a flip-flop or a
latch. Each synthesis system therefore defines its own subset of Verilog HDL including its
own modeling style.
Figure 5.4 shows a circuit that is described in many different ways using Verilog
HDL. A synthesis system that supports synthesis of styles A and B may not support that of
style C. This implies that typically synthesis models are non-portable across different
synthesis models are non-portable across different synthesis systems. Style D may not be
synth & sizable at all.