Carnegie Mellon University

CARNEGIE INSTITUDE of TECHNOLOGY

THESIS
SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

A 7-Bit 2.5GS/sec Time-Interleaved C-2C SAR ADC

For 60GHz Multi-Band OFDM-Based Receivers
ERKAN ALPMAN
ACCEPTED BY THE DEPARTMENT OF

ELECTRICAL and COMPUTER ENGINEERING

___________________________________________________________
ADVISOR, MAJOR PROFESSOR

_______________________
DATE

___________________________________________________________
DEPARMENT HEAD

_______________________
DATE

APPROVED BY THE COLLEGE COUNCIL

___________________________________________________________
DEAN

_______________________
DATE

ABSTRACT

A 7-BIT 2.5GS/sec TIME-I!TERLEAVED C-2C SAR ADC

FOR 60GHz MULTI-BA!D OFDM-BASED RECEIVERS

Alpman, Erkan
Ph.D., Department of Electrical and Computer Engineering
Supervisor: Prof. Dr. L. Richard Carley
August 2009

This thesis presents the design of a 7-bit 2.5GS/s Nyquist Analog-to-Digital Converter
(ADC) in digital 45nm low-power (LP)-CMOS process, intended to be utilized in multiband 60GHz Orthogonal Frequency Division Multiplexing (OFDM) based receivers for
high-speed short-range wireless communication applications. The ADC is implemented
by time-interleaving 16 C-2C Successive-Approximation-Register (SAR) ADCs with a
modified C-2C DAC topology.
Each unit C-2C SAR ADC is composed of a C-2C DAC, a comparator and a digital
controller. The C-2C DAC includes a coarse and a fine radix calibration to mitigate the
parasitic capacitance problem at the intermediate nodes of the DAC and it is also capable
of sampling the input signal without the necessity of an external track-and-hold.. The
comparator is biased with a dynamic biasing scheme to reduce the power dissipation and

ii

its offset is calibrated in the background by only using digital blocks and a low-speed 6bit R-2R DAC.
The mismatches due to time-interleaving are calibrated by including offset, gain and
timing calibrations to the overall converter. Gain and offset calibrations are carried out in
the background by using two extra ADCs which are kept OFF unless the calibration is
ON. Timing calibration is done with a sinusoidal input signal by adjusting on-chip delay
lines to align the clock edges.
The measured ENOB (Effective Number Of Bits) > 6.1b and SFDR (Spur Free Dynamic
Range)< -49dBc for a single C-2C SAR ADC. For the time-interleaved SAR ADC,
ENOB >5.4b, and SFDR > -43dBc up to the Nyquist frequency. The ADC consumes
50mW at 1.1V supply and achieves a Figure-of-Merit (FoM) of 480fJ/conv-step.

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To My Family
and
To The Memory of My Grandparents
Husnu & Ruvide Alpman and Mithat & Leman Erkut

iv

ACK!OWLEDGEME!TS
I would like to express my appreciation and special thanks to my advisor Prof. Dr. L.
Richard Carley for all of his guidance, support, and help throughout the development of
this thesis and during the graduate study.
I also want to thank Hasnain Lakdawala from Intel Corporation for his valuable
suggestions, guidance, and help during my internship at Intel Corporation and also during
the last year of my Ph.D. I am also grateful to my Ph.D. committee members for their
guidance and advices throughout my Ph.D. study. Special thanks to Yorgos Palaskas,
Ashoke Ravi, Ralph Bishop, Miki Moyal, Dale Hackitt, Eshel Gordon, Claudio Jakobson,
Gordon Compton, and other members of Intels MWG and CTG for their help.
I would also like to present my special thanks and deepest gratitude to my friend and
colleague Michael Chen for his friendship, help, and support. I wish to thank Zhenning
Wang and Wei Tai for their friendship and help. Special thanks to Assistant Prof. Dr.
David Ricketts for his suggestions and help and also thanks to the members of CSSI for
creating a friendly study environment and their friendship.
I would like to acknowledge the financial support of the Focus Center for Circuit &
System Solutions (C2S2), one of five research centers funded under the Focus Center
Research Program, a Semiconductor Research Corporation Program.
I am also very grateful to my Intel Parents, Stephanie and Chuck Reynolds, for their
support, help, and friendship during my Ph.D. study.
Last but not least, I wish to express my love and gratitude to my beloved family; for their
understanding and endless love, encouragement and patience through the duration of my
studies and my life.

TABLE of CO!TE!TS

1.

I!TRODUCTIO!..................................................................................................... 1

1.1.

Wireless Communication.................................................................................. 2

1.2.

Modulation Techniques .................................................................................... 4

1.3.

Motivation .......................................................................................................... 5

1.4.

Research Objectives and Thesis Organization ............................................... 8

2.

ADC FU!DAME!TALS ....................................................................................... 11

2.1.

Analog-to-Digital (A/D) Conversion .............................................................. 12

2.2.

Quantization .................................................................................................... 14

2.2.1.

Quantization Error (Noise)............................................................................ 16

2.3.

Sampling........................................................................................................... 21

2.4.

ADC Specifications.......................................................................................... 28

2.4.1.

DC Specifications.......................................................................................... 28

2.4.1.1.

Offset..................................................................................................... 28

2.4.1.2.

Gain Error.............................................................................................. 29

2.4.1.3.

Nonlinearities ........................................................................................ 30

2.4.1.3.1.

Differential Non-Linearity (DNL) ..................................................... 31

2.4.1.3.2.

Integral Non-Linearity (INL) ............................................................. 32

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2.4.1.4.
2.4.2.

3.

Monotonicity ......................................................................................... 34
AC Specifications.......................................................................................... 35

2.4.2.1.

Clock Jitter (Aperture Uncertainty)....................................................... 35

2.4.2.2.

Noise...................................................................................................... 37

2.4.2.3.

SNR and SNDR..................................................................................... 39

2.4.2.4.

Effective Number of Bits (ENOB)........................................................ 40

2.4.2.5.

Spurious Free Dynamic Range (SFDR) ................................................ 40

2.4.2.6.

Bit Error Rate (BER)............................................................................. 41

2.4.2.7.

Figure-of-Merit (FoM) .......................................................................... 41

HIGH-SPEED ADC TOPOLOGIES .................................................................... 42

3.1.

Flash ADCs ...................................................................................................... 43

3.2.

Folding (and Interpolating) ADCs................................................................. 46

3.3.

Subranging (Two-Step) ADCs ....................................................................... 51

3.4.

Pipeline ADCs.................................................................................................. 53

3.5.

Time-Interleaved ADCs.................................................................................. 54

3.6.

State-of-the-Art Performances and Comparison ......................................... 56

4.

SAR ADCS ............................................................................................................... 61

4.1.

Architecture and Operation ........................................................................... 62

4.2.

SAR ADC with Binary-Weighted Capacitive DAC ..................................... 64

4.2.1.

Architecture and Operation ........................................................................... 65

4.2.2.

State-of-the-Art Performance of SAR ADCs with BW DAC....................... 68

4.3.
4.3.1.

SAR ADC with C-2C Capacitive DAC.......................................................... 70

Architecture and Operation of C-2C DAC.................................................... 70

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5.

4.3.2.

SAR ADC with C-2C DAC .......................................................................... 74

4.3.3.

State-of-the-Art Performance of SAR ADCs with C-2C DAC..................... 75

TIME-I!TERLEAVI!G ....................................................................................... 76

5.1.

Time-Interleaving Problems........................................................................... 77

5.2.

Offset Mismatch .............................................................................................. 78

5.3.

Gain Mismatch ................................................................................................ 82

5.4.

Clock Skew....................................................................................................... 87

5.5.

Bandwidth Mismatch...................................................................................... 94

5.6.

Jitter.................................................................................................................. 96

6.

PROPOSED TIME-I!TERLEAVED C-2C SAR ADC ...................................... 99

6.1.

Overview of the Proposed C-2C SAR ADC ................................................ 100

6.2.

Architecture of the Proposed C-2C SAR ADC........................................... 101

6.3.

Operation of the Proposed C-2C SAR ADC............................................... 103

6.4.

Parasitic Capacitance Calibration............................................................... 111

6.4.1.

Coarse Radix Calibration (CRC) ................................................................ 112

6.4.2.

Fine Radix Calibration (FRC) ..................................................................... 113

6.4.3.

CRC and FRC Simulation Results .............................................................. 118

6.4.4.

CRC and FRC Algorithm............................................................................ 120

6.5.

Switch Design................................................................................................. 120

6.5.1.

Reference Voltage Switch Design............................................................... 121

6.5.2.

Input Sampling Switch (Input-aware Boosted Switch)............................... 126

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6.6.

Comparator Design ....................................................................................... 132

6.6.1.

Comparator Architecture............................................................................. 132

6.6.2.

Dynamic Biasing ......................................................................................... 135

6.6.3.

Comparator Offset Background Calibration ............................................... 137

6.7.

Time-Interleaving Topology......................................................................... 140

6.7.1.

Overall Time-Interleaved ADC Architecture.............................................. 140

6.7.2.

Proposed Time-Interleaving Calibration Schemes...................................... 143

6.8.

Reference Voltage Stabilization ................................................................... 145

6.9.

Digital Circuitries and Peripheral Blocks................................................... 148

6.10.

Chip Floor Plan and Layout......................................................................... 151

7.

TEST RESULTS ................................................................................................... 156

7.1.

Test Setup....................................................................................................... 157

7.2.

Measurement Results.................................................................................... 161

8.

7.2.1.

Single C-2C SAR ADC DC and AC Performance ..................................... 161

7.2.2.

Overall Time-Interleaved C-2C SAR ADC Performance........................... 166

CO!CLUSIO!S A!D FUTURE WORK .......................................................... 171

8.1.

Conclusions .................................................................................................... 171

8.2.

Future Works................................................................................................. 175

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LIST of TABLES

Table 2.1: 2-bit quantization and the corresponding analog values .................................. 13
Table 2.2: Resolution vs SQNR for an Ideal ADC ........................................................... 19
Table 3.1: Comparison of high-speed ADCs .................................................................... 59
Table 5.1: Dependence of deterministic mismatch errors on input signal amplitude and
frequency........................................................................................................................... 78
Table 6.1: Target specifications of the proposed ADC..................................................... 99
Table 6.2: Internal node voltages of the C-2C DAC during the reset and input sampling
phase................................................................................................................................ 105
Table 6.3: Internal node voltages of the C-2C DAC during the MSB decision phase. .. 105
Table 6.4: Internal node voltages of the C-2C DAC during the MSB-1 decision phase
when MSB=1. ................................................................................................................. 107
Table 6.5: Internal node voltages of the C-2C DAC during the MSB-1 decision phase
when MSB=0. ................................................................................................................. 108
Table 6.6: Pad assignment of the time-interleaved C-2C SAR ADC ............................ 152
Table 7.1: Power dissipation distribution of the overall ADC........................................ 169

LIST of FIGURES

Figure 1.1: Atmospheric transmittance chart ..................................................................... 6

Figure 1.2: Simplified block diagram of an RF transceiver............................................... 7
Figure 2.1: Analog waveform .......................................................................................... 12
Figure 2.2: Time-discretized waveform........................................................................... 13
Figure 2.3: Final digital waveform................................................................................... 13
Figure 2.4: Digital waveform obtained by a sampling period of T/2 and a 3-bit amplitude
quantization. ...................................................................................................................... 14
Figure 2.5: Transfer functions of a 3-bit quantization example (mid-tread and mid_rise).
........................................................................................................................................... 15
Figure 2.6: Quantization error of a full-scale ramp input. ............................................... 16
Figure 2.7: Quantization error probability density function ............................................ 17
Figure 2.8: Quantization noise spectrum ......................................................................... 20
Figure 2.9: Uniform sampling of a continuous-time signal ............................................. 22
Figure 2.10: Fourier transform of x(t) and y[n]=x(nT) .................................................... 22
Figure 2.11: Ideal reconstruction filter and its time domain waveform........................... 23
Figure 2.12: (a) Different Nyquist Zones (b) Two spectrums resulting in the same output
spectrum if sampled with FS.............................................................................................. 24
Figure 2.13: Sampling with Aliasing ............................................................................... 25
Figure 2.14: Out-band interferer aliasing with the desired signal after sampling............ 25
Figure 2.15: Zero-order hold operation............................................................................ 26
Figure 2.16: Relation between ideal and zero-order hold sampling ................................ 26
Figure 2.17: Spectrum of zero-order hold sampling ........................................................ 27
Figure 2.18: An ideal ADC system .................................................................................. 27
Figure 2.19: Ideal transfer characteristic and the one with offset .................................... 29

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Figure 2.20: Ideal transfer characteristic and the one with gain error ............................. 30
Figure 2.21: Two non-ideal transfer curves ..................................................................... 31
Figure 2.22: (a) Details of DNL (b) DNL plot of an 8-bit converter ............................... 32
Figure 2.23: Endpoint-fit and best-fit methods for INL calculation ................................ 32
Figure 2.24: Non-monotonic transfer characteristic with missing code .......................... 34
Figure 2.25: Clock jitter ................................................................................................... 35
Figure 2.26: a) A simple sampling system b) Equivalent RC network of the sampler c)
Corresponding noise spectrum at the output node when the switch is on. ....................... 38
Figure 2.27: Output spectrum showing the SFDR ........................................................... 40
Figure 3.1: ADC classification based on speed and resolution........................................ 42
Figure 3.2: Schematic of a flash ADC ............................................................................. 43
Figure 3.3: Folding operation........................................................................................... 47
Figure 3.4: a) Real folded signals do not have sharp changes at the folding points

b)

Solution to rounded edge problem in folding operation ................................................... 47

Figure 3.5: Schematic of a folding ADC ......................................................................... 48
Figure 3.6: Interpolation of folded signals....................................................................... 49
Figure 3.7: Input sine wave and 8-times folded output waveform .................................. 50
Figure 3.8: Schematic of a subranging (two-step) ADC.................................................. 51
Figure 3.9: Simplified schematic of a time-interleaved ADC.......................................... 54
Figure 3.10: State-of-the-Art Performance of Flash ADCs [19-36] ................................ 56
Figure 3.11: State-of-the-Art Performance of Folding ADCs [37-44] ............................ 57
Figure 3.12: State-of-the-Art Performance of Subranging and Two-step ADCs [45-53] 58
Figure 3.13: State-of-the-Art Performance of Time-Interleaved ADCs [18, 54-62] ....... 59
Figure 4.1: Block diagram of a SAR ADC ...................................................................... 62
Figure 4.2: a) SAR ADC algorithm for a 3-bit conversion b) Flow chart of SAR ADC
algorithm ........................................................................................................................... 63
Figure 4.3: a) Timing and signal waveforms of a 3-bit SAR ADC b) Detailed timing
diagram of a SAR ADC .................................................................................................... 64
Figure 4.4: Schematic of a SAR ADC with Binary-Weighted Capacitive DAC............. 65

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Figure 4.5: State-of-the-Art Performance of Time-Interleaved SAR ADCs. [55-56, 6062, 64-65] .......................................................................................................................... 69
Figure 4.6: Schematic of an 8-bit two-stage Binary-Weighted Capacitive DAC ............ 70
Figure 4.7: Schematic an ideal C-2C DAC...................................................................... 71
Figure 4.8: Parasitic capacitance problem in C-2C DACs............................................... 72
Figure 4.9: Inclusion of input sampling switches to the C-2C DAC ............................... 74
Figure 5.1: Two time-interleaved ADCs with different offsets ....................................... 79
Figure 5.2: Output waveform of a two-channel time-interleaved ADC with different unit
ADC offset and the corresponding error voltage .............................................................. 80
Figure 5.3: Simulated output spectrum of the Simulink model of two-channel timeinterleaved ADC with different offsets ............................................................................. 80
Figure 5.4: Simulated output spectrum of the Simulink model of a four-channel timeinterleaved ADC with different offsets ............................................................................. 81
Figure 5.5: Two time-interleaved ADCs with different gains ......................................... 83
Figure 5.6: Output waveform of a two-channel time-interleaved ADC with different unit
ADC gains and the corresponding error voltage............................................................... 84
Figure 5.7: Output spectrum of the same two-channel time-interleaved ADC with
different unit ADC gains ................................................................................................... 85
Figure 5.8: Output spectrum of a four-channel time-interleaved ADC with different unit
ADC gains ......................................................................................................................... 86
Figure 5.9: a) Perfectly aligned clock phases of a 4-channel time-interleaved ADC b)
Clock phases with clock skew problem ............................................................................ 88
Figure 5.10: Two time-interleaved ADCs with clock skew problem .............................. 89
Figure 5.11: Output waveform of a two-channel time-interleaved ADC with clock skew
problem and the corresponding error voltage ................................................................... 91
Figure 5.12: Output spectrum of a two-channel time-interleaved ADC with different
clock skew problem........................................................................................................... 92
Figure 5.13: Output spectrum of a four-channel time-interleaved ADC with clock skew
problem.............................................................................................................................. 93
Figure 5.14: Two time-interleaved ADCs with different T&H bandwidths.................... 95

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Figure 5.15: SNR versus jitter and input frequency characteristic of an ideal 7-bit ADC
........................................................................................................................................... 97
Figure 5.16: SNR versus jitter an ideal 7-bit ADC with different input frequencies (2-D
version of Figure 5.15) ...................................................................................................... 98
Figure 6.1: Simplified schematic of the proposed C-2C DAC ...................................... 101
Figure 6.2: Effect of upper switches .............................................................................. 102
Figure 6.3: a) C-2C DAC responsible for charge addition to the output b) C-2C DAC
responsible for charge removal from the output ............................................................. 104
Figure 6.4: Reset and input sampling phase of the proposed C-2C DAC...................... 105
Figure 6.5: MSB decision phase of the proposed C-2C DAC ....................................... 106
Figure 6.6: MSB-1 decision phase of the proposed C-2C DAC when MSB=1............. 106
Figure 6.7: MSB-1 decision phase of the proposed C-2C DAC when MSB=0............. 107
Figure 6.8: Timing of the proposed SAR ADC according to the clock signal .............. 109
Figure 6.9: Switch control signal timing diagram of the C-2C SAR ADC.................... 110
Figure 6.10: Three 7-bit ADC transfer characteristics with different radixes based on the
parasitic capacitance values at the intermediate nodes. .................................................. 111
Figure 6.11: Cbanks used for Coarse Radix Calibration................................................ 112
Figure 6.12: Different capacitance values Cbank can take ............................................ 113
Figure 6.13: Fine Radix Calibration of MSB-1 during MSB decision .......................... 114
Figure 6.14: Residual error after CRC and FRC correction by using a single calibration
voltage ............................................................................................................................. 116
Figure 6.15: Actual timing diagram of the SAR ADC................................................... 117
Figure 6.16: Simulation result showing the transfer characteristics of a 7-bit C-2C SAR
ADC model including the parasitic capacitances (0.9*CU/2 with 10% variability) before
radix calibration............................................................................................................... 118
Figure 6.17: Simulated transfer characteristics of a 7-bit C-2C SAR ADC model
including the parasitic capacitances (0.9*CU/2, 10% variability) after radix calibration.
......................................................................................................................................... 119
Figure 6.18: Simulated INL before and after radix calibrations .................................... 119
Figure 6.19: Simulated DNL before and after radix calibrations................................... 119

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Figure 6.20: Simulated on-resistance of a wide transmission gate with respect to the
input voltage.................................................................................................................... 121
Figure 6.21: Schematic of the boosted switch of the maximum reference voltage ....... 122
Figure 6.22: a) Schematic of the clock booster b) Operation of the clock booster........ 122
Figure 6.23: Operation of the boosted switch ................................................................ 123
Figure 6.24: Floating switches at the intermediate nodes and their parasitic capacitances
......................................................................................................................................... 125
Figure 6.25: Schematic of the conventional bootstrapped switch.................................. 126
Figure 6.26: Schematic of the proposed input-aware boosted switch............................ 128
Figure 6.27: Simulated on-resistance of the input sampling boosted switch for the entire
input range....................................................................................................................... 129
Figure 6.28: Comparison of the simulated on-resistances of the same size boosted and
bootstrapped switches with the same hold capacitor. ..................................................... 130
Figure 6.29: Gate-to-source voltage of the switch transistor of the bootstrapped switch
with the same size as the boosted switch for the entire input range................................ 131
Figure 6.30: Responses at the gate nodes of the conventional bootstrapped switch and the
proposed input-aware boosted switch ............................................................................. 131
Figure 6.31: Schematic of the comparator used in the proposed C-2C SAR ADC along
with the control signals. .................................................................................................. 132
Figure 6.32: Regeneration time / Regeneration Time Constant (tr/) with respect to the
metastability error probability......................................................................................... 134
Figure 6.33: Schematic of the dynamic biasing architecture ......................................... 136
Figure 6.34: Simulated tail current of the preamplifier with respect to the differential
input voltage.................................................................................................................... 137
Figure 6.35: Proposed comparator offset background calibration scheme .................... 138
Figure 6.36: Timing diagram of an 8x time-interleaved 7-bit SAR ADCs.................... 140
Figure 6.37: Timing diagram of the proposed 16x time-interleaved 7-bit SAR ADCs. 141
Figure 6.38: Simplified schematic of the overall time-interleaved ADC ...................... 142
Figure 6.39: Small timing error between the extra ADC and the ADC under calibration.
Input can be approximated as linear within this small time interval............................... 144

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Figure 6.40: Schematic of the on-chip reference voltage distribution for an ADC bank
......................................................................................................................................... 146
Figure 6.41: Simulated reference voltage recovery comparison of the proposed
distribution and decoupling capacitance method ............................................................ 147
Figure 6.42: a) Positive edge-triggered TSPC D flip-flop b) Positive edge triggered
TSPC RS flip-flop ........................................................................................................... 148
Figure 6.43: State machine outputs and their corresponding meanings......................... 149
Figure 6.44: Schematic of the R-2R DAC ..................................................................... 149
Figure 6.45: Simplified schematic of the delay line ...................................................... 150
Figure 6.46: Coarse delay line ....................................................................................... 150
Figure 6.47: Fine delay line ........................................................................................... 151
Figure 6.48: a) Floor plan of the C-2C SAR ADC b) Layout of the C-2C SAR ADC.. 151
Figure 6.49: Floor plan of the overall time-interleaved C-2C SAR ADC ..................... 153
Figure 6.50: Layout of the overall time-interleaved C-2C SAR ADC .......................... 154
Figure 6.51: Bonding diagram of the proposed ADC .................................................... 155
Figure 7.1: a) PCB with a socket b)PCB with package on-board soldering .................. 158
Figure 7.2: Simplified schematic of the test setup. ........................................................ 159
Figure 7.3: a) Overall test setup b) Closer view of the test board.................................. 160
Figure 7.4: Measured transfer characteristic of the C-2C SAR ADC before and after
radix calibration............................................................................................................... 161
Figure 7.5: Measured DNL and INL plots of the proposed ADC before and after radix
calibration........................................................................................................................ 162
Figure 7.6: Measured output spectrums (1M-point FFT) showing the SNDR and SFDR
values of a single C-2C SAR ADC when the input frequency is 5.24MHz and 68.3MHz.
......................................................................................................................................... 163
Figure 7.7: Measured SFDR and SNDR with input frequency of a single C-2C SAR
ADC in the Nyquist zone ................................................................................................ 164
Figure 7.8: Measured output spectrum (1M-point FFT) of a single C-2C SAR ADC
when the input and clock frequencies are 1.29GHz and 1.25GHz, respectively. ........... 165

xvi

Figure 7.9: Measured input amplitude versus SNDR characteristic of the single C-2C
SAR ADC........................................................................................................................ 166
Figure 7.10: Measured output spectrum (1M-point FFT) of the time-interleaved SAR
ADC before and after mismatch calibrations, when the input frequency is 940.5MHz at
full sampling speed.......................................................................................................... 167
Figure 7.11: Measured SFDR and SNDR with input frequency of the time-interleaved
SAR ADC and output spectrum (1M point FFT) for Fin=1.1GHz for a sampling rate of
2.5GS/s ............................................................................................................................ 168
Figure 7.12: Power distribution of the unit SAR ADC and the overall converter ........ 169
Figure 7.13: Die photo and performance summary ...................................................... 170

xvii

CHAPTER I

1. I!TRODUCTIO!
Analog-to-digital conversion is the process of converting continuous quantities into
discrete numbers, and we carry out this process many times in our daily life. Even when
telling someone the time or the temperature, we take a continuous quantity and convert it
to discrete numbers. As the main focus here is an electrical implementation, this process
will be restricted to the conversion of continuous (in terms of time and amplitude)
electrical signals into digital codes.

The analog-to-digital converter (ADC) is the

electronic device which makes this conversion.

ADCs have been worked on, designed, and utilized since Claude Elwood Shannon
founded digital circuit design theory by demonstrating the electrical application of
Boolean algebra in his Masters thesis [1] (claimed to be the most important Masters
thesis of all time). Today, every mixed-signal digital signal processing (DSP) system
with an analog input, such as audio and speech signal processors, sonar and radar signal
processing systems, sensor arrays, wired/wireless communication systems, biomedical
systems, seismic data processors, spectral estimation, statistical signal processing
systems, etc., uses an ADC.
As the specifications and constraints vary significantly for each application, many
different analog-to-digital conversion techniques have been developed.

The most

common ones are: Flash, Folding (and Interpolating), Pipeline, Subranging (or TwoStep), Successive Approximation Register (SAR), Sigma-Delta, Integrating, Cyclic (or
Algorithmic), and Time-Interleaved converters. Each of these ADC architectures has

benefits or disadvantages in terms of speed, power dissipation, resolution, accuracy, input

bandwidth, complexity, scalability, clock latency, linearity etc., making them suit well in
particular applications. For instance, almost all digital voltmeters use an integrating ADC
while high speed sampling oscilloscopes include time-interleaved converters and many
audio systems have a sigma-delta ADC.
Wireless communication is one of the most popular and demanding areas in which ADCs
are widely used, as all receivers working with analog inputs followed by a digital signal
processing system has to have a converter inside. Even in this small ADC application
space, target specifications may change considerably resulting in distinct ADC topologies
to be used. As the main focus of this thesis covers an ADC design intended to be utilized
in a wireless communication system, the next section gives brief information on this
topic.

1.1. Wireless Communication

Wireless communication is the transfer of meaningful data (information) over a distance
without the use of physical wires and today, it is one of the most vibrant areas in the field
of communication. While it has been studied since the 60s, the past decade has seen a
surge of research in this area due to several factors. First, there has been an explosive
increase in demand for wireless connectivity, so far driven mainly by cellular telephony
but expected to be soon eclipsed by wireless data applications. Second, the dramatic
progress in Very Large Scale Integration (VLSI) technology has enabled the
implementation of complicated digital signal processing algorithms and coding
techniques enabling the mobile devices to employ more efficient and complex protocols.
Moreover, the success of second-generation digital wireless standards (IS-95 Code
Division Multiple Access CDMA in particular) provides a solid demonstration that
good ideas from communication theory can have a significant impact in practice [2].

The initial demonstrations of wireless communication go back to late 1890s (Marconis

wireless telegraphy in 1897) and early 1900s (radio reception across Atlantic Ocean in
1901). Within this almost hundred-year period, many types of wireless systems have
flourished while some of them have already disappeared or started losing popularity. For
example, television transmission, in its early days, was broadcast by wireless radio
transmitters, which are increasingly being replaced by cable transmission now. On the
other hand, in telephony, cellular technology is partially replacing the use of the wired
telephone network [2].
Wireless communication can be carried out in many different ways and many different
types of wireless systems can be listed. Cellular networks are of great interest but there
are also the broadcast systems such as AM radio, FM radio, TV and paging systems. In
addition, there are wireless LANs (local area networks) designed to connect laptops and
other portable devices in the local area network with very high data rates. The major
standards of wireless LANs are the IEEE 802.11 family. Furthermore, there are smallerscale standards like Bluetooth or ultra-wideband (UWB) communication whose purpose
is to minimize cabling in an office and simplify transfers between the office and handheld devices. Systems like ad hoc networks and RFID as well as WiMAX can be also
included here [2]. As seen, wireless communication can be carried out in a very short
range (Bluetooth) or in thousands of kilometers (satellites) with very high data rates
(LANs) or with a relatively low data rate (AM radio).
Almost all of the wireless standards are using certain frequency bands in the spectrum
pre-defined for them. As the usage of frequency bands should have a limitation in order
to sustain the communication of many clients at the same time, frequency allocation maps
(one for the United States as of 2003 can be found in [3]) are regulated by the
governments.
In wireless communication, in order to embed a signal into a carrier, the signal has to be
modulated. The next section gives on overview on different modulation techniques.

1.2. Modulation Techniques

Modulation techniques can be classified into two groups: 1) Analog 2) Digital.
Traditional analog modulations include amplitude modulation (AM) and frequency
modulation (FM). In digital modulations, binary 1s and 0s are embedded in the carrier
frequency by changing its amplitude, frequency, or phase.

Subsequently, digital

modulations (keying techniques) can be amplitude shift keying (ASK), frequency shift
keying (FSK), and phase shift keying (PSK) [4].
Quadrature amplitude modulation (QAM) is both an analog and a digital modulation
scheme. It conveys two analog message signals, or two digital bit streams, by changing
(modulating) the amplitudes of the two carrier waves, using the ASK modulation scheme
or AM scheme. These two waves, usually sinusoids, are out of phase with each other by
90 and are thus quadrature carriers.

The modulated waves are summed, and the

resulting waveform is a combination of both PSK and ASK in the digital domain or PM
and AM in the analog domain. In the digital case, a finite number of at least two phases
and at least two amplitudes are used [5].
Some new modulation techniques include Gaussian minimum shift keying (GMSK) and
differential quadrature phase shift keying (DQPSK). GMSK is a type of FSK modulation
that uses continuous phase modulation to avoid abrupt changes and it is used in GSM
systems. DQPSK is a type of phase modulation, which defines four rather than two
phases. It is used in TDMA (time division multiplexing access) systems in the United
States [4].
A significant drawback of traditional radio frequency (RF) systems is that they are quite
vulnerable to sources of interference. Spread spectrum modulation techniques resolve the
problem by spreading the information over a broad frequency range, and these techniques
are very resistant to interference. These techniques are used in code-division multiple

access (CDMA) [4]. CDMA uses codes from a nearly orthogonal code set. Each data bit
is chipped by multiplication with the code. Each user is assigned a unique code from the
code set, so the resulting chipped signals are also nearly orthogonal. Demodulation is
performed by multiplication with the same code set, and it yields a signal only if the
particular code matches that used in the original modulation. Due to orthogonality, data
streams originating from multiplication with the other codes only produce noise-like
outputs [6].
Recently, attempts to push ever more bits per second per hertz through a channel have
motivated wireless designers to implement orthogonal frequency-division multiplexing
(OFDM). In this method, a collection of orthogonal carriers is used instead of the usual
single carrier.

Each of these carriers is separately modulated with a conventional

modulation scheme (such as quadrature-amplitude modulation or PSK), and the

collection of the modulated carriers is transmitted as an ensemble. Aside from lots of bits
per unit time, use of OFDM can facilitate adaptive response to changing channel
conditions. For example, if one part of the spectrum drops out (for instance, due to
fading) the other carriers can compensate.

If the carriers are distributed over a

sufficiently wide spectrum, then the probability of a failed communication can be made
very small. In effect, OFDM embeds a measure of frequency diversity. Todays highestspeed WLAN standards, 802.11a and 802.11g, use OFDM to provide up to 54 Mb/s peak
data rates [6].

1.3. Motivation
The main motivation of the work carried out in this thesis is to design a medium
resolution (7-bit) high speed (2.5GS/sec) Nyquist ADC which is intended to be utilized in
a 60GHz Multi-band OFDM-based receiver.

As seen on the chart given in Figure 1.11, the atmospheric transmittance around 60 GHz
(5mm wavelength) is very poor and the band around this frequency is very hard to use for

Atmospheric
Opacity

long-range wireless communication applications.

Figure 1.1: Atmospheric transmittance chart

Due to high opacity of the atmosphere (i.e. high oxygen absorption), National
Telecommunications and Information Administration (NTIA) - Office of Spectrum
Management (OSM) designated 59-64GHz frequency band for unlicensed devices [3].
As the band is open for everybody to use and todays CMOS technologies have managed
to operate at those high frequencies, the popularity of this band among wireless designers
has increased recently. Although not suitable for long-range applications, this band can
be used for short distance, very high bit-rate (Multi Gb/s) wireless communication
systems. Actually, poor atmospheric transmittance is a beneficial property for short1

http://mc2.gulf-pixels.com/wp-content/uploads/2009/07/Atmospheric-electromagnetic-transmittance-or-

opacity.jpg

distance applications as it keeps the coverage area of transmitters small and enables the
operation of different communication links among many closely located devices without
interfering with each other.
The mentioned 60GHz Multi-band OFDM-based wireless system has been studied by
Intel Corporation - Communications Circuits Laboratory for the mentioned short-range
high data-rate communication applications and the proposed ADC in this thesis was
designed for this system. Figure 1.2 presents a simplified block diagram of an RF
transceiver architecture. The receiver part has a front-end (Low Noise Amplifier) LNA
followed by a mixer and a filter. The filter output is fed to an ADC for DSP.

Figure 1.2: Simplified block diagram of an RF transceiver

Due to complex DSP and low-power constraints, the digital baseband is generally
designed on a low-leakage, high-VT low-power (LP) CMOS process and for this design,
a 45nm LP digital CMOS process was selected. As it is extremely hard to implement the
RF-IC chip (shown with the red dashed line in Figure 1.2) operating at 60 GHz by using
this 45nm digital CMOS process, a more sophisticated process with better analog
performance might be preferable. The ADC can be also put in the RF-IC die as this
sophisticated process will ease the ADC design but in this case a very high speed
communication link has to be built between the RF-IC chip and the digital baseband chip.
This is also very hard and not cost efficient. Hence, the ADC is often included on the

digital baseband chip, but this makes the design of high speed converters challenging.
Due to these challenges, the resolution of the ADC is generally kept low in order to meet
the target speed but this limits the performance of the RF channel. Consequently, simple
modulation schemes like ASK, FSK, or PSK are utilized, but this keeps the bit rate of the
channel low.
In this design, while holding the speed and the bandwidth at the desired level (2.5GS/sec
with Nyquist bandwidth) the resolution was targeted to be pushed as much as possible (7
bits) in order to improve the data rate of the RF channel. This way, a more complex
modulation scheme like QAM-16 can be used. But the ADC should still be in the digital
baseband chip, forcing the converter to be digital-friendly and scalable. In addition, it
should also be power-efficient (Figure of Merit (FoM) less than 1pJ/conv-step).

1.4. Research Objectives and Thesis Organization

The goal of this research is to develop the ADC design mentioned in Section 1.3. The
specific objectives can be listed as:
1) Investigation of the design constraints and the target specifications of the ADC in
detail. A comprehensive literature search has to be performed to observe the state-of-theart performances of different ADC topologies that can be utilized for the application of
interest.
2) Based on the literature search, a good design choice has to be made to pick the right
ADC topology. This ADC topology should be able to meet all the specifications. These
specifications can be briefly listed as: 1) around 3GS/sec sampling rate with Nyquist
bandwidth, 2) ENOB greater than 5 bits over the entire bandwidth, 3) FoM less than
1pJ/conv-step. If the traditional topology can not achieve the desired performance, novel

modifications have to be carried out. The design should reflect and even push forward
the state-of-the-art performance.
3) Future trends in the CMOS technology and scalability have to be taken into account.
The proposed topology should be able to keep its functionality even in future generations
of the system implemented in new technologies.
3) Effective, efficient and easily implementable calibration schemes should be applied
where necessary in order to enhance the performance.
3) The design has to be programmable and test-friendly. Testability and observability
have to be considered as much as possible.
4) A dedicated test-setup should be prepared. All the target specifications have to be
measured and the functionality of all the blocks should be verified. If necessary, more
than one test-setup has to be designed, such as one for initial functionality verification
and one for the actual performance verification.
The organization of the thesis is as follows:
Chapter II explains the fundamentals of ADCs. Firstly, the principles of analog to digital
conversion are presented by covering the quantization and the sampling in detail. Then,
DC (static) and AC (dynamic) specifications of ADCs used for measuring the
performance of converters are discussed thoroughly.
Chapter III makes a comprehensive discussion on high-speed ADC topologies that can be
utilized for the proposed ADC design. Flash, Folding (and Interpolating), Subranging
(and Two-step), Pipeline, and Time-Interleaved ADCs are covered in this chapter,
including their operating principles, advantages and disadvantages, as well as the state-

of-the-art performances. A comparison among these converters is also carried out at the
end of the chapter.
Chapter IV gives detailed information on SAR ADCs. Firstly, the general operation and
the SAR algorithm are explained. Then, both the traditional SAR ADCs with binaryweighted capacitive DACs and those with C-2C DACs are covered thoroughly.

performance comparison is also carried out to make a proper design choice for the
application of interest.
Chapter V analyzes time-interleaving and problems associated with it. Each problem is
discussed by going through mathematical analyses and MATLAB simulation results.
Possible detection and calibration schemes are also explained for each time-interleaving
problem.
Chapter VI presents the proposed ADC architecture which is based on 16 times TimeInterleaved C-2C SAR ADCs. The unit ADC topology, its operation, blocks comprising
the unit ADC, and the calibration schemes utilized in it are explained. In addition, the
overall time-interleaved ADC architecture, operation, and calibration schemes are
covered.
Chapter VII gives the measurement results of the fabricated ADC. Measurements on
both DC and AC specifications are presented including the unit ADC and the overall
ADC performance.
Finally, Chapter VIII concludes this research work and gives a list of possible future
works related with this study.

10

CHAPTER II

2. ADC FU!DAME!TALS
In the real world, almost every signal is an analog signal. These are continuous-time and
continuous-amplitude signals with no constraint on their amplitude and timing.
Basically, an analog signal can take any value at any particular time.
Signal processing can be performed in the analog domain by using these analog signals
directly, without going through an analog-to-digital conversion. However, analog signal
processing requires high-performance, reliable, and reproducible analog designs which
can be extremely difficult, power-hungry, and inefficient especially in new CMOS
technologies. The achievements in the digital world and the trends in the technology
scaling make digital signal processing a powerful, efficient, and cheap tool. Moreover,
computer-aided design tools like synthesizers make these designs easier and less timeconsuming in a more reliable and reproducible way. Consequently, manipulation and
storage of data in the digital domain is a better approach than carrying out everything in
the analog domain. As a result, analog-to-digital converters play an essential role in
almost all signal processing applications.
In this chapter, fundamentals of analog-to-digital conversion are presented. Section 2.1
makes an introduction on A/D conversion and Section 2.2 follows it by explaining the
details of quantization. Section 2.3 covers sampling thoroughly and finally Section 2.4
presents the most common DC and AC specifications of ADCs.

11

2.1. Analog-to-Digital (A/D) Conversion

A digital signal is discrete in terms of both the amplitude and the time. Thus, two main
functions are necessary to obtain a digital waveform:
1) Sampling (To achieve the Discrete Time)
2) Quantization (To achieve the Discrete Amplitude)
In order to show the A/D conversion in an example, consider the simple analog
waveform shown in Figure 1.1.

Figure 2.1: Analog waveform

Initially, lets assume that there is no amplitude quantization and apply sampling with a
sampling period of T. In this case, the time is discretized and the signal can update its
value only at integer multiples of T. Figure 2.2 shows the resulting waveform after this
operation. When the time is equal to an integer multiple of T, the sampled waveform is
equal to the value of the analog signal at that moment and the value stays constant till the
next multiple of T comes.

It can be easily seen that the resulting waveform only

resembles the actual analog signal and there might be an information loss. This can be
tolerable depending on the sampling period and the bandwidth of the analog signal. This
issue is discussed in Section 2.3 in details.

12

Figure 2.2: Time-discretized waveform

The next step is the amplitude quantization. In order to do that, the quantization levels
should be defined first. For this simple example, lets assume a 2-bit quantization as
shown in Table 2.1. Finally, Figure 2.3 presents the digital waveform after this 2-bit
amplitude quantization operation.
Table 2.1: 2-bit quantization and the corresponding analog values
Analog Value

Digital Word

Any value between 0 and 1

00

Any value between 1 and 2

01

Any value between 2 and 3

10

Any value between 3 and 4

11

Figure 2.3: Final digital waveform

13

Similarly, we have an additional information loss due to the quantization and it depends
on the application to figure out whether it is acceptable or not. It can be easily observed
that the accuracy of digitization can be improved by reducing the sampling period and
increasing the number of bits in the quantization process. In order to illustrate this,
Figure 2.4 shows the same analog signal digitized by utilizing a sampling period of T/2
and a 3-bit amplitude quantization. The improvement can easily be observed from the
final digitized data.

Figure 2.4: Digital waveform obtained by a sampling period of T/2 and a 3-bit
amplitude quantization.
As seen, the main functions of an A/D conversion are quantization and sampling. In the
next sections, these two concepts are discussed in detail.

2.2. Quantization
Quantization is simply the procedure of constraining something from a continuous set of
values (such as the real numbers) to a discrete set (such as the integers). In the jargon of
signal processing, it is the process of approximating a signal with a continuous range of
values by a relatively small set of discrete steps.

Figure 2.5 gives two different

implementations of a 3-bit binary quantization example where in both cases, the analog
input with a continuous range from zero to FS (Full Scale) is quantized to a set of 8(=23)

14

different steps [7].

In either implementation, the step size is equal to the Least

Significant Bit (LSB) = FS/2N where N is the number of bits in the digital word and FS is
the Full Scale of the analog input. The mid-tread implementation makes step transitions
in between consecutive k*FS/2Ns, k=0, 1, 2, , 7 and the mid-rise case makes the
transitions exactly at k*FS/2N, k=1, 2, , 7. These two implementations give slightly
different results [8] but the general idea is the same, and similar implementations can also
be shown with negative inputs as well.

Figure 2.5: Transfer functions of a 3-bit quantization example (mid-tread and

mid_rise).
The reverse conversion (digital-to-analog) can also be carried out easily. Each bit in the
digital output has a certain weight and the digital word can be converted back to an
analog value as long as the analog value corresponding to the LSB is known. If it is
assumed that the mid-points in the steps of the transfer function are the corresponding
analog values of the digital words, the analog value for the mid-tread and mid-rise cases
can be expressed as:
Mid-Tread: analog = LSB(b12N-1+ b22N-2+ bN-121+ bN20)

15

Eq. 2.1

Mid-Rise: analog = LSB(b12N-1+ b22N-2+ bN-121+ bN20)+LSB/2

Eq. 2.2

It should be noted that analog can only take discrete values (ideal digital-to-analog
conversion), however the range of the analog input is continuous. For instance, if the
mid-rise implementation is considered, it can be seen that any analog value between FS/8
and FS/4 is considered as 001, and the corresponding analog value is always 3*FS/16.
Thus, there exists an error and analog can be expressed as:
analog = Vanalog+Qerror

Eq. 2.3

where Qerror stands for the quantization error. Quantization error (it will be considered as
noise later) is a fundamental limit due to restricting the signal to a certain number of
discrete steps and it is irreversible. It becomes zero only when the number of bits goes to
infinity. The next section gives detailed information on this phenomenon.

2.2.1.

Quantization Error (!oise)

Quantization error can be extracted from Eq. 2.3 by subtracting Vanalog from analog. It
can easily be figured out that the error is always limited to LSB for an ideal ADC. If
the analog input is swept from 0 to FS, the quantization error of a 3-bit converter will
look like a saw-tooth waveform as shown in Figure 2.6.

7*FS/8
3*FS/4
5*FS/8
FS/2
3*FS/8
FS/4
FS/8

Figure 2.6: Quantization error of a full-scale ramp input.

16

The waveform is periodic within the signal range (0-FS) and a single period can be used
to extract the rms value. Within this single period, the waveform can be expressed as
(given in Figure 2.6 on the right):

Qerror=-x,

-q/2<x<q/2 & q=LSB

Eq. 2.4

Thus, the rms value of the error can be extracted as:

q/2

e =

1
( x )2 dx =

q q / 2

1 x3
q 3

q/2

=
q / 2

q
1 q3
=
q 12
12

Eq.
2.5

As expected, the higher the resolution, the smaller the error and it becomes zero only
when q=LSB goes to zero which corresponds to infinite resolution.

Consequently,

quantization error is a fundamental limit for all A/D converters and it is inevitable.
The approach above takes the quantization error as a deterministic saw-tooth waveform,
since the input is ramped linearly from 0 to FS. A more general approach can be deduced
by using random variables. Assuming that over a long period of time all levels of
uncertainty within the quantization region, Vanalog+Qerror, appear the same number of
times, a uniform probability density function over the interval q/2 to q/2 can be defined
as presented in Figure 2.7 [9].

Figure 2.7: Quantization error probability density function

On this assumption, the mean-square value of will be:

17

( )

q/2

q2
1
2
=

=
dx
q q/ 2
12

Eq. 2.6

where E(.) is the statistical expectation. Similarly, the rms quantization error can be
calculated as q/12. Note that, both the deterministic and the stochastic approaches give
the same result due to the assumption of uniform distribution.

Fortunately, this

assumption is fairly correct and as explained in [10], the quantization noise (it is better to
refer Qerror as noise) is approximately Gaussian and spread more or less uniformly over
the Nyquist bandwidth (= from DC to fS/2, where fS is the sampling frequency of the
converter).
As an important point on the quantization noise discussion so far, the key assumption
here is the input signal and the quantization noise are uncorrelated.

Under certain

conditions where the sampling clock and the input signal are harmonically related, then
the quantization error will become correlated with the input and the energy will be
concentrated at the harmonics of the signal. However, the rms value will still remain
approximately as q/12 [11].
Since, the energy possessed by the quantization noise within the Nyquist band is known,
the theoretical Signal-to-Noise Ratio (SNR) of an ideal converter can be extracted by
assuming a full-scale input sine wave:

FS
2. q
Input =
sin( wt )
sin( wt ) =
2
2

Eq. 2.7

Where N is the resolution of the converter and q=LSB. Therefore, the rms value of the
input signal is:

Input RMS =

2. q
2 2

18

Eq. 2.8

Consequently, the SNR can be calculated from:

Input RMS
S.R = 20 log10
Q
.OISE _ RMS

Eq. 2.9

which gives:

2. q

2. q

2
2
2
2

= 20 log10 3 2 .
S.R = 20 log10
= 20 log10

2
q

12
12

Eq. 2.10

The final expression becomes simply 6.02*N+1.76 dB over the Nyquist band (from DC
to fS/2). This expression is generally referred as the SQNR (Signal-to-QuantizationNoise Ratio) since it only takes into account the quantization noise. Table 2.1 lists the
resolution and the corresponding SQNR values of an ideal converter.

Table 2.2: Resolution vs SQNR for an Ideal ADC

Resolution

SQNR (dB)

Resolution

SQNR (dB)

Resolution

SQNR (dB)

7.78

31.86

55.94

13.8

37.88

10

61.96

19.82

43.9

11

67.98

25.84

49.92

12

74.00

As seen, the SQNR analysis carried out above is done over the entire Nyquist band.
However, the desired signal bandwidth may occupy only a fraction of it. In this case, the
effective quantization noise falling into the band of interest will be smaller. As the
quantization noise outside the signal bandwidth can be filtered out without deteriorating
the desired signal, the SQNR can be improved.

19

As mentioned before, quantization noise is uniform across the Nyquist band and the
mean-square value is q2/12. Consequently, the single-sided spectrum of the quantization
noise can be drawn as shown in Figure 2.8.

Figure 2.8: Quantization noise spectrum

If the bandwidth of the desired signal, BW, is only a fraction of FS/2, then the
quantization noise power falling into the signal bandwidth will be scaled by the
oversampling ratio (OSR):

OSR =

FS
2 BW

Eq. 2.11

As a result, the SQNR expression given in Eq. 2.10 can be updated as:

fS
SQ.R = 6.02 . + 1.76dB + 10 log10

2 BW

Eq. 2.12

It is seen that the smaller the signal bandwidth, the better the SQNR. As a quick
reference, a 0.5-bit improvement can be achieved with each doubling in OSR. This
feature constitutes one of the fundamentals of oversampling ADCs in which high OSRs
are used to improve the resolution.

However, much better improvements in the

resolution can be seen in sigma-delta ADCs where noise shaping is done using a
feedback system.

20

2.3. Sampling
Sampling is the fundamental operation to move a continuous-time waveform into
discrete-time domain.

However, before going into the details of sampling, it is

convenient to cover the representation of continuous and discrete-time signals in time and
frequency domains.
Continuous-time signals can be represented in the frequency domain in terms of their
Fourier Transform (FT) as:
x(t ) X ( F )

X (F ) =

x(t )e

j 2Ft

dt

Eq. 2.13

x(t ) =

X ( F )e

j 2Ft

dF

Similarly, discrete-time signals are represented by their discrete-time Fourier Transform

(DTFT) as:
x[n ] X ( f )

X ( f ) = x[n]e j 2fn

x[n ] =

Eq. 2.14

1/ 2

X ( f )e

j 2fn

df

1 / 2

A discrete-time signal can be constructed by uniformly sampling a continuous-time

signal at T-spaced time intervals. Ideally, this yields a sequence of impulses whose
amplitudes are equal to the amplitude of the signal at the sampling times as shown in
Figure 2.9.

21

Figure 2.9: Uniform sampling of a continuous-time signal

Mathematically, this can be expressed as:
y[n ] = x(nT ) = x(t ) (t nT )

Eq. 2.15

Keeping in mind that the Fourier transform of an impulse train can be written as:

(t nT )
n

2
T

( n ),
S

S =

2
T

Eq. 2.16

and multiplication in the time domain is equivalent to convolution in the frequency

domain, the Fourier transform of the resulting sampled sequence y[n] is found as given in
Eq. 2.17, which is also visualized in Figure 2.10.

y[n ] = x(t ) (t nT ) Y (F ) =
n

1
X ( n S )
T n

Figure 2.10: Fourier transform of x(t) and y[n]=x(nT)

22

Eq. 2.17

This analysis shows one of the most important phenomena of the sampling theory, called
the Nyquist bandwidth. By observing Figure 2.10, it can easily be shown that the original
spectrum of the input signal, x(t), can be totally preserved as long as the following
criterion holds:
B FS B 2 B FS

Eq. 2.18

In other words, the sampling frequency should be at least twice the bandwidth of the
input signal. In this case, by using an appropriate filter, the original signal, x(t), can be
reconstructed out of y[n]. Thus, the sampling process is reversible. Figure 2.11 shows
the ideal reconstruction filter impulse response whose time domain expression can be
written as:

h(t ) = Sinc (tFS ) =

sin (FS t )
FS t

H(F)

h(t)
1

1/FS
-FS/2

FS/2

Eq. 2.19

2/T
-2/T
3/T
-3/T -1/T 1/T

Figure 2.11: Ideal reconstruction filter and its time domain waveform
Since the reconstruction is done by the convolution of y[n] and h(t), the reconstructed
signal becomes:

x (t ) = y[n] h(t ) = x(nT ) (t nT )

n

sin (FS t )
sin (FS (t nT ))
= x(nT )
FS t
FS (t nT )
n

23

Eq. 2.20

which is simply the summation of shifted sinc functions scaled with the sampled values
of x(t). It should also be noted that the original signal, x(t), does not necessarily need to
be localized around DC. Figure 2.12-a presents different Nyquist zones and as long as
the input signal is band-limited with one of them, reconstruction is possible. As an
example, if two signals, p(t) and s(t), with spectrums given in Figure 2.12-b, are sampled
with a sampling frequency of FS, the resulting spectrums will be identical and the
reconstruction will be possible by appropriate filtering. This property of sampling forms
the key idea behind sub-sampling ADCs. One final note on Nyquist zones is, if the signal
is localized at the even-numbered Nyquist zones, a mirrored copy of the signal spectrum
is shifted to the first Nyquist zone after sampling.

Figure 2.12: (a) Different Nyquist Zones (b) Two spectrums resulting in the same
output spectrum if sampled with FS.
As expected, if the condition in Eq. 2.18 is not satisfied, an overlapping will occur
between the adjacent Nyquist zones, causing the well-known phenomenon called aliasing
as presented Figure 2.13. In this case, the output spectrum no longer consists of the
scaled replicas of the input signal spectrum.
possible and aliasing can never be reversed.

24

Thus, the exact reconstruction is not

FS/2

-FS/2

Figure 2.13: Sampling with Aliasing

In most of the applications, the bandwidth of the desired signal can be within the Nyquist
zone, causing no aliasing. However, out-band interferers may fall into the Nyquist zone
after sampling and these interferers can alias with the desired signal (Figure 2.14). In
order to prevent this problem, an anti-aliasing filter is used before sampling which
attenuates the out-band interferers down to tolerable levels.

2FS-B
FS+B

FS-B

-FS+B

-FS-B
-2FS+B

FS/2

-FS/2

Figure 2.14: Out-band interferer aliasing with the desired signal after sampling
So far the ideal sampling and reconstruction are discussed to understand the concept of
sampling but neither the ideal sampling nor the ideal reconstruction is possible in real
applications. First of all, an ideal impulse (Dirac-delta function with infinitesimal time
and finite area) can not be realized physically. In addition, the ideal reconstruction filter
given in Figure 2.11 has perfectly sharp edges which means the time domain response
goes from - to +. Consequently, this filter is non-causal and also physically nonrealizable.
The actual sampling is generally done by holding the sampled value for a certain period
of time till the next sampling takes place. Figure 2.15 gives an example which shows the
operation of a zero-order hold.
25

Figure 2.15: Zero-order hold operation

It can be seen that, if the sequence of impulses in Figure 2.9 are convolved with a
rectangular pulse of magnitude 1 and duration T, the zero-order hold output given in
Figure 2.15 is obtained (Figure 2.16).

Figure 2.16: Relation between ideal and zero-order hold sampling

Since the Fourier Transform of a rectangular pulse is (assume that it is shifted to origin
for simplicity):

rect ( t ) T Sinc T
T
2

Eq. 2.21

and convolution in time domain is multiplication in frequency domain, the spectrum of

the S&H output can be obtained as illustrated in Figure 2.17. It can easily be observed
that the final spectrum does not consist of the replicas of the original input signal
spectrum and the Nyquist Zones are deteriorated by the sinc function.

However,

reconstruction is still possible by designing a proper filter which compensates for the
amplitude reduction due to sinx/x distortion by an increase in the amplitude at the highfrequency band edge.

26

Figure 2.17: Spectrum of zero-order hold sampling

Alternatively, the hold time can be made a small fraction of the sampling period [9].
Consequently, the bandwidth of the sinc function will become broader, causing less
distortion over the signal. Similarly, the sampling frequency can be made higher to
achieve smaller distortion.
As a summary, Figure 2.18 shows an ideal ADC system which consists of a front-end
anti-aliasing filter followed by a sampler and a quantizer. The dashed line symbolizes the
behavior of an ideal ADC whose output generally goes to a DSP block for further
processing.

Figure 2.18: An ideal ADC system

27

The next section explains the non-idealities and common performance metrics of ADCs.

2.4. ADC Specifications

In order to measure the performance of a converter, many different specifications are
utilized.

Depending on the application, some of these specifications can be more

important than the others and an optimization should be carried out to achieve the best
performance. ADC specifications can be classified in two groups: 1) DC (static) and 2)
AC (dynamic) specifications.

DC specifications are related with the static transfer

function of the ADCs where as the AC specifications cover the dynamic performance of
the converters.

2.4.1.

DC Specifications

Transfer characteristic of an ADC depicts the static behavior of the converter. Ideally,
this characteristic is a staircase with perfectly uniform and identical steps over the entire
dynamic range as given in Figure 2.5 where the step size is 1 LSB and the corresponding
quantization error is always limited to 0.5 LSB with no shift in the transfer curve due to
an offset.
Deviations from this ideal transfer characteristic define the DC specifications of the
converter. Many different specifications can be found in the literature but only the most
important and commonly used ones are discussed here.

2.4.1.1.

Offset

Offset is simply a shift for zero input and it changes the transfer characteristic in such a
way that all the steps are shifted by the amount of the offset which is generally expressed
in LSB. Figure 2.19 presents the ideal transfer characteristic of an ADC and the one with
offset.

28

Digital Output

8q

7q

6q

5q

4q

3q

2q

Figure 2.19: Ideal transfer characteristic and the one with offset
For systems utilizing a single ADC, offset can be corrected substantially in the digital
domain by shifting the raw converter output by the amount of the offset voltage in terms
of LSB. However, it can be a more severe problem for time-interleaved applications
where many ADCs operate in parallel and all suffer from different offsets due to
mismatches. In such a case, undesired spurs will appear within the bandwidth of interest
and these spurs can deteriorate the SNDR (Signal-to-Noise-and-Distortion Ratio)
significantly.

Robust offset calibration schemes are generally mandatory for such

applications.

2.4.1.2.

Gain Error

The gain of the transfer characteristic of an ADC can be calculated by drawing a straight
line which interpolates the actual transfer curve. The resulting line can be expressed as
D=O+GA where D represents the digital output, O represents the offset, A represents the
analog input, and G represents the gain. The error on the slope of the straight line is
referred as the gain error and it is generally expressed as the percentage difference
between the ideal and the actual gains but different expressions are also possible such as
full scale error [12].

29

Figure 2.20 shows the ideal transfer curve and the one with gain error. Note that in the
gain error case, the step sizes are also identical to each other but different from the ideal
case.

0..111

With gain
error

0..110
0..101
0..100
0..011
0..010

Ideal

0..001
0..000
0

Analog Input
Figure 2.20: Ideal transfer characteristic and the one with gain error
Similar to offset, gain error can be corrected to a great extent digitally by multiplying the
raw ADC data with a correction coefficient. In time-interleaved applications, a robust
calibration is again required.

2.4.1.3.

onlinearities

So far, both for the offset and the gain error cases, the linearity of the transfer curves have
been preserved. The step sizes were identical to each other but either the zero crossing or
the step size was different from the ideal ones.
The main reason for nonlinearity arises from the variation in the step sizes of the transfer
curve. Figure 2.21 shows two non-ideal transfer curves with non-linearity problems [12].
As given in Figure 2.21-a, these variations can be random with almost no correlation
between successive steps. In this case the interpolating curve can be still very close the
ideal one but the quantization error can vary significantly. In Figure 2.21-b, the step size

30

is small at the beginning but increases as the analog input becomes larger. Thus, there is
a strong correlation between the successive steps and the interpolating curve moves away

Digital Output

Digital Output

from the ideal one. However, the variation in the quantization error might be smaller.

8q

7q
6q

5q

4q

3q
2q

8q
7q

6q

5q
4q

3q
2q

Figure 2.21: Two non-ideal transfer curves

To cover both of the cases presented in Figure 2.21, two different non-linearity
specifications are used: 1) Differential Non-Linearity (DNL) and 2) Integral NonLinearity (INL). Simply, Figure 2.21-a suffers from large DNL but small INL. On the
other hand, Figure 2.21-b suffers from large INL but relatively smaller DNL. Next
sections explain these two non-linearity specifications in details.
2.4.1.3.1. Differential Non-Linearity (DNL)
Ideally, the step-size is always equal to 1 LSB in an ADC transfer curve. In real
converters, there is always a deviation from the ideal case and DNL gives the deviation of
the individual step sizes from this ideal step width. Figure 2.22-a visually explains the
calculation of DNL. Note that, if the DNL is less than -1 LSB, this corresponds to a
missing code. Figure 2.22-b shows a DNL plot example of an 8-bit converter where the
DNL is less than 0.5 LSB. Generally, the maximum value of DNL across the range is
given as the DNL error of the converter.

31

Digital Output
Figure 2.22: (a) Details of DNL (b) DNL plot of an 8-bit converter

2.4.1.3.2. Integral Non-Linearity (INL)

Analogous to the definition of linearity for an amplifier, INL is defined as the deviation
of the actual transfer curve from a straight line. The straight line is generally chosen by
two common methods: 1) the most commonly used straight line is the endpoint-fit line,
drawn after the offset and gain errors are corrected, which goes through the origin and the
full scale. 2) Other common method is the best straight line which is obtained by curve
fitting the transfer curve of the converter. Figure 2.23 presents both of these methods.

Endpoint-fit Line

Best-fit Line

INL

INL

Analog Input

Analog Input

Figure 2.23: Endpoint-fit and best-fit methods for INL calculation

32

Although the best-fit method generally gives better results, endpoint-fit is the most useful
measurement because the deviation from the ideal case makes more sense than the
deviation from an arbitrary best-fit curve. Thus, the endpoint-fit method is chosen as
standard. As a final note, for the endpoint-fit case, INL can be also calculated from the
DNL result by using [12]:

I.L(k ) = (1 + G ) D.L (i )

Eq. 2.22

i =1

where G is the gain error of the transfer curve. The gain error term can be removed if the
DNL is also measured from the gain-corrected transfer curve.
Similar to amplifiers, nonlinearity creates distortion and causes ADC SNDR to degrade.
Thus, an updated expression can be obtained for the SNDR by including the distortion
due to nonlinearity. Note that, if nonlinearity exists, quantization error is no longer
restricted to q (q=LSB). If the DNL of the converter is LSB, then the quantization
error will vary from (1+)q. As a quick back-of-an-envelope calculation, it can be
assumed that the quantization error is uniformly distributed (the worst case assumption).
Consequently, the previously calculated rms quantization error will become:

q
12
{
IDEAL

(1 + )q
Eq. 2.23

12
1
42
4
3
WITH

D.L

And the SQNR calculation given in Eq. 2.10 can be updated to get the new SNDR
expression:

2. q

2
2
= 20 log10 3 2
S.DR = 20 log10
2 1+
(1 + )q

12

33

Eq. 2.24

2.4.1.4.

Monotonicity

As a final note, an ADC is meant to be monotonic if the output code is consistently

increasing (or decreasing) with the increasing (or decreasing) analog input signal. As an
example, Figure 2.24 shows a non-monotonic converter transfer characteristic which also
includes a missing code. Non-monotonicity can be a severe issue especially in feedback
systems like servo applications.

Figure 2.24: Non-monotonic transfer characteristic with missing code

Depending on the converter architecture, an ADC can be more immune to nonmonotonicity or vice versa. For instance, Successive Approximation Register Based
(SAR) ADCs can still be monotonic even though their internal Digital-to-Analog
converter (DAC) is non-monotonic.

On the other hand, an improperly trimmed

subranging ADC, in which the overall transfer characteristic is divided into smaller
sections, may exhibit non-monotonicity or missing codes at the intersection points of the
divided transfer curve sections.
As a final note on monotonicity, it can be shown that a converter is always monotonic if
INL is less than LSB. However, if an ADC is monotonic, it does not imply that
INL< LSB.

34

2.4.2.

AC Specifications

Initial applications of data converters were in measurement and control where the exact
timing of the conversion was usually unimportant, and the data rate was slow. In such
applications, the DC specifications of the converters are important, but the timing and AC
specifications are not. Today, many converters are used in sampling and reconstruction
systems where AC specifications are critical and DC ones may not be that important [11].
AC specifications show the dynamic performance which is determined by the frequency
response and the speed of the converter. In this section, the most commonly used AC
specifications are discussed in detail.

2.4.2.1.

Clock Jitter (Aperture Uncertainty)

In Section 2.3, where sampling is covered, it is always assumed that the continuous-time
input signal is sampled at instants precisely spaced by the sampling period T. However,
due to non-ideal conditions such as noise, clock rise and fall times, device variations and
mismatches, there exists an uncertainty at the sampling instant and this causes a sampleto-sample variation in the instant of sampling. This uncertainty is called clock jitter or
aperture uncertainty which is generally expressed in rms picoseconds.

Figure 2.25: Clock jitter

35

Figure 2.25 shows the clock jitter issue and its effect on sampling. Note that the error
due to jitter has a strong correlation with the slope of the input signal. In the case of a
jittery clock, the sampling is no more uniform and the sampled waveform can be written
as x(nT+n) where n is a random variable and represents the amount of deviation in the
sampling instant. Consequently, the output of the sampler can be written as:
x(nT + n ) x(nT ) + E n

Eq. 2.25

where En is simply the error term due to jitter. Since En is also a random variable, it
appears as noise and degrades the SNR of the converter. The degradation in SNR due to
jitter can be calculated as follows for a sinusoidal input:

x(nT + n ) = A sin (2f in t ) t = nT +n = A sin (2f in (nT + n ))

Eq. 2.26

By using basic trigonometry:

A sin (2f in (nT + n )) = A[sin (2f in nT ) cos(2f in n ) + cos(2f in nT )sin (2f in n )] Eq. 2.27
If n is assumed to be very small when compared with the input frequency:
cos(2f in n ) 1 & sin (2f in n ) 2f in n

Eq. 2.28

Consequently, the sampled sequence can be approximated as:

A sin (2f in (nT + n )) = A sin (2f in nT ) + 2 Af in n cos(2f in nT )

Eq. 2.29

where the first them is the ideal sampled sequence and the second term is the error due to
jitter. If the powers of the ideal sampled sequence and the error term are ratioed, the
SNR can be found as:

36

S.R jitter

A2

2
= 10 log 2
A (2f in )2 n 2
2

20
log
=

2f in n

Eq. 2.30

Eq. 2.30 shows that the SNR degrades with the increasing input frequency. Thus, jitter is
very important especially for high speed wide bandwidth ADCs and it can even be a
fundamental limit for the performance in these applications due to the challenges in the
design of low-noise clock generators and the distribution of the clock inside the ADC.
As a final note, the SNDR expression in Eq. 2.24 can be updated by including the jitter
term given in Eq. 2.30. The resulting expression becomes:

2
.
3 2
1
+
S.DR = 20 log10
2f

+
2
in n
142

43
4 43
4
142
Jitter
Quantization & D.L

1/ 2

Eq. 2.31

where n is the rms jitter of the clock.

2.4.2.2.

oise

Quantization noise is a fundamental limit for data converters but circuits inside the
converter like amplifiers, resistors, current sources, etc. possess thermal noise as well.
This noise also adds to the quantization noise and causes the SNR to deviate from its
theoretical maximum. If the total input referred noise is known, then the total noise can
be written as (assuming no correlation):

. noise = . Quantization + . thermal

Eq. 2.32

Consequently, the SNR expression can be updated accordingly with the total noise:

37

2
2
.

1
2.
3 2

S.DR = 20 log10
+

+
2
V .OISE _ rms
in n
142

12424
142
4
3
4
43
4
42444
3
Quantization & D.L
Jitter
Input .oise

1/ 2

Eq. 2.33

Thermal noise can be critical for wide-bandwidth systems such as Flash ADCs and it
should be kept low enough compared to the quantization noise to make sure that the
degradation is tolerable.
Most of the ADC systems possess a sampling network and this feature comes with one of
the most important noise sources called kT/C noise which is unavoidable in real sampleddata systems.

Figure 2.26: a) A simple sampling system b) Equivalent RC network of the sampler c)

Corresponding noise spectrum at the output node when the switch is on.
Figure 2.26-a shows a simple sampler which consists of a switch and a capacitor. When
the switch is ON, it behaves as a resistor due to the on-resistance of the MOS devices and
the network can be modified as shown in Figure 2.26-b. The thermal noise of a resistor is
white and equal to 4kTRS (single-side representation) and the RC network of the sampler
is a single-pole low-pass filter with the cut-off frequency of 1/RSCH. Thus, the noise
spectrum at the output node when the switch is ON is like the one given in Figure 2.26-c.
The total noise power possessed can be calculated by taking the integral over the entire
bandwidth:

38

PTotal = Vn df =
0

4kTRS

1 + (2fR s C H )

df =

kT
CH

Eq. 2.34

which turns out to be related to just CH but not to RS. When the input signal is sampled,
all of the power stored under the noise spectrum is also aliased down to the Nyquist band.
Consequently, no matter what the sampling frequency is, kT/C noise always appears in
the band of interest. If only the kT/C noise is taken into account, Eq. 2.33 can be written
as:

3 2 . 2 1 2 P
+
+ SIG
S.DR = 20 log10

kT
f in n
2 1+
124
2
4
3
1
42
4
43
4
Quantization & D.L
C
Jitter
{

.oise

1/ 2

Eq. 2.35

The only way a designer can decrease the kT/C noise is enlarging the size of the hold
capacitor. However, this also decreases the bandwidth of the sampler as the RC time
constant become higher in this case. Consequently, there exists a limit for the maximum
hold capacitor size based on the sampling switch on-resistance and the input signal
bandwidth.

2.4.2.3.

SR and SDR

As mentioned before, SNR is the ratio between the input signal power (generally a sine
wave) and the total noise power (both the quantization and the circuitry noise) and it is
generally measured in the entire Nyquist band. SNR depends on the amplitude and the
frequency of the input signal.
SNDR (Signal-to-Noise-and-Distortion Ratio) has a similar definition with SNR but it
also includes the non-linear distortion terms generated by the input sine wave. Thus,

39

SNDR is the ratio between the rms of the input signal and the rms of the harmonic
components in addition to the noise. Similarly, it depends on the frequency and the
amplitude of the input signal. SNDR can also be called SINAD in the literature.

2.4.2.4.

Effective umber of Bits (EOB)

As covered in section 2.2.1, the theoretical SNR expression is 6.02*N+1.76 dB for an Nbit converter. ENOB is simply the output of the reverse operation to figure out the
effective resolution of a real converter and it is found by:

E.OB =

S.DR 1.76
6.02

Eq. 2.36

where SNDR is expressed in dB.

2.4.2.5.

Spurious Free Dynamic Range (SFDR)

SFDR is the ratio between the rms signal amplitude and the rms value of the highest spur
(spurious spectral component) in the first Nyquist zone.

Figure 2.27: Output spectrum showing the SFDR

40

Figure 2.27 gives an output spectrum example showing the SFDR value. SFDR strongly
depends on the input amplitude.

For large inputs, the highest spur is generally a

harmonic component but as the signal amplitude becomes smaller, distortion due to
signal becomes negligible and tones not caused by the input become effective.

2.4.2.6.

Bit Error Rate (BER)

Since the time dedicated for an analog-to-digital conversion is limited, ADCs might
sometimes need more time and give wrong decisions, resulting in wrong output codes.
BER is the number of bit errors that occur within the space of one second and is
measured to determine the signal quality. BER is a critical parameter especially for high
speed ADCs in which the conversion time is considerably short. Rates around 10-9 (1
error in 1 billion conversion) are generally targeted to have high signal quality.

2.4.2.7.

Figure-of-Merit (FoM)

FoM is generally used to compare the performances of different ADCs. It basically gives
an idea on the power efficiency of the converter and it is expressed as:

FoM =

Total Power
2 E.OB 2 BW

Eq. 2.37

where BW is the bandwidth of the input signal and total power is the power consumed by
the converter. FoM is not a solid parameter due to its strong dependence on technology
parameters and signal bandwidth, but can be used to compare efficiency of the converters
used in similar applications.

As a quick reference, converters with FoM less than

1pJ/conv-step are generally accepted as efficient, although there are converters reported
with FoMs around a few fJ/conv-step [13].

41

CHAPTER III

3. HIGH-SPEED ADC TOPOLOGIES

Analog-to-digital conversion is a very general technical term that is carried out in various
different applications. As far as the system requirements are concerned, a long list of
specifications can be prepared.

Based on these specifications, different conversion

techniques can be adapted for different applications. Consequently, many distinct ADC
topologies can be found in the literature such as Flash, Folding (& Interpolating),
Pipeline,

Subranging

(or

Two-step),

Integrating,

Sigma-Delta,

Successive-

Approximation-Register (SAR), Time-Interleaved, Cyclic (or Algorithmic), etc., each

with its own advantages suited well to different system requirements.
Resolution, sampling rate, bandwidth, power consumption, noise, area, clock latency,
scalability, complexity, technology, etc. determine the most feasible topologies for that
particular system. As an example, Figure 3.1 gives a rough classification of ADCs based
on speed and resolution.

Figure 3.1: ADC classification based on speed and resolution

42

High-speed communication systems like serial links [14], UWB [15], and OFDM-based
60GHz receivers [16] require fast conversion rates to meet the communication channel
specifications. Thus, high-speed, low-to-medium resolution ADCs are widely used in
these applications.

The most commonly utilized topologies are Flash, Subranging,

Folding, and Time-interleaved ADCs which are explained in this chapter. Section 3.1
covers Flash ADCs in detail. Then, Section 3.2 goes through the architecture, advantages
and disadvantages of Folding (& Interpolating) ADCs. Section 3.3 gives information on
Subranging and Two-Step ADCs thoroughly. Section 3.4 briefly covers Pipeline ADCs
as an extension to Two-step ADCs and Section 3.5 completes the topology types by
covering Time-Interleaved ADCs.

Finally, Section 3.6 concludes the chapter by

comparing the state-of-the-art performances of the high speed ADC topologies.

3.1. Flash ADCs

Flash ADCs are the fastest single-standing ADC topology, whose operation relies on the
parallel decision of a number of comparators. Figure 3.2 shows the schematic of a
conventional Flash ADC which consists of 2N-1 (N=resolution) comparators, a resistive
ladder, a track & hold (optional), a buffer (optional), and digital logic.

Figure 3.2: Schematic of a flash ADC

43

Each comparator is connected to the input signal and one of the reference taps which are
generally created from stable reference voltages using resistive ladders. When all the
comparators are triggered by the same clock signal, each one compares the input with a
different reference tap at the same time instant.

Consequently, the output of the

comparators is ideally a row of zeros (outputs of the comparators with reference taps
greater than the input signal) followed by a row of ones (outputs of the comparators with
reference taps smaller than the input signal) which is called a thermometer code. Hence,
the exact location of the input voltage can be figured out by checking the zero-one
junction of the thermometer code. The digital logic finds this junction point and outputs
the corresponding binary word.
As seen, Flash ADCs make a conversion at each clock cycle. If the buffer and the T&H
are ignored (they are theoretically not necessary), the speed of the converter is only
limited by the decision delay of the comparators. As the latched comparators have an
exponential growth at their output nodes when they are triggered, the time constant of
this growth, i.e. the regeneration time constant, can be used as a good metric to estimate
this decision delay. Regeneration time constant can be expressed as:

CT
gm

Eq. 3.1

where CT is the total parasitic capacitance at the regeneration node and gm is the
transconductance of the latch transistors. Since comparison is a fundamental operation
for ADCs and Flash ADCs suffer only from comparator delay, they are extremely fast
topologies.
It can be seen that the regeneration time constant has a very strong correlation with the
unity gain frequency, fT, of the process. Consequently, as the technology scales and unity
gain frequency increases, comparators become faster.

44

Thus, Flash ADCs are

substantially scalable topologies. Moreover, since there is no clock latency, Flash ADCs
can be used in feedback systems such as Sigma-Delta modulators.
On the other hand, a Flash ADC needs 2N-1 comparators for an N-bit conversion. For
instance, a 3-bit Flash ADC needs only 7 comparators whereas an 8-bit one consists of
255 comparators. This exponential increase in the number of comparators puts an upper
limit on resolution. Thus, Flash ADCs almost never exceed 8-bit resolution. Moreover,
this exponential increase creates high power dissipation since fast comparators are power
hungry in general. The usage of this power dissipation is also not efficient because, at
each conversion, only a few comparators are critical in giving the decision whereas the
rest just dissipates power to give a trivial answer.
Reference ladder design is also challenging in Flash ADCs. Especially, for high-speed
and high resolution applications, in order to keep the reference taps stable and immune to
the time-variant loads of the comparators, and also to keep the thermal noise of the
resistors small enough, small unit resistors are necessary. However, this increases the
power dissipation. Moreover, the reference voltage generators have to have a very small
output resistance to drive this low-resistance loading of the ladder.
Another disadvantage of the Flash ADCs is the input capacitance. All comparators are
connected to the input node and the capacitive load at the input increases exponentially
with the resolution. This capacitive load is not only large but also nonlinear due to the
voltage dependency of the internal parasitic capacitances of MOS devices. This can
cause a significant bandwidth problem and generally high-speed, high-swing buffers are
necessary for driving. However, these buffers are power hungry and not trivial to design.
A common challenging problem as the speed and resolution increase is the clock and
input distribution. Ideally, a Flash ADC can operate without a front-end T&H. However,
in this case, the matching among the clock and input lines of each comparator becomes
very stringent. Any mismatch in these lines of the comparators can lead to wrong

45

decisions and bubble errors, and degrade the SNDR if not corrected properly. A simple
solution to this problem is a front-end T&H, but again T&H or S&H designs become
more challenging with new technologies. Moreover, if there is no front-end buffer, this
T&H has to drive the big and nonlinear input capacitance of the ADC.
In addition, input referred offset is an inevitable problem for Flash ADCs. In order to
enhance the regeneration time constant of a comparator, minimum length devices are
preferred, which results in high offset voltages. Thus, calibration is generally mandatory.
Last but not least, dynamic comparators suffer from large kickback noise. Almost rail-torail swing at the output can couple to the reference taps and the input node through the
parasitic devices, which produces settling issues. A preamplifier can be utilized to
suppress this effect.

3.2. Folding (and Interpolating) ADCs

The inefficiency problem in Flash ADCs caused the emergence of a relatively efficient
architecture called Folding ADCs. The basic idea behind the Folding ADCs is to use the
same comparator to compare the input with several different reference taps rather than a
single tap as in the case of a Flash converter. In order to achieve this, the input signal is
folded certain times using preamplifiers. Figure 3.3 presents the folding operation for a
4-bit converter with 2-bit folding factor. Each dashed line represents a comparator and it
can be seen that the straight Flash ADC has 15 comparators, whereas the Folding ADC
with 2-bit (=4) folding factor needs only 6 comparators: 3 for the LSBs (horizontal lines
decision in each line segment) and 3 for the MSBs (vertical lines decision of which
segment the input is in). Consequently, the number of comparators can be reduced
significantly as the folding factor increases with the penalty of increase in the number of
preamplifiers responsible for input folding.

Moreover, coarse and fine quantization

operations can be done at the same time. As a result, the speed of a Folding ADC can
reach that of a Flash converter theoretically.
46

Figure 3.3: Folding operation

Note that the folded input signal given in Figure 3.3 has sharp edges at the folding points.
However, these sharp edges are impractical to implement with real circuits as their
responses are always somewhat rounded as presented in Figure 3.4-a.

A common

solution to this problem is using two folded input signals which are shifted by a quarter of
the folding period. This way, one folded signal is always guaranteed to be in the linear
region and the nonlinear rounded parts can be discarded as shown in Figure 3.4-b.

Figure 3.4: a) Real folded signals do not have sharp changes at the folding points b)
Solution to rounded edge problem in folding operation

47

Figure 3.5: Schematic of a folding ADC

Figure 3.5 shows the schematic of a folding ADC in which the coarse ADC is responsible
for the MSBs and it is generally implemented as a Flash converter whose resolution is
equal to log2(folding factor). The front-end preamplifiers are responsible for folding the
input signal. This way, the number of comparators can be scaled by a factor equal to the
folding factor. For instance, if the input signal is folded by 2, each comparator will
compare the input voltage with two different reference taps. Thus the total number of
comparators is reduced by a factor of 2.
It can be seen that there exists a trade-off between the number of comparators and the
number of preamplifiers.

As the folding factor becomes higher, the number of

comparators reduces but that of the preamplifiers increases. Thus, the achieved power
saving might be smaller than expected. In order to further reduce the power dissipation,
some of the folded signals can be generated by interpolating the outputs of the
neighboring folding preamplifiers and these kinds of ADCs are called Folding &
Interpolating ADCs. Figure 3.6 gives an example to interpolation. It should be noted
that a similar interpolation can be applied directly to Flash ADCs as well by interpolating
48

the signals at the latch inputs. The number of latches will still remain the same in this
case but the number of preamplifiers can be reduced.

Figure 3.6: Interpolation of folded signals

A decent power and area saving can be achieved with Folding ADCs. Consequently,
resolutions around 10-bit is doable. Moreover, the loading between stages is relaxed and
the kickback noise is not very critical. Furthermore, preamplifiers can be designed with a
small gain which will reduce the input referred offset of the comparators. Preamplifiers
will contribute to the offset as well but the offset of a dynamic latch is generally higher
than that of an amplifier. Averaging the preamplifier outputs is a common way to reduce
the preamplifier offset, and interpolation is also known to help reduce the offset since it is
technically same as averaging.
However, speed reduction is inevitable due to the addition of preamplifiers. Moreover,
folding amplifiers are implemented with differential pairs whose outputs are connected in
reverse polarity. As the folding rate becomes higher, the number of amplifiers connected
to the same output node increases. This might create a dominant pole and limit the
bandwidth severely. Generally, this issue is solved by cascading folding amplifiers with
small folding rates to create large folding factors. But this adds more delay to the signal
path.
Another serious bandwidth limitation is the implicit frequency multiplication effect due
to folding. Folded signals at the output of the preamplifiers have a higher frequency than
the input as shown in Figure 3.7. It can be shown that, for an input tone at frequency fin,
the maximum instantaneous frequency at the output is (FF=folding factor) [17]:

49

f out _ max = 2 FF f in

Eq. 3.2

Input Sine Wave

1
0.5
0
-0.5
-1

10

10

8-times Folded and Amplified Output

1
0.5
0
-0.5
-1

Figure 3.7: Input sine wave and 8-times folded output waveform
Thus, Nyquist operation is hard to achieve as the bandwidth of the ADC should be well
above the Nyquist frequency. This problem can be solved by using a front-end T&H
before folding preamplifiers.

Consequently, although folding ADCs can operate

theoretically without a T&H, practically it is mandatory.

In addition, the previously mentioned issues on reference tap generation are also valid for
Folding ADCs as they use the same architecture.
Finally, one of the major problems of Folding ADCs is scalability.

Although

comparators can be accepted as scalable, amplifiers are not as they suffer from
nonlinearity and mismatch (a comparator has to be correct at only one point but the
amplifier needs to be linear for the entire input range). Consequently, Folding ADCs
have been losing their popularity with the introduction of new technologies.

50

3.3. Subranging (Two-Step) ADCs

Low resolution ADCs are relatively easier to design, less power hungry, and smaller in
area. As a simple example, a 3-bit Flash ADC design with only 7 comparators is not as
challenging as the design of a 6-bit one with 63 comparators. This principle forms the
fundamental idea behind the Subranging or Two-step ADCs. A high resolution ADC can
be implemented by utilizing two low resolution ones by which the MSBs and the LSBs
are converted separately. Figure 3.8 shows a simplified schematic of a Subranging or
Two-step ADC where an M+N bit ADC is implemented with an N-bit and an M-bit
ADC.

Figure 3.8: Schematic of a subranging (two-step) ADC

The operation is briefly as follow: input is first sampled by the T&H and an N-bit coarse
conversion takes place after sampling. The coarse ADC output is converted back to its
analog value using a DAC inside the residue generator and the DAC output is subtracted
from the sampled input signal to obtain the residue. This residue is either first amplified
or directly passed to the fine M-bit converter for the decision of the LSBs. Finally, the
digital logic combines the fine and coarse conversion outputs to give the M+N-bit digital
code.

51

The main difference between the Subranging and Two-step ADCs is the residue
generation. Two-step ADCs possess a gain stage before the second converter whereas
Subranging ADCs do not amplify the residue.
Subranging (Two-step) ADCs are flexible, because, based on the application and the
particular design constraints, different ADC topologies can be used (although Flash
ADCs are the most common ones) and they can achieve resolutions around 10-bit.
It can be easily observed that there is an inevitable clock latency issue in these ADCs.
The input has to be first converted by the first N-bit ADC and the second ADC has to
wait for the outputs of the first converter and the residue generator. Thus, it might be
problematic to use Subranging ADCs in feedback systems where latency is intolerable.
However, in many applications, the clock latency is not a serious issue as long as the
throughput is high. The overall throughput of a subranging ADC can be still very high
because while the second ADC converts, the first ADC can start converting a new
sampled input in a simple pipeline manner. In fact, Two-step (Subranging) ADCs can be
considered as a special type of Pipeline ADCs, in which there are only two stages.
A subranging ADC can not operate without a T&H, and this might put an upper limit for
the performance as high speed T&H designs are challenging. However, the T&H has to
drive a relatively small-resolution ADC. Consequently, the overall loading is small,
relaxing the design constraints of the T&H.
One of the most important issues in a Subranging ADC is the accuracy. The residue
generator has to have (N+M)-bit accuracy. In order to achieve this, high gain high
bandwidth operational amplifiers might be necessary which are extremely hard to design
in sub-100nm CMOS technologies, thus degrading scalability.
Since the overall transfer curve is divided into two segments, improperly trimmed ADCs
might cause missing or wide codes as well as non-monotonicity at the break points in

52

Subranging ADCs. However, these errors can easily be corrected since their locations
are well-known. On the other hand, the errors of the DAC inside the residue generator
can be more problematic as they influence the entire fine conversion interval.
As a final note, the residue generation of a Subranging converter can be viewed as a nonlinear transformation of the input. Unlike a linear transformation in which the bandlimited characteristic of the input can be preserved, non-linear transformations generate
extra-tones which, in sampled data systems, spread the input spectrum over the entire
Nyquist interval, even if the input has a relatively smaller bandwidth. To preserve the
wide spectrum of the residue, the amplifier and the second ADC must be effective well
above the Nyquist limit since possible attenuations or phase shifts around the Nyquist
will degrade the information associated with the LSBs [12].

3.4. Pipeline ADCs

Although it is not common to see Pipeline ADCs in very high-speed, medium resolution
applications, they will be briefly mentioned here since they can be considered as an
extended version of Subranging (or Two-step) converters.

Basically, the operating

principle of a subranging ADC can be extended to more than 2 ADCs to implement a

Pipeline converter. Pipeline ADCs are commonly implemented with 1 or 2-bit ADC
stages, however more than 2-bit per stage architectures are also available in the literature
[18]. In the case of the widely utilized 1.5-bit per stage topology, each stage outputs 2
bits: one bit is the conversion output of that particular stage while the second bit is
utilized to help the next stages bit decision. 1.5-bit per stage architectures are generally
preferable because a single bit ADC is guaranteed to be linear. Moreover, this half-bit
feature of Pipeline ADCs forms one of the most robust digital calibration schemes in the
ADC world. The last few LSBs in a pipeline ADC are generally obtained by using a
Flash ADC.

53

Similar to subranging ADCs, pipeline ADCs need a front-end T&H and they can achieve
resolutions more than 12 bits. Again the clock latency is large (even larger) but the
overall throughput can still be very high. Residue generation is similarly critical and it
has to have an accuracy more than or equal to the total desired resolution of the
converter. This might put an upper limit for the performance. The need for a high speed,
high bandwidth, and high-swing operational amplifier degrades the scalability
significantly.

3.5. Time-Interleaved ADCs

A single ADC can only reach up to a certain speed. As an example, state-of-the-art
converters can barely go beyond 10GS/s sampling rate with extremely high power
dissipations. However, it is possible to implement very high speed ADCs by using a
number of converters working in parallel which is called a time-interleaved ADC. This
way, if N ADCs are time-interleaved, the overall speed can be boosted N times. The idea
of time-interleaving has been utilized to achieve very high conversion rates (e.g. a few
10s of GS/s), and high sampling rate oscilloscopes are a common application area for
this type of converters. Figure 3.9 shows a simplified schematic of an interleaved ADC
architecture.

Figure 3.9: Simplified schematic of a time-interleaved ADC

54

Although not shown in Figure 3.9, there might be a front-end T&H which drives all
ADCs. In this case, the T&H has to operate at full speed, making the design challenging.
Alternatively, each ADC can possess a separate T&H (distributed T&H approach) which
relaxes the loading and the speed by a factor equal to the number of parallel ADCs.
However, in this case, different clock phases should be generated and distributed
carefully among the converters as a misalignment can degrade the performance
significantly.
Time-interleaving can also be applied to an ADC application which can be implemented
with a single converter. For instance a 6-bit 1.5 GS/s ADC design can be carried out by
using a Flash architecture. However, it is also possible to meet the same specifications
by using a time-interleaved topology in which a certain number of relatively low speed
ADCs is used. At the first glance, meeting the constraints by using many ADCs instead
of a single one might seem inefficient, but low speed ADCs are generally very good in
terms of power and area efficiency. Thus, even if many low speed ADCs should be
interleaved to meet the desired speed, the overall system can still be more efficient than a
single ADC.
In addition, time-interleaving has flexibility on ADC selection. Different ADCs like
Subranging, Pipeline, Flash, Folding, and SAR ADCs can be used as the unit ADC block
for time-interleaving. Advantages and challenges vary based on the selection of unit
converter.
On the other hand, time-interleaved ADCs suffer from mismatch severely.

Any

mismatch on the offsets, gains, and bandwidths of the unit ADCs can create undesired
spurs in the Nyquist band. Similarly, clock skew problem degrades the SNDR if no
front-end T&H is used. Consequently, robust calibration schemes are always required for
this kind of converters. Time-interleaving problems and their calibration methods are
discussed thoroughly in Chapter V.

55

3.6. State-of-the-Art Performances and Comparison

This section gives the state-of-the-art performances of the high-speed ADCs covered in
this Chapter. Then, an overall performance comparison of converters in sub-100nm
CMOS technologies is carried out.

Flash ADC State-of-the-Art Performance

4.5

[1] ISSCC 2006 - 90nm

[2] NORCHIP 2008 - 90nm
[3] CCECE 2005 - 0.18um
[4] JSSC 2008 - 90nm
[5] VLSI-DAT 2007 - 0.13um

FoM (pJ/conversion-step)

4
3.5
3

[3]

2.5
2

[5]

1.5
[2]

1
0.5
0

[4]

[1]
0

10
15
20
Resolution * Speed (Bits * GS/s)

25

Figure 3.10: State-of-the-Art Performance of Flash ADCs [19-36]

Figure 3.10 presents FoM versus (Resolution*Speed) characteristic of the state-of-the-art
CMOS Flash ADCs published in the last 5 years [19-36]. Speed range is kept from
1GS/s to 5GS/s and resolution does not exceed 8 bits. It can be seen from the red dashed
line that, for high-speed medium-resolution applications, it is very challenging to keep
the FoM around 1.5-2 pJ/conv-step. As a short note, two ADCs ([4] and [5]) on Figure
3.10 are seemed to have much better performance than the other ADCs. However,
number [5] is reported based on only simulation results. Number [4] is using low-VT
transistors which are not suitable for this application as the process is a LP Digital CMOS
process.
56

A similar state-of-the-art performance plot is also given in Figure 3.11 for CMOS
Folding & Interpolating ADCs [37-44]. As seen, for Resolution*Speed>10 Bits*GS/s, it
is very hard to keep FoM less than 2pJ/conversion-step. This is an interesting point
because this performance is actually worse than that of Flash ADCs although Folding
ADCs are expected to be more efficient than Flash converters. The main reason behind
this result is the scalability, and as mentioned before, Folding ADCs have been losing
their popularity because of this issue. This scalability issue can be observed from the
processes used in the state-of-the-art designs. As seen from Figure 3.11, all the high
performance ADCs (labeled as [1]-[4] on Figure 3.11) were implemented in 0.18m
CMOS process which also proves that the folding ADCs are not scalable. This also
explains the decrease in the number of published Folding ADCs in the last few years. As
a final note, ADCs labeled with [1]-[3] on Figure 3.11 are reflecting the state-of-the-art
performance but these values are based on simulation results only.

Folding & Interpolating ADC State-of-the-Art Performance

3.5

FoM (pJ/conversion-step)

2.5

[4]
[3]

2
[2]

1.5
[1]

0.5

[1] ICECS 2006 - 0.18um

[2] PRIME 2005 - 0.18um
[3] ICICDT 2008 - 0.18um
[4] ISSCC 2009 - 0.18um

5
10
Resolution * Speed (Bits * GS/s)

15

Figure 3.11: State-of-the-Art Performance of Folding ADCs [37-44]

57

Similarly, Figure 3.12 gives the state-of-the-art performance of CMOS Subranging (Twostep) ADCs in terms of FoM versus Resolution*Speed based on the published works in
the last 5 years [45-53]. The red dashed line shows an estimate interpolation for highspeed and medium-resolution (Resolution*Speed > 10 Bit*GS/s) cases. It can be seen
that the FoM around 1pJ/conv is still challenging for these applications. One interesting
point that should be mentioned here is, the ADC labeled as [3] on Figure 3.12 has much
better efficiency than the other ADCs on the figure. However, this ADC is a modified
version of a Flash ADC and has resolution limitation. Moreover, the architecture relies
on complex analog switching which is a challenging task to design in a 45nm LP Digital
CMOS process. In addition, the mentioned rectification operation in this work needs to
be very accurate to prevent any nonlinearity.

FoM (pJ/conversion-step)

Subranging and Two-Step ADC State-of-the-Art Performance

2.5
[1] CICC 2008 - 0.13um
[2] A-SSCC 2008 - 90nm
[3] ISSCC 2008 - 90nm

1.5

1
[2]
[1]
0.5
[3]
0

4
6
8
10
12
Resolution * Speed (Bits * GS/s)

14

Figure 3.12: State-of-the-Art Performance of Subranging and Two-step ADCs [45-53]

Finally, Figure 3.13 presents the FoM of CMOS Time-Interleaved ADCs with respect to
Resolution*Speed [18, 54-62]. According to the trend based on the red dashed line, it

58

can be concluded that a FoM of 0.5-1pJ/conv-step is challenging for the application of

interest. However, the efficiency of Time-Interleaved ADCs appears to be better than
that of other high-speed converter types covered so far.

Time-Interleaved ADC State-of-the-Art Performance

FoM (pJ/conversion-step)

2.5
[1] ISSCC 2006 - 0.13um
[2] VLSI 2008 - 65nm
[3] ISSCC 2008 - 90nm
[4] JSSC 2008 - 0.13um
[5] JSSC 2008 - 0.13um

1.5
[5]
1
[3]
0.5
[1]
0

[4]

[2]

10
15
20
Resolution * Speed (Bits * GS/s)

25

Figure 3.13: State-of-the-Art Performance of Time-Interleaved ADCs [18, 54-62]

Table 3.1: Comparison of high-speed ADCs

ADC Topologies
Flash

Folding

Subranging

Time-Inter.

Speed

<4GS/s

1-2 GS/s

1-2GS/s

<25GS/s

Resolution

<7 bits

<12 bits

<12 bits

<10 bits

FoM

1.5-2 pJ/conv.

2 pJ/conv.

1-1.5 pJ/conv.

0.5-1 pJ/conv.

Scalability

Yes

Partially

Partially

Yes

T&H

Required

Required

Required

Required

Calibration

Required

Required

Required

REQUIRED

59

To sum up,
Table 3.1 compares the performances of high-speed ADCs. Flash ADCs are good in
terms of speed and scalability but the exponential growth on their size with resolution
makes them limited to low resolution applications.

Folding and Subranging ADCs

present similar performances (Subranging ADCs seem to be more efficient) but they
suffer from scalability. Time-interleaved ADCs do not have a significant speed limit as
more ADCs can be theoretically interleaved to boost the sampling rate. They can also be
more efficient than other high speed ADC types.

However, they require robust

calibration schemes as unit ADCs may suffer from mismatches.

To conclude, different topologies have different advantages and disadvantages among
each other and it is hard to call a topology as the best. However, a good design choice
can be made. For resolutions above 5 bits and sampling rates greater than 1.5GS/s, timeinterleaved ADCs appear to be more advantageous. On the other hand, robust calibration
schemes should be considered to keep the performance at the desired level.

60

CHAPTER IV

4. SAR ADCs
A few decades ago, analog design was easier than it is today since analog designers did
not have to deal with todays short-channel problems, poor analog performance, small
headroom issues, and high device mismatches. However, at that time, capacitors were
occupying too much die area and were lower quality than those of todays standards.
Consequently, it shouldnt be surprising that Pipeline ADCs were dominating over
Successive-Approximation-Register (SAR) ADCs as designing high-speed, highbandwidth, large-swing operational amplifiers was a better design choice than
implementing large capacitor arrays with poor quality. Thus, SAR ADCs had to sit on
the bench until their time came. As the CMOS technology evolved and golden age of
analog designers diminished, analog design became a very challenging task, forcing
designers to utilize digital solutions as much as they could. At the same time, capacitors
became better in terms of quality and area. As a result, SAR ADCs started attracting
analog designers as they turned out to be a good candidate for the ADCs of future
technologies.
Chapter III covered high speed ADC topologies in detail but did not go through SAR
ADCs as they belong to low-to-medium speed, medium-to-high resolution converters
group.

However, their highly digital-friendly architecture and impressive power

efficiency make them very well suited for time-interleaving applications especially in
sub-100nm CMOS technologies in which scalability is a primary concern. Thus, timeinterleaved SAR ADCs started to be commonly used in high-speed communication
systems.

61

This chapter covers SAR ADCs, their architecture, operating principle, advantages,
disadvantages, and their state-of-the-art performance based on recent publications.
Section 4.1 gives a general overview on SAR ADCs by explaining the basics of the
architecture and the operation. Section 4.2 goes over SAR ADCs with binary-weighted
capacitive DAC thoroughly including their architecture, operation, advantages and
disadvantages, and the state-of-the-art performance. Finally, Section 4.3 covers SAR
ADCs with C-2C DAC. This section initially gives information on C-2C DACs and then
explains the possible usage of them in SAR ADCs. Then a comparison is carried out
between SAR ADCs with C-2C DAC and their binary weighted counterparts. A small
discussion on the state-of-the-art performance of C-2C SAR ADCs is also presented at
the end of the chapter.

4.1. Architecture and Operation

Figure 4.1 shows the simplified block diagram of a general SAR ADC which is
composed of an input sampling network (T&H), a comparator, a Digital-to-Analog
Converter (DAC) and a digital controller (SAR Logic).

The DAC has the same

resolution as the ADC.

T&H
Comp

VIN

SAR
LOGIC

DAC

Figure 4.1: Block diagram of a SAR ADC

62

Output
Data

SAR ADCs perform a conversion in multiple clock cycles. At each cycle, decision of a
single-bit is carried out and one clock cycle is generally dedicated for input sampling.
Consequently, an N-bit conversion takes totally N+1 clock cycles, keeping in mind that it
is also possible to dedicate more than one clock cycle for sampling. Figure 4.2-a presents
the SAR ADC algorithm for a 3-bit conversion. As the first step, input is sampled by the
T&H. Then, the SAR logic and the DAC generate Vref/2 at the DAC output where Vref
represents the reference voltage and 0-Vref range is the dynamic range of the input signal.
The comparator compares the input voltage with Vref/2 and if the input is greater, the
MSB is decided as 1, otherwise 0 is assigned for the MSB.

Figure 4.2: a) SAR ADC algorithm for a 3-bit conversion b) Flow chart of SAR ADC
algorithm
After the MSB decision is over, the MSB-1 decision takes place according to the result of
MSB. If the MSB is 1, then the SAR logic makes the DAC output 3Vref/4, otherwise
DAC output goes down to Vref/4. Since the T&H output is kept unchanged, comparator
compares the same input signal with the updated DAC output and based on the
comparator decision, the MSB-1 is set as 1 or 0. Similarly, the LSB decision is carried
out at the end, based on the result of the MSB-1. The SAR algorithm is also summarized
in Figure 4.2-b as a flow chart.
Figure 4.3-a illustrates an example which shows the timing and the T&H and DAC
output waveforms of a 3-bit SAR ADC for a particular conversion period. A detailed

63

timing diagram is presented in Figure 4.3-b but it should be noted that different timing
diagrams are also possible.

Figure 4.3: a) Timing and signal waveforms of a 3-bit SAR ADC b) Detailed timing
diagram of a SAR ADC
The most critical block in a SAR ADC is the DAC, which can be implemented with
many different well-known techniques. However, the most widely used DAC topology
in SAR ADCs is the charge-redistribution based capacitive array [63], as capacitive
arrays do not dissipate static power and improve the power efficiency significantly. The
most common capacitive DAC is the binary-weighted one and it is covered in detail in
the next section. The C-2C architecture is another way to implement a capacitive DAC
and is covered in Section 4.3.

4.2. SAR ADC with Binary-Weighted Capacitive DAC

This section goes over SAR ADCs with binary weighted capacitive DACs by covering
their architecture and operation, as well as the state-of-the-art performance based on
recent publications in the literature. The advantages and drawbacks are also presented .in
this section.

64

4.2.1.

Architecture and Operation

Figure 4.4 shows the schematic of a SAR ADC with binary-weighted capacitive DAC,
the most widely used SAR ADC topology in literature. The binary-weighted capacitive
DAC is composed of capacitors with sizes ranging from 2N-1*CU to 20*CU (N is
resolution of the converter) with an additional unit capacitor at the rightmost side of the
array, making the summation of the sizes of all capacitors equal to 2N*CU.

The

capacitors of the DAC are utilized also for input sampling implicitly, thus there is no
need for an external T&H in this topology.

Figure 4.4: Schematic of a SAR ADC with Binary-Weighted Capacitive DAC

The operation can be explained as follows:
1) Sampling is done by connecting all of the capacitors to the input while SReset resets the
common node of the DAC (node A in Figure 4.4). Thus, the total charge stored in the
capacitors after sampling is equal to 2N*CU*VIN.
2) SReset becomes floating and all the switches except SN (connected to the biggest
capacitor 2N-1*CU) are switched to ground. SN switches to VREF. As there is no current
path for capacitors, the total charge after input sampling is still preserved which can be
written as:
2 . CU V I. = 2 . 1 CU (V REF V A ) +
1
424
3
biggest capacitor

2 . 1 CU
1
424
3
total

65

size of

the rest

(0 V A )

Eq. 4.1

Thus, the voltage at node A after this switching can be found as:
V
2 . 1 V REF 2 . V I.
V A = REF V I.
.
2
2

VA =

Eq. 4.2

Consequently, the input signal will be compared with VREF/2 by the comparator, and the
MSB will be decided.
3) If the MSB is decided as 1, SN remains connected to VREF and SN-1 switches from
ground to VREF. Similarly, the total charge is preserved and the charge redistribution can
be written as:
2 . CU V I. = 2 . 1 CU (V REF V A )
1
424
3
biggest capacitor

2 . 2 CU
1424
3

+
Second

(V REF V A ) +

biggest capacitor

2 . 2 CU
1424
3
total

size of

(0 V A )

Eq. 4.3

the rest

which gives VA as:

VA =

3 2 . 2 V REF 2 . V I.
3V
V A = REF V I.
.
4
2

Eq. 4.4

As a result, VIN is compared with 3VREF/4 and the decision for the MSB-1 is carried out.
If the MSB is found as 0, then SN switches from VREF to ground while SN-1 switches to
VREF. The charge redistribution in this case is:
2 . 2 CU
1424
3

2 . CU V I. =
Second

(V REF V A ) + 2 . 1 + 2 . 2 CU (0 V A )
144
42444
3

biggest capacitor

total

giving VA as:

66

size of

the rest

Eq. 4.5

V
2 . 2 V REF 2 . V I.
VA =
V A = REF V I.
.
4
2

Eq. 4.6

Consequently, the input is compared with VREF/4 for the MSB-1 decision.
4) The same procedure is carried out for all bits to get the N-bit output.
As the common node of the capacitor array (node A) remains floating during the charge
redistribution process, any parasitic capacitor at this node can influence the charge
sharing. If the total parasitic capacitance at this node is considered as CP, then the charge
redistribution equation of the MSB given in Eq. 4.1 can be updated as (the total charge
after sampling is still the same):
2 . CU V I. = 2 . 1 CU (V REF V A ) +
1
424
3
biggest capacitor

2 . 1 CU
1
424
3
total

size of

(0 V A ) C PV A

Eq. 4.7

the rest

and, the voltage at node A becomes:

2 . 1 VREF 2 . VI.
C
V A = 1 + . P
VA =
C
2 CU
2. + P
CU

VREF

VI.

Eq. 4.8

It can be seen that the comparison is still carried out between VREF/2 and VIN, hence the
MSB decision is correct. Moreover, it can be shown that this case is also true for all bit
decisions.

The parasitic capacitance causes only a small attenuation factor for the

comparator input voltage which is a minor concern as long as the comparator has high
enough gain to keep the BER low. This parasitic capacitance immunity feature of the
binary weighted capacitive DAC enables this SAR ADC topology to achieve resolutions
more than 10 bits.

67

Moreover, this architecture is very well-suited for sub-100nm CMOS technologies as the
analog components are a comparator, switches, and capacitors while the rest is a digital
controller. Comparators become faster with new technologies as the regeneration time
constant is directly proportional with the unity gain frequency of the process. Switch onresistance reduces with CMOS scaling and matching and density of Metal-FingerCapacitors in digital CMOS processes improve steadily. Consequently, besides their
power efficiency, SAR ADCs are highly scalable and digital-friendly, making them a
good candidate for time-interleaved applications.
On the other hand, SAR ADCs with binary-weighted capacitive DAC have severe
bandwidth and speed limitations due to three reasons:
(1) All the capacitors should be connected to the input during the input sampling phase,
creating a total capacitive load of 2N*CU.
(2) DAC size increases exponentially with the resolution.
(3) Big capacitors (such as 2N-1*CU) have to be charged or discharged for the decision of
the MSBs.
The bandwidth problem becomes essential especially in high-speed wide-bandwidth
time-interleaved applications. As a simple example, for an input bandwidth around 1
GHz and 7-bit resolution, assuming a reasonable switch-on resistance, the required unit
capacitor size shouldnt exceed a few fFs, which is hard to implement due to poor
matching. A separate front-end T&H can be used to eliminate this problem with the
penalty of increased complexity and power dissipation [62].

4.2.2.

State-of-the-Art Performance of SAR ADCs with BW DAC

As mentioned before, SAR ADCs belong to low-to-medium speed, medium-to-high

resolution converters group which covers a huge application area.

Thus, their

performance varies a lot. As an example, a 10b 1MS/s SAR ADC with a FoM of
4.4fJ/conversion-step was published in 2008 [13]. But, this can not be taken as the startof-the-art performance as the main focus here is SAR ADCs that can be utilized in high-

68

speed applications and a 1MS/s converter does not belong to this group. Thus, only timeinterleaved or those that can be used in time-interleaved applications are considered here.
Figure 4.5 shows the state-of-the-art performance of time-interleaved SAR ADCs with
binary-weighted capacitive DAC published in the last 5 years [55-56, 60-62, 64-65]. As
seen from the red dashed line, for resolution*speed>15 Bits*GS/s, it is hard to keep the
FoM below 0.5-0.8pJ/conv-step.

TI SAR ADC State-of-the-Art Performance

1.1

FoM (pJ/conversion-step)

1
0.9
0.8
0.7
[3]
0.6
0.5
0.4

[2]

[1] ISSCC 2006 - 0.13um

[2] PRIME 2006 - 90nm
[3] JSSC 2008 - 0.13um

0.3
[1]
0.2

5
10
15
Resolution * Speed (Bits * GS/s)

20

Figure 4.5: State-of-the-Art Performance of Time-Interleaved SAR ADCs. [55-56, 6062, 64-65]
As a final note, although not time-interleaved, two recently published SAR ADCs with
potential on being utilized in high-speed applications are: 1) a 9b, 50MS/s SAR ADC
achieving a FoM 65fJ/conv-step [66] and 2) a 9b, 40MS/s SAR ADC achieving a FoM of
54fJ/conv-step [67].

69

4.3. SAR ADC with C-2C Capacitive DAC

The exponential increase in the size of a binary-weighted capacitive DAC might be a
serious problem. However, a capacitive DAC can be also implemented using a C-2C
topology as an analogy to the widely-known R-2R ladder, and can be utilized in a SAR
ADC instead of its binary-weighted counterpart. This section initially explains C-2C
DACs

separately by covering their architecture,

operation,

advantages,

and

disadvantages. Then the possible usage of them in SAR ADCs is discussed and the stateof-the-art performance is presented at the end.

4.3.1.

Architecture and Operation of C-2C DAC

An alternative solution to a binary-weighted DAC is a two-staged binary weighted

capacitive network [68] (an 8-bit example is shown in Figure 4.6) which reduces the
silicon area considerably by utilizing two coupled N/2-bit Binary-Weighted DACs to
implement an N-bit converter.

Figure 4.6: Schematic of an 8-bit two-stage Binary-Weighted Capacitive DAC

As an obvious improvement to this approach, each sub-DAC can further be divided into
smaller sections, eventually giving the C-2C DAC architecture [69-74] at the limit, which
is analogous to an R-2R ladder.

70

Ceq3
SR

SR

Ceq2 Ceq1

SR

SR

out
CU

CU
SN

2CU
SN-1

CU

2CU
Node B

CU

2CU

S2

CU

S1

VREF
MSB

LSB
Figure 4.7: Schematic an ideal C-2C DAC

Figure 4.7 shows an ideal C-2C DAC schematic. The parallel and the series connections
keep the capacitor ratio inside the DAC always constant; preserving the desired radix and
the last unit capacitor on the leftmost side is included to terminate the array properly.
The operation can be briefly explained as follows (SAR algorithm):
1) Initially, all reset switches, SRs, reset the intermediate nodes and the output of the
DAC, and all bottom switches, S1-SN, are connected to ground.
2) Reset switches become floating and S1 switches to VREF. It can be easily shown that
Ceq1 is equal to CU. Thus, the charge redistribution between Ceq1 and the unit capacitor
connected to S1 leads to VREF/2 at the output.
3) If VREF/4 is intended to be obtained at the output, S1 returns back to ground which
makes the DAC output zero again and S2 switches to VREF. Similarly, Ceq3 is equal to CU
and Ceq2 is equal to 2CU/3. After charge distribution, the voltage at node B becomes:

VB =

CU
1
3
V REF =
V REF = V REF
8
CU + C eq 2 + C eq 3
1+1+ 2
3

Consequently, the output voltage is found as:

71

Eq. 4.9

Vout =

2CU
2 3
1
VB = VREF = VREF
3 8
4
CU + 2CU

Eq. 4.10

If 3VREF/4 is desired at the output after VREF/2, then S1 should stay at VREF while S2
switches to VREF. This adds VREF/4 to the output voltage and makes it 3VREF/4.
4) Similar steps can be carried out to generate other voltages at the output.
As seen, the size of the C-2C DAC increases linearly with the resolution, thus occupying
less area then a binary-weighted DAC. Moreover, the capacitor sizes are fixed and small,
making the switches see the same small capacitive load, thus easing the switch design as
well as the layout, since the entire topology is composed of the replicas of a small C-2C
block. Moreover, there is no need for charging or discharging large capacitors, making
the DAC faster than a binary-weighted one.

Figure 4.8: Parasitic capacitance problem in C-2C DACs

On the other hand, unlike the binary-weighted capacitive DAC, C-2C DACs have a major
disadvantage due to the parasitic capacitances at the intermediate nodes inside the DAC
as presented in Figure 4.8. The parasitic capacitances at these nodes shift the capacitor
ratios and change the radix, which can be a severe resolution limit if not calibrated
properly. Moreover, the radix is not only modified but also becomes bit-dependent the
radix is different for each output bit making the digital calibration extremely hard to

72

realize without modifying the DAC topology. Four previously published solutions to this
issue are: (1) connecting the parasitic capacitances to the decision bits in such a way that
the overall radix and the linearity are preserved [69], (2) keeping the radix at 2 by
adjusting the capacitor ratio from C-2C to C-2C where is an arbitrary and generally
non-integer number [70], (3) using a non-binary radix and performing digital calibration
[73], and (4) using advanced processes with minimum parasitic capacitance to mitigate
the problem [74]. The first approach results in a very complex switching network and it
only addresses to a certain type of parasitic capacitance. In the second approach,
generally ends up being an arbitrary non-integer number, which can have severe
implementation issues and might need large number of unit capacitors.

Since the

capacitor matching becomes worse as the size reduces, unit capacitors have a minimum
size limit and this can increase the capacitive loading significantly. In the third approach,
similarly, the parasitic capacitors can be estimated and the capacitor sizes can be adjusted
in such a way that the overall radix of the DAC can be kept fixed but smaller than 2,
including the parasitics. Then the binary output can be obtained using digital calibration.
This approach gives a degree of freedom for picking a realizable capacitor ratio, .
However, it requires additional clock cycles to compensate for the information loss due to
non-binary radix and slows down the conversion rate, which is not desired for timeinterleaved applications. In addition, digital calibration requires multipliers which are
hard to implement. Finally, the last approach uses the advantage of an advanced process
quartz substrate which is not feasible for fully CMOS applications.
A robust and efficient calibration for radix correction is a key point for improving C-2C
DACs. As mentioned above, none of the previously published techniques possess this
robustness, and they are

generally limited with low-to-medium resolutions.

Consequently, C-2C DACs are still not as popular as their binary-weighted counterparts,
although they have potential on improving the speed and the bandwidth by occupying a
smaller area.

73

4.3.2.

SAR ADC with C-2C DAC

As there is no constraint for the DAC shown in the block diagram of the SAR ADC in
Figure 4.1, a C-2C DAC can be directly used in the converter. But in this case, a separate
T&H is required [71]. A better solution is to merge the T&H with the DAC as in the case
of a conventional SAR ADC with Binary-Weighted DAC, which can be performed by
including the sampling switches as shown in Figure 4.9.

Figure 4.9: Inclusion of input sampling switches to the C-2C DAC

This makes a C-2C DAC as compatible with SAR ADCs as a Binary-Weighted DAC.
Moreover, a C-2C DAC has 3 major advantages when compared with its binary weighted
counterpart:
(1) The DAC size increases linearly with the resolution.
(2) The capacitive input loading is fixed, small generally a few unit capacitors, and
independent of the resolution on the first order, consequently the bandwidth is superior.
(3) The loading at each intermediate node inside the DAC is also fixed and small, making
the DAC faster and the switch design easier. Consequently, SAR ADCs with C-2C DAC
have the potential to achieve higher speeds and wider bandwidths while occupying less
area.
On the other hand, the parasitic capacitance problem causes a severe accuracy limitation
and it is hard to achieve high resolutions with this topology. However, high speed

74

communications systems generally require medium resolutions, thus making SAR ADCs
with C-2C DAC still well-suited for these applications.
Besides, even though the capacitive loading can be reduced by using a C-2C DAC in a
SAR ADC, the number of switches connected to the input still remains nearly the same.
Approximately N input sampling switches are still needed for an N-bit converter, and
especially in LP Digital CMOS processes with transistors having very high VTs, these
switches are not simple NMOS or PMOS devices, but rather boosted or bootstrapped
topologies which might have considerable parasitic capacitance.

Furthermore, the

situation becomes worse in time-interleaved schemes where M converters are working in

parallel. In this case, approximately M*N switches are connected to the input. This can
be a more dramatic bandwidth problem than the actual input capacitive load of the DACs.
This issue has not been addressed effectively in the literature expect using a separate
front-end T&H which drives all the ADCs. Such T&Hs have to operate at the speed of
the converter, need very high power dissipation, and have to drive a huge capacitive load
as they drive the overall ADC. In some cases, special processes rather than a LP digital
CMOS process are required to implement these sampling circuitries.

4.3.3.

State-of-the-Art Performance of SAR ADCs with C-2C DAC

Unlike other converter groups, it is hard to give a chart that shows the recently published
state-of-the-art performance of SAR ADCs with C-2C DAC as there are not many
published converters in the literature.

However, as a reference, one of the most

promising results achieved with a similar topology is presented in [61, 73] in which a 6bit 600MS/s time-interleaved SAR ADC is designed achieving a FoM of
0.22pJ/conversion-step. Although, the architecture is asynchronous and the DAC is a CkC DAC where k is an arbitrary number rather than 2, the result can still be taken as a
good reference for the performance of this kind of topologies. Moreover, a recently
published work based on a low speed (137kS/s), high resolution (10-bit) SAR ADC with
C-2C DAC presents a FoM of 0.24pJ/conversion-step [72].

75

CHAPTER V

5. TIME-I!TERLEAVI!G
Digital signal processing has been a very robust and effective tool during the last several
decades with the advances in CMOS technology. In mixed signal systems with analog
inputs, such as those in wireless telecommunication applications, analog-to-digital
conversion is the key function that enables digital signal processing. However, the
improvement in the performance of ADCs is lagging the achievements in digital CMOS
technologies and digital signal processing systems operating on analog inputs are often
limited by the sampling rates of the converters. Even the state-of-the-art very high speed
converters with extremely high power dissipations may not be sufficiently fast for some
applications.
Time-interleaving [75] is a well-known promising solution to this issue as it makes a
certain number of ADCs work in parallel to achieve sampling rates that can not be
practical with a single ADC while keeping the power dissipation in acceptable levels.
Ideally, if N ADCs with sampling rate fs are time-interleaved, the overall sampling rate
can be N*fs without any degradation.
On the other hand, the performance of time-interleaved ADCs is very sensitive to
mismatches among converters as well as the aperture errors among the channels. If these
problems are not calibrated properly, undesired spurs over the signal spectrum can
degrade the performance significantly. This chapter thoroughly covers the problems of
time-interleaving and their detection and calibration schemes.

Section 5.1 gives an

overview on problems degrading SNR in time-interleaved systems. Section 5.2 goes

76

through the offset mismatch issue in detail. Similarly, Section 5.3 explains the gain
mismatch in time-interleaved ADCs. The clock skew problem is discussed in Section
5.4. A rather new concept, bandwidth mismatch in time-interleaved ADCs, is covered in
Section 5.5. Finally, Section 5.6 gives a brief discussion on jitter.

5.1. Time-Interleaving Problems

Non-idealities causing SNR degradation in time-interleaved converters can be classified
in five items:
1) Offset mismatch
2) Gain mismatch
3) Clock skew
4) Bandwidth mismatch
5) Jitter
The first four items are deterministic and they arise from the mismatches among ADCs.
It should be noted that, as long as the parameters of ADCs match, there will not be any
degradation due to time-interleaving. As an example, all of the converters might have an
offset but time-interleaving will not degrade the performance if all the offsets are
identical to each other.
Jitter is a random process and does not emerge due to time-interleaving and it can
influence the performance of any type of converter as it is a fundamental and inevitable
outcome of noisy circuits. However, it might be more problematic for time-interleaving
architectures as they can operate at very high speeds, requiring high-frequency clocks
with small jitter.

77

Table 5.1 gives the dependence of deterministic mismatch errors (jitter is not
deterministic) on input signal amplitude and frequency

Table 5.1: Dependence of deterministic mismatch errors on input signal amplitude and
frequency

Input

Offset

Gain

Mismatch

Mismatch

Independent

Linearly

Linearly

Nonlinearly

dependent

dependent

dependent

Independent

Linearly

Nonlinearly

dependent

dependent

Amplitude
Input

Independent

Clock Skew

Frequency

Bandwidth
Mismatch

Each of these items is discussed in detail in the coming sections including analyses
showing performance degradation, detection methods, and calibration schemes.

5.2. Offset Mismatch

Offset mismatches contribute a periodic additive pattern to the output of the ADC array.
For simplicity, if only two ADC having different offsets are assumed to be timeinterleaved as given in Figure 4.1, and considering that all the other parameters are ideal
while the input is a sinusoid, cos(t+), then the outputs of the ADCs can be written as
[76]:
y1 y[n] = cos(nT + ) + VOS1

y 2 y[n] = cos(nT + ) + VOS 2

n = even
n = odd

Eq. 5.1

where T is the sampling period of the overall converter. Here the quantization error is
also ignored to ease the analysis.

78

Figure 5.1: Two time-interleaved ADCs with different offsets

Considering Eq. 5.1, the output of the converter can be expressed as

y[n ] = cos(nT + ) + VOS + ( 1)

VOS
2

Eq. 5.2

where, VOS=0.5(VOS1+VOS2) and VOS=VOS1-VOS2. Note that S=2/T and (-1)n is also
equal to:

( 1)n

= cos( S nT / 2 )

Eq. 5.3

Consequently, the output becomes,

y[n ] = cos(nT + ) + VOS +

VOS

cos S nT
2

Eq. 5.4

As seen in Eq. 5.4, the second and the third terms show that offset mismatch contributes
to a DC term and a periodic additive pattern as a tone at half of the overall sampling rate
at the output. Moreover, these terms do not depend on the amplitude or the frequency of
the input. A Simulink model of the two-channel time-interleaved ADC was implemented
with only offset mismatch. Figure 5.2 presents the time-domain output waveform of this
ADC model with offset mismatch problem and the corresponding error voltage. As seen,
the error term is independent of the input signal.

79

10

5
Voltage (V)

Output

Error due to
Offset
Mismatch

-5

-10
0

50

100
Time (Sec)

150

200

Figure 5.2: Output waveform of a two-channel time-interleaved ADC with different

unit ADC offset and the corresponding error voltage

100
Input
Signal

50

Tone due
to Offset
Mismatch

Signal Power (dB)

0
-50
DC
term
due to
Offset
Mismatch

-100
-150
-200
-250
-300

0.1
0.2
0.3
0.4
Normalized Frequency (0=> FS/2)

0.5

Figure 5.3: Simulated output spectrum of the Simulink model of two-channel timeinterleaved ADC with different offsets

80

In addition, Figure 5.3 presents the output spectrum of the same ADC model when the
input signal frequency is chosen as 0.1*FS and coherent sampling is performed without
windowing. Tones at DC and FS/2 can be observed due to offset mismatch.
If the analysis is extended to more than two ADCs, it can be found that offset errors cause
distortion at the frequencies [77]:
k
S
M

k = 1,..., M 1

Eq. 5.5

where S is the sampling frequency of the overall time-interleaved converter and M is the
number of converters used for interleaving. Note that the DC term may or may not exist
depending on the offsets of the converters.

Figure 5.4 shows the simulated output

spectrum of the Simulink model of a four-channel time-interleaved ADC with different

offsets when the input signal frequency is 0.05*FS. Tones at FS/4 and FS/2, and a DC
term can be seen at the output.

100
Tones due to Offset Mismatch
50

Signal Power (dB)

Input
Signal

-50
-100
-150
-200
-250
-300

0.1
0.2
0.3
0.4
Normalized Frequency (0=>FS/2)

0.5

Figure 5.4: Simulated output spectrum of the Simulink model of a four-channel timeinterleaved ADC with different offsets

81

Offset mismatch can be detected and calibrated using extra ADCs [78]. As the matching
of the offsets is critical, a reference ADC can be picked and all the other ADC offsets can
be matched to the offset of the reference converter. With extra ADCs this can be done in
the background as the ADC under calibration can be removed from the array while the
other converters perform the normal operation. A simplified LMS algorithm [78] can be
used for estimating the offset difference. Either special inputs or the actual input of the
converter can be used depending on the calibration scheme.
Alternatively, the input signal of the ADC can be multiplied with a random sequence of 1
and -1 [79]. This method spreads the input spectrum and also transforms the spectrum of
the offset into white noise. Eventually a DC term showing the offset of the converter can
be achieved by demodulation and proper filtering.
Moreover, if the input signal is known to be modulo M quasi-stationary, meaning the
signal has a constant mean and this value is same for all converters, it is possible to
eliminate the offset by checking the means of every unit ADC output and equating them
to each other [77]. This technique can also be done in the background.

5.3. Gain Mismatch

Gain mismatches among the parallel channels causes amplitude modulation of the input
samples by the sequence of the converter gains. Again, for simplicity, if a two-channel
time-interleaved ADC with different unit converter gains is taken into account as given in
Figure 5.5, assuming that the other parameters are ideal and the input is a sinusoid,
cos(t+), then the outputs of the unit ADCs become:
y1 y[n] = G1 cos(nT + )

y 2 y[n] = G 2 cos(nT + )

82

n = even
n = odd

Eq. 5.6

where T is the sampling period of the overall converter. Again, the quantization error is
also ignored to ease the analysis.

Figure 5.5: Two time-interleaved ADCs with different gains

Similar to the case in offset mismatch, the overall ADC output can be expressed as:

n G
cos(nT + )
y[n ] = G + ( 1)
2

Eq. 5.7

where, G=0.5(G1+G2) and G=G1-G2. Again keeping in mind that S=2/T and (-1)n is
equal to:

( 1)n

= cos( S nT / 2 )

Eq. 5.8

the output becomes,

cos S nT cos(nT + )
y[n ] = G +
2

cos S nT cos(nT + )
= G cos(nT + ) +
2

Eq. 5.9

If only terms in the Nyquist band are taken into account and simple trigonometric
relations are used, then Eq. 5.9 can be also written as:

83

y[n ] = G cos(nT + ) +

G
cos S nT +
2
2

Eq. 5.10

As seen in Eq. 5.10, the second term shows the tone due to gain mismatch. This term is
similar to an image and it depends on the input frequency of the signal but independent of
the input amplitude.
The Simulink model of the two-channel time-interleaved ADC was also updated to
observe the influence of the gain mismatch. Figure 5.6 shows the time-domain output
waveform of the ADC and the error voltage due to gain mismatch. It can be clearly seen
that the error waveform strongly depends on the input signal frequency, as the largest
error occurs at the peaks of the sine wave. As the amplitude of the error is modulated by
the input signal, this case is similar to Amplitude Modulation (AM).

15
Output
10

Error
Due to Gain
Mismatch

Voltage (V)

-5

-10

-15

50

100
Time (Sec)

150

200

Figure 5.6: Output waveform of a two-channel time-interleaved ADC with different

unit ADC gains and the corresponding error voltage

84

Figure 5.7 presents the output spectrum of the same two-channel time-interleaved ADC
when the input signal frequency is chosen as 0.1*FS and coherent sampling is performed
without windowing. The undesired tone at 0.4*FS can be observed due to gain mismatch.
This frequency can be also written as:

S
2

Eq. 5.11

where is the input signal frequency. This result was also shown above during the
analysis of gain mismatch.

100
Input
Signal

50

Signal Power (dB)

0
-50
Tone due
to gain
mismatch

-100
-150
-200
-250
-300

0.1
0.2
0.3
0.4
Normalized Frequency (0=>FS/2)

0.5

Figure 5.7: Output spectrum of the same two-channel time-interleaved ADC with
different unit ADC gains
In the case of more than two time-interleaved ADCs, it can be shown that the gain errors
cause distortion at the frequencies [77]:

85

k
S
M

k = 1,..., M 1

Eq. 5.12

where S is the sampling frequency of the overall time-interleaved converter and M is the
number of converters used for interleaving. Figure 5.8 shows the simulated output
spectrum (after coherent sampling with no windowing) of the Simulink model of a fourchannel time-interleaved ADC with different gains when the input signal frequency is
0.05*FS. The tones at 0.2*FS (=FS/4 Fin), 0.3*FS (=Fin + FS/4), and 0.45*FS (=FS/2
Fin) can be seen at the output.

100
Input
Signal

50

Tones due to Gain Mismatch

Signal Power (dB)

0
-50
-100
-150
-200
-250
-300
0

0.05

0.1
0.2
0.3
0.4
Normalized Frequency (0=>FS/2)

0.45

0.5

Figure 5.8: Output spectrum of a four-channel time-interleaved ADC with different

unit ADC gains
Gain mismatch can be detected and calibrated in similar ways with offset mismatch and
they are generally calibrated together. Extra ADCs can be used again for detection and
calibration [78]. Using a reference ADC, all the other ADC gains can be matched to the

86

offset of the reference converter. This can be done at the background due to extra ADCs.
Either special inputs or the actual input of the converter can be used depending on the
calibration scheme.
As in the case of offset error, the input signal of an ADC can be multiplied with a random
sequence of 1 and -1 [79] which spreads the input spectrum and also transforms the
spectrum of the offset into white noise. A DC value can be added to the input of the
converter after it is multiplied with the random sequence. Consequently, a DC term can
be achieved by demodulation and proper filtering. This DC term will include both the
offset and the DC value added to the input multiplied with the gain of the converter. If
the offset error is already calibrated, only the term associated with the gain will remain.
Similarly, if the input signal is known to be modulo M quasi-stationary, which also
means the signal has an auto-correlation function which is independent of the time but
only depends on the time difference between the samples and this function is same for all
converters, it is possible to eliminate the gain error by checking the variance of every unit
ADC output and equating them to each other [77].

5.4. Clock Skew

If the overall sampling period of an M-channel time-interleaved ADC is FS, then each
unit ADC should sampling the input at time instants equally spaced with M/FS. Figure
5.9-a shows an example of perfectly aligned clocked phases for a 4-channel timeinterleaved ADC. As seen, the overall ADC samples at every 1/FS, while individual
clock phases have a period of 4/FS. On the other hand, Figure 5.9-b gives a similar
example with the clock skew problem and it can easily be observed that the sampling
instants deviate from the ideal case and they are no longer equally spaced.

This

corresponds to a non-uniform sampling and [80-82] give a detailed analysis on this

phenomenon.

87

Figure 5.9: a) Perfectly aligned clock phases of a 4-channel time-interleaved ADC b)

Clock phases with clock skew problem
Due to clock skew, input samples are phase modulated by the sequence of the timing
mismatches of the ADC channels. The two-channel time interleaved case is taken into
account again with only clock skew problem this time, as shown in Figure 5.10. As only
the alignment between the clock phases matters, without losing the generality, it can be
assumed that clk1 is sampling at the right time instants but clk2 is deviated by dt. In this
case, the outputs can be written as

y1 y[n] = cos(nT + )

n = even

y 2 y[n] = cos(nt + ) t = nT + dt

n = odd

Eq. 5.13

where T is the sampling period of the overall converter. Again, the quantization error is
ignored to ease the analysis.

88

Figure 5.10: Two time-interleaved ADCs with clock skew problem

By combining the two ADC outputs, the overall ADC output can be expressed as:

dt
n dt
y[n ] = cos(nt + ) t = nT + dt (1)n dt = cos nT + ( 1)
+
2
2
2
2

Eq. 5.14

Using the basic trigonometric relation:

cos( A B ) = cos( A) cos(B ) + sin ( A)sin (B )

Eq. 5.15

the expression in Eq. 5.14 can be modified as:

dt

n dt
y[n ] = cos nT + + cos ( 1)
+
2
2

dt

n dt
+
+ sin nT + + sin ( 1)
2
2

Eq. 5.16

Using the facts that cosine is an even and sine is an odd function, and (-1)n is equal to:

( 1)n

= cos(n )

the expression in Eq. 5.16 can be written as:

89

Eq. 5.17

 dt

dt
y[n ] = cos nT + + cos

2
2

dt
dt
+ sin nT + + cos( )sin

2
2

Eq. 5.18

Using the two equations given below:

dt

dt
sin
n = cos( )sin

&

S nT
2

= n

Eq. 5.19

the output expression can be further modified as:

dt
dt
y[n ] = cos
cos nT + +
2
2

dt nT
dt
+ sin
+
sin nT + S
2
2
2

Eq. 5.20

and finally,
dt
dt

y[n ] = cos
cos nT + +
2
2

dt
dt
+ sin
sin S nT + +
2
2
2

Eq. 5.21

The first term in Eq. 5.21 represents the actual input samples which have a small
amplitude modulation due to the clock skew. The second term stands for the tone due to
clock skew. It has the same frequency with the tone due to gain mismatch but there
exists a 90 phase shift. Moreover, the error due to clock skew depends on both the
frequency and the amplitude of the input signal. If the deviation in the clock phases, dt,
is assumed to be small, the approximations given below can be used:

90

 dt
dt dt
cos
1 & sin

2
2
2

Eq. 5.22

Consequently, Eq. 5.21 further simplifies as:

dt
dt

dt S
nT
y[n ] cos nT + +
sin
2
2
2

Eq. 5.23

The Simulink model of the two-channel time-interleaved ADC was also used to
investigate the clock skew problem.

Figure 5.11 shows the time-domain output

waveform of the ADC and the error voltage due to clock skew. Similar to the gain
mismatch case, it can be clearly seen that the error waveform strongly depends on the
input signal frequency, but in this case the largest error occurs at points where the slope
of the sine wave peaks which are the zero-crossing regions. This behavior of the error
term is like Phase Modulation (PM).

10
Output
Error Due
to Clock
Skew

Voltage (V)

-5

-10

50

100
Time (Sec)

150

200

Figure 5.11: Output waveform of a two-channel time-interleaved ADC with clock

skew problem and the corresponding error voltage

91

Figure 5.12 gives the output spectrum of a two-channel time-interleaved ADC with clock
skew problem when the input signal frequency is chosen as 0.1*FS and coherent sampling
is performed without windowing. The undesired tone at 0.4*FS can be observed due to
clock skew. Similar to gain mismatch, this frequency can be also written as:

S
2

Eq. 5.24

where is the input signal frequency.

100
50
Input
Signal

Signal Power (dB)

0
-50

Tone due
to clock
skew

-100
-150
-200
-250
-300

0.1

0.2
0.3
0.4
Normalized Frequency (0=>FS)

0.5

Figure 5.12: Output spectrum of a two-channel time-interleaved ADC with different

clock skew problem
Exactly same as the gain mismatch, in the case of more than two time-interleaved ADCs
with clock skew problem, it can be shown that the clock skew causes distortion at the
frequencies [77]:

92

k
S
M

k = 1,..., M 1

Eq. 5.25

where S is the sampling frequency of the overall time-interleaved converter and M is the
number of converters used for interleaving. Figure 5.13 shows the simulated output
spectrum (after coherent sampling with no windowing) of the Simulink model of a fourchannel time-interleaved ADC with clock skew problem when the input signal frequency
is 0.05*FS. The tones at 0.2*FS (=FS/4 Fin), 0.3*FS (=Fin + FS/4), and 0.45*FS (=FS/2
Fin) can be seen at the output.

100
Input
Signal

50

Tones Due To Clock Skew

Signal Power (dB)

0
-50
-100
-150
-200
-250
-300
0

0.05

0.1
0.2
0.3
0.4
Normalized Frequency (0=>FS/2)

0.45

0.5

Figure 5.13: Output spectrum of a four-channel time-interleaved ADC with clock

skew problem
As the spurs due to clock skew are located exactly at the same frequencies as those of the
gain mismatch problem, initially the gain mismatch should be calibrated before
performing the timing alignment among ADCs.

93

Generally, the offset and gain

calibrations are performed first with similar calibration schemes and then the clock skew
calibration is carried out.
The easiest way to eliminate clock skew is to use a front-end T&H for the timeinterleaved ADC. This eliminates the necessity of the generation of different clock
phases and the distribution of clock signals over unit ADCs. However, in this case, the
T&H should operate at the speed of the overall converter and it has to drive the entire
ADC, which can be a severe speed and bandwidth limitation.
It is generally hard to detect and calibrate clock skew in the background.

In the

foreground, a known sinusoidal signal can be applied and the errors can be extracted
from the images in the output spectrum [80]. Alternatively, a ramp signal with a known
slope can be generated at the input and the difference of the unit ADC outputs can be
checked to estimate the error. This ramp signal can be added to the input (with zero
mean) to carry out the detection in the background with the penalty of reduction in the
headroom [83]. The clock skew error detection can be also carried out in the digital
domain using FIR filters and approximated Hilbert transform [77].
The calibration of the clock skew needs alignment of the clock phases. This can be done
in the analog domain using delay lines [84], or in the digital domain using FIR filters
[76].

5.5. Bandwidth Mismatch

Bandwidth mismatch is a rather new problem considered by designers which arises due
to distributed T&Hs. Each T&H can be represented as a simple RC circuit and the
variation in the R and the C values can change the bandwidth of the sampler. The
mismatch in the bandwidths will cause a gain and a phase variation at the output of each

94

T&H and can degrade the SNDR. Figure 5.14 illustrates this problem on a two-channel
time-interleaved ADC.

R1

C1

T&H

y1

ADC-1

analog
input

clk1
clk1

T&H

y2

ADC-2

digital
output

clk2

clk2
R2

C2

Figure 5.14: Two time-interleaved ADCs with different T&H bandwidths

The derivation of the effect of bandwidth mismatch is quite complicated and it can be
found in [85].

For a sinusoidal input, the output samples of a two-channel time-

interleaved ADC suffering from bandwidth mismatch can be written as:

T
y[n ] = G k ( ) A cos nTS + + k ( )
2

Eq. 5.26

where T=2TS, k=1 for n odd, k=2 for n even and

G k ( ) =

1 e T / 2 k jT / 2
1 e T / 2 k jT 1 + ( k )

k = 1,2

Eq. 5.27

k ( ) = Gk ( ) k = 1,2
With finite T&H bandwidths, using Eq. 5.26 for k=1 and k=2, the ADC output can be
written as [85, 86]:

95



T
T

y[n ] = BS cos nTS + + S + BS cos S nTS + + n

2
2

Eq. 5.28

where the first term is the input signal samples scaled by gain BS, and phase shifted by
S. The second term is an undesired tone due to bandwidth mismatch which appears at
an image frequency of S/2- similar to gain mismatch and clock skew problems. This
is expected as the bandwidth mismatch acts as a combination of gain and phase
mismatches. They are also called AC gain mismatch and AC phase mismatch since the
behavior depends on the input frequency.
Bandwidth calibration methods are in general very hard to implement and the easiest
solution is to eliminate the necessity of calibration by designing the T&Hs to have wideenough bandwidth. In this case, the bandwidth mismatch will not be a very critical
problem as the mismatches in the phase shifts and gains will be small. Alternatively, a
single front-end T&H can be utilized which will eliminate the mismatch problem
completely but this is also a very challenging task especially in LP digital CMOS
processes. Theoretically, a calibration scheme based on FIR filters is possible [85] but it
does not address the issue of distinguishing this problem for the gain mismatch and the
clock skew. If bandwidth mismatch exists, the gain and the clock skew calibrations can
be carried out first with special low-frequency inputs as in this case the bandwidth
mismatch will not be observed. Then the mentioned calibration scheme based on FIR
filters can be performed. However, this makes the gain and the clock skew calibration to
be done in the foreground with special input signals.

5.6. Jitter
The jitter problem is actually not an outcome of time-interleaving. Briefly, it is the
random changes on the clock edges due to device noise and random noise coupled from
the power lines and the substrate. Due to random jitter, additional error will result on the

96

sampled data. As this effect is random in nature, it tends the spread out the effect on the
whole output spectrum by raising the noise floor, reduces the SNDR [83].
However, as time-interleaved ADCs often operate at high speeds and the generation and
the distribution of low-noise, high-frequency clock signals with different phases are very
challenging tasks, jitter becomes a very serious problem for time-interleaved converters.
Figure 5.15 gives the change in the SNR with the input frequency and jitter for an ideal 7bit ADC. The same plot is redrawn in 2-D in Figure 5.16. The rapid decrease in the SNR
due to jitter can be observed easily, especially at high frequencies as the input slope is
high. In order to keep the SNR value above 35dB in this example, the rms jitter should
be at most 1 psec.

45
40

SNR (dB)

35
30
25
20
15
10
1.5
2
2.5
Input Frequency (GHz)

10

5
7.5 Jitter (psec)

2.5

Figure 5.15: SNR versus jitter and input frequency characteristic of an ideal 7-bit
ADC

97

45
40
35
SNR (dB)

Decreasing Input Frequency

30
25
20
15
10

4
6
Jitter (psec)

10

Figure 5.16: SNR versus jitter an ideal 7-bit ADC with different input frequencies (2D version of Figure 5.15)
As jitter is random and changes at every sample, it is very hard to calibrate it. The
designer has to be sure that the clock signal is clean enough for the application of interest.
Even though all the mismatch problems are calibrated effectively, jitter will be a
fundamental limit for the performance of the ADC.

98

CHAPTER VI

6. PROPOSED TIME-I!TERLEAVED C-2C SAR ADC

The proposed ADC was intended to be used in a 60GHz OFDM-based receiver and the
target specifications were 7-bit resolution with an ENOB higher than 5 bits for the entire
input bandwidth, sampling rate around 3GS/s with a wide input bandwidth covering the
overall Nyquist band, and a FoM less than 1pJ/conversion-step. The ADC was also
intended to be designed in a low power (LP) digital 45nm CMOS process. The target
specifications of the proposed ADC are also summarized in Table 6.1:

Table 6.1: Target specifications of the proposed ADC

Resolution

7 bits

ENOB

>5 bits

Sampling Rate

3 GS/sec

FoM

<1pJ/conv-step

Bandwidth

Nyquist

Supply

1.1V

Power Dissipation

<100mW

Process

45nm LP CMOS

As mentioned in the last part of Chapter III where state-of-the-art performances of

high-speed ADCs are presented and compared, time-interleaved ADCs appear to be more
efficient for this particular application. Moreover, the target speed is hard to achieve with
a single ADC and the target resolution is not feasible for a Flash converter. In addition,
the chosen CMOS process was not compatible with Folding and Subranging ADCs as
they suffer from scalability. Consequently a time-interleaved ADC topology was chosen
for the proposed converter.

99

The second decision was on the selection of the unit ADC for time-interleaving. Due to
the challenges of the chosen CMOS process, a digital-friendly and scalable solution was
mandatory and, as mentioned in Chapter IV, SAR ADCs are very well-suited for such an
application. As a result, the unit ADC was picked as a SAR converter.
The final decision was the selection of the DAC for the SAR converter. For the proposed
SAR ADC, the C-2C DAC approach was selected due to its potential for enhancing the
bandwidth and the speed as a front-end T&H with this target speed and bandwidth can
not be designed in this process.

Although a C-2C DAC suffers from parasitic

capacitances and can not achieve high resolutions, the target resolution was only 7 bits,
making the DAC selection still convenient for the application.

6.1. Overview of the Proposed C-2C SAR ADC

Based on the given specifications, a distributed T&H approach is essentially the only
proper design choice as a single front-end T&H design with almost 3GS/s sampling rate
and Nyquist bandwidth driving the overall time-interleaved ADC is impractical in a
45nm LP digital CMOS process. Hence, the unit SAR ADCs should have wide enough
bandwidth to cover the entire Nyquist bandwidth of the overall converter, although their
sampling rate is relaxed as it is divided by a factor equal to the total number of unit
ADCs.
As covered in Chapter IV, SAR ADCs with C-2C DAC have a high potential for
enhancing the bandwidth and the speed while occupying less area due to three reasons.
As a reminder, these are: (1) the DAC size increases linearly with the resolution, (2) the
capacitive input loading is fixed, small generally a few unit capacitors, and
independent of the resolution on the first order, consequently the bandwidth is superior,
(3) the loading at each intermediate node inside the DAC is also fixed and small making

100

the DAC faster and the switch design easier. Consequently, the C-2C DAC approach is a
better design choice than a conventional binary-weighted DAC.
However, the mentioned problems of C-2C DACs should also be addressed.

For

instance, the proposed design should also address the parasitic capacitance issue in an
effective and efficient way. In addition, the number of switches connected to the input
should be reduced to make the design suitable for time-interleaved architectures.

6.2. Architecture of the Proposed C-2C SAR ADC

Figure 6.1 presents the schematic of the proposed SAR ADC with the modified C-2C
DAC [87]. The C-2C DAC consists of two sets of switches, SAs and SRs, and three sets
of capacitors, CU/2, CU, and 2*CU. VMax and VMin represent the maximum and minimum
reference voltages, respectively. The last capacitor at the leftmost side, Ccal, and the
control voltage, Vcal, are included for calibration purposes and they will be discussed later

in this chapter.

Figure 6.1: Simplified schematic of the proposed C-2C DAC

101

It should be noted that, as a major difference from the conventional C-2C DACs, the
proposed DAC has switches at the intermediate nodes as well and these switches were
not included for only resetting the intermediate nodes at the initial phase. They take
place in the charge redistribution process for bit decisions and this plays an important role
because when an upper switch, i.e. one of SAs, is closed, any switching activity done by
the switches on the left of that particular closed switch has no contribution to the output.
This situation is shown in an example in Figure 6.2 where SA1 is connected to VMAX and
the node connected to this switch becomes a low-impedance node. Consequently, any
change at the nodes on the left side of this node (nodes marked with red) has no
contribution to the output.

Figure 6.2: Effect of upper switches

This feature can be used for calibration as the intermediate nodes on the left of the node
connected to the closed switch can be set to a desired initial value without changing the
output voltage. Moreover, this switch scheme also eliminates the necessity of having a
fully symmetric DAC in both left and right directions as the charge redistribution takes
place only towards the output of the DAC.

102

From the three sets of capacitors inside the DAC, only those with sizes CU and 2*CU are
implemented as Metal-Finger-Capacitors (MFC). The remaining capacitors with size
CU/2 represent the total parasitic capacitances at the intermediate nodes but they are also
included as an integral part of the DAC. Their values are adjusted to CU/2 by calibration
which is discussed in detail in Section 6.4.

As seen, the ratio of the capacitors

implemented as MFC is only 2 (CU and 2*CU) and the radix is still preserved even though
the parasitic capacitances are included. This ratio makes the array implementation fairly
easy.
In addition, the input sampling network is merged with the DAC to eliminate the
necessity of a separate T&H. As seen from the schematic in Figure 6.1, the input is
sampled by using only two switches; completely independent of the resolution, as
opposed to the conventional case where nearly N input sampling switches are necessary
for an N-bit converter. Moreover, the capacitive load at the input is still small and not
more than a few unit capacitors. These features of the proposed DAC improve the
bandwidth significantly especially for time-interleaved architectures as there is no frontend T&H in this topology and all the input sampling switches of the unit ADCs are
connected directly to the input.

6.3. Operation of the Proposed C-2C SAR ADC

The functions of the components forming the DAC can be explained briefly as follows:
1) The upper switches, SAs in Figure 6.1 , are only responsible for adding charge to the
DAC output and only the capacitors with sizes CU and CU/2 are used for this addition
operation.
2) Similarly, lower switches, SRs in Figure 6.1, are only responsible for charge removal
but this time all the capacitors take place for the charge removal operation. This way, the
entire DAC can be considered as 2 different C-2C DACs merged together as shown in
Figure 6.3.

103

u
u

u
u

u
u

Figure 6.3: a) C-2C DAC responsible for charge addition to the output b) C-2C DAC
responsible for charge removal from the output
DAC #1) SAs, CUs, and CU/2s form the C-2C DAC responsible for charge addition
(Figure 6.3-a).
DAC #2) SRs and all the capacitors (CU/2s, CUs, and 2*CUs) form the C-2C DAC
responsible for charge removal (Figure 6.3-b).
Since these 2 DACs share the same CUs and CU/2s, the overall capacitor area is still no
larger than a single C-2C DAC. The operation of the proposed SAR ADC can be briefly
summarized as follows: (For simplicity, assume that VMin=0 & VMax=Vref and initially
SAs are connected to VMin and SRs are connected to VMax):

104

1) Reset and Input Sampling: SA1 & SR0 sample the input and Sreset resets the DAC output
(=comparator input) (Figure 6.4). The internal node voltages of the DAC in this phase

are presented in Table 6.2.

Figure 6.4: Reset and input sampling phase of the proposed C-2C DAC
Table 6.2: Internal node voltages of the C-2C DAC during the reset and input sampling
phase.

!ode

Voltage

Vin

gnd

Vin

Vref

Vref

2) MSB Decision: SA1 switches to VMax and SR0 switches to VMin (Figure 6.5). Only two
unit capacitors between node A and C contribute to the charge redistribution which
creates 0.5*Vref-Vin at the comparator input. Table 6.3 summarizes the internal node
voltage in this phase.

Table 6.3: Internal node voltages of the C-2C DAC during the MSB decision phase.
!ode

Voltage

Vin
Vref

Vin
gnd

gnd

Vref

Vref

105

Figure 6.5: MSB decision phase of the proposed C-2C DAC

3-a) MSB-1 Decision If MSB=1: If Vin>0.5*Vref, then the next comparison should be
carried out between Vin and 0.75*Vref. In this case, SA1 & SR1 become floating and SA2
switches from VMin to VMax (Figure 6.6). Note that the 2*CU capacitor connected to
switch SR1 also becomes floating and can not contribute to the charge redistribution in

this phase.

Figure 6.6: MSB-1 decision phase of the proposed C-2C DAC when MSB=1
It can be shown that Ceq1 and Ceq2 in Figure 6.6 are equal to CU/2 and CU, respectively:

106

C eq1 =

CU CU
C
= U
2
CU + CU

& C eq 2 = C eq1 //

CU
= CU
2

Eq. 6.1

As node B switches from ground to Vref, due to charge redistribution between Ceq2 and
CU (connected between nodes B and A), voltage at node A increases by Vref/2. Similarly,
as the voltage at node A increases by Vref/2, due to charge redistribution between two unit
capacitors on the right side of node A, the DAC output increases by Vref/4. Since the
initial voltage at the DAC output was 0.5*Vref-Vin, the new value becomes 0.75*Vref-Vin.
Table 6.4 summarizes the internal node voltages of the DAC in this phase.

Table 6.4: Internal node voltages of the C-2C DAC during the MSB-1 decision phase
when MSB=1.

!ode

Voltage

Vref
1.5*Vref

gnd
Vref

gnd

Vref
1.5*Vref

Vref

3-b) MSB-1 Decision If MSB=0: If Vin<0.5*Vref, the next comparison should be between
0.25*Vref and Vin. In this case, SA1 becomes floating, SA2 remains at VMin and SR1
switches from VMax to VMin (Figure 6.7).

Figure 6.7: MSB-1 decision phase of the proposed C-2C DAC when MSB=0

107

Similarly, the equivalent capacitances labeled as Ceq1, Ceq2, and Ceq3 in Figure 6.7 can be
easily calculated as CU/2, CU, and 2*CU, respectively, which is also presented explicitly
in Eq. 6.2:

C eq1 =

CU CU
C
= U
2
CU + CU
C eq 3

& C eq 2 = CU

&
Eq. 6.2

C
= C eq1 // C eq 2 // U = 2CU
2

In this case, as the voltage at node D switches from Vref to ground, the charge
redistribution between Ceq3 and 2*CU (the one connected between node D and node A)
makes the voltage at node A decrease by 0.5*Vref. Similarly, as the voltage at node A
decreases by 0.5*Vref, due to the charge redistribution between two unit capacitors on the
right side of node A, the DAC output decreases by 0.25*Vref. Since the initial voltage at
the DAC output was 0.5*Vref-Vin, after the charge redistribution process, the new value
becomes 0.25*Vref-Vin. Table 6.5 summarizes the internal node voltages of the C-2C
DAC in this phase.

Table 6.5: Internal node voltages of the C-2C DAC during the MSB-1 decision phase
when MSB=0.

!ode

Voltage

Vref
0.5*Vref

gnd

gnd

Vref
gnd

Vref

4) In a similar manner, the mentioned sequence of operations is repeated for all bit
decisions for an overall conversion time of N+1 clock cycles in order to get the N-bit
output data. Basically, in the next bit decision cycle, if a higher voltage is needed at the
DAC output, which means that the previous bit decision gives 1, the next upper switch
(one of SAs) switches from ground to Vref and adds more charge to the output.
Otherwise (the previous bit decision is 0), the next lower switch (one of SRs) switches

108

from Vref to ground and removes the excess charge from the DAC output to decrease the
voltage.
Figure 6.8 gives a possible timing scheme for the proposed C-2C SAR ADC with respect
to the clock signal. As seen, a full clock cycle is dedicated for input sampling and array
resetting, which is followed by the bit decision cycles. One bit is decided at each clock
cycle whose half period is used for charge redistribution while the other half is assigned
to the comparator to give its decision. In some cases when the settling is critical, more
than one clock cycle can be also assigned for the input sampling and the duty cycle can
be also adjusted accordingly if necessary.

Figure 6.8: Timing of the proposed SAR ADC according to the clock signal
In addition, Figure 6.9 presents the simplified timing diagram of the switch control
signals of the proposed C-2C SAR ADC based on the operation described above. In the
diagram, SA1_R and SA1_L represent the switches on the Right and Left sides labeled as SA1
in Figure 6.1, which is the case for all switch names in the timing diagram. The red parts
in the diagram show the case when the previous bit decision is 0. It should be noted that
the actual timing diagram is slightly different from the one given in Figure 6.9, as the one
given below is only a simplified version and does not include any switching activity for
calibration. The actual timing diagram will be presented later in the chapter, but the
simplified diagram given below can be used as a good starting point to understand the
operation.

109

Figure 6.9: Switch control signal timing diagram of the C-2C SAR ADC

110

6.4. Parasitic Capacitance Calibration

As mentioned in Section 6.2, the capacitors with sizes CU/2 are not implemented as
MFCs, and they represent the total parasitic capacitance at the intermediate nodes of the
DAC. In order to keep the radix at 2, the total parasitic capacitance at each node has to
be equal to CU/2.

As an example, Figure 6.10 shows three different transfer

characteristics of the proposed SAR ADC with different radixes. The black curve is the
ideal case when the parasitics are equal to CU/2 (Cpar=CU/2), while the blue curve shows
the case when Cpar>CU/2 which reduces the radix. Similarly, the red curve represents the
case when Cpar<CU/2, resulting in a radix greater than 2. All calculations so far have been
carried out assuming that Cpar=CU/2 but it has not been explained yet how their sizes are
adjusted. In reality, even though the parasitics are adjusted to be equal to CU/2 with
detailed extracted simulations, process variations will surely cause a deviation. Thus, a
calibration scheme is mandatory to keep them at the right value after fabrication.

120

Radix<2

Output Code (Decimal)

Radix=2
100

Radix>2

80
60
40
20
0

-60

-40
-20
0
20
40
Normalized Input Differential Voltage

60

Figure 6.10: Three 7-bit ADC transfer characteristics with different radixes based on
the parasitic capacitance values at the intermediate nodes.

111

Two different radix calibration schemes are implemented for the proposed C-2C SAR
ADC: (1) Coarse Radix Calibration (CRC) and (2) Fine Radix Calibration (FRC). The
CRC is implemented in order to adjust the parasitic capacitances at every intermediate
node of the DAC to be approximately equal to half of the unit capacitor, CU/2. After the
CRC is carried out, the FRC supplies or removes excess charge at the output of the DAC
to compensate for the residual error remaining from the CRC during each bit decision
cycle.

6.4.1.

Coarse Radix Calibration (CRC)

In order to implement the CRC, capacitor banks (Cbank) are included to every
intermediate node of the C-2C DAC as shown in Figure 6.11. Cbank is simply a variable
capacitor whose capacitance value can be adjusted in discrete steps by using the control
switches (as shown on the right in Figure 6.11). The capacitors used in the Cbank are the
dummy capacitors (~5fF each) around the C-2C ladder and they cost no extra area

nk

VMax

VMin

VMax

nk

nk

VMin

ba

ba

ba

VMin

VMax

VMin

VMax

VMin

VMax

penalty.

Figure 6.11: Cbanks used for Coarse Radix Calibration

112

The nominal capacitance of the Cbank is the mid-value of its total range and it has been
verified with extracted simulations that the total parasitic capacitance (CP+Cbank in
Figure 6.11) at each intermediate node is equal to CU/2 when Cbanks are at the nominal
value. In the case of a process variation, the capacitance of each Cbank can be increased
or decreased accordingly to keep the total parasitic capacitance around the desired value.
Figure 6.12 gives possible capacitance values that a Cbank can take if the unit capacitors
in the Cbank are assumed as 5fF and the parasitic capacitance of a floating switch is
taken as 1fF. The discrete values are [3.59, 3.80, 4.39, 6.67, 7.76, 7.97, 8.56, 10.83,
11.93, 12.13, 12.73, 15] fF and the nominal value of the Cbanks is kept as 8.56fF which
is roughly the mid value of the entire range.

16

Capacitance of the Cbank (fF)

14
12
10
8
6
4
1

3
4
5
6
7
8
9
10
Number of Possible Switch Settings

11

12

Figure 6.12: Different capacitance values Cbank can take

6.4.2.

Fine Radix Calibration (FRC)

As described above, Cbanks can only take discrete capacitance values. Thus, it is highly
probable to have a small residual error after CRC is performed, and FRC is responsible to
minimize this residual error. CCAL and VCAL in Figure 6.1 are included at the LSB (i.e.

113

the leftmost) node of the DAC to implement FRC. As mentioned before, when an upper
switch (SA) is closed, any switching activity taking place on the left side of that particular
switch has no contribution to the output. This feature forms the basic idea behind FRC.
When an upper switch is closed, the FRC algorithm changes the intermediate nodes
slightly by using CCAL and VCAL.

This additional or removed charge at every

intermediate node compensates for the residual error of the next bit and the FRC is
updated at every bit decision. As an example, Figure 6.13 presents the FRC of the
MSB-1 during the decision of the MSB. As seen, SA1 is connected to VMAX and creates a
low impedance node. Consequently, the changes at the nodes (marked with blue) on the
left side of the low impedance node can not influence the output voltage of the DAC.
During this phase, if additional charge is required, the calibration switch switches from
Vcal to ground and removes charge to the intermediate nodes. Otherwise, it switches from
Vcal to ground to pump excess charge. Similarly, when the next bit decision starts, the
intermediate nodes can be reset and then set to a desired value again by the calibration

Figure 6.13: Fine Radix Calibration of MSB-1 during MSB decision

114

VMin

VMin

VMax

u/

VMax

u/

C
VMin

VMax

VMin

u/

VMin

VMax

VMin

VMax

VMin

VMax

Vcal

u/

VMax

voltage.

It should be noted that the MSB decision neither suffers from any parasitic capacitance
nor any residual charge error because of the fact that the input sampling and the bit
decision are carried out by utilizing the same capacitors of the C-2C DAC. Hence, this
case is almost identical to the one for the MSB decision cycle in a conventional SAR
ADC with Binary-Weighted capacitive DAC. Since the MSB decision does not require
the FRC, during the MSB decision phase, the FRC corrects the residual error for the
MSB-1.

Similarly, during the MSB-1 decision cycle, the calibration adjusts the

intermediate nodes of the C-2C DAC for the MSB-2 decision, which goes on like this for
all bit decisions.
As an important point on the FRC, all of the SA switches on the left side of the closed one
should be left floating for the FRC. However, it is up to the designer to leave SR switches
floating or not during the calibration period. But it should be taken into account that this
design choice will change the equivalent capacitance seen by the calibration capacitor.
Hence a different calibration voltage, Vcal, (or calibration capacitor, Ccal) should be
selected accordingly. Moreover, at each bit decision cycle, the equivalent capacitance
seen by the calibration capacitor changes as a closer SA switch will be turned on at each
time. Hence the voltages at the intermediate nodes of the C-2C DAC change slightly at
different bit decision cycles.
One critical point in the FRC is the selection of the calibration voltage, Vcal. It has to be
figured out if only a single voltage (which is very easy to implement) is enough for
correcting all bit decisions or if it is necessary to use different voltage values for different
bit decisions. In order to observe this issue, a model of the proposed 7-bit C-2C SAR
ADC is implemented in MATLAB including parasitic capacitances at the intermediate
nodes of the DAC with a random variation of 20%. Initially, the CRC is performed to
adjust the capacitance values roughly to CU/2. Then, the residual error is observed for
each output bit. Figure 6.14 shows the normalized residual error (blue bars) for each bit
after the CRC is carried out (Note that the residual error for the MSB is not included in
the figure as the error is zero for this particular bit decision). The red line shows the

115

correction achieved for each bit by utilizing only a single calibration voltage (and a
reasonably small calibration capacitor in the order of the unit capacitor of the DAC) and
it can be seen that a decent correction is obtained which is verified to be good enough for
a 7-bit implementation by checking the linearity specifications of the DAC. As a result, a
single calibration voltage is used for all bit decisions in this design. As a final note, VCAL
is implemented with a simple 6-bit R-2R DAC with no stringent resolution or accuracy
requirement.

Normalized Error Voltage

2
3
4
5
Bit Numbers (1==>LSB and 6==>MSB-1)

Figure 6.14: Residual error after CRC and FRC correction by using a single
calibration voltage
As mentioned before, due to the FRC, the actual timing diagram of the DAC control
switches is slightly different then the one shown in Figure 6.9.

The actual timing

diagram of the control switches that covers the FRC is presented in Figure 6.15. The
same switch names are used as in Figure 6.9 and again the red parts in the diagram show
the condition when the previous bit decision is 0.

116

Figure 6.15: Actual timing diagram of the SAR ADC

117

6.4.3.

CRC and FRC Simulation Results

The performance of the calibration algorithms was observed by modeling the proposed
ADC using Cadence, Verilog-A, and MATLAB. Figure 6.16 presents the simulation
result showing the transfer characteristics of the 7-bit C-2C SAR ADC model including
the parasitic capacitances (0.9*CU/2 with 10% variability) before radix calibration. The
parasitic capacitances are assumed to be 0.9*CU/2 (a deviation is considered) with 10%
variability.

120

Output Code (Decimal)

100

actual
ideal

80

60

40

20

20

40

60
80
Normalized Input Voltage

100

120

Figure 6.16: Simulation result showing the transfer characteristics of a 7-bit C-2C SAR
ADC model including the parasitic capacitances (0.9*CU/2 with 10% variability) before
radix calibration.
The same simulation result after radix calibrations is shown in Figure 6.17.
improvement in the linearity can be easily observed.

The

To further investigate the

improvements in the linearity and to give more insight, the calibrated and non-calibrated
INL and DNL plots were obtained as shown in Figure 6.18 and Figure 6.19, respectively.
Non-calibrated INL is found as 3.5LSB but it reduces down to 0.8LSB after
calibration. Similarly, DNL improves from -0.7/0.35LSB to 0.4LSB.

118

120

100
actual
ideal
80

60

40

20

20

40

60

80

100

120

Figure 6.17: Simulated transfer characteristics of a 7-bit C-2C SAR ADC model
including the parasitic capacitances (0.9*CU/2, 10% variability) after radix calibration.
4
3

INL (LSB)

2
1
0
-1
-2

without calib.

-3

with calib

-4
0

20

40

60
80
Normalized Input Voltage

100

120

Figure 6.18: Simulated INL before and after radix calibrations

0.6
without calib.
with calib.

0.4

DNL (LSB)

0.2
0
-0.2
-0.4
-0.6
-0.8

20

40

60
80
Normalized Input Voltage

100

120

Figure 6.19: Simulated DNL before and after radix calibrations

119

6.4.4.

CRC and FRC Algorithm

Although the proposed calibration schemes are shown to be effective, a simple and easy
algorithm should be developed for them, as complex algorithms may consume too much
time and not suitable for batch fabrications.
Proposed radix calibrations are done at the start-up and do not require any special input
signal. As mentioned before, Figure 6.10 shows three offset-free 7-bit ADC transfer
functions: one with a radix of exactly 2, one with a radix smaller than 2, and finally one
with a radix greater than 2. The key point in these transfer functions is, as long as the
maximum and minimum points of the transfer functions match with those of the one with
radix 2, it can be concluded that the radix of the ADC is corrected. This property is used
to build the proposed calibration algorithm and in order to implement it, the maximum
and the minimum reference voltages of the ADC are shorted to the inputs and the radix is
changed till the correct data is obtained at the output. Initially, the CRC is performed to
approximately adjust the radix to two. Then the FRC is carried out in a similar manner
for fine tuning. The same calibration method can be repeated by reversing the polarity of
the inputs to see if the ADC is offset-free or not. This is actually a critical step as an
ADC with offset can lead to wrong decisions in this algorithm and it has to be corrected
first.
As the maximum and minimum reference voltages are already available inside the ADC,
there is no need for an external special test signal for radix calibration. The only addition
to the ADC topology is switches to short the inputs and the reference voltages, which is a
very minor additional hardware with almost no area or power penalty.

6.5. Switch Design

Switch design is a very challenging part of the proposed SAR ADC as the design is
carried out in a LP Digital CMOS process in which the threshold voltage of the MOS

120

devices is high and single MOS transistors can not operate as switches properly for the
entire input voltage range. As an example, Figure 6.20 shows the simulated on-resistance
of a fairly wide transmission gate with respect to the input voltage. When the input is
around the supply voltage (1.1V) or the ground, the on-resistance is nearly 100, and the
switch operates properly. But it increases up to roughly 3.5K at the mid point which
means neither the NMOS nor the PMOS device is turning on at around 0.55V. Hence, a
transmission gate can not be directly used as a good switch.

Consequently, either

boosting [88] or bootstrapping [89-90] techniques should be used to enhance the switch
overdrive voltage and reduce the on-resistance.

Figure 6.20: Simulated on-resistance of a wide transmission gate with respect to the
input voltage
Three different switches are necessary for the proposed design: 1) input sampling switch,
2) maximum reference voltage switch, and 3) minimum reference voltage switch. As
each type has its own specifications, they need different designs.

6.5.1.

Reference Voltage Switch Design

The minimum and the maximum reference voltages used in the proposed SAR ADC are
200mV and 700mV, respectively. As 200mV is low enough, a single PMOS transistor is

121

preferred for the minimum reference voltage switch. But 700mV is very close to the mid
point of the rail-to-rail swing and boosting is inevitable for the maximum reference
voltage switch design.

Figure 6.21: Schematic of the boosted switch of the maximum reference voltage
Figure 6.21 shows the schematic of the boosted switch used for the maximum reference
voltage (For simplicity it will be called as reference switch from now on). The transistor
level schematic of the clock booster is also presented in Figure 6.22-a whose operation is
simply shifting the level of the input signal from 0-VDD to VDD-2VDD as explained in
Figure 6.22-b.

Figure 6.22: a) Schematic of the clock booster b) Operation of the clock booster

122

The reference switch is simply a boosted topology which is optimized to have nearly VDD
(1.1V) across the gate and the source of M1 when the input is equal to the maximum
reference voltage, 700mV. Figure 6.23 presents the operation of the boosted switch by
showing the node voltages during different clock phases.

Figure 6.23: Operation of the boosted switch

When phi is low, the switch is OFF. In this phase, the hold capacitor, CH, is charged to
VDD by turning ON the switches M2 and M4. Transistors M8 and M9 short the gate of M1
to ground keeping the switch transistor OFF. M6 charges the node C to VDD, thus turns
OFF M7. Mdio and M5 stay at the edge of conduction and node D is almost equal to the
threshold voltage of this transistor.
When phi becomes high, node A is charged to VDD by M3. Since M9 is also OFF in this
phase, there is no current flow path for CH, and as a result, node B tries to go to 2VDD as
M4 is OFF. The increase in node B, turns ON M5 and as M6 is OFF in this phase, node C
drops down to a level approximately equal to the threshold voltage of Mdio.

123

Consequently, M7 turns ON and connects the gate of M1 to CH. However, this makes all
the parasitic capacitances of the right side of M7, most importantly the gate capacitance
of M1, to be seen by the hold capacitor and a charge sharing takes place. As a result, the
voltage at node B drops down to an arbitrary value. By detailed extracted simulations,
this arbitrary value is adjusted to be around VDD+VREF_MAX (1.1V+0.7V) and the gate-tosource voltage of M1 becomes VDD when the switch is ON.
Three important design choices make this boosted switch very fast:
1) The size of the hold capacitor was chosen as 20fF after extracted simulations. This is a
very small value, and charging and discharging such a small capacitor enhances the speed
considerably.
2) The gate of M5 is connected to node B rather than the control signal phi. As node B
exceeds VDD when the switch is ON, M5 turn ON in a very short time with a very high
overdrive voltage, discharging the node C quickly. Consequently, M7 turns ON rapidly
and charges the gate of M1 in a short period of time. Moreover, Mdio protects M5 and M7
from breakdown during this phase. As node B reaches VDD+VREF_MAX, the gate-to-source
voltages of M5 and M7 become VDD+VREF_MAX-VTH_Mdio which is slightly above VDD but
still safe for the breakdown. This can be considered as a benefit of the LP digital CMOS
process as the threshold voltage of the transistors is high.
3) The body node of the switch transistor M1 is biased with an OFF transistor, Moff,
instead of directly connecting the body to ground. Due to leakage current, the body
voltage of M1 stays always higher than ground and reduces the threshold voltage of M1,
making the switch faster.
Using an OFF device to bias the body node of the switch transistor has another very
important benefit. As explained in the operation of the proposed SAR ADC as well as
shown in the timing diagram of the control switches in Figure 6.15, SA switches become
floating after they contribute to the bit decision that they are responsible for.
Consequently, these floating switches contribute to the parasitic capacitances at the
intermediate nodes.

124

VMax
VDD

VMin

VMax

Cu

2Cu

CGD

CDB

Figure 6.24: Floating switches at the intermediate nodes and their parasitic
capacitances
Figure 6.24 shows an arbitrary intermediate node with two floating switches and their
parasitic capacitances which are CGD and CDB. As the transistors are OFF, there is no
channel under the gate and CGD is simply a constant overlap capacitance, COV. However,
CDB can be expressed as [91]:

C DB =

CJ 0
VR

1 +

Eq. 6.3

where CJ0 is the depletion capacitance per unit area, VR is the reverse bias voltage across
the PN junction, 0 is the built-in potential of the PN junction, and m is a constant which
is typically equal to 1/2 for abrupt junctions and 1/3 for graded junctions. It is seen that
CDB depends on the voltage across itself. As intermediate node voltages change at every
bit decision, if bodies of the switch transistors are connected to the rails, then the change
at these node voltages will be directly observed across the junctions and this will change
the parasitic capacitances at these nodes. This is a severe problem as the radix will be
influence by the parasitic capacitance change at every bit decision.
125

As a result, a

dynamic radix calibration scheme is necessary for compensation which is very hard,
almost impractical, and a significant limitation for the accuracy. However, it has been
observed from the simulation results that, if the body is biased with an OFF transistor,
due to leakage, the body node tends to track the changes in the drain. This reduces the
voltage variation across the junction by almost 50% and reduces the variation in the
parasitic capacitances significantly, hence improves the accuracy.

A similar OFF

transistor was also utilized for the PMOS transistors which are used as the minimum
reference voltage switches.

6.5.2.

Input Sampling Switch (Input-aware Boosted Switch)

The final switch design is the input sampling switch and the most commonly used
sampling switch with constant overdrive voltage is the conventional bootstrapped
topology [89] as given in Figure 6.25. However, a different topology is picked for the
proposed design. In order to understand the reasons behind this design choice, it is
convenient to cover the operation of the bootstrapped switch first.

Figure 6.25: Schematic of the conventional bootstrapped switch

126

The operation of a bootstrapped switch is similar to the boosted switch described above
with several distinctions. Similarly, when phi is low, the switch is OFF. M9 shorts the
gate of M1 to ground and the capacitor is charged to VDD. M6 keeps node C at VDD and
M7 stays OFF in this phase.
When phi becomes high, as initially node A is grounded, M5 discharges the gate of M7
and turns it ON. This lets the charge on the hold capacitor flow onto the gate of M1 and
M2 and turns ON these transistors. As M2 turns ON, the voltage at node A charges up to
the input voltage, which increases the voltage at node B as there is no current path for the
capacitor. Consequently the voltage at the gate of M1 and M2 becomes ideally Vin+VDD.
M10 is functionally not necessary but improves the circuit reliability by ensuring that the
gate-to-source voltage of M7 does not exceed VDD.
As seen, when the bootstrapped switch is ON, the gate-to-source voltage of M1 ideally
remains as VDD. However, this topology suffers from low speed due to two reasons:
1) There is an inevitable speed reduction when the input voltage becomes higher as Node
A needs more time to be charged to Vin in this case. Similarly, if node A becomes too
high, M5 will struggle to charge node C as single NMOS transistors are not good switches
at high voltages. In this case, the circuit has to wait for M10 to turn on and charge node
C.
2) As also mentioned for the boosted switch, when the switch turns ON, there is an
inevitable charge sharing between the hold capacitor and the parasitic capacitances,
especially the gate capacitance of the switch transistor. Due to this charge sharing, the
voltage at the gate of the switch transistor can never reach Vin+VDD in reality. This
problem is even worse for the bootstrapped switch because the gate capacitance of M2
also takes place in this process. The only way to mitigate this problem is by using a large
hold capacitor. But this increases the area and also charging and discharging such a large
capacitor reduces the speed severely.

127

In addition, two transistors are connected to the input. This increases not only the
parasitic loading but also the glitches due to charge injection at the input side. This
problem is especially critical for time-interleaved applications as many switches are
connected to the input.
Due to the mentioned drawbacks of the bootstrapped switch, a modified version of the
proposed reference switch was decided to be used for sampling as the speed of the
boosted switch is significantly higher. Moreover, the small hold capacitor (20fF) reduces
the area considerably. However, the boosted switch is optimized only for the maximum
reference voltage (700mV) and can not be directly used as a sampling switch as it is not
input-aware. This can cause not only input dependent on-resistance but also breakdown
problems. Since the gate of M1 in the boosted switch always goes to 700mV+VDD, if this
switch is directly used for input sampling, the gate-to-source voltage of M1 will always
exceed VDD when the input is less than 700mV. In the worst case when the input is equal
to the minimum reference voltage (200mV), the gate-to-source voltage becomes
VDD+500mV, which is a severe breakdown problem. Thus, a modification is mandatory
while keeping the benefits.

Figure 6.26: Schematic of the proposed input-aware boosted switch

128

Figure 6.26 shows the schematic of the input-aware boosted switch. MCLIP is included to
the original topology given in Figure 6.21 in order to achieve the input-awareness. MCLIP
and the body-to-source PN junction diode of M1 (shown in gray) create a current path
between the gate of M1 and the input. However, this path can only turn on if the
following condition is satisfied:
V gate Vin > Von _ diode + VTH _ MCLIP

Eq. 6.4

As again the benefit of the LP Digital CMOS process, the threshold voltage is high and
VON_DIODE+VTH_MCLIP is roughly equal to VDD. Consequently, whenever the gate-tosource voltage of M1 exceeds VDD, the mentioned path turns on and discharges the gate
node. Thus, the gate-to-source voltage is kept around VDD. Since the hold capacitor is
very small in this case, the amount of charge needed to be removed from the gate is very
small, causing a smaller glitch at the input.
Figure 6.27 presents the simulated on-resistance of the boosted switch for the entire input
range, which varies slightly from 135 to 215. The capacitive load seen by each
sampling switch is roughly 150fF and this corresponds to a 3-dB cut-off frequency of
approximately 5.5GHz. Thus, the sampler covers the entire Nyquist band.

Figure 6.27: Simulated on-resistance of the input sampling boosted switch for the
entire input range

129

Figure 6.28: Comparison of the simulated on-resistances of the same size boosted and
bootstrapped switches with the same hold capacitor.
The use of a small capacitor is one of the key points for the high speed operation. Just to
compare the performances, a same size bootstrapped switch was designed by using the
same hold capacitor. Figure 6.28 shows the comparison of the simulated on-resistances
of these same-size boosted and bootstrapped switches. As seen, the bootstrapped switch
is not working properly as the on-resistance of the switch changes from 700 to 2.5K.
The main reason is the hold capacitor is very small and can not charge the gate nodes of
M1 and M2 properly. Due to inadequate charge sharing, the voltage at the gate of these
transistors can not become high enough to turn on the switch. To validate this problem,
Figure 6.29 presents the gate-to-source voltage of the switch transistor, M1, for the entire
input range, which never exceeds 0.65V. Thus, a considerably higher hold capacitor is
required to achieve a similar performance of the boosted switch, which is a severe speed
limitation.
In addition, in the boosted switch topology, there is only one transistor connected to the
input which reduces the charge injection problem by a factor of 2.

130

Bootstrapped Switch Gate-to-Source Voltage

0.65

Switch Transistor VGS (V)

0.64
0.63
0.62
0.61
0.60
0.59
0.58
0.57
0.56
0.55
0.54
0.15

0.25

0.35

0.45
0.55
Input Voltage (V)

0.65

0.75

Figure 6.29: Gate-to-source voltage of the switch transistor of the bootstrapped switch
with the same size as the boosted switch for the entire input range
As a final note, unlike the conventional bootstrapped switches, in this proposed inputaware boosted topology, the gate-to-source voltage of M1 always tries to go above VDD
(the switch was slightly modified to achieve that) but it is pulled back by the discharge
path (MCLIP and PN junction diode). Consequently, the voltage at the gate of M1 looks
like an over-damped response rather than an under-damped signal as in the case of a
bootstrapped switch. This feature enhances the settling and the speed significantly.
Figure 6.30 explains this property on an example.

Figure 6.30: Responses at the gate nodes of the conventional bootstrapped switch and
the proposed input-aware boosted switch

131

6.6. Comparator Design

This section covers the comparator architecture of the proposed SAR ADC as well as the
offset background calibration technique and the dynamic biasing for power reduction.

6.6.1.

Comparator Architecture

The key parameter in high speed comparator designs is the regeneration time-constant:

= CT g
m

Eq. 6.5

where CT is the total capacitance at the latch output and gm is the transconductance of the
latch transistors. This parameter determines how fast a comparator can operate and it is
strongly correlated with the unity gain frequency of the process. As the speed is limited
by the process, unless some speed enhancement techniques such shunt peaking [92] are
applied, there is not too much a designer can do other than keeping the time-constant as
low as possible. Thus, a standard topology is picked for the comparator.

Figure 6.31: Schematic of the comparator used in the proposed C-2C SAR ADC along
with the control signals.

132

Figure 6.31 shows the schematic of the comparator used in the proposed C-2C SAR ADC
along with the control signals. It consists of a low-gain preamplifier (M1-M4) followed
by a latch (M9-M15) similar to the common comparator architectures found in the
literature.

When the latch_b signal is high, the comparator is in the reset mode.

Transistors M13-M15 reset the outputs of the latch (inputs of the inverters at the output) to
ground. But the preamplifier is still functional and switch transistors M7 and M8 are ON,
letting the output current of the preamplifier flow onto the latch. Ideally, the latch
outputs should stay at ground in this phase but, since the reset transistors of the latch are
not perfect switches with zero on-resistance, there is still a resistance from the latch
outputs to ground. Thus, the preamplifier current flowing into the latch outputs makes a
voltage drop at these nodes. When the latch_b signal becomes low, the cross-coupled
latch transistors, M11 and M12, become released and regenerate the output according to
the initial voltage drops at the output nodes.

As seen in Figure 6.31, the switch

transistors, M7 and M8, use a slightly delayed version of the latch signal. This lets the
preamplifier current flow into the latch outputs for a short period of time after the latch is
released and improves the regeneration speed.
As mentioned, regeneration time-constant is a very critical speed-related parameter for
latched comparators since the smaller the regeneration time-constant, the lower the BitError-Rate (BER). BER can be expressed in terms of metastability for the latched
comparators. Briefly, metastability is a problem that occurs in all latching comparators
when the input is very close to the comparator decision point as a relatively long time is
required to resolve the comparison in this case. Similar to the definition of the BER
given in Chapter II, the metastability problem occurs when the comparator needs more
time to switch to a valid output state than is available in the latch interval. In this case, a
wrong decision or an invalid output, such as having 1 or 0 at both the output and its
complement, can be seen. As metastability is strongly related to how fast a comparator
can operate, metastability error probability can be expressed in terms of the regeneration
time-constant:

133

PE =

VO tr
e
Vin AO

Eq. 6.6

where VO is the minimum output voltage swing required for valid logic levels, Vin is the
input voltage of the comparator, AO is the gain of the preamplifier, tr is the time
dedicated for the regeneration and is the regeneration time constant of the comparator.
In order to achieve some numerical values to observe how small the regeneration timeconstant should be, a simple calculation can be carried with some assumption. The
comparator should be able to resolve 1/2 LSB at the input, thus Vin can be taken as 1/2
LSB. VO is roughly equal to the full scale input range, thus can be taken as 2N LSB
where N is the resolution of the converter. As the target resolution is 7 bits in this
particular design, all these values can be plugged in and the remaining unknown term, tr/
ratio, with respect to the metastability error probability can be calculated as given in

Regeneration Time / Regeneration Time-Constant

Figure 6.32.

28
27
26
25
24
23
22
21
20 -10
10

-9

-8

10
10
Metastability Error Probability

-7

10

Figure 6.32: Regeneration time / Regeneration Time Constant (tr/) with respect to the
metastability error probability

134

As a rule of thumb, error probability is generally desired to be around 10-9 which means 1
error out of 1 billion comparisons. tr/ ratio corresponding to this error probability is
nearly 25.5. As 1.5GHz clock frequency was the target for individual proposed SAR
ADCs, and if half of the period is dedicated for regeneration, tr can be calculated as
333psec. By putting a safety margin, it is taken as 300psec and the regeneration time
constant is found as 11.8psec.
11.8psec was chosen as the target time-constant however, in order to improve the offset,
devices greater than minimum size were preferred for the cross-coupled devices of the
latch which degraded the speed. The final simulated time-constant was calculated as
15psec.
In addition, two additional features are included to the comparator to enhance the
performance: (1) dynamic biasing and (2) background offset calibration.

The next

sections cover these features.

6.6.2.

Dynamic Biasing

Briefly, dynamic biasing is used to increase or decrease the power dissipation of the
comparator where necessary. When the input voltages of a comparator are far apart from
each other, the decision is very trivial and does not require high power dissipation.
However, as the input voltages become closer, either more time or more power should be
used to get the right comparison. If the difference between the input voltages can be
sensed in an efficient way, the power of the comparator can be adjusted properly. In a
SAR ADC, at each conversion, comparator inputs become very close only for 1 or 2 bit
decisions. Thus, power saving can be achieved by reducing the consumption for the
decision of other bits.
The key point of dynamic biasing is the input sensing. Input difference can be sensed in
many different ways but if the power utilized for sensing is higher than the achieved

135

power saving, then the dynamic biasing will have no benefit. Thus, an efficient sensing
method is very important.

VDD
In+

InVDD

In+

In-

bias

Dynamic
Baising

MCS1

bias
Mbias

MCS2
Mbias

Figure 6.33: Schematic of the dynamic biasing architecture

An efficient dynamic biasing scheme is developed for the proposed comparator which is
shown in Figure 6.33. It should be noted that the voltage at the common node of the
differential pair is determined by the input voltages, In+ and In-, and if the inputs are far
apart from each other, one input transistor will be OFF while the other one carries all the
tail current. Consequently, the voltage at the common node will be:
Vcom = Vin _ high VGS _ on _ tr

Eq. 6.7

where VIN_HIGH is the high input voltage and VGS_ON_TR is the gate-to-source voltage of
the ON transistor. As the inputs come closer, voltage at the common node will start
dropping and will become minimum around where VIN+=VIN-. The simple common
source (CS) amplifier implemented with MCS1 and MCS2 in Figure 6.33, senses the change
in the common node and adjusts the body voltage of the tail transistor, thus changes the
threshold voltage and the tail current accordingly.

136

Figure 6.34: Simulated tail current of the preamplifier with respect to the differential
input voltage
Figure 6.34 shows the simulated tail current of the preamplifier with respect to the input
differential voltage. A 15% power saving is achieved for the comparator with this
scheme. A higher saving can be achieved by connecting the output of the CS amplifier
directly to the gate of the tail transistor but processes variations might be vital in this
case. Although not very critical for a SAR ADC as there is only one comparator,
dynamic biasing can be very useful for Flash ADCs.

6.6.3.

Comparator Offset Background Calibration

An ideal comparators decision point is where the inputs are identical to each other. Any
deviation from this ideal point is simply the offset of the comparator. Offset calibration
is generally a mandatory requirement for high speed comparators as the minimum size
devices, which suffer from too much mismatch, are preferred to achieve the maximum
possible speed.
Many different offset calibration schemes can be found in the literature but the
commonly used ones can be classified as follows:

137

(1) Capacitive [93]: works based on storing the offset of the comparator on to a capacitor
during the auto-zeroing period and utilizing it to remove the offset during the
comparison. This can be an effective background calibration but capacitors occupy large
areas especially in Digital CMOS processes.
(2) DAC [94]: a current DAC can be connected to the outputs the comparator
preamplifier to supply or remove excess current to eliminate the offset. This approach
does not use any capacitors and is compatible with digital CMOS processes. However
the DAC loads the preamplifier output and reduces the bandwidth.
(3) Dynamic element matching (DEM) [95] and (4) Averaging [96]: These techniques
are very suitable for architectures with many comparators but they do not suit well in
SAR ADCs where there is only a single comparator.
(5) Amplifier or Trimmable Buffer [97]: A high gain amplifier can mitigate the offset of
the comparator, or a trimmable buffer can be used to shift the threshold of the comparator
in the opposite direction of the offset but they add additional delay to the signal path.
(6) Redundancy: Based on the fact that the offset distribution is Gaussian, out of many
comparators, the one with the lowest offset can be picked but this approach does not use
the silicon are efficiently.

Figure 6.35: Proposed comparator offset background calibration scheme

138

An effective comparator background offset calibration scheme is developed for the

proposed C-2C SAR ADC, which is also illustrated in Figure 6.35. This scheme is very
well suited especially to SAR ADCs as it uses the input sampling phase to perform the
calibration.

In general for all SAR ADC types, during the input sampling phase,

comparator inputs are shorted to a common mode voltage. The output of the comparator
in this phase is unimportant and not meaningful but it gives the sign of the comparator
offset. This information can be utilized for calibrating the offset and the proposed
calibration scheme is implemented based on this property. As presented in Figure 6.35,
the calibration network consists of an R-2R DAC, a 7b up/down counter, and some
digital circuitry.
The calibration algorithm can be explained as follows: at each input sampling phase, the
output of the comparator is fed to the 7-bit up-down counter which changes the input data
of the 6-bit R-2R DAC connected to the body nodes of the input transistors of the
comparator. This feedback loop adjusts the threshold voltage of the input transistors by
changing the body voltage to minimize the offset in at most 128 cycles (as the counter is
7-bit), where one cycle corresponds to 8 clock cycles of the comparator as the calibration
takes place only during the input sampling phase. With this scheme, approximately
85mV input-referred offset voltage is managed to be calibrated with an accuracy of
approximately 1.3mV per step. As a final note, since the R-2R DAC updates its output at
every eight clock cycles, there is no stringent timing requirement for the DAC and a low
power architecture can be utilized.
As a comparison to the previously mentioned comparator calibration schemes, the
proposed calibration architecture does not require capacitors, does not cause additional
loading to the comparator, and does not need redundancy or trimmable devices. It is very
compatible with Digital CMOS processes and it can be carried out in the background for
SAR ADCs.

139

6.7. Time-Interleaving Topology

So far, the individual C-2C SAR ADC and its implementation details have been covered
thoroughly. However, the overall ADC consists of 16 of these converters working in
parallel in a time-interleaved architecture. This section covers the overall ADC topology
and the calibration methods used for eliminating the mismatch problems due to timeinterleaving.

6.7.1.

Overall Time-Interleaved ADC Architecture

As an N-bit SAR ADC samples the input signal at every N+1 clock cycles, it is very
convenient to time-interleave N+1 converters. With this interleaving scheme, a single
clock signal can be utilized for all converters without generating and aligning different
clock phases.

Figure 6.36: Timing diagram of an 8x time-interleaved 7-bit SAR ADCs

Figure 6.36 gives the timing diagram of 8 times time-interleaved 7-bit SAR ADCs and, as
seen, at each clock cycle one ADC samples the input while the rest carries out the bit

140

decisions of the previously sampled inputs. As long as the ADCs are programmed
properly such that they sample at the right clock period, then a single clock signal is
enough for all converters. As the generation of different clock phases and their alignment
with respect to each other is a very challenging task, this interleaving scheme is very
common in time-interleaved SAR ADCs.
The proposed time-interleaving topology uses the same principle with a small
modification. In order to interleave more ADCs while using the same clock signal, each
ADC was designed to operate at either clock edge. This way, 16 ADCs are able to be
time-interleaved while 8 of them work at the positive clock edge and the rest at the
negative edge. Figure 6.37 shows the timing diagram of the proposed 16 times timeinterleaved 7-bit SAR ADCs

Figure 6.37: Timing diagram of the proposed 16x time-interleaved 7-bit SAR ADCs
Consequently, the time-interleaving scheme is implemented with 16 ADCs as shown in
Figure 6.38, with 2 extra ADCs to allow background calibration of the mismatch related
problems.

141

Figure 6.38: Simplified schematic of the overall time-interleaved ADC

Each ADC runs at 1.25GHz, can work at either edge of the clock, and has a
programmable delay line and a state machine. The programmable delay line is utilized to
align the clock edges of the SAR ADCs to eliminate the clock skew problem due to
interleaving. The state machine enables relative timing control among the ADCs, in
other words, it determines at which clock edge and which clock period the ADC should
sample the input for an effective sampling rate of 2.5GS/s. ADC outputs are fed to
output drivers which consist of register blocks and strong output buffers that are capable
of driving the long output buses.

142

As the overall speed of the ADC makes testing hard without using an on-chip memory,
the outputs of the individual converters were directly connected to two output buses and
the reconstruction is done externally using MATLAB. In this scheme, only two ADC
outputs can be captured externally at a particular time and the reconstruction is done as
follows:
1) First capture the data of ADC-1 and ADC-2.
2) Then capture the data of ADC-2 and ADC-3
3) Align the two sets of data captured from ADC-2, which aligns ADC-1 and ADC-3.
4) Repeat these actions for all ADCs to obtain and align all converter outputs.

6.7.2.

Proposed Time-Interleaving Calibration Schemes

As many converters work in parallel, the mismatches between the ADCs degrade the
overall performance of the ADC and need to be calibrated. As mentioned in Chapter V,
three main mismatch problems are offset, gain, and clock skew. It should be noted that
the degradation is due to mismatch. In other words, all of the ADCs might have a gain
and offset problem but as long as they have the same gain and offset, no degradation will
occur due to time-interleaving.
Offset and gain errors are removed by a background calibration using the extra ADCs.
The extra ADC clones the state machine settings of each ADC to be calibrated one by
one. This way, the extra ADC samples and converts at the same time as the ADC under
calibration and their outputs can be written as:

ADC extra = Gextra * Vin (nTS ) + VOS _ extra

ADC under _ cal = Gunder _ cal * Vin (nTS ) + VOS _ under _ cal

Eq. 6.8

where G and VOS represent the gain and offset of the converters, respectively and
Vin(nTS) is the currently sampled input. The gain and the offset of the calibrated ADC
are adjusted to match the long term mean (represents offset) and rms (represents gain)

143

values of those of the extra ADC. Although two ADCs are supposed to sample at the
same time, there might still be a small sampling time error between these converters. In
this case, the outputs can be updated as:

ADC extra = Gextra * Vin (nTS ) + VOS _ extra

ADC under _ cal = Gunder _ cal * Vin (nTS + dT ) + VOS _ under _ cal

Eq. 6.9

where dT represents the small timing error. As the error is small, the input can be
approximated as a linear waveform in that region as shown in Figure 6.39.

Figure 6.39: Small timing error between the extra ADC and the ADC under
calibration. Input can be approximated as linear within this small time interval.
As a result, the outputs of the ADCs can be approximated as:

ADC extra = Gextra * Vin (nTS ) + VOS _ extra

ADC under _ cal = Gunder _ cal * Vin (nTS ) + dT

dVin
dt

+ VOS _ under _ cal

Eq. 6.10

nTS

Any amplitude-limited signals first-order time-derivative (i.e. its slope) has to have zero
mean; otherwise the signal should be constantly increasing or decreasing. As the longterm mean and rms values are checked for the calibration, the error term due to timing
diminishes and does not degrade the calibration.

144

After the gain and offset problems are calibrated, the timing calibration [76, 77] of the
ADCs is done. In this calibration the extra ADCs are not used and they do not operate to
minimize the power dissipation. In this case, a known sinusoidal signal is applied to the
input, thus this calibration can not be carried out in the background. The standard
deviation of the difference of neighboring ADC outputs are made equal by adjusting the
programmable delay lines. Here, neighboring ADC outputs means the outputs of the
ADCs which sample consecutively. As the input is a well-known sinusoid, the long term
standard deviations of the neighboring ADC outputs should ideally be identical. Any
mismatch shows the existence of a timing error (as the offset and the gain is already
calibrated) and delay lines are adjusted accordingly to equate the standard deviations.
This timing calibration was done using a sinusoidal signal but in real work application
this can be accomplished during the packet header of the communication standard (eg.
OFDM based 60GHz receiver).
As a final note, the extra ADCs impose a 13% area penalty, but a small power penalty as
they can be turned off except during calibration.

6.8. Reference Voltage Stabilization

A stable reference voltage is very critical for the performance of time-interleaved ADCs.
In the proposed design, including the extra ADCs for calibration, 9 ADCs are triggered at
every clock edge causing a large current drawn from the reference voltages and they
should be able to drive this big load. Moreover, the recovery time is only half a clock
cycle as the rest of the ADCs will be triggered at the next clock edge.
The reference voltages are generated internally with R-2R DACs with the option of using
external supplies by disconnecting the DACs. Because the wire bonds are inductors
which act as high impedance at high frequencies, limiting the AC current, if the external
voltages are utilized, converters should not draw large currents from the reference

145

voltages. Similarly, if on-chip DACs are utilized, they have to have very good driving
capability. A common solution is using on-chip decoupling capacitors but this is not
practical for the proposed ADC due to large loading. Assuming 200fF loading on the
reference voltages from each ADC, this corresponds to 1.8pF for each ADC bank (9
ADCs). Simulation results show that the required decoupling capacitor size should be
around 200pF to keep the references stable, which is impractical to implement on-chip.

ref_max
ref_min

DAC

ref_max
ref_min

Goes to
ADCn-1

Goes to
ADCn

DAC

ref_max

Global
OTAs

ref_min

Goes to
ADCn+1

Local
OTAs
Figure 6.40: Schematic of the on-chip reference voltage distribution for an ADC bank
Consequently, active OTAs were used for the reference voltages. Figure 6.40 shows the
schematic of the on-chip reference voltage distribution for an ADC bank. The overall
converter was implemented as two ADC banks (9 ADCs each) and the identical reference
voltage distribution structure was used for both banks. As seen, each ADC has its own

146

OTAs and each bank has also two global OTAs. OTAs were designed with inverters as
they are the fastest amplifiers available in a CMOS process. In addition to OTAs, local
and global decoupling capacitors were included as well to improve the performance and
stability.
With this implementation, almost no current is drawn from the reference voltages, as the
rails supply all the current through the active devices. This way, a current cancellation is
also achieved as some of the ADCs remove their excess charge through reference
voltages while some need more charge. In addition, the PSSR of an inverter is greater
than 1 which improves the settling and stability.

Figure 6.41: Simulated reference voltage recovery comparison of the proposed

distribution and decoupling capacitance method
Figure 6.41 shows the simulated reference voltage recovery comparison of the proposed
distribution with active OTAs and the mentioned decoupling capacitance method where a
decoupling capacitor of 80pF is used. The improvement in the recovery can easily be
observed with the proposed distribution.

147

The proposed reference voltage distribution scheme was not optimized for minimum
power dissipation. In order to achieve a reliable performance, the overall scheme was
over-designed and the total power dissipation is 60mW. This power dissipation was not
included to the FoM calculation of the converter.

6.9. Digital Circuitries and Peripheral Blocks

Digital circuitries were mostly implemented with standard CMOS cells with simple
combinational and sequential elements and a detailed discussion is not necessary.
However, several important points are highlighted here.
In order to improve the speed, flip-flops at the critical signal path were implemented with
True-Single-Phase-Clock (TSPC) Flip-Flops, as shown in Figure 6.42 [98].

This

topology can reduce the flip-flop delay down to two inverter delays. The control logic of
the C-2C DAC switches and the state machine of the ADC were designed using these
flip-flops.

Figure 6.42: a) Positive edge-triggered TSPC D flip-flop b) Positive edge triggered

TSPC RS flip-flop

148

The state machine is simply a special 7-bit shift register which tells the ADC what to do
at each clock cycle.

Figure 6.43 gives the output states and their corresponding

meanings. Each state machine is resettable and loadable, thus they can be externally set
to an initial value in order to properly program the chip for time-interleaving.

Figure 6.43: State machine outputs and their corresponding meanings

Several R-2R DACs were utilized in the ADC, such as in 1) DC bias generation, 2) Fine
Radix calibration, and 3) Comparator Calibration. Figure 6.44 shows the schematic of
the R-2R DAC, where R is either 16K if the speed and loading is not critical (DC bias
generation) or 3K where necessary.

Figure 6.44: Schematic of the R-2R DAC

As mentioned before, each ADC has an adjustable delay line to align the clock edges
properly and mitigate the clock skew problem. The topology of the delay line is shown
in Figure 6.45. As seen, the overall delay line is controlled by 13 bits (clk_cont<5:0>,

149

di<5:0>, and halfbit) and it is composed of a coarse (controlled by clk_cont<5:0>) and a

fine delay line (controlled by di<5:0> and halfbit).

Figure 6.45: Simplified schematic of the delay line

The internal structure of the coarse delay line is presented in Figure 6.46. It basically
uses the delay of standard CMOS gates. Each delay cell either passes the input without
putting a delay or makes it go through a gate and a buffer.

Figure 6.46: Coarse delay line

The fine delay line is implemented with varactors and inverters as shown in Figure 6.47.
The loading at the output of the inverters is adjusted by changing the capacitances of the
varactors. The half-bit is used for fine tuning as it does not make a rail-to-rail change on
the varactor voltage.

150

Figure 6.47: Fine delay line

Finally, a serial port is utilized for the entire converter programming. 56 bits are assigned
for each ADC and another 56 bits were used for global programming. Thus, totally a
(56*18+56) 1064-bit serial port is used.

6.10.Chip Floor Plan and Layout

The floor plan of a single C-2C SAR and its layout are given in Figure 6.48. A single
ADC occupies an area of 0.1mm x 0.5mm.

Figure 6.48: a) Floor plan of the C-2C SAR ADC b) Layout of the C-2C SAR ADC

151

The floor plan of the overall time-interleaved C-2C SAR ADC is given in Figure 6.49.
The chip occupies a total area of 1.5mm x 2mm and has 74 pads, most of which are
supply and ground connections. Table 6.6 gives the pad assignments of the overall ADC.
There are five different supply voltages: 1)VCCD: Digital VCC, 2) VCCA: Analog VCC,
3) VCCIO: VCC For I/O pads, 4) VCCOUT: VCC for output drivers, and finally 5)
VCCREF: VCC for Reference OTAs.

SCDI, SCLKIN, FCLKM, SCANIN, and

SCANOUT are the connections related to the serial port and CH1_OUT<7:0> and
CH2_OUT<7:0> are the lines of the two output buses. DUTY_OUT is included to check
the duty cycle of the internal clock and VCOM is the common mode input voltage of the
comparator during sampling. BIAS and BIAS2 are the bias voltages of the comparator.
Table 6.6: Pad assignment of the time-interleaved C-2C SAR ADC
1

VCCD

20

CH1_OUT<1>

39

CH2_OUT<6>

58

VCCD

VCCD

21

CH1_OUT<2>

40

CH2_OUT<7>

59

SCLKIN

GND

22

GND

41

VCCOUT

60

FCLKM

GND

23

CH1_OUT<3>

42

VCCOUT

61

VCOM

GND

24

CH1_OUT<4>

43

GND

62

GND

GND

25

CH1_OUT<5>

44

GND

63

VCCREF

VCCA

26

CH1_OUT<6>

45

VCCIO

64

VCCREF

VCCA

27

CH1_OUT<7>

46

VCCIO

65

VIN+

REF_MIN

28

GND

47

DUTY_OUT

66

GND

10

REF_MAX

29

GND

48

REF_MIN_BUS

67

VIN-

11

BIAS

30

OUT_CLK

49

REF_MAX_BUS

68

VCCREF

12

BIAS2

31

GND

50

SCDI

69

VCCRE

13

VCCIO

32

GND

51

VCCA

70

GND

14

VCCIO

33

CH2_OUT<0>

52

VCCA

71

SCANIN

15

GND

34

CH2_OUT<1>

53

GND

72

SCANOUT

16

GND

35

CH2_OUT<2>

54

GND

73

CLKINN

17

VCCOUT

36

CH2_OUT<3>

55

GND

74

CLKINP

18

VCCOUT

37

CH2_OUT<4>

56

GND

19

CH1_OUT<0>

38

CH2_OUT<5>

57

VCCD

152

Figure 6.49: Floor plan of the overall time-interleaved C-2C SAR ADC
Finally Figure 6.50 shows the layout of the overall ADC and Figure 6.51 gives the
bonding diagram of the ADC on a 48-pin QFN package.

153

Figure 6.50: Layout of the overall time-interleaved C-2C SAR ADC

154

48

37

36

12

25
13

24
Figure 6.51: Bonding diagram of the proposed ADC

155

CHAPTER VII

7. TEST RESULTS
One of the most challenging periods of an analog design process is the testing and
verification. As the system becomes complicated, more failure mechanisms emerge,
making testing more time and effort consuming, as understanding the behavior of the
chip and figuring out the reasons behind any unexpected result and failure is a very tough
process.
A time-interleaved ADC is a fairly complex system as there is a certain number of
converters working in parallel with several calibration schemes.

Moreover, as the

sampling speed of the converter becomes higher, the capability of the test equipments
become limited, forcing the designers to come up with wise design choices for easier
testing. As an example, the state-of-the-art Logic Analyzer systems have sampling rates
at around 1 GS/s and converters with sampling rates greater than this value are hard to
test at the full speed.
The measurements of the fabricated time-interleaved C-2C SAR ADCs were carried out
in Communications Circuits Laboratory at the Jones Farm Campus of the Oregon
Facilities of Intel Corporation.

Both the unit ADC and the overall converter

performances were measured including the DC (static) and the AC (dynamic)

performance metrics.
This chapter covers the test methodology, test setups and the measurement results of the
proposed time-interleaved C-2C SAR ADC. Section 7.1 goes through the test setup in

156

detail by giving the testing methodology as well as the equipments and their usage.
Section 7.2 presents the measurement results of the unit SAR ADCs and the overall timeinterleaved converter by covering both the DC (static) and the AC (dynamic)
performance metrics.

7.1. Test Setup

The fabricated chips were packaged in 48-pin QFN packages and as the number of pads
is high, the testing was preferred to be carried out using Printed-Circuit-Boards (PCBs)
although probing is very common for high-speed testing.

Two special PCB were

designed for the testing of the proposed ADC as shown in Figure 7.1. The first PCB
(Figure 7.1-a) has a standard socket for the 48-pin QFN package and this PCB was used
for the initial verification of the functionality of the ADCs as well as their peripheral
blocks such as the serial port, DC bias generation DACs, the clock divider, etc... A
socket is very convenient here as many chips can be tested using one board. This testing
also helped in choosing the functional dice as the yield of the utilized digital CMOS
process was not high.
However, standard sockets generally suffer from very high pad (i.e. pin) inductance and
they significantly deteriorate the performance of high speed circuitries due to loading. In
order to observe the actual high-speed performance of the proposed converter and to
eliminate the undesired inductance of the socket, a package on-board PCB was also
prepared as shown in Figure 7.1-b. In this PCB, the packaged die was soldered directly
on to the board and the socket is completely discarded. The clock lines on the board were
also updated to make the impedance matching as good as possible, and the output bus
was replaced with an improved architecture to ease the connections and the
measurements. Here, the previously tested and functionally verified dice were soldered
on the board.

157

SOCKET

(a)

Package-On
Board

(b)

Figure 7.1: a) PCB with a socket b)PCB with package on-board soldering

158

Figure 7.2: Simplified schematic of the test setup.

The simplified schematic of the test setup is presented in Figure 7.2. The equipment used
in the set-up and their functions are:
1) Agilent Logic Analyzer System (16903A): To capture the digital data coming from the
ADC outputs
2) Agilent PSG Signal Generator (E8267C): To generate of the input signal
3) Agilent ESG Signal Generator (E4428C): To generate the clock signal
4) Tektronix Digital Stimulus System (HFS 9009): To generate the data for the serial
programming of the chip including the control signals of the serial port
5) Agilent DC Power Supply (E3614A): To generate VDD for the board. The board has
discrete regulators to generate different supply voltages for the chip and only a single
power supply is necessary. However, several power supplies were also kept in the test
setup as any DC bias generation on the board or inside the chip can be disconnected and
an external supply can be used.
6) HP Oscilloscope: For quick verification of node voltages on the board
7) Agilent Multimeter (34401A): For quick verification of the dc voltages and the duty
cycle of the chip clock (which can be measured from the DUTYOUT node).

159

8) PC: The entire testing was carried out using MATLAB. The PC was responsible for
the GPIB interface as well as the data storage and manipulation during testing.
Figure 7.3 shows the pictures of the test setup and a closer view of the board.

Figure 7.3: a) Overall test setup b) Closer view of the test board

160

7.2. Measurement Results

The maximum speed achieved by the ADC is 2.5GS/s with Nyquist bandwidth. The
design was carried out with a target speed of 3GS/s but an on-chip problem due to the
clock driver limited the speed to 2.5GS/s. Both the unit C-2C SAR ADC and the overall
time-interleaved ADC performances were measured at this speed and the coming sections
present them in detail.

7.2.1.

Single C-2C SAR ADC DC and AC Performance

The measured transfer characteristic of the C-2C SAR ADC before and after radix
calibration is shown in Figure 7.4. The improvement after calibration can be easily
observed as the calibrated curve becomes very close the ideal one.

Figure 7.4: Measured transfer characteristic of the C-2C SAR ADC before and after
radix calibration.

161

In order to get more insight on the achieved improvement, the measured DNL and INL
plots of the ADC before and after radix calibration are presented in Figure 7.5. As seen,
radix calibration improves the DNL value from +1.3/-1LSB to 0.5LSB, and INL from
6.5LSB to 0.8LSB

Figure 7.5: Measured DNL and INL plots of the proposed ADC before and after radix
calibration
As mentioned, the sampling rate of the overall ADC is 2.5GS/s and 16 converters work in
parallel. Consequently, the sampling rate of a single ADC becomes 156.25MHz (Nyquist
frequency is 78.125MHz) and the clock frequency is 1.25GHz as both the negative and
the positive edges were used for interleaving. Figure 7.6 gives two measured output
spectrums (1M-point FFT) showing the SNDR and SFDR values of a single C-2C SAR

162

ADC when the input frequency is 5.24MHz and 68.3MHz. For both cases, the SNDR is
greater than 38dB while SFDR is always less than -50dBc.

Figure 7.6: Measured output spectrums (1M-point FFT) showing the SNDR and
SFDR values of a single C-2C SAR ADC when the input frequency is 5.24MHz and
68.3MHz.
Figure 7.7 shows the measured SFDR and SNDR with input frequency of a single C-2C
SAR ADC in the Nyquist zone. As seen the responses are fairly flat and the SFDR is less

163

than -49dBc while the SNDR is better than 38dB for entire input range. The single ADC
has an ENOB of 6.1 bits and the FoM is around 180fJ/conv by using the definition
below:

FoM =

Total Power
2 E.OB f S

Eq. 7.1

Figure 7.7: Measured SFDR and SNDR with input frequency of a single C-2C SAR
ADC in the Nyquist zone
Since the ADC is used in a time-interleaved topology with a sampling rate of 2.5GS/s and
having Nyquist bandwidth (1.25GHz), a single ADC should also be able to have the same
bandwidth as there is no front-end T&H. Hence, a 1.29GHz input was applied to a single
ADC and the SNDR and the SFDR values were checked. Figure 7.8 gives the measured
output spectrum (1M-point FFT) for this case in which the 1.29GHz input signal is
aliased down to 40MHz as the clock frequency is 1.25GHz. As seen the measured SNDR
and SFDR values are very close to the SNDR and the SFDR values reported above for
the Nyquist bandwidth of a single SAR ADC, showing that the input sampling network
of a single ADC has wide enough bandwidth to be utilized in the proposed time-

164

interleaving scheme.

Also, in addition to the reported FoM value above, another

common FoM expression in the literature is:

FoM =

Total Power
2 E.OB 2 ERBW

Eq. 7.2

where ERBW stands for the Effective Resolution Bandwidth of the ADC. As a single
SAR ADC can sample an input signal at 1.29GHz, the ERBW of the single C-2C SAR
ADC can be approximately taken as 1.25GHz which gives a FoM value of 20fJ/convstep.

Figure 7.8: Measured output spectrum (1M-point FFT) of a single C-2C SAR ADC
when the input and clock frequencies are 1.29GHz and 1.25GHz, respectively.
Figure 7.9 presents the measured input amplitude versus SNDR characteristic of the
single C 2C SAR ADC. As seen, the SNDR increases almost linearly with the amplitude
which proves the good linearity of the converter.

165

Figure 7.9: Measured input amplitude versus SNDR characteristic of the single C-2C
SAR ADC.

7.2.2.

Overall Time-Interleaved C-2C SAR ADC Performance

The linearity of the overall converter can be accepted as the linearity of a single SAR
ADC as time-interleaving basically averages the transfer curves. But, it should be noted,
there might be degradation in linearity due to mismatches. However, this degradation is
not directly caused by the converters but comes from the variations in the offsets, gains,
and clock edges.
Figure 7.10 compares the measured output spectrums (1M-point FFT) of the timeinterleaved SAR ADC before and after mismatch calibrations (offset, gain, and clock
skew) when the input frequency is 940.5MHz at full sampling speed. Big spurs due to
mismatches at the spectrum of the non-calibrated case become smaller after the

166

calibrations are carried out and almost a 5-bit improvement is achieved in SNDR with a
10.5dB improvement in SFDR.

Figure 7.10: Measured output spectrum (1M-point FFT) of the time-interleaved SAR
ADC before and after mismatch calibrations, when the input frequency is 940.5MHz at
full sampling speed

167

The measured SNDR and SFDR of the overall converter sampling at 2.5GS/s with input
frequency is shown in Figure 7.11 along with an output spectrum (1M point FFT) for an
input frequency of 1.096GHz when the input is full-scale. The SFDR is less than -43dBc
and SNDR is better than 34dB within the Nyquist band, which corresponds to an ENOB
of 5.4 bits.

Figure 7.11: Measured SFDR and SNDR with input frequency of the time-interleaved
SAR ADC and output spectrum (1M point FFT) for Fin=1.1GHz for a sampling rate of
2.5GS/s

168

The total power dissipation of the overall time-interleaved ADC is 50mW (excluding the
reference generation) and it is distribution is given in Table 7.1.

Table 7.1: Power dissipation distribution of the overall ADC

Single ADC power dissipation (Total=2mW)
Comparator and Analog blocks

0.5mW

Digital Control Logic

1.5mW

Overall ADC power dissipation (50mW)

16 ADCs

32mW

Clock buffers and peripheral blocks

18mW

Power Distribution
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%

Reference Power
Clock Power
Digital Power
Analog Power

Single ADC

Overall ADC

Figure 7.12: Power distribution of the unit SAR ADC and the overall converter
Figure 7.12 shows the percentage power distribution of the unit SAR ADC and the
overall converter. It can be seen that for a unit SAR ADC around 25% of the power
dissipation is done by the analog blocks mainly by the comparator whereas 75% is
consumed the digital blocks. This is primarily because the digital blocks have custom
gates and flip-flops optimized for maximum speed and these custom designs are power

169

hungry. For the overall chip, almost half of the power dissipation goes to the reference
distribution network. This network was over-designed and a power optimization can be
carried out for improving the efficiency. The second major power dissipation source is
the global and local clock distribution which covers slightly less than 20% of the overall
power. The rest of the power is dissipated by the digital and analog blocks of the ADCs.
Finally, the overall FOM of the converter for input frequencies within the Nyquist band is
480fJ/conv. The measured bit error rate is around 10-7-10-6 which is very close to the
value calculated from the regeneration time constant of the comparator. Finally, Figure
7.13 shows performance summary and die shot of the TI SAR ADC.

Process

45nm LP CMOS

Active Area

1mm2

Resolution

7 bits

Sample Rate

2.5GS/s

Supply Voltage

1.1V

Vref_max

700mV

Vref_min

200mV

Input Range

1.0Vpp differential

Power Consumption

50mW

D!L/I!L

0.5LSB / 0.8LSB

Single ADC S!DR/SFDR

>38dB/ <-49dBc

Single ADC E!OB

6.1b within !yquist

Single ADC FOM

180fJ/conv

TI SAR ADC S!DR/SFDR >34dB/ <-43dBc

TI SAR ADC E!OB

>5.4b within !yquist

TI SAR ADC FOM

480fJ/conv

Figure 7.13: Die photo and performance summary

170

CHAPTER VII

8. CO!CLUSIO!S A!D FUTURE WORK

The research performed in the framework of this thesis involves the design and testing of
a 7-bit, 2.5GS/sec, 16-times time-interleaved C-2C SAR ADC in a low-power 45nm
standard digital CMOS process. The fabricated chip is intended to be utilized in a 60GHz
OFDM-based receiver for high-speed low-range wireless communication applications.
The design and the measurements were carried out at Communications Circuits
Laboratory (CCL) in the Jones Farm Campus of Intel Corporation, OR and the chip
fabrication was done by Taiwan Semiconductor Manufacturing Company (TSMC).
This chapter summarizes the work that has been carried out in the framework of this
thesis. Section 8.1 gives the conclusions and finally Section 8.2 presents most if not all
possible future works that can be done over the same research area.

8.1. Conclusions
Important achievements were gained during this research. Based on them, the following
conclusions can be presented:
1) The design constraints and the target specifications of the ADC were investigated in
detail. A wide and deep literature search was performed to observe the state-of-the-art
performances of the ADC topologies that can be utilized for the application of interest.

171

Based on the given specifications and the results of the literature survey, the timeinterleaving scheme was picked for the proposed ADC.
2) A comprehensive search was done to select a right unit ADC topology that is
supposed to be utilized for time-interleaving. As the process is a 45nm LP digital CMOS
process, SAR ADCs were picked among SAR, Flash, Folding, and Subranging ADCs,
since they are digital friendly and scalable architectures.
3) Two different SAR ADC topologies (with binary weighted DAC and with C-2C
DAC) and their state-of-the-art performances were investigated. Due to their potential of
improving the speed and the bandwidth, the one with a C-2C DAC was chosen for the
proposed SAR ADC.
4) Previously published C-2C DAC topologies, their advantages and disadvantages,
performance limitations, calibration schemes were thoroughly covered to improve the
performance of the proposed SAR ADC. It has been observed that the biggest drawback
comes from the parasitic capacitance issue inside the DAC and a novel C-2C DAC
architecture was designed with two different calibration schemes (CRC and FRC) to
compensate the radix problem due to parasitics. These calibration schemes do not require
any special input signal or complicated circuitries and are carried out at the start-up of the
converter.
5)

The number of input sampling switches necessary for sampling was scaled

significantly for the proposed design.

This improves the bandwidth considerably

especially for high-speed time-interleaved ADCs as there are many ADCs working in
parallel, resulting in a huge number of switches connected to the input if there is no frontend T&H.
6) As the threshold voltage of the CMOS process is high and the switch design is
challenging, different boosted and bootstrapped switch topologies were searched. A high
speed input-aware boosted switch design was carried out which was utilized both for the

172

reference voltage and the input sampling. This switch occupies a very small area and
achieves very high speed which improves the bandwidth significantly.
7) Different comparator offset calibration schemes were explored thoroughly as high
speed comparators suffer from large offset voltages. A very effective offset background
calibration scheme was developed for the comparator of the proposed SAR ADC. Unlike
the previously published works on offset-calibration, the proposed calibration scheme
does not require capacitors, does not cause additional loading, and does not need
redundancy or trimmable devices. It is very compatible with Digital CMOS processes
and can be carried out at the background for SAR ADCs.
8) A dynamic biasing scheme was included to the comparator design to improve the
efficiency of the converter by increasing or decreasing the power dissipation where
necessary. Although not very important for the proposed SAR ADC, this dynamic
biasing scheme can be very effective for converter topologies with many comparators
such as Flash ADCs.
9) A detailed research was carried out on time-interleaving. Problems due to offset and
gain mismatches and clock skew were covered thoroughly and different background and
foreground calibration schemes were investigated.
10) Sixteen 7-bit C-2C SAR ADCs were time-interleaved to achieve the target sampling
rate of 2.5GS/s. This corresponds to an individual ADC sampling rate of 156.25MHz.
Each unit ADC was designed to cover an ERBW of 1.25GHz, making the overall ADC
have Nyquist bandwidth at full speed.
11) As mismatches among time-interleaved unit ADCs degrade the performance of the
overall converter, offset, gain and clock skew calibration schemes were implemented
with the proposed SAR ADC. Two extra ADCs were added to the design in order to
calibrate gain and offset mismatches in the background.

173

On-chip delay lines were

included to every unit ADC in order to align the clock edges and eliminate the clock
skew problem.
12) The overall ADC occupies 1.5mm x 2mm including 74 pads most of which are only
for supply and ground connections. 5 different supply voltages were used inside the chip
to minimize the coupling between different components and improve the noise immunity
of the circuitries.
13) The fabricated ADCs were packaged in a 48-pin QFN package. Both the DC and the
AC performance metrics for measured. Two different 4-layer PCBs were prepared for
the measurements. The first PCB was implemented with a socket and used to verify the
functionality of the chip.

The second PCB was implemented with a chip-on-board

architecture in which the packaged dies were soldered directly on the board. This board
was utilized to observe the performance limits of the functionally verified converters.
14) A single C-2C SAR consumes 2mW from a 1.1V supply and occupies an area of
0.1mm x 0.5 mm. The linearity of the converter was measured before and after radix
calibration. Radix calibration improves the DNL value from +1.3/-1LSB to 0.5LSB,
and INL from 6.5LSB to 0.8LSB. The measured SFDR is less than -49dBc and the
measured SNDR is better 38dB for a single SAR ADC for entire input range. The single
ADC has ENOB=6.1 bits and FOM=power/(sample-rate*2ENOB) =180fJ/conv.
15) The overall ADC consumes 50mW from a 1.1V (excluding the reference generation)
with an active area of 1mm2. The total area including pads is 1.5mm x 2mm. The
measured SNDR and SFDR of the 16 times time-interleaved ADC sampling at 2.5GS/s
are better than -43dBc and 34dB, respectively, in the Nyquist bandwidth.

This

corresponds to an ENOB of 5.4 bits within the Nyquist band. The overall FoM of the
converter for input frequencies within the Nyquist band is 480fJ/conv.

174

16) Overall performance of the proposed time-interleaved C-2C SAR ADC is very
comparable with the state-of-the-art performances of converters having similar
specifications and even better than most of these converters. This ADC is the first 7-bit
converter implemented in a LP 45nm Digital CMOS process achieving 2.5GS/s sampling
rate with Nyquist bandwidth, to the best of the authors knowledge.

8.2. Future Works

Although very important achievements were obtained in the framework of this thesis,
more research and improvement can be still carried out as future works. These works can
be listed as follows:
1) The resolution can be improved by exploring more effective and more accurate radix
calibration schemes. Moreover, a new background calibration scheme can be developed
in order to eliminate the necessity of halting the operation of the converter for calibration.
2) The target speed was 3GS/s but due to an on-chip problem with the clock divider,
sampling rate of the proposed ADC reached up to 2.5GS/s. A modified design can be
carried out by fixing the problem. Moreover, the speed of the ADC can be improved by
using minimum size devices in the comparator and minimizing the delay of the digital
cells at the critical path.
3) The clock skew problem due to time-interleaving was solved by on-chip delay lines
however the proposed calibration is not done in the background as a sinusoidal input is
necessary. The possibilities of implementing a new calibration scheme that can be
applied in the background can be investigated. A digital calibration technique based on
FIR filters can be also considered instead of delay lines.

175

4) Metastability error probability can be reduced by improving the comparator.

Moreover, a digital metastability check circuitry can be implemented to mitigate the
BER. BER can be also improved by equating the delays (setup times) of the control logic
of the DAC switches.
5) The ADC can be implemented in more advanced CMOS processes like 32nm and
22nm digital CMOS to observe the scalability and estimate the future performance.
General purpose transistor models for these kinds of processes are available in the
literature.
6) The proposed input-aware boosted switch enhances the speed and the bandwidth
considerably.

However, the on-resistance of the switch might become higher than

expected if the signal has a sharp rising edge which might be possible if the signal
frequency is very close to the Nyquist band corner. The switch design can be improved
to solve this problem.
7) Possible improvement techniques on reference voltage generation and distribution can
be explored. A bandgap design can be added to the system and the OTA designs can be
enhanced or buffers with strong driving capability can be utilized instead of OTAs.
8) The proposed comparator offset background calibration scheme is very effective but
covers a limited range as the body biasing can change the threshold voltage of the
transistors up to a certain range. A new offset calibration scheme can be proposed by
adding a coarse calibration which enables to use minimum size devices in the comparator
to boost the speed.
9) The reference voltage distribution of the overall ADC was not optimized for minimum
power dissipation. The overall power dissipation is 60mW and exceeds the total power
dissipation of the ADC including clock power. An optimized design can be carried out to
improve the efficiency of the system.

176

10) An on-chip memory can be included in the ADC design to simplify the measurements
by connecting each ADC output to a memory block. This will eliminate the necessity of
using a high speed Logic Analyzer system and the external reconstruction of the overall
ADC data can be much easier as all ADC outputs can be captured at the same time.
11) Similarly, a very high speed Logic Analyzer system can be utilized for the future
implementations. Systems achieving sampling rates over 10GS/s are now commercially
available.

177

REFERE!CES

[1]

C. E. Shannon, A Symbolic Analysis of Relay and Switching Circuits,

Dissertation for Degree of Master of Science, Massachusetts Institute of
Technology, Dept. of Electrical Engineering, August 1937.

[2]

D. Tse and P. Viswanath, Fundamentals of Wireless Communication, Cambridge

University Press, 2005, pp. 1-5.

[3]

http://www.ntia.doc.gov/osmhome/allochrt.pdf

[4]

B. Furht, M. Ilyas, Wireless Internet Handbook Technologies, Standards, and

Applications, CRC Press, 2003, pp. 7.

[5]

http://en.wikipedia.org/wiki/Quadrature_amplitude_modulation

[6]

T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge

University Press, 2004, pp. 76-77

[7]

N. S. Jayant and P. Noll, Digital Coding of Waveforms Principles and Applications

to Speech and Video, Prentice-Hall, 1984, pp. 118.

[8]

W. K. Miller and J. Lansford, An Evaluation of the Effects of Quantization

Technique on the Performance of Digital Matched Filters in a Direct Sequence
Spread Spectrum Receiver, IEEE Inter. Symp. on Spread Spect. Techniques and
Appl., vol 2, pp. 347-351, July 1994

[9]

R. v. d. Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog

Converters, Kluwer Academic Publishers, 2003

[10] W. R. Bennett, Spectra of Quantized Signals, Bell System Technical Journal,

vol.27, pp. 446-471, July 1948
[11] W. Kester, Ed., The Data Conversion Handbook, Newnes 2005
[12] F. Maloberti, Data Converters, Springer 2007
[13] M. v. Elzakker, E. v. Tujil, P. Geraedts, D. Schinkel, E. Klumperink, B. Nauta, A
1.9 W 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC, ISSCC

178

Dig. Tech. Papers, pp. 244-245, Feb. 2008

[14] M. Harwood, et al., "A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC
with Digital Receiver Equalization and Clock Recovery," ISSCC Dig. Tech.
Papers, pp. 436-437, Feb. 2007.
[15] M. Verhelst, N. V. Helleputte, G. Gielen, W. Dehaene, A Reconfigurable, 0.13um
CMOS 110pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and
Sub-cm Ranging, ISSCC Dig. Tech. Papers, pp. 250-251, Feb. 2009.
[16] S. Pinel, S. Sarkar, P. Sen, B. Perumana, D. Yeh, D. Dawn, J. Laskar, A 90nm
CMOS 60GHz Radio, ISSCC Dig. Tech Papers, pp. 130-131, Feb. 2008.
[17] S. Limotyrakis, K. Y. Nam, B. A. Wooley, Analysis and Simulation of Distortion
in Folding and Interpolating A/D Converters, IEEE Trans. Circuits and SystemsII, vol. 49, no. 3, pp. 161-169, Mar. 2002.
[18] S. K. Gupta, M. A. Inerfield, J. Wang, A 1-GS/s 11-bit ADC With 55-dB SNDR,
250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved
Architecture. IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 26502657, Dec.
2006.
[19] A. Ismail, and M. Elmasry, A 6-Bit 1.6-GS/s Low-Power Wideband Flash ADC
Converter in 0.13-m CMOS Technology, IEEE J. Solid-State Circuits, vol. 43,
no. 9, pp. 19821990, Sept. 2008.
[20] C. Lu, L. Huang, W. Li, A 2-Bit 4GS/s Flash A/D Converter in 0.18 m CMOS
for an IR-UWB Communication System, .inth International Conference on
Solid-State and Integrated Circuit Technology, pp. 1965-1968, Oct. 2008
[21] S. Sheikhaei, S. Mirabbasi, A. Ivanov, An Encoder For a 5GS/S 4-Bit Flash ADC
In 0.18m CMOS, Canadian Conference on Electrical and Computer
Engineering, pp. 698-701, May 2005
[22] J. E. Proesel and L. T. Pileggi, A 0.6-to-1V Inverter-Based 5-bit Flash ADC in
90nm Digital CMOS, Proc. IEEE CICC, pp. 153156, Sept. 2008
[23] C. Sandner, M. Clara, A. Santner, T. Hartig, and F. Kuttner, A 6-bit 1.2-GS/s
Low-Power Flash-ADC in 0.13-m Digital CMOS, IEEE J. Solid-State Circuits,
vol. 40, no. 7, pp. 14491505, July 2005
[24] K. Deguchi, N. Suwa, M. Ito, T. Kumamoto, T. Miki, A 6-bit 3.5-GS/s 0.9-V 98mW Flash ADC in 90-nm CMOS, IEEE J. Solid-State Circuits, vol. 43, no. 10,
pp. 23032310, Oct. 2008

179

[25] J. Kim, M.-Y. Kim, H.-K. Lee, I. Jung, C. Kim, Low-power Architecture for a 6bit 1.6GS/s Flash A/D Converter, ICCE Dig. Tech. Papers, pp. 1-2, Jan. 2009.
[26] H.-G. Wei, U-F. Chio, Y. Zhu, S.-W. Sin, S.-P. U, R.P. Martins, A Power
Scalable 6-bit 1.2GS/s Flash ADC with Power on/off Track-and-Hold and
Preamplifier, Proc. IEEE ISCAS, pp 5-8, May 2008
[27] K. A. Shehata, H. Husien, H. F. Ragai, 1.5GSPS 4-bit flash ADC using 0.18m
CMOS, International Conference on Microelectronics, pp. 311-314, Dec. 2007
[28] B.-W. Chen, S.-K. Hsien, C.-S. Chiang, K.-C. Juang, A 6-Bit, 1.2-GS/s ADC with
Wideband THA in 0.13-m CMOS, IEEE Asian Solid-State Circuits Conference,
pp. 381-384, Nov. 2008
[29] H. Yu and M.-C. F. Chang, A 1-V 1.25-GS/S 8-Bit Self-Calibrated Flash ADC
in 90-nm Digital CMOS, IEEE Trans. Circuits and Systems-II Express Briefs, vol.
55, no. 7, pp. 668-672, July 2008.
[30] T. Sundstrom and A. Alvandpour, A 2.5-GS/s 30-mW 4-bit Flash ADC in 90nm
CMOS, Proc. IEEE .ORCHIP, pp. 264-267, Nov 2008.
[31] Y.-Z. Lin, C.-W. Lin, S.-J. Chang, A 2-GS/s 6-bit Flash ADC with Offset
Calibration, IEEE Asian Solid-State Circuits Conference, pp. 385-388, Nov. 2008.
[32] I-H. Wang and S.-I. Liu, A 1V 5-Bit 5Gsample/Sec CMOS ADC for UWB
Receivers, IEEE Int. Symp. on VLSI-DAT, pp. 1-4, Apr. 2007.
[33] S. Sheikhaei, S. Mirabbasi, A. Ivanov, A 43mW Single-Channel 4GS/s 4-Bit
Flash ADC in 0.18m CMOS, Proc. IEEE CICC, pp. 333336, Sept. 2007.
[34] Y.-Z. Lin, Y.-T. Liu, S.-J. Chang, A 5-bit 4.2-GS/s Flash ADC in 0.13-m
CMOS, Proc. IEEE CICC, pp. 213216, Sept. 2007.
[35] M. Choi, J. Lee, J. Lee, H. Son, A 6-bit 5-GSample/s Nyquist A/D Converter in
65nm CMOS, IEEE Symp. on VLSI Circuits, pp. 16-17, June 2008.
[36] G. V. d. Plas, S. Decoutere, S. Donnay, A 0.16pJ/Conversion-Step 2.5mW
1.25GS/s 4b ADC in a 90nm Digital CMOS Process, ISSCC Dig. Tech. Papers,
pp. 2308-2309, Feb. 2006.
[37] R. Thirugnanam, D. S. Ha, S. S. Choi, Design of a 4-bit 1.4 GSamples/s Low
Power Folding ADC for DS-CDMA UWB Transceivers, IEEE International
Conf. on Ultra-Wideband, pp. 536-541, Sept. 2005.

180

[38] D. Lee, S. Yeo, H. Kang, D. Kim, J. Moon, M. Song, Design of a 6-bit 1GSPS
Fully Folded CMOS A/D Converter For Ultra Wide Band (UWB) Applications,
IEEE International Conference on Integrated Circuit Design and Technology, pp.
113-116, June 2008.
[39] K. Makigawa, K. Ono, T. Ohkawa, K. Matsuura, M. Segami, A 7bit 800Msps
120mW Folding and Interpolation ADC Using a Mixed-Averaging Scheme,
Symp. on VLSI Circuits Dig. Tech. Papers, pp. 138-139, 2006.
[40] R. C. Taft, P. A. Francese, M. R. Tursi, O. Hidri, A. MacKenzie, T. Hoehn, P.
Schmitz, H. Werker, A. Glenny, A 1.8V 1.0GS/s 10b Self-Calibrating UnifiedFolding-Interpolating ADC with 9.1 ENOB at Nyquist Frequency, ISSCC Dig.
Tech. Papers, pp. 78-79, Feb. 2009.
[41] Y. Chen, Q. Huang, T. Burger, A 1.2V 200-MS/s 10-bit Folding and Interpolating
ADC in 0.13-m CMOS, 33rd European Solid State Circuits Conf., pp. 155-158,
Sept. 2007.
[42] J. Moon, S. Jung, S. Hwang, M. Song, A 6b 100MS/s 0.28mm2 5mW 0.18um
CMOS F/I ADC with a Novel Folder Reduction Technique, 13th IEEE
International Conf. on Electronics, Circuits and Systems, pp. 140-143, Dec. 2006.
[43] D. Lee, J. Song, J. Shin, S. Hwang, M. Song, T. Wysocki, Design of a 1.8V 8-bit
500MSPS Folding-Interpolation CMOS A/D Converter with a Folder Averaging
Technique, 18th European Conf. on Circuit Theory and Design, pp. 356-359, Aug.
2007.
[44] H. Movahedian and M. S. Bakhtiar, A 1.5V 8-Bit Low-Power Self-Calibrating
High-Speed Folding ADC, PhD Research in Microelectronics and Electronics,
pp. 55-58, July 2005.
[45] P. M. Figueiredo, P. Cardoso, A. Lopes, C. Fachada, N. Hamanishi, K. Tanabe, J.
Vital, A 90nm CMOS 1.2V 6b 1GS/s Two-Step Subranging ADC, ISSCC Dig.
Tech. Papers, pp. 2320-2329, Feb. 2006.
[46] K. Ohhata, K. Uchino, Y. Shimizu, Y. Oyama, K. Yamashita, A 770-MHz, 70mW, 8-bit Subranging ADC using Reference Voltage Precharging Architecture,
IEEE Asian Solid-State Circuits Conference, pp. 41-44, Nov. 2008.
[47] D. J. Huber, R. J. Chandler, A. A. Abidi, A 10b 160MS/s 84mW 1V Subranging
ADC in 90nm CMOS, ISSCC Dig. Tech. Papers, pp. 454-455, Feb. 2007.
[48] Y. Shimizu, S. Murayama, K. Kudoh, H. Yatsuda, A Split-Load Interpolation-

181

Amplifier-Array 300MS/s 8b Subranging ADC in 90nm CMOS, ISSCC Dig.

Tech. Papers, pp. 552-553, Feb. 2008.
[49] Y.-C. Lien and J. Lee, A 6-b 1-GS/s 30-mW ADC in 90-nm CMOS Technology,
IEEE Asian Solid-State Circuits Conference, pp. 45-48, Nov. 2008.
[50] H.-Y. Huang, Y.-Z. Lin, S.-J. Chang, A 5-bit 1 GSample/s Two-Stage ADC with
a New Flash Folded Architecture, Proc. IEEE TE.CO., pp. 1-4, Oct 2007.
[51] B. Verbruggen, J. Craninckx, M. Kuijk, P. Wambacq, G. V. d. Plas, A 2.2mW 5b
1.75GS/s Folding Flash ADC in 90nm Digital CMOS, ISSCC Dig. Tech. Papers,
pp. 252-253, Feb. 2008.
[52] N. Ning, L. Fan, S. Wu, Y. Liu, G. Liu, Q. Yu, M. Yang, An 8-Bit 250MSPS
Modified Two-Step ADC, Proc. International Conf. on Communications, Circuits
and Systems, pp. 2197-2200, June 2006.
[53] Z. Cao, S. Yan, A 52mW 10b 210MS/s Two-Step ADC for Digital-IF Receivers
in 0.13m CMOS, Proc. IEEE CICC, pp. 309312, Sept. 2008.
[54] C.-C. Hsu, C.-C. Huang, Y.-H. Lin, C.-C. Lee, Z. Soe, T. Aytur, and R.-H. Yan,
A 7b 1.1GS/s Reconfigurable Time-Interleaved ADC in 90nm CMOS, Symp. on
VLSI Circuits Dig. Tech. Papers, pp. 66-67, June 2007.
[55] S. M. Louwsma, A. J. M. v. Tuijl, M. Vertregt, B. Nauta, A 1.35 GS/s, 10 b, 175
mW Time-Interleaved AD Converter in 0.13 m CMOS, IEEE J. Solid-State
Circuits, vol. 43, no. 4, pp. 778786, Apr. 2008.
[56] B. P. Ginsburg and A. P. Chandrakasan, 500-MS/s 5-bit ADC in 65-nm CMOS
With Split Capacitor Array DAC, IEEE J. Solid-State Circuits, vol. 42, no. 4, pp.
739747, Apr. 2007.
[57] W.-H. Tu, T.-H. Kang, A 1.2V 30mW 8b 800MS/s Time-interleaved ADC in
65nm CMOS, Symp. on VLSI Circuits Dig. Tech. Papers, pp. 72-73, June 2008.
[58] A. Varzaghani and C.-K. K. Yang, A 4.8 GS/s 5-bit ADC-Based Receiver With
Embedded DFE for Signal Equalization, IEEE J. Solid-State Circuits, vol. 44, no.
3, pp. 901915, Mar. 2009.
[59] C.-C. Hsu, F.-C. Huang, C.-Y. Shih, C.-C. Huang, Y.-H. Lin, C.-C. Lee, B. Razavi,
An 11b 800MS/s Time-interleaved ADC with Digital Background Calibration,
ISSCC Dig. Tech. Papers, pp. 464-465, Feb. 2007.
[60] B. P. Ginsburg, A. P. Chandrakasan, Highly Interleaved 5b 250MS/s ADC with

182

Redundant Channels in 65nm CMOS, ISSCC Dig. Tech. Papers, pp. 240-241,
Feb. 2008.
[61] S.-W. M. Chen and R. W. Brodersen, A 6b 600MS/s 5.3mW Asynchronous ADC
in 0.13m CMOS, ISSCC Dig. Tech. Papers, pp. 2350-2359, Feb. 2006.
[62] P. Schvan, et.al., A 24GS/s 6b ADC in 90nm CMOS, ISSCC Dig. Tech. Papers,
pp. 544-545, Feb. 2008.
[63] J. L. McCreary and P. R. Gray, All-MOS charge redistribution analog-to-digital
conversion techniques Part 1, IEEE J. Solid-State Circuits, vol. SC-10, no. 6,
pp. 371379, Dec. 1975
[64] S. Dondi, D. Vecchi, A. Boni, M. Bigi, A 6-bit, 1.2 GHz Interleaved SAR ADC
in 90nm CMOS, PhD Research in Microelectronics and Electronics, pp. 301-304,
2006
[65] C.-C. Liu, Y.-T. Huang, G.-Y. Huang, S.-J. Chang, C.-M. Huang, C.-H. Huang, A
6-bit 220-MS/s Time-Interleaving SAR ADC in 0.18-m Digital CMOS Process,
IEEE Int. Symp. on VLSI-DAT, pp. 215-218, Apr. 2009
[66] J. Craninckx, G. V. d. Plas, A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b
Charge-Sharing SAR ADC in 90nm Digital CMOS, ISSCC Dig. Tech. Papers,
pp. 246-247, Feb. 2007.
[67] V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. V. d. Plas, J. Craninckx, An
820W 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS.
ISSCC Dig. Tech. Papers, pp. 238-239, Feb. 2008.
[68] Y. S. Yee, L. M. Terman, and L. G. Heller, A Two-Stage Weighted Capacitor
Network for D/A-A/D Conversion, IEEE J. Solid-State Circuits, vol. SC-14, no.
4, pp. 778781, Aug. 1979
[69] S. P. Singh, A. Prabhakar, and A. B. Bhattcharyya, C-2C Ladder-Based D/A
Converters for PCM codecs, IEEE J. Solid-State Circuits, vol. SC-22, no. 6, pp.
11971200, Dec. 1987
[70] L. Cong, Pseudo C-2C Ladder-Based Data Converter Technique, IEEE Trans.
Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 10, pp. 927-929, Oct.
2001
[71] Y.-M. Liao and T.-C. Lee, A 6-b 1.3Gs/s A/D Converter with C-2C SwitchCapacitor Technique, IEEE Int. Symp. on VLSI-DAT, pp. 1-4, Apr. 2006.

183

[72] H. Kim, Y. Min, Y. Kim, and S. Kim, A Low Power Consumption 10-bit Rail-toRail SAR ADC Using a C-2C Capacitor Array, IEEE Int. Conf. on EDSSC, pp. 14, Dec. 2008.
[73] S.-W. M. Chen, R. W. Brodersen, A 6-bit 600-MS/s 5.3-mW Asynchronous ADC
in 0.13-m CMOS, IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 26692680,
Dec. 2006.
[74] S.-W. Lee, H.-J. Chung and C.-H. Han, C-2C Digital-to-Analogue Converter on
Insulator, IEEE Electron. Lett., vol. 35, no. 15, pp. 1242-1243, July 1999.
[75] W. C. Black, Jr. and D. A. Hodges, Time Interleaved Converter Arrays, IEEE J.
Solid-State Circuits, vol. SC-15, no. 6, pp. 1022-1029, Dec. 1980.
[76] S. M. Jamal, D. Fu, M. P. Singh, P. J. Hurst, S. H. Lewis, Calibration of SampleTime Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter,
IEEE J. Solid-State Circuits-I: Regular Papers, vol. 51, no. 1, pp. 130139, Jan.
2004.
[77] J. Elbornsson, F. Gustafsson, J.-E. Eklund, Blind Adaptive Equalization of
Mismatch Errors in a Time-Interleaved A/D Converter System, IEEE Trans.
Circuits Syst. I: Regular Papers., vol. 51, no. 1, pp. 151-158, Jan. 2004.
[78] K. C. Dyer, D. Fu, S. H. Lewis, P. J. Hurst, An Analog Background Calibration
Technique for Time-Interleaved Analog-to-Digital Converters, IEEE J. SolidState Circuits, vol. 33, no. 12, pp. 19121919, Dec. 1998.
[79] A. Cabrini, F. Maloberti, R. Rovatti, G. Setti, On-line Calibration of Offset and
Gain Mismatch in Time-Interleaved ADC using a Sampled-data Chaotic Bitstream, Proc. IEEE ISCAS, pp 3398-3401, May 2006
[80] Y-C Jenq, Digital Spectra of Nonuniformly Sampled Signals: A Robust Sampling
Time Offset Estimation Algorithm for Ultra High-speed Waveform Digitizers
Using Interleaving, IEEE Trans. Instrum. Meas, vol. 39, no. 1, pp. 71-75, Feb.
1990.
[81] Y-C Jenq, Digital Spectra of Nonuniformly Sampled Signals: Fundamentals and
High Speed waveform digitizers, IEEE Trans. Instrum. Meas, vol. 37, pp. 245251, June. 1988.
[82] Y-C Jenq, Digital Spectra of Nonuniformly Sampled Signals: Digital Table Lookup Tunable Oscillators, IEEE Trans. Instrum. Meas, vol. 37, no. 1, pp. 358-362,
Sept. 1988.

184

[83] H. Jin and E. K. F. Lee, A Digital-Background Calibration Technique for

Minimizing Timing-Error Effects in Time-Interleaved ADCs, IEEE Trans.
Circuits Syst. II: Analog and DSP, vol. 47, no. 7, pp. 603-613, July 2000.
[84] Z. Liu, K. Honda, M. Furuta, S. Kawahito, Timing Error Calibration in TimeInterleaved ADC by Sampling Clock Phase Adjustment, IEEE Proc. IMTC, pp. 14, Ma7 2007.
[85] T.-H. Tsai, P. J. Hurst. S. H. Lewis, Bandwidth Mismatch and Its Correction in
Time-Interleaved Analog-to-Digital Converters, IEEE Trans. Circuits Syst. II:
Express Briefs, vol. 53, no. 10, pp. 1133-1137, Oct. 2006.
[86] N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, K. Kobayashi, Explicit
Analysis of Channel Mismatch Effects in Time-Interleaved ADC Systems, IEEE
Trans. Circuits Syst. I: Fundamental Theory and Applications, vol. 48, no. 3, pp.
261-271, Mar. 2001.
[87] E. Alpman, H. Lakdawala, L. R. Carley, K. Soumyanath, A 1.1V 50mW 2.5GS/s
7b Time-Interleaved C-2C SAR ADC in 45nm LP Digital CMOS, ISSCC Dig.
Tech. Papers, pp. 76-77, Feb. 2009
[88] H.-C. Hong and G.-M. Lee, A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail
8-bit Successive Approximation ADC, IEEE J. Solid-State Circuits, vol. 42, no.
10, pp. 21612168, Oct. 2007
[89] A. M. Abo and P. R. Gray, A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-todigital converter, IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599606, May
1999
[90] D. Aksin, M. Al-Shyoukh, and F. Maloberti, Switch bootstrapping for precise
sampling beyond supply voltage, IEEE J. Solid-State Circuits, vol. 41, no. 8, pp.
19381943, Aug. 2006
[91] D. A. Johns and K. Martin, Analog Integrated Circuit Design, Wiley 1997, pp. 610
[92] S. Shekhar, J. S. Walling, D. J. Allstot, Bandwidth Extension Techniques for
CMOS Amplifiers, IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 24242439,
Nov. 2006
[93] B. Razavi and B. A. Wooley, Design techniques for high-speed, high-resolution
comparators, IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 19161926, Dec.
1992

185

[94] S. Park, Y. Palaskas, M. P. Flynn, A 4GS/s 4b Flash ADC in 0.18m CMOS,

ISSCC Dig. Tech. Papers, pp. 2330-2331, Feb. 2006
[95] E. Fogleman, I. Galton, W. Huff, and H. Jensen, A 3.3-V Single-Poly CMOS
Audio ADC DeltaSigma Modulator with 98-dB Peak SINAD and 105-dB Peak
SFDR, IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 297307, Mar. 2000
[96] K. Kattrnann and J. Barrow, A Technique for Reducing Differential NonLinearity Errors in Flash AID Converters. ISSCC Dig. Tech. Papers, pp. 170-171,
Feb. 1991
[97] S. Park, Y. Palaskas, A. Ravi, R. E. Bishop, and M. P. Flynn, A 3.5 GS/s 5-b
Flash ADC in 90 nm CMOS, IEEE Proc. CICC, pp. 489492, Sep. 2006
[98] J. M. Rabaey, Digital Integrated Circuits, Prentice Hall, 1995

186