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3, MARCH 2006


A High-Efficiency Fully Digital Synchronous Buck

Converter Power Delivery System Based
on a Finite-State Machine
Dae Woon Kang, Member, IEEE, Yong-Bin Kim, Senior Member, IEEE, and James T. Doyle, Senior Member, IEEE

AbstractA fully digital, self-adjusting, and high-efficiency

power supply system has been developed based on a finite-state
machine (FSM) control scheme. The system dynamically monitors
circuit performance with a delay line and provides a substantially
constant minimum supply voltage for digital processors to properly operate at a given frequency. In addition, the system adjusts
the supply voltage to the required minimum under different
process, voltage, and temperature and load conditions. The design
issues of the fully digital power delivery system are discussed
and addressed. This digital FSM scheme significantly reduces the
complexity of control-loop implementation ( 1800 gates) and
power consumption (
at 1.2 V) compared to other
approaches based on proportionalintegraldifferential control.
The power delivery control system is fabricated in a 0.132.
CMOS process and its core die size is 160 110

Index TermsAdaptive voltage scaling, digital switcher, high

yield, low-power dissipation.


HE STRONG demand for low-power computing has been

driven by a growing variety of portable and battery-operated electronic devices. These span a broad range of performance and functions with respect to throughput. Power consumption is a limiting factor in VLSI integration for portable
applications. The resulting heat dissipation also limits the feasible packaging and performance of the VLSI chip. Since the
dynamic power dissipation in synchronous digital integrated cir, reducing the supply voltage is an
cuits is determined by
effective way to reduce power consumption. However, the gate
delay of a digital gate is inversely proportional to the supply
voltage. Therefore, the application operates at a reduced clock
frequency with a lower supply voltage at the cost of performance
reduction to meet the low power requirement. This is not a desirable solution to keep pace with the current demand for improved
Adaptive voltage scaling (AVS) can decrease power consumption without sacrificing performance provided the tasks
performed are finished within the allowed time. If AVS is
employed to dynamically adjust both clock frequency and

Manuscript received December 14, 2004; revised October 29, 2005.

D. W. Kang and J. T. Doyle are with National Semiconductor Corporation,
Longmont, CO 80501 USA (e-mail:;
Y.-B. Kim was with the University of Utah, Salt Lake City, UT 84112 USA.
He is now with the Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115 USA (e-mail:
Digital Object Identifier 10.1109/TVLSI.2006.871764

supply voltage depending on the computational work load,

the power consumption required for the given task can be
dynamically and adaptively optimized. For instance, in many
portable-computing devices such as MP3-players and digital
cameras, the full processing capability of a processor is not
always required. There are certain times when the operating
frequency may be reduced; and a lower frequency means a
longer allowable delay. This increased time margin also allows
the supply voltage level to be lowered albeit with an increased
propagation delay. Since power consumption is quadratic
with supply voltage and proportional to operating frequency,
reducing both allows excellent energy-efficient operation. From
the tradeoff between performance and energy consumption,
supplying just enough voltage to a system at a given frequency
represents the optimum power consumption [1][9].
Techniques for minimizing power consumption using AVS
have been proposed for digital applications at a fixed throughput
[6], and demonstrated on silicon for microprocessor application
[7]. Their performance is improved for variable-rate digital
signal processing throughput [8] and [9]. Most previous works
used analog- or mixed-mode circuit techniques for these implementations, which caused yield and tuning problems due
to process, voltage, and temperature (PVT) variations. The
contribution of this paper is to extend these efforts by considering yield issues and the compensation of fabrication process
parameter nonuniformity in a single die, reference voltage
fluctuation, and temperature variation.
The conventional AVS system implemented using analog- or
mixed-mode circuitry presents another practical issue in utilizing AVS systems. This is the reuse of predefined intellectual
property (IP) along with fabrication process migration. Soft-IP
type is the only way to make the transition to deep-submicrometer technologies and multimillion-gate silicon systems in an
economical and timely manner. As systems-on-chip (SOC) become larger and more complex, they perform many different
functions on a single piece of silicon. Unless predefined parts
are used, the SOC is too expensive to produce and impossible
to bring to market in a timely manner. As one of these efforts,
the fully digital self-adjusting minimum-power supply system
is implemented as a soft-IP form.
This paper presents a fully digital synchronous adaptive buck
converter power delivery system that compensates the impact
of operational and intrinsic parameter fluctuations on circuit
performance and can be provided in soft-IP form. The implementation of the fully digital self-adjusting minimum-power
supply system to regulate the supply voltage as the minimum

1063-8210/$20.00 2006 IEEE



required operating value at given PVT and frequency is presented along with the detail algorithm to compensate the PVT
variations. The methodology for compensating the impact of
operational and parameter fluctuations on CMOS circuit performance is discussed in Section II. The implementation of the
fully digital self-adjusting minimum supply system and analysis
of measured results from fabricated test chips are described in
Section III and Section IV, respectively.
A. Yield Improvement by Adjusting Supply Voltage
While the operating frequency limits allowable propagation
delay, this delay strongly depends on intrinsic process parameters, supply voltage, and junction temperature. The propagation
delay in a MOSFET is proportional to the product of the active
resistance of the MOSFET and load capacitance as in (1)

is the velocity saturation term,
is the process
is the supply voltage,
transconductance parameter,
the threshold voltage,
is the drain capacitance,
is the
is the interconnect capacitance.
gate capacitance, and
In deep-submicrometer circuit design, variations due to the
process variation cause differences in transistor and interconnect characteristics across a single die. They, in turn, impact
the performance of circuits since they generate deviations in
MOSFET drive current, resulting in propagation delay distributions of the critical path across a chip. Furthermore, the distribution of process parameters expands from die to die within
a wafer as well as a lot. After fabrication, operating variations
such as power supply voltage, and across-chip temperature also
affect the propagation delay. By combining both operational
and process induced variations, the propagation delay fluctuates
from 18% to 32% [10]. The yield of CMOS logic circuits satisfying a specific performance requirement is significantly influenced by the magnitude of critical path delay deviations due to
both operational and intrinsic parameter fluctuations.
Process parameters and operating junction temperature are
not controllable, but supply voltage is. Therefore, if the supply
voltage can be adjusted to guarantee the same propagation delay
regardless of the other operating conditions, various simulations
are not needed to assure proper functionality. Instead, only one
case, the worst case simulation with small margin is needed to
guarantee proper operation after fabrication. If a design is fabricated at the best process corner and is operating at low temperature, it needs less than 3/4 of the minimum supply voltage
required to operate at the worst case [10]. This results in power
savings by reducing supply voltage with regard to process and
temperature. Moreover, the distribution of the variations can be
moved to the desirable position by increasing supply voltage as
shown in Fig. 1 [10]. On the other hand, by dynamically adjusting the supply voltage, the individual die is adjusted to the

Fig. 1. n

critical-path delay distribution shift from the nominal delay

V for a desired yield.

) due to an increase in

desirable performance. Typically the supply voltage should be

raised for dies that are operating slowly and lowered for the dies
that are performing fast. Therefore, the yield of the chip is improved if an AVS system is employed.
B. Delay Monitoring Under Different Operating Conditions
The propagation delay depends on PVT conditions which are
not determined before fabrication. Moreover, the junction temperature is determined at the moment of operation. Both are not
controllable, only observable. Alternatively, the supply voltage
is an adjustable factor to guarantee a desirable delay. Due to the
observability of process and temperature and the controllability
of supply voltage for the propagation delay in digital circuit, it
is possible to monitor and control critical path delay using its
replica circuit. This guarantees the minimum propagation delay
for operation at a given frequency.
Since the performance of a digital system is limited by its
worst case critical path delay, an exact replica of this delay path
within a single chip is one of the most accurate ways to measure delay variation with respect to different PVT variations.
However, designers normally balance delay paths as much as
possible. Moreover, critical paths may differ depending on operating conditions; therefore, identifying a single path may be
difficult. Instead, a series chain of primitive cells is considered
to model the critical path delay. The delay of a simple delay cell
properly tracks the critical path of digital circuits under various
operating environments [5]. Fig. 2 illustrates equivalent voltages
to guarantee the same propagation delay under different corners
of a 0.13- m process technology. By fabricating the critical path
replica of a digital circuit on the same die, its propagation delay
closely tracks the critical path of a chip over variations of PVT.
In designing the critical path replica to compensate the supply
voltage change due to PVT variations, the characterization data
such as load current at the target supply voltage and operating
frequency are considered since both will change as the load current changes. Fig. 3 shows the supply voltage changes due to the
load current variations.


Fig. 2. Function of supply voltage for a 0.13- process delay transfer characteristic at the best (bottom line), typical (middle line), and the worst (top line)


Fig. 4. Block diagram of a typical digital-controlled dcdc converter.

D. AVS Compensation Issues Over PVT

and Frequency Variations

Fig. 3. Supply voltage level shift (55 mV, top wave) due to variations of load
current change between 50 and 250 mA.

C. Prior Digital Control-Loops of DCDC Converter

Fig. 4 shows a typical digital-controlled switching converter
which consists of an analog-to-digital converter (ADC), a PID
compensator, a reference source, a digital pulse width modulator
(DPWM) regulator, and a dcdc converter [5]. The low-pass induct-capacitor (LC) filter in a dcdc converter is a two-pole resonant system to store energy. Since the response of a two-pole
system may have excessive energy, any transitions introduced
in the system may cause damped oscillation with a long decay
time in the LC network. Thus, to maintain a roughly constant
supply voltage in response to changes in PVT, load, and frequency, a compensation circuit is necessary. The compensation
circuit eliminates the ringing effect by adding a zero that cancels one pole in the LC network, resulting in a stable first-order
To achieve fast stable response in the pulsewidth modulation (PWM) mode, a discrete-time PID controller is typically
used. The PID control provides loop stability without sacrificing
bandwidth and improves the loops transient response. However, the implementation adds a heavy hardware burden because
a PID control equation is typically expressed in terms of the current and prior values of duty ratio, error between the current and
reference voltage, and the gains of the proportional (P), integral
(I), and differential (D) blocks that are multiplied by the error
signal as shown in Fig. 4.

To provide an error signal for a PID control loop, prior approaches require a reference source (constant voltage [11] or
fixed frequency [3]) that occupies space reserved for a design
and consumes power. Since the reference is implemented as
an analog- or mixed-signal circuit, it is difficult to implement
a fully digital AVS controller. Moreover, the pitfall of the reference based supply voltage schemes [3], [4], and [11] with regard to only a given frequency, is that its supply voltage is usually not the minimum voltage in which a chip operates properly.
The reason is that the propagation delay strongly varies in response to PVT as in (1) while a frequency determines an allowable propagation delay. In other words, if a chip is fabricated
at the best process corner and operates at low temperature, its
minimum supply voltage is only 3/4 of the minimum voltage to
guarantee the proper function at the worst case. The minimum
power consumption at the best case is about half of the worst
case due to the quadratic dependency of power. Therefore, the
adaptive-power supply system considers PVT and load conditions as well as operating frequency.
The presented AVS requires some additional restrictive considerations compared to prior AVS implementations due to both
delay and parameter variations. First, higher digital-to-analog
converter (DAC) resolution is needed since AVS is prone to be
in a limit-cycling mode. If the ADC has a 6-bit resolution at
3.3 V, the worst case step voltage is about 50 mV. If DAC has
7 bits, its resolution at 3.6 V is about 28 mV and may avoid
limit-cycling. However, the step voltage is about 26.5 mV at the
best case as shown in Fig. 2. This results in limit-cycling since
7-bit DAC resolution at the worst case is less than that of 6-bit
ADC at the best case. Therefore, 8-bit DAC resolution is needed
to prevent limit-cycling from occurring. The DACs higher resolution than the ADC often results in multiple DAC values in the
ADC. When a high to low transition occurs with a frequency
change, the highest DAC voltage level equal to the ADC level
may be a settling point. Alternatively, during low to high, the
lowest level may be acquired.



Fig. 5. Block diagram of all digital self-adjusting minimum power supply system.

Fig. 6. Circuit schematic of slacktime detector.


A block diagram of the all digital self-adjusting minimum
power supply system is presented in Fig. 5. The system consists of a closed-loop controller, a fixed frequency clock signal
(CLK), frequency information (FI), a dcdc buck-converter, and
a processor as a load current source. The loop controller consists of a slacktime detector, a voltage adjuster, and a PWM
modulator. The presented controller performs the following discrete-time compensation:
is the next value of the duty ratio,
are the frequency compensation, the current values
of the detected error, and the accumulated compensation, respectively, and is error scaling factor. As in (2), the control
approach does not request any previous values, while an accumulated compensation factor is needed. The variations of PVT

and load are dynamically updated in the compensation factor.

During updating, the duty ratio is controlled by a finite-state
machine (FSM) which maintains a substantially constant supply
voltage. The scaling coefficient is used to increase the error resolution and it is implemented by the shift-right function instead
of multiplication.
A. Slacktime Detector
Slacktime detection is the ability to determine the minimum
voltage required for a given operating frequency. It requires continuous monitoring of a critical path delay through the digital
circuitry with respect to PVT, load, and frequency. The proposed slacktime detector consists of a chain of delay cells and a
tap register as shown in Fig. 6. The principle of a delayline as an
ADC, is based on the relation between supply voltage and propagation delay. The slacktime detector determines the voltage
level of the delaylines supply based on the propagation delay
through the delayline. In other words, the delay, along with the
supply voltage, is converted to a digital value by sampling the



via a loop controller. The delayline is characterized at the worst

case with regard to fixed-frequency input sources. Delay of the
delayline implies its process corner, junction temperature, and
supply voltage at a given work load. From this measurement, a
desirable constant supply voltage is determined in response to
PVT and load variations. This guarantees the propagation delays just less than the critical path delay limitation and assures
proper operation.
B. Voltage Adjuster

Fig. 7. Timing diagram of delayline outputs and clocks.

There are three considerations for designing a delayline to

monitor the critical path timing over PVT variations. The first requirement is to avoid the worst case crossover effect on the nonlinear characteristics between delay and voltage. The crossover
becomes worse when the delay increases longer or the voltage
decreases. Therefore, the margin for proper circuit operation is
applied for high-crossover ratio. Determination of the resolution
of delayline is the second consideration. A fine step size results
in very slow settling while a coarse step size can cause hysteretic
oscillation. The last requirement is to minimize the hardware
burden for delayline. As semiconductor fabrication technology
improves, circuit delay is shorter and, in turn, the number of
needed cells to implement a critical path delay is larger.
From the last delayline design requirement, the cell of a delayline should have low performance. A NOR structure slowly
transits at high-to-low transition compared to a NAND circuits
transition. However, low-to-high transition time of a NOR gate
is the same as that of a NOT gate and is faster than a NAND gate.
Therefore, a pair of NOR and NOT gates is selected as the unit
delay cell. The number of delay cells between taps is determined
by increasing a step voltage so the accumulated voltage steps
require one more tap active than the prior accumulated steps
voltage at the worst case. The number of delay cells between
taps varies because the propagation delay is not a linear function of supply voltage.
The inverted input of the delay cell (NOR-INV) receives the
input clock signal or the output of prior delay cell; and the noninverted input is connected to a delayline enable signal. The
sampling clock signal lags the input clock signal by a 1/4 of
a period. The tap register samples the values of the delayline at
1/4 period intervals after the input clock pulse begins to propagate through the delayline. Fig. 7 shows the timing of the inputs DX12 DX27 at each tap, the input clock signal (ICLK),
the sample clock signal (SCLK), and delayline enable signal
The magnitude of the supply voltage is inferred by determining how far along the delayline the input clock pulse propagates in a 1/4 period. Therefore, a delayline in the negative feedback path of a closed loop reflects variations in circuit performance in response to variations of PVT, load, and frequency,
and adaptively scales the regulated voltage of a buck converter

The voltage adjuster consists of an error compensator, a frequency compensator, a process, voltage, and temperature compensator, and a control block as shown in Fig. 8. The major
role of the voltage adjuster is to compensate a supply voltage
error at a given frequency from the measurement of the slacktime detector and to provide a desirable constant voltage level
against variations of frequency as well as PVT. In addition, for
high-speed and low-overshoot/undershoot start-up, it controls
soft-start operation.
1) Error Compensator: The role of the error compensator
as in (2), and to generate a
is to detect the voltage error,
proportionally compensated value. It receives the propagation
delay word TX(27:12) from the slacktime detector and detects
the position of one and zero pair of taps as shown in Fig. 9.
The compensator converts the propagation delay position to an
error voltage by comparing it to the reference delay position
along with supply voltage under worst case conditions. In turn,
it generates a proportionally compensated propagation delay
word ECW(5:0) that represents a reference value at a default
frequency plus a compensated error value.
2) Frequency Compensator: The frequency compensator
adjusts the duty cycle of the PWM pulse based on the desired
supply voltage at a given frequency. The first subtractor, SUB1,
in Fig. 10 generates a difference between the frequency information, FI(5:0), and the internal reference voltage level,
RFI(5:0). The difference implies the desirable voltage variation
in response to a given frequency. The up/down counter (CNT)
receives the difference and counts up or down at the load signal
(LOAD) until the output of the counter is equal to the difference.
This prevents the supply level and frequency variation from
abruptly changing and reduces ringing. The second subtractor,
SUB2, receives the proportionally compensated propagation
delay word ECW(5-0) from the error compensator and the
shift-lefted counter number for the subtrahend, and generates a
frequency compensated propagation delay word FCW1(5-0).
The compensated error-step from the delayline is the same as
the resolution of the delayline (6 bits). However, the resolution
of the DAC is higher than that of the ADC, and the error step also
has a higher resolution. To increase the control resolution, the
proportionally compensated error-value should be scaled close
to the resolution of the DAC. The third subtractor, SUB3, provides a reference supply voltage word FCW2(5:0) at a given
frequency FI(5:0). The one-bit higher resolution compensated
word FCW(7:1) is generated by adding the frequency compensated word to the reference supply voltage word. However, a
7-bit DAC for a 6-bit ADC is insufficient to avoid limit-cycling
(Section II). Therefore, dither logic generates a least significant bit (LSB) of the frequency compensated word FCW(0).



Fig. 8. Block diagram of voltage adjuster against variations of frequency and PVT.

Fig. 9. One-zero edge detector and an example of encoding procedure.

The LSB is toggled (average value) unless the desired voltage is

not achieved. When the supply voltage reaches a target voltage,
the LSB is set to zero. The frequency compensated word represents the reference value plus half of the compensated error
value and an additional LSB. FCW is corresponding to
in (2).
3) Process, Voltage, and Temperature Compensator: It
consists of an internal dynamic voltage reference source, a
pulsewidth generator, and a ringing stopper as shown in Fig. 11.
The internal dynamic voltage reference source adds or subtracts
one, two, or three steps according to the increment/decrement
indicators U1, U2, U3, D1, D2, D3, and generates an internal
dynamic voltage reference, IREF(7-0). The reference value
compensates the fluctuations due to process and temperature
variations as well as the quantization error of the external supply
voltage. Fig. 12 illustrates the equivalent supply voltages which
ensure the same propagation delay at different operational
and intrinsic parameters. The pulsewidth generator, ADD1,
receives the frequency compensated word FCW(7:0) and the
as in (2)] IREF(7-0), and
accumulated compensation [

generates a normal PWM pulsewidth NPW(7-0). The ringing

stopper receives three inputs: a shift-lefted PWM pulsewidth, a
normal PWM pulsewidth, and a shift-righted PWM pulsewidth.
It outputs a pulsewidth word PW(7-0) in response to selection
signals UP, NR, and DOWN. Since the high-valued derivative
direction of supply voltage during frequency-changing or
starting-up is unchanged by the step-size compensated value
NPW(7:0), emphasized activation (double or half size of PWM
pulse) is needed.
4) Control Block of Voltage Adjuster: The control block consists of a clock generator, a tap selector, an FSM, a control signal
generator, and a false low-level detector. The clock generator
outputs a 1/4 frequency input clock signal, ICLK, and a 1/4 period lagged SCLK from an external clock input, CLK, a 1/32
frequency PWM LOAD and a delayline RSTN from the SCLK,
and a frequency doubled clock (DCLK) from the external input
clock, CLK, as shown in Fig. 13.
The tap selector chooses one of 4-taps prior-tap INCSET,
center-tap CNTTAP, next-tap DECSET, and next next-tap
DECSET2 from 16-taps TX12TX27 of a slacktime detector in



Fig. 10. Block diagram of frequency compensator.

Fig. 11. Block diagram of PVT compensator.

Fig. 12. Supply voltages corresponding to the equivalent propagation delay at

different conditions: (a) best case, (b) typical case, and (c) worst case.

response to external frequency information FI(5:0). The control

signal generator outputs increment or decrement indicators UP,
UP3, DOWN, and DOWN3 in response to the status of the tap
detector, the state CS2-CS0 from a finite-state machine, and
external frequency information.
The FSM in Fig. 14 receives monitor signals from the other
control modules and datapath block, and it outputs control
signals to the datapath block. The monitor signals consist of the
first tap TX12, the last tap TX27, the 4-taps INCSET, CNTTAP,
DECSET, and DECSET2, two frequency-change indicators
INC and DEC, and the external FI. The control signals consist
of a current state CS(2-0), a low-voltage state signal LOW,

a high-voltage state signal HIGH, and a clear signal CLR

of a PWM pulsewidth counter. The states from 000 to 011
control a soft-start routine to avoid large overshoot/undershoot
with high-speed saturation. In the states from 100 to 111, the
FSM controls the duty cycle of the DPWM according to the
current-voltage status detected by the 4-taps varying over PVT
conditions. The outputs of the FSM are used to change the
counter number of the PVT compensator at weighed steps and
to double or halve the counter number. This accelerates the
supply voltage to the appropriate value for various PVT quickly
and stably in start-up as well as normal operation.
The DACs higher resolution than ADC gives multiple DAC
values for a given ADC output. During a high-to-low voltage
transition with frequency change, the highest DAC voltage level
equal to the ADC level may be a settling point. The false lowlevel detector steps down the voltage level until a true minimum
DAC level at a given frequency is detected. As shown in Fig. 15,
the supply voltage settles at the first high DAC level in an ADC
bin by the FSM and, in turn, converges to the bottom DAC level
by the false low-level detector.
C. DPWM Pulse Modulator
The DPWM pulse modulator in Fig. 16 consists of a loadable
down counter and a pulse generator. Counter loads the PWM
pulsewidth PW(7-0) from the voltage adjuster by the LOAD,
changing a binary output of counter as a count in response to
the DCLK. DPWM pulse modulator outputs a pulse modulated
signal PWM defined by the binary input value PW(7-0) of



Fig. 13. Block diagram of clock generator and a timing diagram of clocks.

Fig. 14. State diagram of the FSM.



Fig. 15. Supply voltage lock acquisitions.

Fig. 18. Measured output voltage with tap value and supply voltage at the best
(bottom lines), and the worst (middle lines) cases at room temperature. The top
dashed line is the ideal case at the worst condition.

E. LC Filter Construction
Fig. 16. Block diagram of PWM modulator.

The all-digital self-adjusting minimum power supply system

includes a driver connected to PWM modulator drives
filter generates a dc supply voltage on AVS power
supply node in response to a pulse modulated signal PMS. Befilter is an intermittently unstable system, it is imcause the
portant to choose proper and values. First of all, from the
maximum ripple requirement [9],
product can be chosen as
in (3)

Fig. 17. Die photo and layout.

is the ripple voltage,
is the input voltage, is
is the switching frequency, and
the duty ratio of
is a product of inductance and capacitance. For example,
kHz, and
then required
The next consideration is the minimum oscillation (damped
natural) frequency in (4)

D. DPWM Driver
The single loop design eliminates most of the analog circuit
including references, ramp generators, and ADC comparators,
normally associated with analog synchronous buck converters.
A driver chip less than 1 mm on a side can easily be develbump chip
oped and placed in a low-cost SOT23-5 or a
package. A 0.5- m power CMOS process serves as an excellent
choice for the driver for supplies less than 5.5 V, which is the
case in virtually all cell phones today. Additional features such
as over and under voltage protection, thermal shutdown, and
dead time (nonoverlapping phase) generation can be included.
The driver can generate an arbitrarily large current (1 A) without
significantly impacting stability and efficiency. Also, the driver
chip can be directly driven at low voltage since level shifters
are included in the input. Furthermore, the need for trims and
voltage corrections normally associated with analog switches
are eliminated.

is the damped natural frequency, is the inductance,

is the capacitance, and is the sum of resistances (switch TR
condition is expressed in
and ESR). From (4), the minimum
The widths of the field-effect transistor (FET) drivers are
sized so that
from (1). Therefore,
. From
H and
The fully digital self-adjusting minimum-power supply
system provides a closed-loop automatic supply adjustment



Fig. 19. AVS supply voltage: (a) soft start of the worst process corner, (b) 50-mV supply voltage fluctuation (top signal) during load transition (bottom pulses)
between 65 and 350 mA (1-grid: 200 mV, 1 ms), (c) low to high full swing (0.7 to 1.1 V) of worst process corner sample, (d) high to low full swing (0.9 to 0.6 V)
of the worst process corner sample, (e) low to high 4-step swing (120 mV) of the best process corner sample, and (f) high to low 4-step swing (160 mV) of the
worst process corner sample (1-grid: 200 mV, 40 s).

mechanism to generate the optimum operating voltage for core

processors in response to variations of PVT as well as those
of frequency and load. The switching frequency of the buffer
and the
is 625 MHz. The DPWM resolution is 8 bits,
output voltage resolution is about 12.5 mV. The frequency
information from the ADC has a 6 bit resolution (50 mV at
worst case) to prevent output voltage-level overlapping due to

ripple and noise. Therefore, the output voltage of the presented

AVS converter can regulate any voltage at ADC resolutions
between 0.7 and 1.2 V. The peak ripple is 5-mV minimum.
The power dissipation from the AVS controller is 100
8-bit DAC resolution, which is a significant power reduction
from the previous digital controller in the prior art [3] that has
4.4 mW at 1.3 V. Fig. 17 shows the die photo and layout.


Fig. 18 shows measured output voltages of the sampled chips

fabricated at different process corners (best and worst). It illustrates the equivalent tap voltages needed to guarantee the same
propagation delay at different corners of a 0.13The slacktime detector is designed to provide a reference delay
with the 1.1 V reference (Ref) tap voltage at the worst process
. The tap voltage required to provide the
corner and 135
same delay at the worst corner (SSS) and the best corner (FFF)
at room temperature become 1.025 and 0.8 V, respectively, as
shown in Fig. 18. Therefore, the power consumption of the chip
fabricated at the best corner is less than the chip fabricated at
the worst corner and operating at room temperature by at least
35%. Fig. 19 demonstrates the presented AVS controllers performance on load transition, soft start, and frequency transitions.
The maximum transition time for full swing is less than 80 .
Measured data show that a digitally controlled AVS regulator is
suitable for low-power applications that require energy-efficient
A fully digital adaptively adjusting high-efficiency supply
system embedded within a digital system has been described.
The presented approach provides a constant minimum supply
voltage between 0.7 and 1.2 V with the maximum peak ripple
of 5 mV, and guarantees less propagation delay than critical
path delay over changes in PVT, load, and frequency. Therefore, the fully digital technique holds promise as a controller for
AVS regulation in digital applications that present a hostile environment for noise-sensitive analog circuits. Moreover, it contributes to the yield improvement since the propagation delay
variations due to the variations of intrinsic parameter and operating condition are compensated by dynamically adjusting the
supply voltage.


[8] L. Nielson, C. Niessen, J. Sparso, and K. van Berkel, Low-power

operation using self-timed circuits and adaptive scaling of the supply
voltage, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 2, no.
4, pp. 391397, Dec. 1994.
[9] A. Chandrakasan, V. Gutnik, and T. Xanthopoulos, Data driven
signal processing: An approach for energy efficient computing, in
Proc. IEEE ISLPED Dig. Tech. Papers, Aug. 1996, pp. 347352.
[10] K. A. Bowman, X. Tang, J. C. Eble, and J. D. Meindl, Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance, IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 11861193,
Aug. 2000.
[11] A. Consoli, F. Gennaro, C. Cavallaro, and A. Testa, A comparative
study of different buck topologies for high-efficiency low-voltage applications, in Proc. Power Elect. Spec. Conf., 1999, pp. 6065.

Dae Woon Kang (M03) received the B.S. and

M.S. degrees in electrical engineering from Yonsei
University, Seoul, South Korea, in 1991 and 1993,
respectively, and the Ph.D. degree in electrical and
computer engineering from Northeastern University,
Boston, MA in 2003. His Ph.D. dissertation was
titled Low-power digital adaptive voltage controller
design based on hybrid control and reverse phase
He was a summer intern for the National Semiconductor Corporation in 2002, when he designed a fully
digital adaptive voltage scaling (AVS) controller. He was a summer intern for
Compaq Corporation in 2001, when he was involved in developing the latest version of the Alpha processor. His role was Alphas clock-tree and delay-locked
loop (DLL) analysis and migration to a 0.125- SOI technology. He was also
a Senior Application-Specified Integrated Circuit (ASIC) Design Engineer at
Samsung Electronics from 1993 to 1998. He developed several ASIC designs.
He is currently a Senior Circuit Design Engineer at the National Semiconductor
Corporation, Longmont, CO. He has authored several papers and patents, issued
or pending. His research interests include AVSs, DLLs, and low-power digital
circuits and methodologies.

The authors greatly appreciate the help that G. Walker, at the
National Semiconductor Corporation, provided in designing the
[1] T. D. Burd and R. W. Brodersen, Design issues for dynamic voltage
scaling, in Proc. ISLPED Conf., 2000, pp. 914.
[2] K. Suzuki et al., Variable supply-voltage scheme for low-power highspeed CMOS digital design, IEEE J. Solid-State Circuits, vol. 33, no.
3, pp. 454462, Mar. 1998.
[3] G.-Y. Wei and M. Horowitz, A fully digital, energy-efficient, adaptive
power-supply regulator, IEEE J. Solid-State Circuits, vol. 34, no. 4,
pp. 520528, Apr. 1999.
[4] J. Kim and M. Horowitz, An efficient digital sliding controller for
adaptive power supply regulation, in Proc. Very Large Scale Integr.
(VLSI) Circuits Dig. Tech. Papers Conf., 2001, pp. 133136.
[5] D. W. Kang, Low-power digital adaptive voltage controller design
based on hybrid control and reverse phase mode, Ph.D. dissertation,
Dept. Elect. Comp. Eng., Northeastern Univ., Boston, MA, 2003.
[6] V. von Kaenel, P. Macken, and M. Degrauwe, A voltage reduction
technique for battery operated systems, IEEE J. Solid-State Circuits,
vol. 25, no. 5, pp. 11361140, Oct 1990.
[7] T. Kuroda et al., Variable supply-voltage scheme for low-power highspeed CMOS digital design, IEEE J. Solid-State Circuits, vol. 33, no.
3, pp. 454462, Mar. 1998.

Yong-Bin Kim (SM00) was born in Seoul, South

Korea, in 1960. He received the B.S. degree in
electrical engineering from Sogang University,
Seoul, in 1982. He received the M.S. degree from
the New Jersey Institute of Technology, Newark, and
the Ph.D. degree from Colorado State University,
Fort Collins, in 1989 and 1996, respectively, both in
computer engineering.
From 1982 to 1987, he was with the Electronics
and Telecommunications Research Institute, South
Korea, as a Member of the Technical Staff. From
1990 to 1993, he was with Intel Corporation as a Senior Design Engineer and
involved in micro-controller chip design and Intel P6 microprocessor chip
design. From 1993 to 1996, he was with the Hewlett-Packard Company, Fort
Collins, CO, as a member of the Technical Staff involved in HP PA-8000 RISC
microprocessor chip design . From 1996 to 1998, he was with Sun Microsystems, Palo Alto, CA, as an individual contributor involved in 1.5-GHz Ultra
Sparc5 CPU chip design. From 1998 to 2000, he was an Assistant Professor in
the Department of Electrical Engineering at the University of Utah, Salt Lake
City, UT. He is currently the Zraket Endowed Professor in the Department
of Electrical and Computer Engineering at Northeastern University, Boston,
MA. His research focuses on low-power analog circuit design and high-speed
low-power VLSI circuit design and methodology.



James T. Doyle (SM03) received the B.S.E.E. degree from the University of Nebraska, Lincoln, NE,
in 1972, and the M.B.A. degree from Nova Southeastern University, Fort Lauderdale, FL, in 1992.
He was a Chief Technologist for the CCG Division of the Intel Corporation, Chandler, AZ. He was
the Chief Architect of the 3G Mitsubishi Analog
Baseband Chip and also the Technical Lead on the
Solano 815 Chip Set project at Intel. He spent 13
years in Motorolas Handheld Products Division,
Fort Lauderdale, FL, and contributed to the HT, MX

Saber Radio Line. He is presently a Senior Member of the Technical Staff

(SMTS) and Chief Technologist of the Nationals Portable Power Product
Group (PPS). He is currently responsible for CMOS PA controller design at
National Semiconductor Corporation, Longmont, CO. Two national designs
are currently being used in TriQuint GSM, GPRS, and EDGE PA modules,
which are the smallest in the industry. He is a contributing author to the
ISO8803.3 Ethernet Standard. He is credited with approximately 50 patents
and has published approximately 10 technical articles, as well as, designed or
modified over 200 chips throughout his career.
Mr. Doyle is a Registered Professional Engineer in the State of Colorado.