Latest in Chip Fabrication

Shadan womens College of Engineering And Technology

Abstract: The industry is at an exciting crossroads.
All these developments are good for consumers, who
thrive on smaller, faster, cheaper chips which power
the smaller, faster portable electronic devices that
power the world we live in. The semiconductor
A triple threat of new complex technology
advancements faces semiconductor manufacturing
three-dimensional interconnect (3D Ic), extremeultraviolet lithography (eUV) and 450mm wafers. To
reap the benefits, the industry needs to resolve both
technical and business related issues.
Uma Gupta with inputs from Debasish paul
Choudhury, Semi India President, and Ivo Bolsens,
Senior Vice President and Cto, Xilinx.

industry will continue to deliver what the consumer

wants and needs
Introduction:
smaller and smaller is becoming increasingly
complex, utilising the most advanced capabilities of
physics, chemistry, electrical and mechanical
engineering among other disciplines.
Every aspect of chip manufacturing latest in Chip
fabrication technology is continually improved to
manufacture smaller devices with better performance.
Most semiconductor manufacturers and their
equipment and materials suppliers spend a significant
portion of their revenues on research and
development.
New technology advancements
A triple threat of new complex technology
advancements faces the industrythree-dimensional
interconnect (3D IC), extreme-ultraviolet lithography
(EUV) and 450mm wafers. Despite highly-evolved
industry collaboration processes such as the
International Technology Roadmap for
Semiconductors (ITRS), SEMI International
Standards and the growth of international research
consortiums, major process milestones in lithography,
wafer sizes and new transistor architectures remain
unclear and have made coordinated industry planning
more necessary than ever before.

Historically, ICs have followed Moores Law,

doubling logic capacity every two years while costing
half as much with each new generation of process
technology. Today, Moores Law is suffering from
mounting die costs, while no longer delivering
traditional performance increases or keeping pace
with the growing demand for increased bandwidth
and capacity.
The latest technologies and approaches have set out
to achieve more than Moore to enable nextgeneration silicon scaling at the current-generation
process technology. The process of making chips

The most important challenges in semiconductor

manufacturing are the move to larger (450mm)
wafers, the commercialisation of EUV, and various
ways to utilise three-dimensional (3D) device
structures and packaging technologies.
Move to 450mm wafers
Periodically, the industry adopts a larger wafer size
standard to improve the efficiency and affordability
of manufacturing. These manufacturers claim that
larger wafers are necessary to keep pace with
Moores Laws cost targets.

complex because it is intertwined with the 450mm

planning challengereinforcing the need for more
transparency in planning and funding.
Emerging architectures and technologies
Traditional planar CMOS transistors start to run into
severe electrical current leakage issues past sub20nm nodes. To overcome these issues,
manufacturers of both logic and memory devices are
looking at a variety of alternatives.
For logic devices, two alternatives have come to the
forefront: Fin-type field-effect transistors or FinFETs,
and ultra-thin-body silicon-on-insulator or UTB-SOIs
(also referred to as fully depleted or FD-SOIs). Intel
has already announced its first FinFET device. Other
device manufacturers continue to look at both the
alternatives.

450mm wafer is much larger than the current 300mm

The industry-wide cost of R&D to transition to a

larger wafer size (including the development of new
manufacturing tools) is estimated between $16 billion
and $30 billion. Some chipmakers have already
committed to advancing this transition.

Memory device manufacturers are looking at

alternatives to todays charge-based memories
including resistive RAMs, spin-torque transfer RAMs
and phase-change memories.
These new memories will increase the speed of
memory devices while at the same time lowering the
overall power requirements.

Intel has announced that its D1X fab in Oregon will

be 450mm-compatible. The fab is expected to
complete in 2013. Taiwan Semiconductor
Manufacturing Company (TSMC) plans to build a
450mm pilot line by 2013-14. Interuniversity
Microelectronics Centre, Belgium (IMEC) and
International SEMATECH Manufacturing Initiative
(ISMI) have well-established programmes focused on
the challenges posed by manufacturing with 450mm
wafers, and Albany, NY basedColleges of
Nanoscale Science and Engineering at SUNY
Polytechnic Institute is expanding facilities to
encompass 450mm R&D programme.

3D and 2.5D packaging

3D interconnects using through-silicon vias are
critical for meeting the challenging performance and
power target demands of wireless, networking,
computing and graphics devices, not to mention the
consumer demands for small portable devices.

EUV lithography rollout

EUV is a widely debated transition. Moving from
deep-ultraviolet lithography to extreme ultraviolet
lithography is a major shift. Industry players continue
to make tremendous investments to develop the nextgeneration technology that will scale devices to
smaller dimensions. The EUV lithography rollout is

2011 was a breakthrough year for 3D ICs, as

companies like IBM, Micron, Samsung, ST-Ericsson
and Xilinx grabbed headlines for deliver-ing the
industrys first 3D ICs based on through-silicon via
technology or disclosing their 3D IC R&D plans.

Advantages:1. Connectivity. 3D enables thousands

of low-latency, low-power die-to-die connections that
provide 100x bandwidth/watt of conventional printed
circuit boards (PCBs) or multi-chip modules.
2. Capacity. No longer limited by the die size and
defect density that Moores Law dictates, multiple

smaller dies can be inter-connected, and greater

capacity and higher yield achieved than with a
monolithic IC.
3. Crossovers. With 3D one can mix and match
different types of dies (processors, memories, fieldprogrammable gate arrays (FPGAs) and analogue) in

3D packaging saves space by stacking chips and

using through-silicon vias to connect the chips as
opposed to traditional wire-bonding methods. The
chips can be of the same type as in hybrid memory
cubes, or an integrated stack of heterogeneous
devices.

order to produce system-on-chips (SoCs) that were

never before possible.

challenges because of mechanical stress and

cracking.

Another similar packaging technol-ogy which is

gaining steam is 2.5D, where die slices are mounted
side-by-side on a passive silicon interposer substrate
that is used just to connect the active dies. 2.5D offers
many of the benefits of full 3D without challenges
like complex design rules, co-design of the different
stacked dies, heat dissipation and integration of
through-silicon vias with deep submicron active
devices.

Notwithstanding, both 3D and 2.5D are likely to have

a long future.

Both 3D and 2.5D packaging technologies have their

own advantages and disadvantages depending on the
application. For instance, while 3D offers significant
benefits, it also presents new design and
manufacturing challenges. The precision alignment of
through-silicon vias and solder microbumps is critical
during assembly. The differing thermal coefficients of
silicon substrates and microbumps cause reliability

Conclusion:
Semiconductor manufacturing is very expensive. In
general, for 300mm wafer sizes using leading-edge
technology, foundries cost $3-5 billion with
capacities up to 40-50k per month. For memories, the
cost is $8-11 billion with capacities up to 200-250k
per month. Equipment account for majority of the
cost. Front-end equipment are much more expensive
than back-end equipment as these add more value to
the final semiconductor product.
Refrences:
A Rogner et al 1991 J. Micromech. Microeng. 1
167. doi:10.1088/0960-1317/1/3/007

The big issue for all the semiconductor manufacturing companies is Where is the RoI? The cost for 3D
with through-silicon via will be compared to the costs of the manufacturing facilities for the next node
Fabless semiconductor companies (which design chips but dont have their own
manufacturing facilities) outsource the fabrication of the devices to a semiconductor
foundry. The foundry is a semiconductor fab that fabricates the designs of other
companies.
Increasingly, theres an industry shift towards the foundry-based model. Instead of
designing and manufacturing chips themselves, today, more companies choose to focus on
only the chip design to avoid the expensive R&D and equipment costs associated with
manufacturing. While this improves efficiencies, lowers costs and increases yields, it will also
lead to even more industry consolidation. Currently, only fifteen companies manufacture
devices at 32nm and below (this does not include R&D and pilot lines). This compares to 28
companies, which were leading edge in 2001 (manufacturing on 200mm wafers150nm
and 130nm). And it is highly unlikely that any new company will enter the market.
The big issue for all the semiconductor manufacturing companies is Where is the return on
investment (ROI)? The cost for 3D with throughsilicon via (TSV) will be compared to the
costs of the manufacturing facilities for the next node. Fab costs for the 22nm node are
expected to approach $6 billion, so few logic or memory integrated device manufacturers or
foundries will be able to afford such costs.
By mid-2013 to early 2014, a preliminary 450mm R&D production line will be established at
the Colleges of Nanoscale Science and Engineering at SUNY Polytechnic Institute at Albany,
New York. The facility will be the focus of the recently-announced Global 450 Consortium
(G450C) efforts and is expected to contain 50 different tool types. The objective of the pilot
line will be to develop data to support the purchase of production-line tools. Many believe
that once 450mm enters full production, further 300mm node development will cease for
tool suppliers due to limited resources and poor ROI.
Once 450mm is fully developed, spare capacity in 300mm will emerge, encouraging a
migration from 200mm production, impacting the viability and competitiveness of both
200mm and 300mm fabs. In 15-20 years, even low-volume, mature technologies in microelectromechanical systems (MEMS), power and analogue could migrate to 450mm fabs.
Advancements in 2.5D and 3D technologies will open up new market opportunities and
enable a new level of system-level integration never before possible on silicon platforms.
But there are still some hurdles to overcome for 3D IC design and manufacturing to become
mainstreamboth technical and business related. For example, the semiconductor industry
must come together to set standards for design enablement, manufacturing, test and chipto-chip interfaces.
The interposer-based active-on-pas-sive 2.5D stacked silicon interconnect (SSI) technology
could be a lower-risk alternative to full 3Despecially for FPGAsthat will offer power, cost
and reliability advantages for many years to come.
Heading into 2012
The industry is at an exciting crossroads. All these developments are good for consumers,
who thrive on smaller, faster, cheaper chips which power the smaller, faster portable

electronic devices that power the world we live in. The semiconductor industry will continue
to deliver what the consumer wants and needs!