Unit 1 8085 and 8086 Processor

1.

Draw and Explain the architecture of 8085?

Hardware Architecture

8085: 8 bit processor can process 8 bits in an instant.

It has 40 pins has a Dual Inline Package-(Made of epoxy material) known as DIP 40.
Pin 40 = power pin (+5 volt is given hence the 5 in the name 8085); Pin 20 = ground pin
Pins on 8085 chip can be grouped into
o Address Bus
o Data Bus
o Power supply & frequency
o Control & Status Signals
o Externally initiated signals
o Serial I/O ports

Buses in 8085:
8
Has 8 data lines hence can connect to 2 ( 256 nos ) I/O peripherals
16
6
10
Has 16 address lines hence has a memory capacity of 2 bits ( 2 x 2 = 64 KB )
In address bus, the higher byte A8 A15 are unidirectional
The lower order Address & data lines are bidirectional
The lower byte of the address line (A0 A7) and all the 8 Data lines (D0-D7) are multiplexed & hence
termed (AD0 AD7)
When ALE (Address enable latch) is enabled (during the early part of the execution), address is passed
through the lines, else data is passed (during the late part of the execution).
Hence 8085 has Von Neumann (or Princeton) architecture instruction fetch (or address fetch) and data
operation share a common bus.
ALU Arithmetic and Logical unit:

is responsible for all the arithmetic and Logical operations of the Processor
depends on the Accumulator and the temporary registers for its internal operations

Accumulator:

Special case register and Primary RAM memory in 8085

In every Arithmetic or logical operation, one of the operands is stored in Accumulator
The result of the same operation is usually stored in the accumulator

Temporary Register:

Not accessible to the user.

Used in internal operations of the processor.

General Purpose Registers:

Registers are RAM locations that can be accessed by the processor very easily.
They are
o B,C,D,E,H,L each have a capacity of 8 bits
o Can be used as 16 bit register pairs (BC , DE , HL pairs)

Stack Pointer:

Points always to the top of the stack.

The stack is used to store return address when the processor goes to perform a ISR (Interrupot Service
Routine).
Since it stores address, it is a 16 bit special case register.
Works in a LIFO last in First out Fashion.

Program Counter:

Stores the address location of the next instruction to be executed.

Since it stores address, it is a 16 bit special case register

Flags:
They indicate the current condition of the processor. They are given as follows.

Zero Flag:
ZF = 1, if ALU result = 0.
Sign Flag:
SF = 1, if MSB of ALU = 1.
Parity Flag:
PF = 1, if ALU result has even parity.
Carry Flag:
CF = 1, if carry occurs.
Auxiliary Carry Flag: ACF = 1, if carry occurs from lover to higher nibble (useful internally for BCD addition)

PSW - Processor Status Word:

The 8 bits of the accumulator + The 8 bits of the Flag are called = PSW
Hence its a 16 bit register

2.

Explain the interrupts in 8085?

Interrupts:

These are subroutines that the microprocessor responds to during its normal functioning.
Once the subroutine is responded to the microprocessor returns to the program with the help of stack
pointer and the stack.
The interrupts have priority assigned to them as given in the table.
Interrupts TRAP, RST 7.5, RST 6.5, RST 5.5 are called as Vector interrupts because their ISR are stored in
permanent locations as given in the table.
Masking can be termed as selective disabling- because the interrupts can be made active or inactive
depending on the needs and the concerns of the programmer. Interrupts RST 7.5, RST 6.5, RST 5.5 can be
masked.
TRAP is a non-maskable interrupt and has the highest priority assigned to it.
For INTR interrupt, (without the address of the service routine) is simply responded with an active low
signal INTA
There are 2 types of triggers to initiate the interrupts- thy are level triggered and edge triggered.

Hardware
Interrupts

Priority

Vector Address

Masking

Types of trigger

TRAP
RST 7.5
RST 6.5
RST 5.5

Highest

Non maskable Interrrupt

edge, level triggered

positive edge triggered

INTR

Lowest

0024 H
003C H
0034 H
002C H
Non Vector
Interrupt

3.

What is DMA? Explain the process in whole.

Mask-able
Level triggered

DMA (Direct Memory Access) Transfer:

When the processor needs to be accessed again and again when performing a repeated data copying
operation, then
o to save time & power, control of the data transfer lines is given to the input device controller
o HOLD & HLDA are used for this process
HOLD is sent from I/O device to the processor asking for control of the data lines
HLDA is sent from processor to the I/O device acknowledging the transfer of the control of the data lines.
In DMA, there are 2 modes
o Burst Mode
o Cycle stealing

Monitor Routines:
Reset in and Reset out are called as Monitor Routines.
Reset in takes the pointer of the microprocessor to 0000 where some already programmed stuff is kept.
Reset out is used to announce, the microprocessor is being reset to its connected peripherals.
Ready pin is used to connect the microprocessor with slow peripherals.
The clock out is used to communicate the frequency of the microprocessor to its peripherals.

Main Control Signals / Instructions:

IO/M, RD, WR are the three active low control signals that combine together to form the four important
active low control instructions.

Used for drawing timing diagram.

These are formed as given in the following table.

MEMR

MEMW

IOR

IOW

IO/M

RD

WR

4.

Draw and explain the architecture of 8086 processor ?

8086 Processor:

8086: First 16 bit processor can process 16 bits in an instant.

It has 40 pins has a Dual Inline Package (Made of epoxy material) - known as DIP 40.
Has 29,000 transistors
Frequency range of operation: 6 10 MHz

8086 architecture has 2 stage pipe-lining instruction execution. The central processing logic has been divided into

BIU (Bus interface Unit)

o Fetches the instructions or the data from the memory
o Interfaces with peripherals and its ports
o Writes data to memory
o Has a 6 byte instruction object code queue
Follows FIFO execution
Pre-fetching operation of BIU can be executed in parallel with EU operation, hence
speed of operation is improved.

EU (Execution Unit)
o Tells BIU where to fetch the instructions or the data from
o Decodes the instructions received from the queue
o Executes the instructions

Hence BIUs queue helps EU to function faster. When EU is executing an instruction, BIU is busy fetching
the next instruction for the queue. This is called pipe lining (or) Parallel Processing.

It Follows Von Neumann architecture, where the 16 data lines are multiplexed

Multiprocessing in 8086:
8086 has 2 modes of operation: Helps to manage single and multiprocessing environment.

Minimum Mode (MN/MX = 1)

o Caters to single processor environment
Maximum Mode (MN / MX = 0)
o Caters to multiprocessor environment

What is Offset address in 8086?

It is the 8086 is the logical address that the program "thinks about" when it addresses a location in
memory. The Execution Unit (EU) is responsible for generating the offset address. The Bus Interface Unit
(BIU), on the other hand, takes the offset address and adds it to four times the selected segment register
value in order to determine a real address, which is now 20-bits in length.

Registers in 8086
It has 14 Sixteen Bit registers

Data Registers - (General Purpose but also has some special functions)
o Has 4 - Sixteen bit data registers
AX primary accumulator
BX used as base register while calculating data memory address
CX used to hold count in multi-iteration operations & loops
DX used in I/O instructions, multiply and divide instructions
o Upper and lower bytes are stored and addressed separately
o Hence can be used as 8 bit registers AH,AL,BH,BL,CH,CL,DH,DL
o Here L indicates lower; H indicates Higher; X indicates extended register

Segment Registers
o Additional Registers Used to generate memory address from the offset address in BIU

Has 4 - Sixteen bit registers

Code Segment
Used for addressing 64 KB of the memory location in the code segment of the
memory, where code of the executable program is stored
Data Segment
Points to the data segment of the 64 KB memory where the data is stored.
Stack Segment
Addressing stack segment of the memory
Extra Segment
Is another (additional) data segment of the memory space

Pointer and Index registers

o Used for pointing and indexing. They are
Stack Pointer
Holds offset address within the stack
Base pointer
Holds offset within the data
Source Index
Used to store offset of source data in data segment

5.

Destination Index
Used to store offset of destination data in source segment
Instruction Pointer
Instruction Register
o Points to the next instruction to be executed.

used in string
manipulations

Explain the Flags in 8086?

They indicate the current condition of the processor. They are given as follows.

Zero Flag:
ZF = 1, if ALU result = 0.
Sign Flag:
SF = 1, if MSB of ALU = 1.
Parity Flag:
PF = 1, if ALU result has even parity.
Carry Flag:
CF = 1, if carry occurs.
Auxiliary Carry Flag: ACF = 1, if carry occurs from lover to higher nibble (useful internally for BCD addition)
Trap Flag:
TF = 1, step by step error decoding is done
INTR Flag:
IF = 1, mask-able interrupt of INTR is enabled.
Direction Flag:
DF = 0, String is processed from lowest address to highest. Used for String
Manipulation
Overflow Flag
OF = 1, when over flow occurs as a result of signed operation

6.

Explain 8086 as a Multiprocessor and with regard to the interrupts?

8086 as Multiprocessor-

When a processor can be connected to work in cooperation with other processors in a connected
environment then it is termed as Multiprocessing.
(MN / MX) pin enables Multiprocessing in 8086. Hence 8086 has 2 states of operation.
o Minimum Mode
Active when (MN / MX) = 1, 8086 acts as a single processor
o Maximum Mode
Active when (MN / MX) = 0, 8086 acts as a Multiprocessor

8086 Interrupts:

These are subroutines that the microprocessor responds to during its normal functioning.
Once the subroutine is responded to the microprocessor returns to the program with the help of stack
pointer and the stack.
There are 2 types of interrupt in 8086 based on where they arise from
o External Interrupts Arises from outside the processor (Eg- from the peripheral devices)
o Internal Interrupts Arises from inside the processor
Masking can be termed as selective disabling- because the interrupts can be made active or inactive
depending on the needs and the concerns of the programmer. In 8086, Interrupts are classified again into
two types based on masking. They are
o NMI
Non Maskable interrupt interrupt cannot be masked.
o INTR Interrupt
Interrupt can be masked
8086 has Nested Interrupts
o That is - Interrupts can be interrupted by a higher order interrupt.
o This is enabled by the LIFO concept of the stack.