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Circuit 1:
Step 1: Design: Current Mirror is as shown in Fig.1.
Calculated Node voltages, currents and device parameters are as below.
VDD =1.8v, (VGS VT) = VON = 0.2v, ID1 = 24A, VDS1 = VGS1 = VGS2 = 0.7v,
( nCox ) = 300
A/v2.
( WL )=2
1.8V DS 1.80.7
=
44 K
24
24
R = 44K.
Step 2: Simulation setup:
Mentor graphics design architect is used for schematic simulation and 180nm technology
is used. Schematic setup of current mirror circuit 1 is as shown in fig1.
Click here to see log file of the simulation.
Step 3: Results:
Node voltages and the currents of the simulated current mirror circuit 1 is given below with the
expected values as per the design calculation.
Voltage/Current
Simulated
Calculated/
Expected
Voltage/Current
Simulated
Calculated/
Expected
VGS1
VDS1
ID1
0.725V
0.725V
24A
0.7V
0.7V
24A
VGS2
VDS2
ID2
0.725V
0.739V
24A
0.7V
0.7V
24A
Page | 2
Circuit 2: Here the resistive load in the fig1 is replaced by active PMOS load.
Step 1: Design: Current Mirror is as shown in Fig.2.
Calculated Node voltages, currents and device parameters are as below.
VDD =1.8v, (VGS VT) = VON = 0.2v, ID1 = 24A, VDS1 = VGS1 = VGS2 = 0.7v, VSGP = 1.1v,
( nCox ) = 300 A/v2.
( WL )
( WL ) =1.22
p
Page | 3
Step 3: Results:
Node voltages and the currents of the simulated current mirror circuit 2 is given below with the
expected values as per the design calculation.
Voltage/Current
Simulated
Calculated/
Expected
Voltage/Current
Simulated
Calculated/
Expected
VGS1
VDS1
ID1
0.725V
0.725V
24A
0.7V
0.7V
24A
VGS2
VDS2
ID2
0.725V
0.714V
23.9A
0.7V
0.7V
24A
VSGP
VSDP
IDP
1.08V
1.08V
23.9A
1.1V
1.1V
24A
Page | 4
Circuit 3:
Step 1: Design: Current Mirror is as shown in Fig.3.
Calculated Node voltages, currents and device parameters are as below.
VDD =1.8v, (VGS VT) = VON = 0.2v, ID1 = 24A, VDS1= VDS2 = VGS1 = VGS2 = 0.7v, VG4 = VG3 =
C
2*(VT + VON) = 2*(0.5+0.2) = 1.4V, VD3 = (VT + 2VON) = (0.5+0.4) = 0.9V, ( n ox ) = 300
A/v2.
( WL )
=4
1,2,3,4
1.8V D 3 1.80.9
=
=37.5 K
24
24
R = 37.5K.
Step 2: Simulation setup:
Mentor graphics design architect is used for schematic simulation and 180nm technology
is used. Schematic setup of current mirror circuit 3 is as shown in fig 3.
Click here to, see log file of the simulation.
Step 3: Results:
Node voltages and the currents of the simulated current mirror circuit 3 is given below with the
expected values as per the design calculation.
Voltage/Current
Simulated
Calculated/
Expected
Voltage/Current
Simulated
Calculated/
Expected
VGS1
VDS1
ID1
0.68V
0.68V
24A
0.7V
0.7V
24A
VGS2
VDS2
ID2
0.68V
0.75V
23.9A
0.7V
0.7V
24A
VG3
VD3
ID3
1.36V
1.3V
23.9A
1.4V
0.9V
24A
VG4
VD4
ID4
1.36V
1.36V
24A
1.4V
1.4V
24A
Page | 5
Step 4: Observation:
1. If
( WL )
2,3
Page | 6
Circuit 4: In this circuit, MOS2 is diode connected instead of MOS1 in the earlier circuit.
Step 1: Design: Current Mirror is as shown in Fig.4.
Calculated Node voltages, currents and device parameters are as below.
VDD =1.8v, (VGS VT) = VON = 0.2v, ID1 = 24A, VDS1= VDS2 = VGS1 = VGS2 = 0.7v, VG4 = VG3 =
C
2*(VT + VON) = 2*(0.5+0.2) = 1.4V, VD3 = (VT + 2VON) = (0.5+0.4) = 0.9V, ( n ox ) = 300
A/v2.
( WL )
1,2,3,4
=4 => W
1,2,3,4 = 0.72m and L1,2,3,4 = 0.18m.
1.8V D 3 1.80.9
=
=37.5 K
24
24
R = 37.5K.
Step 2: Simulation setup:
Mentor graphics design architect is used for schematic simulation and 180nm technology
is used. Schematic setup of current mirror circuit 4 is as shown in fig 4.
Click here to see log file of the simulation.
Step 3: Results:
Node voltages and the currents of the simulated current mirror circuit 4 is given below with the
expected values as per the design calculation.
Voltage/Current
Simulated
Calculated/
Expected
Voltage/Current
Simulated
Calculated/
Expected
VGS1
VDS1
ID1
0.67V
0.69V
24A
0.7V
0.7V
24A
VGS2
VDS2
ID2
0.67V
0.67V
23.8A
0.7V
0.7V
24A
VG3
VD3
ID3
1.5V
0.905V
23.8A
1.4V
0.9V
24A
VG4
VD4
ID4
1.5V
1.5V
24A
1.4V
1.4V
24A
Page | 7
( WL )
2,3
Page | 8
Circuit 5:
Step 1: Design: Current Mirror is as shown in Fig.5.
Calculated Node voltages, currents and device parameters are as below.
VDD =1.8v, (VGS VT) = VON = 0.2v, ID2 = ID5 = 48A, VDS1= VDS2 = VON = 0.2v, VGS1 = VGS2 = VD4
= (VT + VON) = 0.7v, VG5 = VG4 = VG3 = (VT + 2VON) = (0.5+0.4) = 0.9V, VD3 = 2VON = 0.4V,
( nCox ) = 300 A/v2.
( WL )
=8
1,2,3,4
( WL ) = 41 ( WL )
5
=2
1,2,3,4
1.8V D 3 1.80.4
=
=29.16 K
48
48
R = 29.16K.
With the designed value of (W,L)3,4, M1 and M2 goes to linear region. In order to make those
transistor to operate in saturation, (W, L)3,4 is changed to (2.88 m, 0.18 m).
Page | 9
Simulated
Calculated/
Expected
Voltage/Current
Simulated
Calculated/
Expected
VGS1
VDS1
ID1
0.714V
0.166V
47.37A
0.7V
0.2V
48A
VGS2
VDS2
ID2
0.714V
0.174V
48A
0.7V
0.2V
48A
VG3
VD3
ID3
0.851V
0.418V
47.37A
0.9V
0.4V
48A
VG4
VDS4
ID4
0.851V
0.54V
48A
0.9V
0.5V
48A
VGS5
VDS5
0.851V
0.851V
0.9V
0.9V
ID5
48A
48A
P a g e | 10