1.

Design a circuit for bcd to excess-3 code conversion

Ans:
module converter(output [3:0]ex,input [3:0]bcd);
assign ex[0]=~bcd[0];
assign ex[1]=~(bcd[1]^bcd[0]);
assign ex[2]=bcd[2]^(bcd[1]|bcd[0]);
assign ex[3]=bcd[3]|bcd[2]&(bcd[1]|bcd[0]);
endmodule
module test;
wire [3:0]ex;
reg [3:0]bcd;
reg [3:0]i;
converter a(ex,bcd);
initial
begin
$monitor("%d bcd=%b excess3=%b",$time,bcd,ex);
for(i=0;i<10;i=i+1)
#5 bcd=i;
end
endmodule
2. Design a 4-bit binary ripple counter.
Ans:
module flip_flop(output reg q,input clk,clr);
always@(clr)
begin
if(clr==1)
assign q=0;
else
deassign q;
end
always@(negedge clk)
q=~q;
endmodule
module ripple(output [3:0]q,input clk,clr);
flip_flop f1(q[0],clk,clr);
flip_flop f2(q[1],q[0],clr);
flip_flop f3(q[2],q[1],clr);
flip_flop f4(q[3],q[2],clr);
endmodule
module test;
reg clk=0,clr;
wire [3:0]q;
ripple r(q,clk,clr);
initial
begin
$monitor("%d q=%b",$time,q);
clr=1;
#10 clr=0;
#150 $finish;
end
initial
forever
#5 clk=~clk;
endmodule

3. Design a sequential circuit which will output z=1 for the input sequence that
ends in either 010 or 1001, otherwise z=0.
Ans:
module seq_detector(output reg z,input a,clk);
reg [0:3]seq=0;
always@(posedge clk)
#1 begin
seq=seq>>1;
seq[0]=a;
if(seq==4'b1001||seq[0:2]==3'b010)
z=1;
else
z=0;
$display("out= %b",z);
end
endmodule
module test;
wire z;
reg a,clk=0;
integer i=0;
seq_detector obj(z,a,clk);
initial
begin
$monitor("%d inp=%b",i,a);
@(posedge clk) a=0;
@(posedge clk) a=1;i=i+1;
@(posedge clk) a=1;i=i+1;
@(posedge clk) a=0;i=i+1;
@(posedge clk) a=0;i=i+1;
@(posedge clk) a=1;i=i+1;
@(posedge clk) a=0;i=i+1;
@(posedge clk) a=1;i=i+1;
@(posedge clk) a=1;i=i+1;
@(posedge clk) $finish;
end
always
#5 clk=~clk;
endmodule
4. Define a function to multiply two 4-bit numbers a and b. The output is an 8-b
it value. Invoke the function by using stimulus and check results.
Ans:
module multiply(output reg [7:0]z,input [3:0]a,b);
always@(*)
z=mult(a,b);
function [7:0]mult;
input [3:0]a,b;
mult=a*b;
endfunction
endmodule
module test;
wire [7:0]z;
reg [3:0]a,b;
multiply obj(z,a,b);
initial
begin
$monitor("%d z=%b a=%b b=%b",$time,z,a,b);
#0 a=4'b1010;b=4'b1011;

#10 a=4'b1011;b=4'b1010;
end
endmodule
5. Design a divide-by-14 ripple up counter.
Ans:
module flip_flop(output reg q,input clk,clr);
always@(clr)
begin
if(clr==1)
assign q=0;
else
deassign q;
end
always@(negedge clk)
q=~q;
endmodule
module ripple(output [3:0]q,input clk,clr);
reg clr1;
always
#1 clr1=clr;
always@(q)
if(q==14)
assign clr1=1;
else
deassign clr1;
flip_flop f1(q[0],clk,clr1);
flip_flop f2(q[1],q[0],clr1);
flip_flop f3(q[2],q[1],clr1);
flip_flop f4(q[3],q[2],clr1);
endmodule
module test;
reg clk=1,clr;
wire [3:0]q;
ripple r(q,clk,clr);
initial
begin
$monitor("%d q=%b",$time,q);
clr=1;
#10 clr=0;
#150 $finish;
end
initial
forever
#5 clk=~clk;
endmodule
6. Implement the following boolean function f(a,b,c,d,e)= (0,1,4,5,16,17,21,25,29
) using multiplexer.
Ans:
module mux(output f,input a,b,c,d,e);
assign f=a?(b?(c?(~d&e):(~d&e)):(c?(~d&e):(~d))):(b?(c?(0):(0)):(c?(~d):(~d))
);
endmodule
module test;
wire f;
reg a,b,c,d,e;

reg [5:0]i;
mux obj(f,a,b,c,d,e);
initial
begin
$monitor("%d %b%b%b%b%b f=%b",$time,a,b,c,d,e,f);
for(i=0;i<32;i=i+1)
#1{a,b,c,d,e}=i;
end
endmodule
7. Design a circuit for 8421 to 84-2-1 code conversion.
Ans:
module converter(output reg [3:0]z,input [3:0]a);
always@(a)
begin
z[0]=a[0];
z[1]=a[1]^a[0];
z[2]=a[2]^(a[1]|a[0]);
z[3]=a[3]|a[2]&(a[1]|a[0]);
end
endmodule
module test;
reg [3:0]a,i;
wire [3:0]z;
converter obj(z,a);
initial
begin
$display("time
8421
84-2-1");
$monitor("%d %b %b",$time,a,z);
for(i=0;i<13;i=i+1)
#1 a=i;
end
endmodule
8. Design a 4*16 decoder using two 3*8 decoder.
Ans:
module dec3_8(output [7:0]d,input enable,input [2:0]inp);
assign d[7]=~inp[2]&~inp[1]&~inp[0]&enable;
assign d[6]=~inp[2]&~inp[1]&inp[0]&enable;
assign d[5]=~inp[2]&inp[1]&~inp[0]&enable;
assign d[4]=~inp[2]&inp[1]&inp[0]&enable;
assign d[3]=inp[2]&~inp[1]&~inp[0]&enable;
assign d[2]=inp[2]&~inp[1]&inp[0]&enable;
assign d[1]=inp[2]&inp[1]&~inp[0]&enable;
assign d[0]=inp[2]&inp[1]&inp[0]&enable;
endmodule
module dec4_8(output [15:0]d,input [3:0]inp,input enable);
dec3_8 obj1(d[15:8],~inp[3],inp[2:0]);
dec3_8 obj2(d[7:0],inp[3],inp[2:0]);
always@(enable)
begin
if(~enable)
force d=0;
else
release d;
end
endmodule

module test;
wire [15:0]d;
reg enable;
reg [3:0]inp;
reg [4:0]i;
dec4_8 obj(d,inp,enable);
initial
begin
$monitor("%d inp=%b %b",$time,inp,d);
#2for(i=0;i<16;i=i+1)
#1 inp=i[3:0];
end
initial
begin
enable=0;
#1enable=1;
end
endmodule
9. Design a 4-bit synchronous binary counter.
Ans:
module flip_flop(output reg q,input clk,clr,t);
always@(posedge clk)
begin
if(t)
q=~q;
end
always@(clr)
begin
if(clr)
assign q=0;
else
deassign q;
end
endmodule
module counter(output [3:0]q,input clk,clr);
flip_flop f1(q[0],clk,clr,1);
flip_flop f2(q[1],clk,clr,q[0]);
flip_flop f3(q[2],clk,clr,q[0]&q[1]);
flip_flop f4(q[3],clk,clr,q[0]&q[1]&q[2]);
endmodule
module test;
reg clk=0,clr;
wire [3:0]q;
counter obj(q,clk,clr);
initial
forever
#5clk=~clk;
initial
begin
$monitor("%d %b",$time,q);
#0clr=1;
#4clr=0;
#180 $finish;
end
endmodule
10. Design a combinational circuit that has 4 inputs (a, b, c, d), which represe

nt a bcd digit. The circuit has two groups of 4- outputs s,t,u,v and w,x,y,z. Ea
ch group represents a decimal number which is five times the input number. For e
xample, if abcd=0111 the outputs are 0011 0101. Assume that the invalid bcd dig
its do not occur as inputs.
Ans:
module comb(output reg s,t,u,v,w,x,y,z,input a,b,c,d);
integer i=0;
integer j=0;
always@(*)
begin
i={a,b,c,d};
j=i*5;
i=j%10;
j=j/10;
{s,t,u,v}=j[3:0];
{w,x,y,z}=i[3:0];
end
endmodule
module test;
wire s,t,u,v,w,x,y,z;
reg a,b,c,d;
integer i;
comb obj(s,t,u,v,w,x,y,z,a,b,c,d);
initial
begin
$monitor("%d inp=%b%b%b%b op=%b%b%b%b %b%b%b%b",$time,a,b,c,d,s,t,u,v,w,
x,y,z);
for(i=0;i<10;i=i+1)
#1 {a,b,c,d}=i[3:0];
end
endmodule
11.

Design the decoder circuit using switch level modeling.

Ans:
module decoder(output [0:3]d,input [1:0]s);
wire in_s0,in_s1,p0,p1,p2,p3;
supply1 pwr;
supply0 grnd;
pmos p1(in_s0,pwr,s[0]);
nmos n1(in_s0,grnd,s[0]);
pmos p2(in_s1,pwr,s[1]);
nmos n2(in_s1,grnd,s[1]);
nmos n3(d[0],grnd,s[0]);
nmos n4(d[0],grnd,s[1]);
pmos p3(p0,pwr,s[0]);
pmos p4(d[0],p0,s[1]);
nmos n5(d[1],grnd,in_s0);
nmos n6(d[1],grnd,s[1]);
pmos p5(p1,pwr,in_s0);
pmos p6(d[1],p1,s[1]);
nmos n7(d[2],grnd,s[0]);
nmos n8(d[2],grnd,in_s1);
pmos p7(p2,pwr,s[0]);
pmos p8(d[2],p2,in_s1);
nmos n9(d[3],grnd,in_s0);
nmos n10(d[3],grnd,in_s1);

pmos p9(p3,pwr,in_s0);
pmos p10(d[3],p3,in_s1);
endmodule
module test;
wire [0:3]d;
reg [1:0]inp;
integer i;
decoder obj(d,inp);
initial
begin
$monitor("%d inp=%b %b",$time,inp,d);
for(i=0;i<4;i=i+1)
#1inp=i;
end
endmodule
12. Design a circuit for gray to binary code conversion.
module converter(output reg [3:0]binary,input [3:0]gray);
always@(*)
begin
binary[3]=gray[3];
binary[2]=gray[3]^gray[2];
binary[1]=gray[3]^gray[2]^gray[1];
binary[0]=gray[3]^gray[2]^gray[1]^gray[0];
end
endmodule
module test;
wire [3:0]binary;
reg [3:0]gray;
integer i;
converter obj(binary,gray);
initial
begin
$monitor("%d %b
%b ",$time,gray,binary);
for(i=0;i<16;i=i+1)
#1 gray=i;
end
endmodule
13. Design a 5-32 line decoder using four 3-8 line decoders with enable and one
2-4 line
decoder.
Ans:
module decoder2_4(output reg [0:3]d,input [1:0]inp);
always@(*)
case(inp)
2'b00: d=4'b1000;
2'b01: d=4'b0100;
2'b10: d=4'b0010;
2'b11: d=4'b0001;
endcase
endmodule
module decoder3_8(output [0:7]d,input [2:0]inp,input enable);
assign d[0]=~inp[2]&~inp[1]&~inp[0]&enable;
assign d[1]=~inp[2]&~inp[1]&inp[0]&enable;
assign d[2]=~inp[2]&inp[1]&~inp[0]&enable;

assign d[3]=~inp[2]&inp[1]&inp[0]&enable;
assign d[4]=inp[2]&~inp[1]&~inp[0]&enable;
assign d[5]=inp[2]&~inp[1]&inp[0]&enable;
assign d[6]=inp[2]&inp[1]&~inp[0]&enable;
assign d[7]=inp[2]&inp[1]&inp[0]&enable;
endmodule
module decoder5_32(output [0:31]d,input [4:0]inp);
wire [0:3]enable;
decoder2_4 obj(enable,inp[4:3]);
decoder3_8 obj1(d[0:7],inp[2:0],enable[0]);
decoder3_8 obj2(d[8:15],inp[2:0],enable[1]);
decoder3_8 obj3(d[16:23],inp[2:0],enable[2]);
decoder3_8 obj4(d[24:31],inp[2:0],enable[3]);
endmodule
module test;
wire [0:31]d;
reg [4:0]inp;
integer i;
decoder5_32 obj5(d,inp);
initial
begin
$monitor("%d %b %b",$time,inp,d);
for(i=0;i<32;i=i+1)
#1 inp=i;
end
endmodule
14. Design a 4-bit bcd ripple counter.
Ans:
module flip_flop(output reg q,input clk,clr);
always@(clr)
begin
if(clr==1)
assign q=0;
else
deassign q;
end
always@(negedge clk)
q=~q;
endmodule
module ripple(output [3:0]q,input clk,clr);
reg clr1;
always
#1 clr1=clr;
always@(q)
if(q==10)
assign clr1=1;
else
deassign clr1;
flip_flop f1(q[0],clk,clr1);
flip_flop f2(q[1],q[0],clr1);
flip_flop f3(q[2],q[1],clr1);
flip_flop f4(q[3],q[2],clr1);
endmodule
module test;
reg clk=1,clr;
wire [3:0]q;
ripple r(q,clk,clr);

initial
begin
$monitor("%d q=%b",$time,q);
clr=1;
#10 clr=0;
#150 $finish;
end
initial
forever
#5 clk=~clk;
endmodule
15. Design a sequential circuit which gives the output as 1 when the number of 1s
is odd and it has received at least 2 consecutive 0s.
Ans:
module seq_detector(output reg z,input a,clk);
reg [2:0]state=0;
always@(posedge clk)
#0 begin
case({state,a})
4 b0000: {state,z}=4 b1000;
4 b0001: {state,z}=4 b0010;
4 b0010: {state,z}=4 b1010;
4 b0011: {state,z}=4 b0000;
4 b1000: {state,z}=4 b0100;
4 b1001: {state,z}=4 b0010;
4 b1010: {state,z}=4 b0111;
4 b1011: {state,z}=4 b0000;
4 b0100: {state,z}=4 b0100;
4 b0101: {state,z}=4 b0111;
4 b0110: {state,z}=4 b0111;
4 b0111: {state,z}=4 b0100;
default: {state,z}=4 b1000;
endcase
end
endmodule
module test;
reg a,clk=0;
wire z;
integer t;
seq_detector obj(z,a,clk);
always@(posedge clk)
t=$time;
initial
begin
$monitor("%d a=%b z=%b",t,a,z);
@(posedge clk) a=1;
@(posedge clk) a=0;
@(posedge clk) a=1;
@(posedge clk) a=1;
@(posedge clk) a=0;
@(posedge clk) a=0;
@(posedge clk) a=0;
@(posedge clk) a=1;
@(posedge clk) a=0;
@(posedge clk) a=0;
@(posedge clk) a=1;
@(posedge clk) a=1;

@(posedge clk) $finish;

end
always
#5 clk=~clk;
endmodule
16.Design a divide by 6 ripple down counter.
Ans:
module flip_flop(output reg q,input clk,clr);
always@(clr)
begin
if(clr==1)
assign q=0;
else
deassign q;
end
always@(negedge clk)
q=~q;
endmodule
module ripple(output [3:0]q,input clk,clr);
reg clr1=1,clr2=1;
flip_flop f1(q[0],clk,clr);
flip_flop f2(q[1],~q[0],clr2);
flip_flop f3(q[2],~q[1],clr);
flip_flop f4(q[3],~q[2],clr1);
always
begin
#1 clr1=clr;
clr2=clr;
end
always@(q)
begin
if(q==15)
begin
assign clr1=1;
assign clr2=1;
end
else
begin
deassign clr1;
deassign clr2;
end
end
endmodule
module test;
reg clk=1,clr;
wire [3:0]q;
ripple r(q,clk,clr);
initial
begin
$monitor("%d q=%b",$time,q);
clr=1;
#10 clr=0;
#200 $finish;
end
initial
forever
#5 clk=~clk;

endmodule
17. A majority logic function is a boolean function that is equal to 1 if the m
ajority of the variables are 1. The function is 0 otherwise. Write an hdl user-d
efined primitive for a 3-bit majority function.
Ans:
primitive my_majority(f,a,b,c);
output f;
input a,b,c;
table
// a b c f
1 1 ? : 1;
1 ? 1 : 1;
? 1 1 : 1;
0 0 ? : 0;
0 ? 0 : 0;
? 0 0 : 0;
endtable
endprimitive
module test;
wire f;
reg a,b,c;
integer i;
my_majority obj(f,a,b,c);
initial
begin
$monitor("%d %b%b%b
f=%b",$time,a,b,c,f);
for(i=0;i<8;i=i+1)
#1 {a,b,c}=i;
end
endmodule
18. Design a code converter that converts a decimal digit from the 8,4,-2,-1 cod
e to bcd.
Ans:
module converter(output [3:0]bcd,input [3:0]inp);
assign bcd[0]=inp[0];
assign bcd[1]=inp[0]^inp[1];
assign bcd[2]=inp[2]^(inp[0]|inp[1]);
assign bcd[3]=inp[3]&inp[2]|inp[3]&~inp[1]&~inp[0];
endmodule
module test;
wire [3:0]bcd;
reg [3:0]inp;
converter obj(bcd,inp);
initial
begin
$monitor("%d
84-2-1=%b
bcd=%b",$time,inp,bcd);
inp=4 b0000;
#1 inp=4 b0111;
#1 inp=4 b0110;
#1 inp=4 b0101;
#1 inp=4 b0100;
#1 inp=4 b1011;
#1 inp=4 b1010;
#1 inp=4 b1001;
#1 inp=4 b1000;

#1 inp=4 b1111;
end
endmodule
19. Write an hdl behavioral description of a 4-bit comparator with a 6-bit outpu
t. Bit 5 is for equal, bit 4 for unequal, bit 3 for greater than, bit 2 for less
than, bit 1 for greater than or equal, bit 0 for less than or equal.
Ans:
module comparator(output reg [5:0]result,input [3:0]a,b);
reg [3:0]x;
always@(*)
begin
x=a~^b;
result[5]=&x;
result[4]=~result[5];
result[3]=a[3]&~b[3]|x[3]&a[2]&~b[2]|x[3]&x[2]&a[1]&~b[1]|x[3]&x[2]&x[1]&a[
0]&~b[0];
result[2]=~a[3]&b[3]|x[3]&~a[2]&b[2]|x[3]&x[2]&~a[1]&b[1]|x[3]&x[2]&x[1]&~a
[0]&b[0];
result[1]=result[5]|result[3];
result[0]=result[5]|result[2];
end
endmodule
module test;
wire [5:0] result;
reg [3:0]a,b;
comparator obj(result,a,b);
initial
begin
$monitor("%d a=%b b=%b result=%b",$time,a,b,result);
#0 a=4 b1010;b=4 b1011;
#1 a=4 b1110;b=4 b1011;
#1 a=4 b0010;b=4 b0010;
#1 a=4 b1111;b=4 b0000;
#1 a=4 b0001;b=4 b1011;
end
endmodule
20.Design a johnson counter.
Ans:
module d_flipflop(output reg q,input d,clk,clr);
always@(posedge clk)
q=d;
always@(clr)
begin
if(clr)
assign q=0;
else
deassign q;
end
endmodule
module johnson(output [3:0]out,input clk,clr);
d_flipflop obj1(out[3],~out[0],clk,clr);
d_flipflop obj2(out[2],out[3],clk,clr);
d_flipflop obj3(out[1],out[2],clk,clr);
d_flipflop obj4(out[0],out[1],clk,clr);

endmodule
module test;
wire [3:0]out;
reg clk=1,clr=1;
johnson obj(out,clk,clr);
initial
forever
#5clk=~clk;
initial
begin
$monitor("%d %b",$time,out);
#10 clr=0;
#150 $finish;
end
endmodule
21.Design a sequence detector that detects any input sequence ending in 101 and
produces an output z=1. Overlapping is permitted.
Ans:
module seq_detector(output reg z,input a,clk);
reg [0:2]seq=0;
always@(posedge clk)
#1 begin
seq=seq>>1;
seq[0]=a;
if(seq==3 b101)
z=1;
else
z=0;
$display("out= %b",z);
end
endmodule
module test;
wire z;
reg a,clk=0;
integer i=0;
seq_detector obj(z,a,clk);
initial
begin
$monitor("%d inp=%b",i,a);
@(posedge clk) a=0;
@(posedge clk) a=1;i=i+1;
@(posedge clk) a=1;i=i+1;
@(posedge clk) a=0;i=i+1;
@(posedge clk) a=0;i=i+1;
@(posedge clk) a=1;i=i+1;
@(posedge clk) a=0;i=i+1;
@(posedge clk) a=1;i=i+1;
@(posedge clk) a=1;i=i+1;
@(posedge clk) $finish;
end
always
#5 clk=~clk;
endmodule
22.Design a circuit for bcd to seven segment decoder
Ans:

module segment(output a,b,c,d,e,f,g,input [3:0]inp);

assign a=inp[0]~^inp[2]|inp[1]|inp[3];
assign b=inp[0]~^inp[1]|~inp[2];
assign c=inp[0]|~inp[1]|inp[2];
assign d=~inp[0]&~inp[2]|inp[1]&~inp[2]|inp[3]|~inp[0]&inp[1]|inp[0]&~inp[1]&
inp[2];
assign e=~inp[0]&(~inp[2]|inp[1]);
assign f=~inp[0]&(inp[2]|~inp[1])|inp[3]|~inp[1]&inp[2];
assign g=~inp[0]&inp[2]|~inp[1]&inp[2]|inp[3]|inp[1]&~inp[2];
endmodule
module test;
wire a,b,c,d,e,f,g;
reg [3:0]inp;
integer i;
segment obj(a,b,c,d,e,f,g,inp);
initial
begin
$monitor("bcd=%b segment=%b%b%b%b%b%b%b",inp,a,b,c,d,e,f,g);
for(i=0;i<10;i=i+1)
#1 inp=i;
end
endmodule
23.Design a 4 input priority encoder using udp
Ans:
primitive valid(v,a0,a1,a2,a3);
output v;
input a0,a1,a2,a3;
table
0 0 0 0 : 0;
b b b b : 1;
endtable
endprimitive
primitive my_msb(msb,a0,a1,a2,a3);
output msb;
input a0,a1,a2,a3;
table
0 0 0 0 : x;
1 0 0 0 : 0;
b 1 0 0 : 0;
b b 1 0 : 1;
b b b 1 : 1;
endtable
endprimitive
primitive my_lsb(lsb,a0,a1,a2,a3);
output lsb;
input a0,a1,a2,a3;
table
0 0 0 0 : x;
1 0 0 0 : 0;
b 1 0 0 : 1;
b b 1 0 : 0;
b b b 1 : 1;
endtable
endprimitive
module prio_enc(output msb,lsb,v,input [0:3]inp);
valid obj(v,inp[0],inp[1],inp[2],inp[3]);
my_msb obj1(msb,inp[0],inp[1],inp[2],inp[3]);

my_lsb obj2(lsb,inp[0],inp[1],inp[2],inp[3]);
endmodule
module test;
wire msb,lsb,v;
reg [0:3]inp;
integer i;
prio_enc obj(msb,lsb,v,inp);
initial
begin
$monitor("inp=%b valid=%b encoded=%b%b",inp,v,msb,lsb);
for(i=0;i<16;i=i+1)
#1 inp=i;
end
endmodule
24.Implement a serial adder circuit.
Ans:
module fa(output s,c,input a,b,cin);
assign s=a^b^cin;
assign c=a&b|(a^b)&cin;
endmodule
module dff(output reg q,input d,clk,set,reset);
always@(posedge clk)
q=d;
always@(reset,set)
begin
if(reset)
assign q=0;
else if(set)
assign q=1;
else
deassign q;
end
endmodule
module serialadd(output [3:0]sum,output reg cout,input [3:0]a,b);
wire s,q,c;
wire [3:0]r1,r2;
reg clk=0,clr=1;
fa fa1(s,c,r1[0],r2[0],q);
dff obj0(sum[0],sum[1],clk,0,clr);
dff obj1(sum[1],sum[2],clk,0,clr);
dff obj2(sum[2],sum[3],clk,0,clr);
dff obj3(sum[3],s,clk,0,clr);
dff obj5(r1[0],r1[1],clk,a[0]&clr,~a[0]&clr);
dff obj6(r1[1],r1[2],clk,a[1]&clr,~a[1]&clr);
dff obj7(r1[2],r1[3],clk,a[2]&clr,~a[2]&clr);
dff obj8(r1[3],0,clk,a[3]&clr,~a[3]&clr);
dff obj9(r2[0],r2[1],clk,b[0]&clr,~b[0]&clr);
dff obj10(r2[1],r2[2],clk,b[1]&clr,~b[1]&clr);
dff obj11(r2[2],r2[3],clk,b[2]&clr,~b[2]&clr);
dff obj12(r2[3],0,clk,b[3]&clr,~b[3]&clr);
dff obj13(q,c,clk,0,clr);
initial
begin
#3 clr=0;
#35 cout=q;
#1 $finish;
end

always
#5clk=~clk;
endmodule
module test;
reg [3:0]a,b;
wire cout;
wire [3:0]sum;
serialadd obj(sum,cout,a,b);
initial
begin
$monitor("%d c=%b sum=%b",$time,cout,sum);
a=4 b 1011; b=4 b 1010;
end
endmodule
25.Design a 8-bit ring counter.
Ans:
module dff(output reg q,input d,clk,set,reset);
always@(posedge clk)
q=d;
always@(set)
begin
if(set)
assign q=1;
else
deassign q;
end
always@(reset)
begin
if(reset)
assign q=0;
else
deassign q;
end
endmodule
module ringcounter(output [0:7]q,input clk,set);
dff obj0(q[0],q[7],clk,set,0);
dff obj1(q[1],q[0],clk,0,set);
dff obj2(q[2],q[1],clk,0,set);
dff obj3(q[3],q[2],clk,0,set);
dff obj4(q[4],q[3],clk,0,set);
dff obj5(q[5],q[4],clk,0,set);
dff obj6(q[6],q[5],clk,0,set);
dff obj7(q[7],q[6],clk,0,set);
endmodule
module test;
reg clk=0,set=1;
wire [0:7]q;
ringcounter obj(q,clk,set);
initial
begin
$monitor("%d %b",$time,q);
#2set=0;
#100 $finish;
end
always
#5 clk=~clk;
endmodule

26.Design a counter with the following repeated binary sequence: 0,1,2,3,4,5,6.

Use jk flipflops.
Ans:
module jk_ff(output reg q,input j,k,clk,reset);
always@(reset)
begin
if(reset)
assign q=0;
else
deassign q;
end
always@(negedge clk)
q=j&~q|~k&q;
endmodule
module counter(output [2:0]q,input clk,clr);
reg clr1;
jk_ff obj0(q[0],1,1,clk,clr1);
jk_ff obj1(q[1],q[0],q[0],clk,clr1);
jk_ff obj2(q[2],q[0]&q[1],q[0]&q[1],clk,clr1);
always@(clr,q)
clr1=clr|q[0]&q[1]&q[2];
endmodule
module test;
wire [2:0]q;
reg clk=1,clr=1;
counter obj(q,clk,clr);
always
#5 clk=~clk;
initial
begin
$monitor("%d %b",$time,q);
#1 clr=0;
#100 $finish;
end
endmodule
27.Design a circuit to convert alphanumeric character to its corresponding ascii
code.
Ans: module test;
reg [7:0]a;
initial
begin
$monitor("%c %d",a,a);
#1 a="0";
#1 a="a";
#1 a="z";
end
endmodule
28.Define a task to compute the factorial of a 4-bit number. The output is a 32bit value. The result is assigned to the output after a delay of 10 time units.
Also design a circuit for fibonacci series generation.
Ans:
FACT:
module test;
reg [31:0]out;
reg [3:0]in;

task factorial;
output [31:0]out;
input [3:0]in;
integer i,j;
begin
j=1;
for(i=2;i<=in;i=i+1)
j=j*i;
#10 out=j;
end
endtask
initial
begin
$monitor("%d in=%b out=%b",$time,in,out);
#2 in=4 b0101;
factorial(out,in);
#2 in=4 b1010;
factorial(out,in);
#2 in=4 b0011;
factorial(out,in);
end
endmodule
FIBO:
module fibonnaci(output reg [31:0]out,output reg [31:0]count,input [31:0]n);
integer prev=0;
integer i=1;
integer a;
initial
begin
#0 out=1;
count=i;
for(i=2;i<=n;i=i+1)
begin
#1 count =i;
a=out;
out=out+prev;
prev=a;
end
end
endmodule
module test;
wire [31:0]out;
reg [31:0]n;
wire [31:0]count;
fibonnaci obj(out,count,n);
initial
begin
$monitor("count=%d %d",count,out);
n=32 d10;
end
endmodule
29.Write the truth table for the boolean function y=(a&b)|(c^d). Define a udp th
at implements this boolean function. Assume that the inputs will never take the
value x.
Ans:
primitive mine(f,a,b,c,d);

output f;
input a,b,c,d;
table
1 1 ? ? : 1;
? ? 0 1 : 1;
? ? 1 0 : 1;
0 0 0 0 : 0;
0 0 1 1 : 0;
0 1 0 0 : 0;
0 1 1 1 : 0;
1 0 0 0 : 0;
1 0 1 1 : 0;
endtable
endprimitive
module test;
wire f;
reg a,b,c,d;
integer i;
mine obj(f,a,b,c,d);
initial
begin
$monitor("a=%b b=%b c=%b d=%b f=%b",a,b,c,d,f);
for(i=0;i<16;i=i+1)
#1 {a,b,c,d}=i[3:0];
end
endmodule
30.Design a 4-bit bcd adder
Ans:
module fa(output s,c,input a,b,cin);
assign s=a^b^cin;
assign c=a&b|(a^b)&cin;
endmodule
module bcd_adder(output [3:0]sum,output cout,input [3:0]a,b,input cin);
wire [3:0]bi_sum;
wire [3:0]c;
wire [3:0]add;
wire x,y,z,u;
wire cond;
fa fa0(bi_sum[0],c[0],a[0],b[0],cin);
fa fa1(bi_sum[1],c[1],a[1],b[1],c[0]);
fa fa2(bi_sum[2],c[2],a[2],b[2],c[1]);
fa fa3(bi_sum[3],c[3],a[3],b[3],c[2]);
assign cond=c[3]|bi_sum[3]&bi_sum[2]|bi_sum[3]&~bi_sum[2]&bi_sum[1];
assign add[0]=0;
assign add[3]=0;
assign add[1]=cond;
assign add[2]=cond;
assign cout=cond;
fa fa4(sum[0],x,add[0],bi_sum[0],0);
fa fa5(sum[1],y,add[1],bi_sum[1],x);
fa fa6(sum[2],z,add[2],bi_sum[2],y);
fa fa7(sum[3],u,add[3],bi_sum[3],z);
endmodule
module test;
reg [3:0]a,b;
wire cout;

wire [3:0]sum;
bcd_adder obj(sum,cout,a,b,1);
initial
begin
$monitor("a=%b b=%b bcdsum=000%b%b",a,b,cout,sum);
#1 a=4 b1000;b=4 b0001;
#1 a=4 b1001;b=4 b1001;
end
endmodule
31.Design a 4-bit combinational circuit for 2s complement.
Ans:
module twoscomp(output reg [3:0]out,input [3:0]in);
always@(*)
begin
out[0]=in[0];
out[1]=in[0]^in[1];
out[2]=in[2]^(in[1]|in[0]);
out[3]=~in[3]|~in[2]&~in[1]&~in[0];
end
endmodule
module test;
wire [3:0]out;
reg [3:0]in;
integer i;
twoscomp obj(out,in);
initial
begin
$monitor("inp=%b 2 scomp=%b",in,out);
for(i=1;i<16;i=i+1)
#1 in=i[3:0];
end
endmodule
32. Design a combinational circuit that generates the 9s complement of a bcd digi
t
Ans:
module ninesscomp(output reg [3:0]out,input [3:0]in);
always@(*)
begin
out[0]=~in[0];
out[1]=in[1];
out[2]=in[2]^in[1];
out[3]=~in[3]&~in[2]&~in[1];
end
endmodule
module test;
wire [3:0]out;
reg [3:0]in;
integer i;
ninesscomp obj(out,in);
initial
begin
$monitor("inp=%b 9 scomp=%b",in,out);
for(i=0;i<10;i=i+1)
#1 in=i[3:0];

end
endmodule
33. Design a sequence detector to detect 3 or more consecutive 1s.
Ans:
module dff(output reg q,input d,clk,clr);
always@(posedge clk)
q=d;
always@(clr)
begin
if(clr)
assign q=0;
else
deassign q;
end
endmodule
module seq_detector(output reg z,input a,clk);
wire [1:0]q;
reg clr;
assign d_0=q[0]&q[1]|a&~q[0];
assign d_1=q[0]&q[1]|a&(q[0]|q[1]);
dff d0(q[0],d_0,clk,clr);
dff d1(q[1],d_1,clk,clr);
always@(posedge clk)
begin
$display("%b",q);
z=a&q[1]|q[1]&q[0];
end
initial
begin
clr=1;
#2 clr=0;
end
endmodule
module test;
reg a,clk=0;
reg [15:0]sequence=16 b0001_0110_1111_1000;
wire z;
always
#5clk=~clk;
seq_detector obj(z,a,clk);
always@(posedge clk)
begin
a=sequence[15];
sequence=sequence<<1;
#1 $display("a=%b z=%b",a,z);
end
initial
#250 $finish;
endmodule
34. Design a 4-bit up down synchronous counter
Ans:
module flip_flop(output reg q,input clk,clr,t);
always@(posedge clk)
begin
if(t)

q=~q;
end
always@(clr)
begin
if(clr)
assign q=0;
else
deassign q;
end
endmodule
module counter(output [3:0]q,input clk,clr,control);
flip_flop f1(q[0],clk,clr,1);
flip_flop f2(q[1],clk,clr,q[0]&control|~q[0]&~control);
flip_flop f3(q[2],clk,clr,q[0]&q[1]&control|~q[0]&~q[1]&~control);
flip_flop f4(q[3],clk,clr,q[0]&q[1]&q[2]&control|~q[0]&~q[1]&~q[2]&~control)
;
endmodule
module test;
reg clk=0,clr,control;
wire [3:0]q;
counter obj(q,clk,clr,control);
initial
forever
#5clk=~clk;
initial
begin
$monitor("%d %b",$time,q);
#0clr=1;control=1;
#4clr=0;
#180 clr=1;control=0;
#1 clr=0;
#180 $finish;
end
endmodule
35. Write a module to convert a positive integer to roman numeral
Ans:
module roman;
integer l0,l1;
integer in,i;
reg [8*8:1]temp,out;
always@(in)
begin
l0=in%10;
l1=in/10;
case(l0)
0: temp[4*8:1]="
";
1: temp[4*8:1]="I ";
2: temp[4*8:1]="II ";
3: temp[4*8:1]="III ";
4: temp[4*8:1]="IV ";
5: temp[4*8:1]="V ";
6: temp[4*8:1]="VI ";
7: temp[4*8:1]="VII ";
8: temp[4*8:1]="VIII";
9: temp[4*8:1]="IX ";
default: temp[3*8:1]="
endcase

";

case(l1)
0: temp[8*8:4*8+1]="
";
1: temp[8*8:4*8+1]=" X";
2: temp[8*8:4*8+1]=" XX";
3: temp[8*8:4*8+1]=" XXX";
4: temp[8*8:4*8+1]=" XL";
5: temp[8*8:4*8+1]=" L";
6: temp[8*8:4*8+1]=" LX";
7: temp[8*8:4*8+1]=" LXX";
8: temp[8*8:4*8+1]="LXXX";
9: temp[8*8:4*8+1]=" XC";
default: temp[8*8:4*8+1]="
endcase
out=temp;
end
initial
begin
$monitor("%d %s",in,out);
for(i=1;i<100;i=i+1)
#1 in=i;
end
endmodule

";

36. Design a jk counter that goes through the states

4.

7,4,8,3,9,2,10,1,11,0,7,

Ans:
module jk_ff(output reg q,input j,k,clk,reset);
always@(reset)
begin
if(reset)
assign q=0;
else
deassign q;
end
always@(negedge clk)
q=j&~q|~k&q;
endmodule
module counter(output [3:0]q,input clk,clr);
jk_ff obj0(q[0],~q[2]&(q[3]|~q[1]),q[3]|q[2],clk,clr);
jk_ff obj1(q[1],~q[2],q[3]|q[0],clk,clr);
jk_ff obj2(q[2],~q[0]&~q[3]&~q[1],~q[0],clk,clr);
jk_ff obj3(q[3],q[2]^(q[0]|q[1]),1,clk,clr);
endmodule
module test;
wire [3:0]q;
reg clk=0,clr=1;
counter obj(q,clk,clr);
always
#5 clk=~clk;
initial
begin
$monitor("%d %b",$time,q);
#1 clr=0;
#150 $finish;
end
endmodule
37.Design an excess-3-to-binary decoder using the unused combinations of the cod

e as dont care conditions.

Ans:
module ex3_bi(output [3:0]bi,input [3:0]ex3);
assign bi[0]=~ex3[0];
assign bi[1]=ex3[0]^ex3[1];
assign bi[2]=ex3[2]^(~ex3[1]|~ex3[0]);
assign bi[3]=ex3[3]&(ex3[2]|ex3[1]&ex3[0]);
endmodule
module test;
wire [3:0]bi;
reg [3:0]ex3;
integer i;
ex3_bi obj(bi,ex3);
initial
begin
$monitor("ex3=%b
binary=%b",ex3,bi);
for(i=3;i<16;i=i+1)
#1 ex3=i[3:0];
end
endmodule
38. Design a sequential circuit with two j k flip-flops a and b and two inputs e
and x. If e = 0, the circuit remains in the same state regardless of the value
of x. When e = 1 and x = 1, the circuit goes through the state transitions from
00 to 01 to 10 to 11 back to 00, and repeats. When e = 1 and x = 0, the circ
uit goes through the state transitions from 00 to 11 to 10 to 01 and back to 00
, and repeats.
39. It is necessary to design an asynchronous sequential circuits with two input
s, x1 and x2, and one output, z. Initially, both inputs and output are equal to
0. When x1 or x2 becomes 1, z becomes 1. When the second input also becomes 1,
the output changes to 0. The output stays at 0 until the circuit goes back to th
e initial state.
40. Design a 5 bit synchronous binary counter using t flip flop.
Ans:
module flip_flop(output reg q,input clk,clr,t);
always@(posedge clk)
begin
if(t)
q=~q;
end
always@(clr)
begin
if(clr)
assign q=0;
else
deassign q;
end
endmodule
module counter(output [4:0]q,input clk,clr);
flip_flop f0(q[0],clk,clr,1);
flip_flop f1(q[1],clk,clr,q[0]);
flip_flop f2(q[2],clk,clr,q[0]&q[1]);
flip_flop f3(q[3],clk,clr,q[0]&q[1]&q[2]);
flip_flop f4(q[4],clk,clr,q[0]&q[1]&q[2]&q[3]);

endmodule
module test;
wire [4:0]q;
reg clr=1,clk=0;
always
#5 clk=~clk;
counter obj(q,clk,clr);
initial
begin
$monitor("%d %b",$time,q);
#2 clr=0;
#250 $finish;
end
endmodule
41. Given a memory size 64 words, with 8 bits per word, write verilog code to sw
ap the contents of memory in reverse order, that is, transfer word at 0 to word
at 63, word 1 to word 62 and so on.
Ans:
module test;
reg [7:0]mem[63:0];
integer j;
task swap;
reg [7:0]temp;
integer i;
begin
for(i=0;i<32;i=i+1)
begin
temp=mem[i];
mem[i]=mem[63-i];
mem[63-i]=temp;
end
end
endtask
initial
begin
for(j=0;j<64;j=j+1)
mem[j]=j[7:0];
for(j=0;j<64;j=j+1)
#1 $display("%d",mem[j]);
#2 swap();
for(j=0;j<64;j=j+1)
$display("%d",mem[j]);
end
endmodule
42. Design a circuit that will give output 1 anytime a letter within the string d
igital system design, appears at the input in ascii code.
Ans:
module detector(output reg z,input [7:0]a);
reg [21*8:1]gstring="digital system design";
integer i,flag;
reg [7:0]temp;
always@(a)
begin
flag=0;

for(i=0;i<21;i=i+1)
begin
temp={gstring[i*8+8],gstring[i*8+7],gstring[i*8+6],gstring[i*8+5],gst
ring[i*8+4],gstring[i*8+3],gstring[i*8+2],gstring[i*8+1]};
if(a==temp)
flag=1;
end
if(flag)
z=1;
else
z=0;
end
endmodule
module test;
reg [7:0]a;
wire z;
detector obj(z,a);
initial
begin
$monitor("a=%d a=%c z=%b",a,a,z);
#1 a=97;
#1 a=99;
#1 a=101;
#1 a=110;
end
endmodule
43. Design a gray code converter to drive a seven segment indicator. The four in
puts to the converter circuit (a, b, c, d) represent a decimal digit coded using
the gray code. Assume that only i/p combinations representing the digits 0 to 9
can occur as inputs, so that the unused combinations are don t care terms.
Ans:
module indicator(lig,a,b,c,d);
input a,b,c,d;
output reg [6:0]lig;
initial
begin
lig= d0;
end
always@(a,b,c,d)
begin
case({a,b,c,d})
4 b0000:lig=7 b1111110;
4 b0001:lig=7 b0110000;
4 b0011:lig=7 b1101101;
4 b0010:lig=7 b1111001;
4 b0110:lig=7 b0110011;
4 b0111:lig=7 b1011011;
4 b0101:lig=7 b1011111;
4 b0100:lig=7 b1110000;
4 b1100:lig=7 b1111111;
4 b1101:lig=7 b1111011;
default:lig=7 b0;
endcase
end
endmodule
module st;

reg a,b,c,d;
wire [6:0] out;
reg q;
integer j;
indicator i(out,a,b,c,d);
initial
$monitor($time," %b %b %b %b %b",a,b,c,d,out);
initial
begin
for(j=0;j<15;j=j+1)
#5{a,b,c,d}=j;
#180 $finish;
end
endmodule
44. Design a task to compute even parity of a 16-bit number. The result is a 1-b
it value that is assigned to the output after three positive edges of clock. (us
e a repeat statement).
Ans:
module even_parity(output reg p,input [15:0]in,input clk);
integer temp=0,i=0;
always@(in)
begin
repeat(16)
begin
temp=temp^in[i];
i=i+1;
end
@(posedge clk)begin
@(posedge clk)begin
@(posedge clk)begin
p=temp;
end
end
end
end
endmodule
module test;
reg clk=0;
reg [15:0]in;
wire p;
even_parity obj(p,in,clk);
always
#5clk=~clk;
initial
begin
$monitor("%d in=%b p=%b",$time,in,p);
#0 in=16 b0100_1010_1110_0000;
#100 $finish;
end
endmodule
45. Design a 8-bit jerky ring counter.
Ans:
8 bit ring counter itself

46. Design a jk counter that must go through states 0,3,6,0...if a control line
is high and 0,2,4,6,0...if the control line is low.
Ans: done
47. Describe a generic n-bit counter with asynchronous negative level reset. Ins
tantiate this generic counter as a 5-bit counter. Verify this 5 bit counter usin
g a test bench.
Ans:
module flip_flop(output reg q,input clk,clr);
always@(clr)
begin
if(clr==1)
assign q=0;
else
deassign q;
end
always@(negedge clk)
q=~q;
endmodule
module gen_counter(input [3:0]n,input clk,clr);
parameter p=n-1;
reg [p:0]q;
reg [p:0]nw_clk;
reg [p:0]nw_clr;
integer i;
always@(q)
begin
nw_clk[0]=clk;
for(i=1;i<n;i=i+1)
nw_clk[i]=~q[i-1];
end
always@(clr)
for(i=0;i<n;i=i+1)
nw_clr[i]=clr;
flip_flop a[p:0](q,nw_clk);
initial
$monitor("%d %b",$time,q);
endmodule
module test;
reg clk=1,clr=1;
reg [3:0]n=5;
gen_counter obj(n,clk,clr);
initial
begin
#1 clr=0;
#200 $finish;
end
always
#5 clk=~clk;
endmodule
48. Write a program to find the size of the largest gap between two successive 1
s in a 16 bit word.
Ans:

module largest(output reg [3:0]z,input [0:15]in);

integer max;
integer i,j,k,l;
always@(in)
begin
max=0;
for(i=0;i<16;i=k)
begin
if(in[i]==1)
begin
for(j=i+1;in[j]!=1;j=j+1)
l=in[j];
if((j-i-1)>max)
max=j-i-1;
k=j;
end
else
k=i+1;
end
z=max[3:0];
end
endmodule
module test;
wire [3:0]z;
reg [0:15]in;
largest obj(z,in);
initial
begin
$monitor("in=%b z=%b",in,z);
#1 in=16 b1001_1000_1101_1111;
end
endmodule
49. Design a circuit that can shift a 4 bit vector w=w3w2w1w0 one bit position
to the right when a control signal shift is equal to 1. Let the outputs of the c
ircuit be a 4 bit vector y=y3y2y1y0 and a signal k, such that if shift = 1 then
y3=0, y2=w3, y1=w2, y0=w1 and k=w0. If shift=0, then y=w and k=0.
Ans: done
50. Draw A sequential circuit with two d flip flops and one input x_in. A) when
x_in is 0, the state of the circuit remains the same. When x_in is 1, the circui
t goes through the state transitions 00 to 01, to 11, to 10, back to 00 and repe
ats. B) when x_in is 0, the state of the circuit remains the same. When x_in is
1, the circuit goes through the state transitions from 00 to 11, to 01, to 10, b
ack to 00 and repeats.
Ans: done
WALLACE:
module ha(output sum,carry,input a,b);
assign sum=a^b;
assign carry=a&b;
endmodule
module fa(output sum,carry,input a,b,c);
assign sum=a^b^c;
assign carry=a&b|(a^b)&c;

endmodule
module propadd(output [4:0]sum,output cout,input [4:0]a,b);
wire [4:0]c;
fa fa0(sum[0],c[0],a[0],b[0],0);
fa fa1(sum[1],c[1],a[1],b[1],c[0]);
fa fa2(sum[2],c[2],a[2],b[2],c[1]);
fa fa3(sum[3],c[3],a[3],b[3],c[2]);
fa fa4(sum[4],c[4],a[4],b[4],c[3]);
buf(cout,c[4]);
endmodule
module wallace(output [9:0]mult,input [4:0]a,b);
wire [4:0]p0,p1,p2,p3,p4,s0,c0,s1,c1,s2,c2;
assign p0=a&{5{b[0]}};
assign p1=a&{5{b[1]}};
assign p2=a&{5{b[2]}};
assign p3=a&{5{b[3]}};
assign p4=a&{5{b[4]}};
ha ha1(s0[0],c0[0],p0[1],p1[0]);
fa fa1(s0[1],c0[1],p0[2],p1[1],p2[0]);
fa fa2(s0[2],c0[2],p0[3],p1[2],p2[1]);
fa fa3(s0[3],c0[3],p0[4],p1[3],p2[2]);
ha ha2(s0[4],c0[4],p1[4],p2[3]);
ha ha3(s1[0],c1[0],s0[1],c0[0]);
fa fa4(s1[1],c1[1],s0[2],c0[1],p3[0]);
fa fa5(s1[2],c1[2],s0[3],c0[2],p3[1]);
fa fa6(s1[3],c1[3],s0[4],c0[3],p3[2]);
fa fa7(s1[4],c1[4],p2[4],c0[4],p3[3]);
ha ha4(s2[0],c2[0],s1[1],c1[0]);
fa fa8(s2[1],c2[1],s1[2],c1[1],p4[0]);
fa fa9(s2[2],c2[2],s1[3],c1[2],p4[1]);
fa fa10(s2[3],c2[3],s1[4],c1[3],p4[2]);
fa fa11(s2[4],c2[4],p3[4],c1[4],p4[3]);
propadd obj(mult[8:4],mult[9],c2,{p4[4],s2[4:1]});
buf(mult[0],p0[0]);
buf(mult[1],s0[0]);
buf(mult[2],s1[0]);
buf(mult[3],s2[0]);
endmodule
module test;
wire [9:0]out;
reg [4:0]a,b;
wallace obj(out,a,b);
initial
begin
$monitor("a=%b b=%b mult=%b",a,b,out);
a=5 b10001;b=5 b00101;
end
endmodule