Examples of FPLD Families:

Actel ACT,
Xilinx LCA,
Altera MAX 5000 & 7000

Actel ACT Family

The Actel ACT family employs multiplexer-based logic cells.
A row-based architecture is used in which the logic cells are arranged in rows with
horizontal routing channels between adjacent rows of logic cells.

Interconnect

Logic cell

ACT 1 Logic Modules

ACT 1 FPGAs use a single type of logic module.
Logic Module
Actel ACT

M1

A0
A1

0
1
S

0
1
S

B1
SB

SA

F1

'1'

F2

B0
B1

F2

D
'1'

SB

S3

S0
S1

A1

M3

M2

B0

Logic Module

A0

F1

0
1
S

SA

(a)

Logic Module

S0

F1
0
1

0
1

F2

S3

S1

O1

0
1

'0'
B

O1

F = (A B) + (B' C) + D
(b)

(c)

(d)

(a) An Actel FPGA. (b) An ACT 1 logic module. (c) An implementation of an ACT 1 logic module using
pass transistors. (d) An example of function implementation by an ACT 1 logic module.

ACT 2 and ACT 3 Logic Modules

Both ACT 2 and ACT 3 FPGAs use two types of logic module.
C-Module
D00
D01
D10
D11

S-Module (ACT 2)

A1
B1
A0
B0

D00
D01
D10
D11

OUT

S1

A1
B1

S0

A0
CLR

S-Module (ACT 3)
D00
D01
D10
D11

SE
Y

A1
B1

S1
S0

S0

(b)

(c)

SE (sequential element)
1
D
C2
C1
CLR

S1

A0
B0
CLR
CLK

CLK
(a)

SE
Y

SE
1

S
master
latch
combinational
logic for clock
and clear

S
slave
latch

CLK

C2
C1

CLR

CLR

flip-flop macro
D
CLK

(d)

1D

C1
(e)

(a) The C-module used by both ACT 2 and ACT 3 FPGAs. (b) The ACT 2 S-module. (c) The ACT 3
S-module. (d) Equivalent circuit of the SE. (e) The sequential element configured as a positive-edgetriggered D flip-flops.
4

Routing Architecture of ACT Family

A row-based architecture.
Each horizontal channel consists of a number of routing tracks.
Some routing tracks are segmented where adjacent segments can be connected
through antifuses to form longer lines.

There are also some vertical tracks running through the logic modules and horizontal channels.

FILENAME.APP=6822FG13.PS

I/O module

Antifuses

Vertical segments

Segmented
routing
channels

Rows of
logic
modules

Routing architecture of an Actel ACT FPGA.

6

Xilinx LCA Family

The Xilinx LCA family employs LUT-based logic cells.
A symmetrical array architecture is used.

Interconnect
Logic cell

Configurable Logic Block of LCA Family

We consider the XC4000 devices for an example.
The XC4000 FPGAs use a single type of configurable logic block (CLB).
Each CLB contains two 4-input LUTs that feed a 3-input LUT. This allows a CLB to
implement any two logic functions with four or less variables, or some function with
five or more variables.

A CLB can also be configured to be used as memory e.g. as two 161 memory
SRAMs.

The outputs of the function generators can be optionally stored in flip-flops inside a
CLB.

6-37

Figure 6-32 Simplified Diagram of a Xilinx Configurable Logic Block

(Adapted with permission of Xilinx, Inc.)

H1
G1

Look up Table
for G'

G2

G'

DIN

S/R

EC

MUX

G3
G4

16 bits of SRAM

S/R
Control

DIN

PRE

F'

Look up Table
for H'

H' S

EC
CLR

M M
H'

MUX

8 bits of SRAM

MUX

YQ

G'

1
M

G'

H'
S

F1

Look up Table
for F'

F2

F'

MUX

F3
F4

S/R
Control

DIN

16 bits of SRAM

PRE

F'

XQ

G'

H' S

EC
CLR

M M

MUX

M
K (CLOCK)

MUX

1
M

F'

H'
S
M

- SRAM cell

Routing Architecture of LCA Family

A typical Xilinx LCA FPGA consists of a two-dimensional array of CLBs with horizontal routing channels between rows of blocks and vertical routing channels between columns.

Routing tracks are segmented which can be interconnected inside the switch matrices.

Each interconnect point inside a switch matrix is formed by 6 pass transistors to

allow connections between adjacent segments and/or between the vertical and
horizontal lines that meet there.

10

T-153

Xilinx XC4000 FPGA Structure (Adapted with Permission of

Xilinx, Inc.)

Long lines

Single length

- Input/Output Block (IOB)

- Configurable logic block (CLB)

- Switch matrix

11

M
M

d
e

(a)

(b)

(a) A switch matrix. (b) Example of connections made through a switch matrix.
12

Altera MAX 5000 & 7000 Family

The Altera MAX family employs PAL-based logic cells.
The logic cells are called macrocells.
A hierarchical PLD architecture is used where the macrocells are grouped into
larger blocks called logic array blocks.

PLD block

Chipwide interconnect

13

Logic Array Block of MAX Family

Each logic array block (LAB) contains 16 macrocells.
A simplified macrocell showing its basic PLD-like combinational logic structure:

...

See Fig. 3.5 of text for the complete structure of a macrocell.

In addition to the basic combinational logic structure shown above
each macrocell has a flip-flop
there are special connections that allow sharing of product terms between different macrocells in the same LAB.
14

Routing Architecture of MAX 5000 & 7000 Family

The LABs are interconnected by a chipwide interconnect called programmable interconnect array (PIA).

The PIA acts as a global bus and is built such that the connections between different
pairs of LABs all have the same delay.

15

T-150

Altera MAX 7000 Structure (Reprinted with Permission of

Altera Corporation, Altera Corp., 1991)

I/O control block

Logic
array
block

Logic
array
block

Logic
array
block

Logic
array
block

Programmable interconnect array

I/O
control
block

Logic
array
block

Logic
array
block

Logic
array
block

Logic
array
block

Logic
array
block

Logic
array
block

Logic
array
block

Logic
array
block

Logic
array
block

Logic
array
block

Logic
array
block

Logic
array
block

I/O
control
block

I/O control block

16

Comparison of FPLD Families

Programming
technology
Architecture
Logic cell type
Interconnect
Interconnect
delay
Basic
logic cells
Logic cell
contents

Actel ACT 3
antifuse

Xilinx XC4000
SRAM

Altera MAX 7000

EPROM

row-based
multiplexer-based
segmented channels

symmetrical array
LUT-based
segmented channels with
switch matrices
variable

hierarchical-PLD
PAL-based
programmable interconnection
architecture
fixed

Configurable
Logic Block (CLB)
3 LUTs,
2 D flip-flops,
10 MUXes.

16 macrocells
in a LAB
Macrocell:
5 ANDs, 1 OR, 1 EXOR,
1 flip-flop, 3 MUXes.

Two or one.
Any two 4-input functions,
or one selected function
of
9 inputs.
64 CLBs (XC4002XL)
to
3136 CLBs (XC4085XL)

Multiple wide input

functions per LAB

variable

Combinational
functions
per logic cell

C-module and
S-module
C-module: 4:1 MUX,
2-input OR, 2-input AND.
S-module: 4:1 MUX, 2-input OR,
2-input AND, latch/D flip-flop.
One.
Most 3-and 4-input
functions.

Basic
logic cells
per chip

104 S+96 C (A1415)

to
697 S+680 C (A14100)

32 macrocells (EPM7032)
to
256 macrocells (EPM70256E)

17