VISVESVARAYA TECHNOLOGICAL UNIVERSITY

Jnana Sangama, Belgaum - 580 014

A
Project Report
on
Differential Amplifier with Buffer Configuration
Submitted in Partial Fulfillment for the award of the Degree

Master of Technology
in

VLSI Design and Testing

Submitted By

Mr.Abhishek C Math
(USN:2BV13LDT02)
Under the guidance of

Dr.Rajshekar.B.Shettar

B. V. BHOOMARADDI COLLEGE OF
ENGINEERING AND TECHNOLOGY HUBLI-31
2013-2014
B.V.BHOOMARADDI COLLEGE OF

ENGINEERING AND TECHNOLOGY HUBLI-31

CERTIFICATE
This is to certify that the Project report entitled Differential Amplifier with Buffer Configuration is a bonafide work carried out by
Mr. Abhishek C Mathi bearing (USN: 2BV13LDT02) as a part
of VISVESVARAYA TECHNOLOGICAL UNIVERSITYS M.Tech in VLSI
Design and Testing at B. V. Bhoomaraddi College of Engineering and Technology, Vidyanagar, Hubli for the academic year 2013-2014.

Dr.Rajshekar.B.Shettar
Guide

Dr.Uma Mudenagudi
Head of the Department

Dr.Ashok Shettar
Principal

External Viva
Name of Examiners

Signature with date

1) ..................
2)..................

ABSTRACT

In this paper we present a design of a cmos amplifier with the buffer

configuration which operates at 1.8V power supply. Here we are making to
design the op amp as a buffer which drives a 2pf capacitive load. The proposed design produces an open loop gain of 50dB and Unity Gain Bandwidth
of 10MHz in UMC 0.18micron technology. The op amp designed is a single
stage differential amplifier. The differential amplifier plays an excellent performance as input amplifier and application with the possibility of feedback
to the input. The differential amplifier circuit is characterised in terms of
self bias capability, common mode rejection, voltage gain and the unity gain
bandwidth product.

ACKNOWLEDGMENTS

The sense of contentment and elation that accompanies the successful

completion of our project and its report would be incomplete without mentioning the names of the people who helped us in accomplishing this.
We take this opportunity to thank our principal Dr. Ashok Shettar, for
providing healthy environment in the college, which helped in concentrating
on the task. We express a deep sense of gratitude to our H. O. D. Dr. Uma
Mudenagudi for providing the inspiration required for taking the project to
its completion.
We sincerely thank to our guide Dr.Rajshekar.B.Shettar for their inspiring guidance and promising support they gave during the course of completion.
We sincerely thank to our project coordinator Dr.Saroja Sidmal,for
great support and encouragement
Last but not the least we like to thank all the staff members, teaching
and non - teaching staff for helping us during the course of the project.

Mr.Abhishek C Math

Contents
1 Introduction
1.1 Buffer Amplifier . . . . .
1.2 Why is this circuit useful?
1.3 Problem Statement . . . .
1.4 Objective of the Project .
1.5 Methodology . . . . . . .
1.6 Organization of the report

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2 Literature Survey
2.1 Simple Differential Amplifier . . . . . . . . . . . . . . . . . . .
2.2 Telescopic cascode op amps . . . . . . . . . . . . . . . . . . .

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3 Design of Differential Amplifier

3.1 differential Amplifier . . . . . . . . . . . . .
3.2 Large signal analysis of differential amplifier
3.3 Small Signal Model . . . . . . . . . . . . . .
3.4 Frequency Response of Fifferential Amplifier
4 Simulation and Results
4.1 EVALUATION OF DEVICE . . .
4.2 PVT Analysis . . . . . . . . . . . .
4.3 Schematic of Differential Amplifier
4.4 Summary . . . . . . . . . . . . . .

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5 Conclusion
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5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

iii

List of Figures
1.1

Buffer Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1
2.2
2.3

Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . .
Telescopic cascode op amps . . . . . . . . . . . . . . . . . . .
cascode op amp with input and output shorted . . . . . . . .

6
7
7

3.1
3.2
3.3
3.4
3.5

Single-ended output differential amplifier in dc state . . . . . .

Variations of differential amplifier drain currents versus input .
Variations of differential amplifier drain currents versus input .
5 pack differential amplifier . . . . . . . . . . . . . . . . . . .
Differential amplifier with two main capacitances impacting
on frequency response . . . . . . . . . . . . . . . . . . . . . .
High-frequency small-signal equivalent circuit for differential
amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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3.6
4.1
4.2
4.3

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schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
AC response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Amplifier in the Buffer Configuration . . . . . . . . . . . . . . 21

iv

List of Tables
3.1

Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1
4.2
4.3
4.4
4.5
4.6
4.7

Evaluation of NMOS Device

Evaluation of PMOS Device
Device Sizes . . . . . . . . .
PVT Analysis for 1.8V . . .
PVT Analysis for 1.62V . .
PVT Analysis for 1.92V . .
Summary . . . . . . . . . .

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Chapter 1
Introduction
CMOS Op amp is one of the most versatile and important building blocks
in analog circuit design. Based upon the value of their output resistance they
are being classified into two categories
1. UNBUFFERED OPERATIONAL AMPLIFIER: These are Operational Transconductance Amplifiers (OTA), which have high output resistance.
2. BUFFERED OPERATIONAL AMLIFIER: These are Voltage Operational Amplifiers, which have low output resistance. Operational amplifiers
are amplifiers (controlled sources) that have sufficiently high forward gain
so that when negative feedback is applied, the Closed-loop transfer function
is practically independent of the gain of the opamp. The primary requirement of an op-amp is to have an open loop gain that is sufficiently large to
implement negative feed back concept.

1.1

Buffer Amplifier

A buffer amplifier, or simply a buffer, is an electronic amplifier that

is designed to have an amplifier gain of 1. Buffers are used in Impedance
matching, the benefit of which is to maximize energy transfer between circuits
or systems. The below fig1 shows the diagram of a voltage buffer. There are
two main kinds of buffer circuits, Voltage buffers and Current buffers. The
purposes of each is to isolate the mentioned characteristic to avoid loading the
input circuit or source from the output stage. Another name by which buffer
amplifiers are known as is a voltage follower. The name is given because of
1

Differential Amplifier with Buffer configuration

Figure 1.1: Buffer Amplifier

the characteristic of the amplifier to output a signal of the same amplitude
as the input (given the unity gain [gain of 1 or 0dB] ). If the difference
betweenV+ and V is negligibly small so thatV+ = V we must have:
Vout = Vin

(1.1)

A buffer amplifier is used to isolate the oscillator from the following circuits,
impedance matching, and extra tuned circuits to clean up the signal. But
gain is usually less than one. With a buffer amp, you get a cleaner more stable
signal of the proper impedance for the next circuits and they cant effect the
oscillator. If the load on the oscillator varies it will cause frequency and
amplitude instability. This is what the buffer amp is used to avoid. A buffer
amp has a very high input impedance so it doesnt load up the oscillator.
And it has the right output impedance to satisfy the following circuit

1.2

Why is this circuit useful?

There are many situations where you do not want to draw current from a
circuit (i.e. load the circuit). Some of those situations are: oA bridge
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Differential Amplifier with Buffer configuration

circuit or a voltage divider circuit - maybe where there is a resistive sensor

in the bridge or voltage divider - and drawing current when you measure
the voltage would be enough to change the voltage. oA rectifier/filter where
the output is across a capacitor. In that situation drawing current from the
capacitor will discharge the capacitor, reducing the voltage.

1.3

Problem Statement

The amplifier block is to be designed to meet the defined specification of

buffered amplifier. Buffered amplifier which provides the high input impedance
to low output impedance. The design is to be implemented using UMC
180nm technology for a gain factor of 1. Tool: Cadence (Virtuoso Schematic
and Layout Editor, Spectre and Assura DRC, LVS).

1.4

Objective of the Project

To design the buffer configuration in differential amplifier for open loop gain
of 50db and UGB=10MHz and evaluate the performance parameter .The
layout of the amplifier is build.To understand the characteristics and applications of the buffer amplifier. The main characteristics under consideration
are high gain, high PSRR, high output swing and UGB. Performance of any
circuit depends upon these characteristics. At reduced supply voltages, output swing becomes an important parameter. At large supply voltages, there
is a trade off among speed, power and gain.

1.5

Methodology

Literature survey of the amplifier architectures is carried out after going

through various papers. All the devices used in the design were characterized and the required parameters like threshold voltage Vth,VDS and VGS
of a transistor were extracted. After under-standing the working of amplifier, basic circuits were simulated with ideal conditions and specifications.
Later with these specifications, the circuits are designed in Cadence Virtuoso
schematic editor and simulated using ADE tool. The schematic and symbol representation for major units of buffered amplifier namely differential
amplifier, current mirror is done and the behaviour of each unit is verified
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Differential Amplifier with Buffer configuration

by transient, DC and AC analysis. The layout is designed and checked by

running DRC and LVS using cadence virtuoso layout simulator.

1.6

Organization of the report

1. Chapter 1 - Deals with the project definition, objective and specifications of the project.
2. Chapter 2 - Deals with the Literature Survey .
3. Chapter 3 - This chapter deals with working of Differential Amplifier.
4. Chapter4 - Deals with Result Analysis

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

Chapter 2
Literature Survey
The differential amplifier is an important stage of a very large area of applications, including high-performances analog/mixed ICs, such as operational
amplifiers, voltage comparators, voltage regulators, video amplifiers, modulators and demodulators or A/D and D/A converters. The linearity of the
classical CMOS differential amplifier is relatively poor because of the fundamental nonlinear characteristic of MOS transistors, resulting the possibility
of achieving a relatively good linearity only for a restricted input voltage
range (the amplitude of the input voltage for the classic differential amplifier
using MOS transistors in saturation have to be below a few hundreds of mV).

2.1

Simple Differential Amplifier

In a differential amplifier the output signal generally is the amplified version

of the difference of two inputs of the amplifier. Because of the exclusive properties of this type of amplifier, it is considered as one of the most important
building blocks in many analog circuits. The fig 2.1 shows the single ended
output differential amplifier.the small signal ,low frequency gain of both circuits is equal to gmN (rON ||rOP ).The bandwidth is usualyy determined by the
load capapcitance CL

2.2

Telescopic cascode op amps

In order to achieve high gain ,the differential cascade topologies can be

2
2
used.such circuits displays a gain on the order of gmN [(gmN rON
||(gmP rOP
)],but
5

Differential Amplifier with Buffer configuration

Figure 2.1: Differential Amplifier

at the cost of output swing and additional poles these configuration are called
telescopic cascade op amps. (a): The circuit providing a single-ended output
suffers from a mirror pole at node X, creating stability issues. (b): Fully
differential topology, the output swing is given by 2[VDD (VOD1 + VOD3
+ VCSS + VOD5 + VOD7)] where V ODj denotes the overdrive
voltage of Mj Another drawback of telescopic cascodes is the difficult in shorting their inputs and outputs, e.g., to implement a unity-gain buffer. Cascode op amp with input and output shorted unit gain feedback topology as
shown in fig2.2 Output swing: M2 and M4 in saturation Vout <= Vx + VT H2
and Vout >= Vb + VT H4 . Since Vx <= Vb + VGS4 ,Vb VT H4 <= Vout <=
Vb VGS4 + VT H2 Since the op amp attempts to force Vout to be equal to
Vin , forVin < Vb VT H4 , we have Vout Vin and M4 is in triode region while others
are saturated. Under this condition, the open-loop gain of the op amp is reduced. As Vin and Vout hence exceed Vb VTH4, M4 enters saturation and
the open-loop gain reaches a maximum. For Vb VT H4 < Vin < Vb (VGS4 VT H2 ),
both M2 and M4 are saturated and for Vin > Vb (VGS4 VT H2 ), M2 and M1
enter the triode region, degrading the gain. Thus, a cascode op amp is rarely
used as a unit-gain buffer

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Differential Amplifier with Buffer configuration

Figure 2.2: Telescopic cascode op amps

Figure 2.3: cascode op amp with input and output shorted

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Chapter 3
Design of Differential Amplifier
In this chapter we present the method for designing the differential amplifier using small signal model analysis.We have designed a CMOS differential
amplifier with active load single-ended output for the specifications mentioned in Table1.We have used UMC 180nm CMOS Technologyin which we
selected the model N3 3M M and P3 3M M for NMOS and PMOS respectively,
for simulation in Cadence Spectre tool.

3.1

differential Amplifier

A single-ended output differential amplifier can be implemented by putting

a PMOS current mirror on top of the circuit as illustrated in Figure 3.1. In
this circuit, (M1, M2) and also (M3, M4) are mutually identical with each
other and thus the tail current I0 is equally divided between M1 (M3) and M2
(M4) in the absence of differential input voltage. In this situation because of
the circuit symmetry, the dc voltage level at the drain of M1 and M2 is the
same and equals to where P = c0x (W/L)p P is th ehole charge carrier

Differential Amplifier with Buffer configuration

3.2

Large signal analysis of differential amplifier

Figure 3.1: Single-ended output differential amplifier in dc state

When an ac differential input voltage is superimposed on the bias common
mode voltage the drain current in M1 and M2 will change around its static
value of I0 /2 in the opposite direction. In the differential
amplifiershown

in Figure 3.2 for variation of vi in the range of 2I0 / < vi < + 2I0 /
When vi rises rises, due to the positive voltage gain of the amplifier, the
output voltage with a steep positive slope goes up and M4 quickly approaches
the triode region where the voltage gain starts dropping. This occurs for a
rather low positive change in vi .After M4 enters the triode region, with more
increase in vi the output voltage v0 continues to rise with a lower rate. At
the same time the tail current steers toward M1 and the current of M2 and
M4 approaches zero. When differential input voltage reaches the entire tail
current flows through M1 and thus M2 turns off. At this point, M4 is in
triode with zero drain current, which means the drain-source voltage of M4
is zero and thus the output voltage is fixed on VDD. When input voltage
changes in the negative direction, the output voltage rapidly drops again due
to the differential amplifier voltage gain and this time M2 goes to the triode
region. As long as the tail transistor operates in saturation, M5 acts as a
current source, and M3 with a diode connection structure always remains in
saturation. On the other hand, if the source-to-drain voltage of M4 is more
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Differential Amplifier with Buffer configuration

than VDD,SAT it will operate in saturation and the current mirror consisting
of M3 and M4 forces M1 and M2 to have the same current even though M2 is
in triode and therefore the drain currents of M1 and M2 remain on I0 /2. For
large negative differential input voltage the tail transistor ultimately enters
the triode region where the tail current starts decreasing with the input.
As a result, the drain currents of M1 and M2 also decrease in parallel with

Figure 3.2: Variations of differential amplifier drain currents versus input

each other. The drain currents of M1 and M2 versus the differential input
voltage variation are plotted in Figure 3.2. The large-signal characteristic
of the CMOS differential amplifier with a current mirror load is depicted
in Fig 3.3. The active load differential amplifier has better performance
only if all transistors are identical. The use of identical transistors leads
to no mismatch, hence offset voltage becomes zero, but practically it is not
possible. Practical differential amplifiers have non-zero common mode gain,
therefore, the CMRR becomes finite and they have non-zero offset voltage.
In this paper we have assumed finite input common mode range (ICMR) for
the calculation of all parameters and have neglected the body effect. The
circuit arrangement for CMOS differential amplifier with active load and
single ended output is shown in Fig3.4. Transistors M1,M2and M3, M4have
identical size. To achieve better performance in voltage gain, bandwidth and
gain bandwidth product, all transistors should be in saturation region but it
hampers the output swing. Therefore, to improve the output swing and to
maintain the other characteristic parameters at acceptable levels, the load
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Differential Amplifier with Buffer configuration

Figure 3.3: Variations of differential amplifier drain currents versus input

transistors and biasing transistors should be in linear region.The elow fig 3.4
shows the 5 pack differential amplifier

Figure 3.4: 5 pack differential amplifier

3.3

Small Signal Model

The transistor sizes for this design have been calculated through the analysis
of the small signal model of the circuit shown in Fig3.4.1In the differential
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Differential Amplifier with Buffer configuration

amplifier the design parameters are the W/L values of M1 through M5 and
the current in M5,I5 (Vbias is an external voltage that defines I5 and generally
is replaced by the input of a current mirrors)
the starting point of design consists of two types of information. One is the
design constraint such as the poer supply,the technology and the temperature. The other type of information is the specifications.The specifications
for the differential amplifier is shown in table3.
1.Small signal gain,Av
2.Frequency response for a given load capacitance 3dB
3.Input Common Mode Voltage range
4.Slew rate for a given load capacitance ,SR
the design is implemented with the relationships that describe the specifications and the use of these relationships to solve for the dc currents and W?L
values of all transistors.
Av =gm1 *Rout (1)
from the above eqn (1) we get the (W/L)1,2 value
3dB =1/(Rout CL ) (2)
the eqn920 gives the first pole location of the diff amp
V ic(max) = V dd V gs3 + V tn1 (3)
from eqn(3)we get the (W/L)3,4 value
V ic(min) = V ds5(sat) + V gs1 = V ds5(sat) + V gs2 (4)
we get the ratio of current mirrors (W/L)5 Specification

3.4

Frequency Response of Fifferential Amplifier

The study of the behavior of both differential and common-mode voltage

gains (Acm and Acm) of a differential amplifier in the frequency domain is
important. Indeed, the first shows how fast the amplifier is able to follow
the rapid changes in the input differential signal and the second provides
a figure of merit for the amplifier about its capability to attenuate highfrequency disturbance signals that appear at the input as common-mode
noise. To simplify the frequency analysis we consider only two main inter-

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

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Differential Amplifier with Buffer configuration

Table 3.1: Specification

nal capacitances of the circuit that form two largest time constants at their
corresponding nodes. Figure 3.11 shows a differential amplifier where Ca
represents the gate capacitance of the current mirror load and Cb is the
total capacitance including the load capacitance at the output node. The
equivalent resistance seen at node A is rather small 1/gm3 but its parasitic
capacitance Ca that mainly consists of the gate-source capacitance of M3
and M4 could be considerable in such a way that its corresponding time
constant is noticeable. The high resistance at the output and the equivalent
capacitance at this node create the dominant time constant of the circuit
at this node. The highfrequency small-signal equivalent circuit of Figure
3.11 is depicted in Figure 3.12 in which we have ignored the body effect
in M1 and M2 and also neglected the output resistance of the tail current.
It is also assumed that two pairs of (M1, M2) and (M3, M4) are mutually symmetrical. The transconductance and output resistance for NMOS
devices are denoted by gmN and roN respectively, and those of PMOS devices by gmP and roP . Before writing the required equations to obtain the
circuit transfer function, first we replace the indicated lower-part of the circuit with its Thevenin equivalent circuit. This can be done by replacing the
two voltage-controlled current sources by their Thevenin equivalent circuits
as illustrated in Figure 3.13. The equivalent Thevenin voltage and resistance are Vt =gM n roN (V 1 V 2)=gM n roN V i and Rt=2roN , respectively.By
replacing the lower-part circuit in Figure 3.12 with the Thevenin equiva-

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

13

Differential Amplifier with Buffer configuration

lent circuit, we get a simplified form of the small-signal equivalent circuit

shown in Figure 3.14 where ZA =1/(gmp + sCA ) and ZB =rop /(roP sCB ) are
the impedances obtained from the parallel combination of CA with 1/(gmp

Figure 3.5: Differential amplifier with two main capacitances impacting on

frequency response

Figure 3.6: High-frequency small-signal equivalent circuit for differential amplifier.

and that of CA with roP , respectively. the voltgae gain for for the differential amplifier is AV s =Avo (1 + s/wz)/(1 + s/wp1)(1 + s/wp2)) where
Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

14

Differential Amplifier with Buffer configuration

Avo = (2gmN gmP roN roP )/(1 + 2gmP (roN + roP ))

where wp1 is the dominant pole of the circuit and is given by
wp1 = 1/(roN ||roP )Cb
The nondominant pole is created by the current mirror circuit, hence known
as the mirror pole

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15

Chapter 4
Simulation and Results
4.1

EVALUATION OF DEVICE

The below table shows the evaluation of the device, which helps in the proper
selection of the device. since in umc1 80nm technology there are two types of
devices one is thep3 3m m and n3 3m m and p1 8m m and n1 8m m. in this paper
we using the n3 3m m and p3 3m m device for the simulation which provides the
high gain and ugb
For L=2u,W=18u,Idc=20uA

Table 4.1: Evaluation of NMOS Device

// // //
The W/L ratios of the different devices

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Differential Amplifier with Buffer configuration

Table 4.2: Evaluation of PMOS Device

Table 4.3: Device Sizes

4.2

PVT Analysis

In the below table the PVT Analysis is done for the different devices

for VDD=1.8V

Table 4.4: PVT Analysis for 1.8V

for VDD=1.62V

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Differential Amplifier with Buffer configuration

Table 4.5: PVT Analysis for 1.62V

for VDD=1.92V

Table 4.6: PVT Analysis for 1.92V

4.3

Schematic of Differential Amplifier

The below figurs shows the schematic of Differential amplifier AC Response

for the open loop gain and also show the first loop location of the diff amp
The below figures show the Amplifier in the Buffer Configuration

4.4

Summary

Simulation results obtained using Cadence Spectre tool shown in below table

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Differential Amplifier with Buffer configuration

Figure 4.1: schematic

Table 4.7: Summary

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Differential Amplifier with Buffer configuration

Figure 4.2: AC response

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Differential Amplifier with Buffer configuration

Figure 4.3: Amplifier in the Buffer Configuration

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Chapter 5
Conclusion
5.1

Conclusion

In this paper a high performance CMOS differential amplifier with active load
and single-ended outputcircuit is designed and characterized. The design is
carried out using UMC 180technology in Cadence Spectretool. The models
used are N 33M M and P 33M M for the NMOS and PMOS transistors
respectively. We have achieved better results than the target values set for
the design. The obtained results are summarized in Table 4.

22

Bibliography
[1] Han Shuguang Chi Baoyong,Wang Zhihua A Novel Off
set2Cancellation Technique for Low Voltage CMOS Differential
Amplifiers Chines journal of semiconductors, Vol. 27, No. 5, pp.
778-782, 2006.
[2] A.D. Grasso,S. Pennisi, High-Performance CMOS Pseudo-Differential
Amplifier Circuits and Systems, ISCAS 2005. IEEE InternationalSymposium on, pp. 1569 1572, 23-26 May 2005.
[3] B.J. Hosticka, Improvement of the Gain of CMOS Amplifiers IEEE
Journal of Solid-State Circuits, vol. SC-14, Issue 6, Dec.1979, pp.11111114. 1996.
[4] Behzad Razavi Design of analog cmos integrated circuits McGrawHill, 2001.
[5] Phillip E. Allen and Douglas R. Holberg CMOS analog circuit Design
McGraw-Hill, 2001.