Verilog Lab

Exercise No.
Half adder
Date:
Aevin Thomas-RA1412008010010
Type: Combinational design
Aim : To design a Half adder in structural, dataflow and behavioral modeling using verilog and
verify the functionality with test bench.
Simulation tool: ModelSim 10.3
Circuit diagram:
Verilog program:
//Structural modeling
module ha_st (output sum,cout,input a,b);
xor(sum,a,b);
and(cout,a,b);
endmodule
//Data flow modeling
module ha_dt(output sum,cout,input a,b);
assign sum=a^b;
assign cout=a&b;
endmodule
//Behavioral modeling
module ha_bh(output reg sum,cout,input a,b);
always@(*)
begin
sum=a^b;
cout=a&b;
end
endmodule
//Half adder test bench
module ha_tb();
reg A,B;
wire SUM,COUT;
//Half adder instance
ha_dt(SUM,COUT,A,B);
//Stimulus generation
initial
begin
A=1'b0;B=1'b0;
#10
A=1'b0;B=1'b1;
#10
A=1'b1;B=1'b0;
#10
A=1'b1;B=1'b1;
#10
A=1'bx;B=1'bx;
end
endmodule
Test wave form:
Exercise No. 2
Single bit full adder

Date:
Aim : To design a single bit Full adder in structural, dataflow and behavioral modeling using
verilog and verify the functionality with test bench.
Circuit diagram:
Verilog program:
//Structural modeling
module fa_st(output sum,cout,input a,b,cin);
wire p,g1,g2;
xor(p,a,b);
xor(sum,p,cin);
and(g1,a,b);
and(g2,p,cin);
or(cout,g1,g2);
endmodule
//Data flow modeling
module fa_dt(output sum,cout,input a,b,cin);
assign sum=(a^b)^cin;
assign cout=(a&b)|(a&cin)|(b&cin);
endmodule
//Data flow modeling with concatenation
module fa_cn(output sum,cout,input a,b,cin);
assign {cout,sum}=a+b+cin;
endmodule
//Behavioral modeling
module fa_bh(output reg sum,cout,input a,b,cin);
always@(*)
{cout,sum}=a+b+cin;
endmodule
//Full adder test bench

module fa_tb();
reg A,B,CIN;
wire SUM,COUT;
//Full adder instance
fa_dt f0(SUM,COUT,A,B,CIN);
initial
begin
A=1'b0;B=1'b0;CIN=1'b0;
#10
A=1'b0;B=1'b0;CIN=1'b1;
#10
A=1'b0;B=1'b1;CIN=1'b0;
#10
A=1'b0;B=1'b1;CIN=1'b1;
#10
A=1'b1;B=1'b0;CIN=1'b0;
#10
A=1'b1;B=1'b0;CIN=1'b1;
#10
A=1'b1;B=1'b1;CIN=1'b0;
#10
A=1'b1;B=1'b1;CIN=1'b1;
#10
A=1'bx;B=1'bx;CIN=1'bx;
end
endmodule
Test wave form:
Exercise No. 3
4 to 1 Multiplexer
Date:
Aim : To design a 4 to 1 Multiplexer in structural, dataflow and behavioral modeling using
Circuit diagram:
Verilog program:
//4 to 1 mux, structural modeling
module mux4_1_st (output out,input i0,i1,i2,i3,s0,s1);
wire a0,a1,a2,a3;
and(w0,i0,~s1,~s0);
and(w1,i1,~s1,s0);
and(w2,i2,s1,~s0);
and(w3,i3,s1,s0);
or(out,w0,w1,w2,w3);
endmodule
//4 to 1 mux , data flow modeling
module mux4_1_dt (output out,input i0,i1,i2,i3,s0,s1);
assign out = (i0&~s1&~s0)|(i1&~s1&s0)|(i2&s1&~s0)|(i3&s1&s0);
endmodule
//4 to 1 mux, behavioral modeling
module mux4_1_bh (output reg out,input i0,i1,i2,i3,s0,s1);
always @ (*)
case ({s1,s0})
2'b00 : out = i0;
2'b01 : out = i1;
2'b10 : out = i2;
2'b11 : out = i3;
default out = 1'bx;
endcase
endmodule
//4 to 1 mux test bench
module mux4_1_tb ();
reg [5:0] mux_in;
wire out_tb;
//4*1 mux instance
mux4_1_st m0 (out_tb,mux_in[5],mux_in[4],mux_in[3],mux_in[2],mux_in[1],mux_in[0]);
initial
begin
mux_in = 6'b100000;
#10
mux_in = 6'b010010;
#10
mux_in = 6'b001001;
#10
mux_in = 6'b000111;
#10
mux_in = 6'bx;
end
endmodule
9
Test wave form:
10
Exercise No. 4
8 to 1 Multiplexer
Date:
Aim : To design a 8 to1 Multiplexer using 4 to1 multiplexer in verilog and verify the
functionality with test bench.
Block diagram:
11
Verilog program:
//mux8 to 1 using mux4 to 1
module mux8_1 (output [2:0] out, input [2:0]i0,i1,i2,i3,i4,i5,i6,i7,s );
wire [2:0]m0_out,m1_out;
mux4_1_vt m0 (m0_out,i0,i1,i2,i3,s[1:0]);
mux4_1_vt m1 (m1_out,i4,i5,i6,i7,s[1:0]);
assign out = s[2] ? m1_out : m0_out;
endmodule
//4 to 1 mux, behavioral modeling with vector input
module mux4_1_vt (output reg [2:0]out,input [2:0]i0,i1,i2,i3,input [1:0]s);
always @ (*)
if (s==2'b00) out = i0;
else if (s==2'b01) out = i1;
else out = 3'bx;
endmodule
//8 to 1 mux test bench
module mux8_1_tb ();
reg [2:0]i0_tb,i1_tb,i2_tb,i3_tb,i4_tb,i5_tb,i6_tb,i7_tb,s_tb;
wire [2:0] out_tb;
//8*1 mux instance
mux8_1 m0(out_tb,i0_tb,i1_tb,i2_tb,i3_tb,i4_tb,i5_tb,i6_tb,i7_tb,s_tb );
initial
begin
i0_tb = 3'b000;
i1_tb = 3'b001;
i2_tb = 3'b010;
i3_tb = 3'b011;
i4_tb = 3'b100;
i5_tb = 3'b101;
i6_tb = 3'b110;
i7_tb = 3'b111;
end
reg [2:0]i;
initial
for (i=0; i<=7;i=i+1)
#10 s_tb = i;
endmodule
12
Test wave form:
13
Exercise No. 5
1 to 4 Demultiplexer
Date:
Aim : To design a 1 to 4 demultiplexer in structural, dataflow and behavioral modeling using
Circuit diagram:
14
Verilog program:
//1 to 4 demux, structural modeling
module demux1_4_st (output o0,o1,o2,o3,input in,s0,s1);
and(o0,in,~s1,~s0);
and(o1,in,~s1,s0);
and(o2,in,s1,~s0);
and(o3,in,s1,s0);
endmodule
//1 to 4 demux, data flow modeling
module demux1_4_dt (output o0,o1,o2,o3,input in,s0,s1);
assign o0=in&~s1&~s0;
assign o1=in&~s1&s0;
assign o2=in&s1&~s0;
assign o3=in&s1&s0;
endmodule
//1 to 4 demux, behavioral modeling
module demux1_4_bh (output reg o0,o1,o2,o3,input in,s0,s1);
always @ (*)
case ({s1,s0})
2'b00 : begin o0=in;o1=1'bx;o2=1'bx;o3=1'bx;end
2'b01 : begin o0=1'bx;o1=in;o2=1'bx;o3=1'bx;end
2'b10 : begin o0=1'bx;o1=1'bx;o2=in;o3=1'bx;end
2'b11 : begin o0=1'bx;o1=1'bx;o2=1'bx;o3=in;end
default begin o0=1'bx;o1=1'bx;o2=1'bx;o3=1'bx;end
endcase
endmodule
//1 to 4 demux test bench
module demux1_4_tb ();
reg [2:0] demux_in;
wire o0_tb,o1_tb,o2_tb,o3_tb;
//1*4 demux instance
demux1_4_st m0 (o0_tb,o1_tb,o2_tb,o3_tb,demux_in[2],demux_in[1],demux_in[0]);
initial //Stimulus generation
begin
demux_in = 3'b100;
#10
demux_in = 3'b110;
#10
demux_in = 3'b101;
#10
demux_in = 3'b111;
#10
demux_in = 3'bx;
end
endmodule
15
Test wave form:
16
Exercise No. 6
1 to 8 Demultiplexer
Date:
Aim : To design a 1 to 8 demultiplexer using 1 to 4 Demultiplexer in verilog and verify the
Block diagram:
17
Verilog program:
//1 to 8 demux using 1 to 4 demux
module demux1_8 (output[0:7]o,input [2:0]s,input in);
wire w0,w1;
//demux instance
demux1_4_st d0(o[0],o[1],o[2],o[3],w0,s[0],s[1]);
demux1_4_st d1(o[4],o[5],o[6],o[7],w1,s[0],s[1]);
demux1_2_dt d2(w0,w1,in,s[2]);
endmodule
//1 to 2 demux, data flow modeling
module demux1_2_dt (output o0,o1,input in,s);
assign o0=in&~s;
assign o1=in&s;
endmodule
//1 to 4 demux, structural modeling
module demux1_4_st (output o0,o1,o2,o3,input in,s0,s1);
and(o0,in,~s1,~s0);
and(o1,in,~s1,s0);
and(o2,in,s1,~s0);
and(o3,in,s1,s0);
endmodule
//1 to 8 demux test bench
module demux1_8_tb ();
reg [2:0] s_tb;
reg [2:0]i;
reg demux_in;
wire [0:7]o_tb;
//1*4 demux instance
demux1_8 d0 (o_tb,s_tb[2:0],demux_in);
initial
begin
demux_in =1'b1;
for (i=0; i<=7;i=i+1)
#10 s_tb = i;
end
endmodule
18
Test wave form:
19
Exercise No. 7
Encoder
Date:
Aim : To design a 8 to 3 Encoder in behavioral modeling using verilog and verify the
Circuit diagram:
20
Verilog Program:
//8 to 3 Encoder
module encoder (output reg [2:0]out,input [7:0]in,en);
always@(*)
begin
if(en)
case(in)
8'b10000000:out=3'b000;
8'b01000000:out=3'b001;
8'b00100000:out=3'b010;
8'b00010000:out=3'b011;
8'b00001000:out=3'b100;
8'b00000100:out=3'b101;
8'b00000010:out=3'b110;
8'b00000001:out=3'b111;
default out=3'bx;
endcase
else out=3'bz;
end
endmodule
//Encoder test bench
module encoder_tb ();
reg [7:0]in_tb;
reg en_tb;
wire [2:0]out_tb;
//Encoder instance
encoder e0(out_tb,in_tb,en_tb);
initial
begin
en_tb=1'b0;
#10
en_tb=1'b1;
#10
in_tb=8'b10000000;
#10
in_tb=8'b01000000;
#10
in_tb=8'b00100000;
#10
in_tb=8'b00010000;
#10
in_tb=8'b00001000;
#10
in_tb=8'b00000100;
#10
in_tb=8'b00000010;
#10
in_tb=8'b00000001;
#10
in_tb=8'bx;
end
endmodule
21
Test wave form:
22
Exercise No. 8
Decoder
Date:
Aim : To design a3 to 8 Decoder in behavioral modeling using verilog and verify the
Circuit diagram:
23
Verilog program:
//3 to 8 decoder
module decoder (output reg [7:0]out,input [2:0]in,en);
always@(*)
begin
if(en)
case(in)
3'b000:out=8'b10000000;
3'b001:out=8'b01000000;
3'b010:out=8'b00100000;
3'b011:out=8'b00010000;
3'b100:out=8'b00001000;
3'b101:out=8'b00000100;
3'b110:out=8'b00000010;
3'b111:out=8'b00000001;
default out=8'bx;
endcase
else out=8'bz;
end
endmodule
//Decoder test bench
module decoder_tb ();
reg [2:0]in_tb;
reg en_tb;
wire [7:0]out_tb;
//Decoder instance
decoder d0(out_tb,in_tb,en_tb);
initial
begin
en_tb=1'b0;
#10
en_tb=1'b1;
#10
in_tb=3'b000;
#10
in_tb=3'b001;
#10
in_tb=3'b010;
#10
in_tb=3'b011;
#10
in_tb=3'b100;
#10
in_tb=3'b101;
#10
in_tb=3'b110;
#10
in_tb=3'b111;
#10
in_tb=3'bx;
end
endmodule
24
Test wave form:
25
Exercise No. 9
Comparator
Date:
Aim : To design a N bit parameterized comparator in behavioral modeling using verilog and
Block diagram:
26
Verilog program:
//Nbit comparator
module cmpNbit (Alarger,Blarger,Eql,A,B);
parameter N = 4;
output reg Alarger, Blarger , Eql;
input [N-1:0] A,B;
always @ (*)
if (A==B)
begin
Eql = 1'b1; Alarger = 1'b0; Blarger = 1'b0;
end
else if (A>B)
begin
end
else if (B>A)
begin
end
else
begin
Eql = 1'bx; Alarger = 1'bx; Blarger = 1'bx;
end
endmodule
//Comparator test bench
module cmpNbit_tb();
reg [3:0]A_tb,B_tb;
wire Eql_tb,Alarger_tb,Blarger_tb;
//comparator instance
cmpNbit c0(Alarger_tb,Blarger_tb,Eql_tb,A_tb,B_tb);
initial
begin
A_tb=4'd6;B_tb=4'd8;
#10
#10
#10
A_tb=4'dx;B_tb=4'dx;
end
endmodule
27
Test wave form:
28
Exercise No. 10
2*2 Multiplier
Date:
Aim: To design a 2*2 Multiplier in structural modeling using verilog and verify the
functionality.
Circuit diagram:
29
Verilog program:
//Multiplier 2*2, structural modeling
module multiplier2_2 (output [3:0]prod, input[1:0]a,b);
wire [3:0]y,z;
and (y[0],a[0],b[0]);
and (y[1],a[1],b[0]);
and (y[2],a[0],b[1]);
and (y[3],a[1],b[1]);
ha h1 (z[0],z[1],y[1],y[2]);
ha h2 (z[2],z[3],z[1],y[3]);
assign prod={z[3],z[2],z[0],y[0]};
endmodule
//Half adder
module ha (output sum,cout,input a,b);
xor(sum,a,b);
and(cout,a,b);
endmodule
30
Test wave form:
31
Exercise No. 11
32
4*4 Multiplier
Date:
Aim : To design a 4*4 Multiplier in structural modeling using verilog and verify the
Circuit diagram:
33
Verilog program:
//Multiplier 4*4, structural modeling
module multiplier4_4 (output [7:0] prod,input [3:0]a,b);
wire [3:0]y0,y1,y2,y3,s0,s1,s2,c0,c1,c2;
and (y0[0],a[0],b[0]);
and (y0[1],a[1],b[0]);
and (y0[2],a[2],b[0]);
and (y0[3],a[3],b[0]);
and (y1[0],a[0],b[1]);
and (y1[1],a[1],b[1]);
and (y1[2],a[2],b[1]);
and (y1[3],a[3],b[1]);
and (y2[0],a[0],b[2]);
and (y2[1],a[1],b[2]);
and (y2[2],a[2],b[2]);
and (y2[3],a[3],b[2]);
and (y3[0],a[0],b[3]);
and (y3[1],a[1],b[3]);
and (y3[2],a[2],b[3]);
and (y3[3],a[3],b[3]);
fa f1 (s0[0],c0[0],y0[1],y1[0],1'b0);
fa f2 (s0[1],c0[1],y0[2],y1[1],c0[0]);
fa f3 (s0[2],c0[2],y0[3],y1[2],c0[1]);
fa f4 (s0[3],c0[3],1'b0,y1[3],c0[2]);
fa f5 (s1[0],c1[0],s0[1],y2[0],1'b0);
fa f6 (s1[1],c1[1],s0[2],y2[1],c1[0]);
fa f7 (s1[2],c1[2],s0[3],y2[2],c1[1]);
fa f8 (s1[3],c1[3],c0[3],y2[3],c1[2]);
fa f9 (s2[0],c2[0],s1[1],y3[0],1'b0);
fa f10 (s2[1],c2[1],s1[2],y3[1],c2[0]);
fa f11 (s2[2],c2[2],s1[3],y3[2],c2[1]);
fa f12 (s2[3],c2[3],c1[3],y3[3],c2[2]);
assign prod={c2[3],s2[3],s2[2],s2[1],s2[0],s1[0],s0[0],y0[0]};
endmodule
34
//Full adder
module fa (output s,cout,input a,b,cin);
assign {cout,s}=a+b+cin;
endmodule
//Multiplier test bench
module multiplier_tb();
reg [3:0]a_tb,b_tb;
wire [7:0]out_tb;
//multiplier instance
booth_mul m0 (out_tb,a_tb,b_tb);
//Stimulus generration
initial
begin
a_tb=4'd6;b_tb=4'd4;
#10
a_tb=4'd2;b_tb=4'd12;
#10
a_tb=4'd6;b_tb=4'd3;
end
endmodule
35
Test wave form:
36
Exercise No. 12
Arithmetic and Logic Unit

Date:
Aim : To design a 8 bit ALU in behavioral modeling using verilog and verify the functionality
with test bench.
Block diagram:
37
Verilog program:
//Arithematic and Logic Unit
module alu (output reg [7:0]Dout,output reg Cout,Oflow, input [7:0]A,B,input [2:0]Sel,input
CLR,M,CE,CLK);
reg [7:0]mul;
localparam and_add =3'b000;
localparam or_sub =3'b001;
localparam xor_mul =3'b010;
localparam nand_div =3'b011;
localparam nor_mod =3'b100;
localparam xnr =3'b101;
always @ (posedge CLK or posedge CLR)
if (CLR)
begin Dout <= 8'b0; Cout <=1'b0; Oflow <= 1'b0; end
else if (CE)
if (M)
case (Sel)
and_add : begin Dout <= A&B;Cout <=1'b0;Oflow <= 1'b0; end
or_sub : begin Dout <= A|B;Cout <=1'b0;Oflow <= 1'b0; end
xor_mul : begin Dout <= A^B;Cout <=1'b0;Oflow <= 1'b0; end
nand_div : begin Dout <= ~(A&B);Cout <=1'b0;Oflow <= 1'b0; end
nor_mod : begin Dout <= ~(A|B);Cout <=1'b0;Oflow <= 1'b0; end
xnr : begin Dout <= ~(A^B);Cout <=1'b0;Oflow <= 1'b0; end
default begin Dout<=Dout;Cout <=1'b0;Oflow <= 1'b0; end
endcase
else if (~M)
case (Sel)
and_add : begin {Cout,Dout} <= A+B;Oflow <= 1'b0; end
or_sub : begin {Cout,Dout} <= A-B;Oflow <= 1'b0; end
xor_mul : begin {mul,Dout} <= A*B;Cout <=1'b0;
if(mul!=8'b0)Oflow=1'b1; end
nand_div : begin Dout <= A/B;Cout <=1'b0;Oflow <= 1'b0; end
nor_mod : begin Dout <= A%B;Cout <=1'b0; Oflow <= 1'b0;end
default begin Dout <= Dout;Cout <=1'b0;Oflow <= 1'b0; end
endcase
else Dout <=Dout;
else Dout <=8'bz;
endmodule
38
// ALU test bench

module alu_tb ();
reg [7:0]A_tb,B_tb;
reg [2:0]Sel_tb;
reg CLK_tb,CLR_tb,CE_tb,M_tb;
wire [7:0]Dout_tb;
wire Cout_tb,Oflow_tb;
//ALU instance
alu a0 (Dout_tb,Cout_tb,Oflow_tb,A_tb,B_tb,Sel_tb,CLR_tb,M_tb,CE_tb,CLK_tb);
always #10 CLK_tb=~CLK_tb;
initial
begin
CLK_tb=1'b0;A_tb=8'd4;B_tb=8'd2;
CLR_tb=1'b1;CE_tb=1'bx;M_tb=1'bx;Sel_tb=3'bx;
#5 CLR_tb=1'b0;CE_tb=1'b1;M_tb=1'b0;Sel_tb=3'b000;
#20
CLR_tb=1'b0;CE_tb=1'b1;M_tb=1'b0;Sel_tb=3'b001;
#20
#20
#20
#20
#20
#20
#20
#20
#20
#20
#1000 $stop;
end
endmodule
39
Test wave form:
40
Exercise No. 13
Latch
Date:
Type: Sequential design
Aim : To design D latch and SR latch in behavior modeling using verilog and verify the
Circuit diagram:
41
Verilog program:
//Clocked d latch
module d_latch (output reg q,input d,rst,clk);
always@(clk or rst)
if(rst)
q<=1'b0;
else
q<=d;
endmodule
//SR latch
module sr_latch (output reg q,input s,r);
always@(s or r)
case (s,r)
2'b00:q<=q;
2'b01:q<=1'b0;
2'b10:q<=1'b1;
2'b11:q<=1'bx;
endcase
endmodule
42
Test wave form:

//D latch
//SR latch
43
Exercise No. 14
Flip flop
Date:
Aim : To design T flip flop, JK flip flop, D flip flop, and T flip flop using D flip flop in behavior
modeling using verilog and verify the functionality.
Circuit diagram:
44
Verilog program:
//D flip flop,-ve edge triggered
module d_ff (q,d,clk,rst);
output q;
input d,clk,rst;
reg q;
always @ (posedge rst or negedge clk)
if(rst)
q<=1'b0;
else q<=d;
endmodule
//T flop
module t_ff (q,clk,rst);
output q;
input clk,rst;
reg q;
if(rst)
q<=1'b0;
else
q<=~q;
endmodule
//T flop using D flop,d->t
module ct_ff (q,clk,rst);
output q;
input clk,rst;
wire d;
//D flop instance
D_FF d0 (q,d,clk,rst);
not n0 (d,q);
endmodule
//Clocked J K flip flop
module jk_ff (output reg q,input j,k,clk);
always@(posedge clk)
case ({j,k})
2'b00:q<=q;
2'b01:q<=1'b0;
2'b10:q<=1'b1;
2'b11:q<=~q;
endcase
endmodule
45
Test wave form:

//D Flip flop
//T flip flop
46
//T flip flop using D flip flop
//JK Flip flop
47
Exercise No. 15
SISO Shift register

Date:
Aim : To design SISO Shift register in behavior modeling using verilog and verify the
Block diagram:
48
Verilog program:
//SISO
module siso (output sout,input sin,sh_dir,rst,clk);
reg [15:0]sh_reg;
always@(posedge clk or rst)
if(rst)
sh_reg<=16'b0;
else if(sh_dir)//right shift
sh_reg<={sin,sh_reg[15:1]};
else if(~sh_dir)//left shift
sh_reg<={sh_reg[14:0],sin};
else sh_reg<=sh_reg;
assign sout=sh_dir?sh_reg[0]:sh_reg[15];
endmodule
//SISO test bench
module siso_tb();
reg sin_tb,rst_tb,clk_tb,sh_dir_tb;
wire sout_tb;
//siso instance
siso s0(sout_tb,sin_tb,sh_dir_tb,rst_tb,clk_tb);
always #10 clk_tb=~clk_tb;
initial
begin
clk_tb=1'b0;
rst_tb=1'b1;
sin_tb=1'b1;
#20
rst_tb=1'b0;
repeat (17)@(posedge clk_tb)
sh_dir_tb=1'b0;//left shift
#20
rst_tb=1'b1;
#20
rst_tb=1'b0;
repeat (17)@(posedge clk_tb)
sh_dir_tb=1'b1;//right shift
#1000
$stop;
end
endmodule
49
Test wave form:
50
Exercise No. 16
Barrel shift register

Date:
Aim : To design Barrel shift register in behavior modeling using verilog and verify the
functionality.
Block diagram:
51
Verilog program:
//Barrel shift
module barrel_shift (out,d,count,sh_dir,rst,clk);
input[15:0]d;
input [4:0]count;
input clk,sh_dir,rst;
output reg[15:0]out;
always@(posedge clk or posedge rst)
begin
if(rst)
out<=16'b0;
else if(sh_dir)
case (count)
5'd0:out<=d;
5'd1:out<={1'b0,d[15:1]};
5'd2:out<={2'b0,d[15:2]};
5'd3:out<={3'b0,d[15:3]};
5'd4:out<={4'b0,d[15:4]};
5'd5:out<={5'b0,d[15:5]};
5'd6:out<={6'b0,d[15:6]};
5'd7:out<={7'b0,d[15:7]};
5'd8:out<={8'b0,d[15:8]};
5'd9:out<={9'b0,d[15:9]};
5'd10:out<={10'b0,d[15:10]};
5'd11:out<={11'b0,d[15:11]};
5'd12:out<={12'b0,d[15:12]};
5'd13:out<={13'b0,d[15:13]};
5'd14:out<={14'b0,d[15:14]};
5'd15:out<={15'b0,d[15:15]};
5'd16:out<=16'b0;
default:out<=out;
endcase
else if (~sh_dir)
case (count)
5'd0:out<=d;
5'd1:out<={d[14:0],1'b0};
5'd2:out<={d[13:0],2'b0};
5'd3:out<={d[12:0],3'b0};
5'd4:out<={d[11:0],4'b0};
5'd5:out<={d[10:0],5'b0};
5'd6:out<={d[9:0],6'b0};
5'd7:out<={d[8:0],7'b0};
5'd8:out<={d[7:0],8'b0};
52
5'd9:out<={d[6:0],9'b0};
5'd10:out<={d[5:0],10'b0};
5'd11:out<={d[4:0],11'b0};
5'd12:out<={d[3:0],12'b0};
5'd13:out<={d[2:0],13'b0};
5'd14:out<={d[1:0],14'b0};
5'd15:out<={d[0:0],15'b0};
5'd16:out<=16'b0;
default:out<=out;
endcase
else out<=out;
end
endmodule
//barrel shift test bench
module barrel_shift_tb();
reg [15:0]d_tb;
reg [4:0]count_tb;
reg rst_tb,clk_tb,sh_dir_tb;
wire [15:0]out_tb;
//barrel shift instance
barrel_shift b0(out_tb,d_tb,count_tb,sh_dir_tb,rst_tb,clk_tb);
initial
begin
clk_tb=1'b0;
rst_tb=1'b1;
d_tb=16'd24;
sh_dir_tb=1'b0;
#20
rst_tb=1'b0;
for (count_tb=5'd0;count_tb<=5'd15;)
#20
count_tb=count_tb+5'd1;
#20
sh_dir_tb=1'b1;d_tb=16'd24;
for (count_tb=5'd0;count_tb<=5'd15;)
#20
count_tb=count_tb+5'd1;
end
endmodule
53
Test wave form:
54
Exercise No. 17
4 bit counter
Date:
Aim : To design a 4 bit counter in structural modeling using verilog and verify the functionality
with test bench.
Block diagram:
55
Verilog program:
//Ripple_carry_counter
module ripple_carry_counter (q,rst,clk);
output [3:0] q;
input clk,rst;
//TFF instances
T_FF t0 (q[0],clk,rst);
T_FF t1 (q[1],q[0],rst);
T_FF t2 (q[2],q[1],rst);
T_FF t3 (q[3],q[2],rst);
endmodule
//T_FF
module T_FF (q,clk,rst);
output q;
input clk,rst;
wire d;
//D_FF instance
D_FF d0 (q,d,clk,rst);
not n0 (d,q);
endmodule
//D_FF
module D_FF (q,d,clk,rst);
output q;
input d,clk,rst;
reg q;
if(rst)
q<=1'b0;
else
q<=d;
endmodule
56
//Counter test bench

module ripple_carry_counter_tb();
reg rst_tb,clk_tb;
wire [3:0]count;
//Counter instance
ripple_carry_counter c0(count,rst_tb,clk_tb);
//Clock initialization
initial
begin
clk_tb=1'b0;
forever #10 clk_tb = ~clk_tb;
end
initial
begin
rst_tb=1'b0;
#5 rst_tb = 1'b1;
#20 rst_tb = 1'b0;
#1000 $stop;
end
initial $monitor ($time,,, rst_tb,,,clk_tb,,,count);
endmodule
57
Display results:
58
Test wave form:
59
Exercise No. 18
Task and Function

Date:
Type: Task and function
Aim : To design a Parity checker, Logical operation and full adder using task and function in
verilog and verify the functionality.
Block diagram:
60
Verilog program:
//Logical operation
module logic_oper (output reg [15:0]ab_and,ab_or,ab_xor,input [15:0]a,b);
always@(*)
bitwise_oper(ab_and,ab_or,ab_xor,a,b);
//task definiton
task bitwise_oper (output [15:0]AB_AND,AB_OR,AB_XOR,input [15:0]A,B);
begin
AB_AND=A&B;
AB_OR=A|B;
AB_XOR=A^B;
end
endtask
endmodule
//Parity calculation
module parity_cal (output reg parity,input [15:0]addr);
always@(addr)
begin
parity=calc_parity(addr);
$display("Parity=%b",calc_parity(addr));
end
//Function definition
function calc_parity(input [15:0]ADDR);
begin
calc_parity=^ADDR;
end
endfunction
endmodule
//Full adder using task
module fa_tsk(output reg sum,output cout,input a,b,cin);
reg s0,c0,c1;
always@(*)
begin
ha (s0,c0,a,b);
ha (sum,c1,s0,cin);
end
assign cout=c0|c1;
task ha(output S,C,input A,B); //Task half adder
begin
S=A^B;
C=A&B;
end
endtask
endmodule
61
Test wave form:

//Logic operation using task
//Full adder using task
//Parity generator using functions
62
Exercise No. 19
Universal Shift Register

Date:
Type: Sequential design with task and function
Aim : To design a Universal Shift Register with task and function in behavior modeling using
Block diagram:
63
Verilog program:
//Universal shift register
module usr (output [15:0]Pout,
output reg Sout,
input [15:0]Pin,
input Sin,CLR,CLK,SET,LOAD,MOD,CE,Sh_dir);
`define PS 1'b0
`define SS 1'b1
reg [15:0]Sh_reg;
always @ (posedge CLK or posedge CLR or posedge SET)
if (CLR)
Sh_reg = 16'b0;
else if (SET)
Sh_reg = 16'hffff;
else if (CE)
if (LOAD)
Sh_reg = Pin;
else if (MOD == `PS )
Sh_reg = Pshift(Sh_reg,Sh_dir);
else if (MOD == `SS)
Sh_reg = Sshift(Sh_reg,Sh_dir,Sin);
else Sh_reg <=Sh_reg;
else Sh_reg <=Sh_reg;
function [15:0]Pshift (input [15:0] Fn_reg,input CTRL);
Pshift = CTRL ? (Fn_reg>>1) : (Fn_reg<<1);
endfunction
function [15:0]Sshift (input [15:0] Fn_reg,input CTRL,Sin);
Sshift = CTRL ? ({Sin,Fn_reg[15:1]}) : ({Fn_reg[14:1],Sin});
endfunction
always @ (posedge CLK)
if(Sh_dir) Sout <= Sh_reg[0];
else if (~Sh_dir) Sout <= Sh_reg[15];
else Sout <=Sout;
assign Pout = Sh_reg;
endmodule
64
//USR test bench

module usr_tb();
reg [15:0]Pin_tb;
reg Sin_tb,CLR_tb,CLK_tb,SET_tb,LOAD_tb,MOD_tb,CE_tb,Sh_dir_tb;
wire [15:0]Pout_tb;
wire Sout_tb;
//usr instance
usr
u(Pout_tb,Sout_tb,Pin_tb,Sin_tb,CLR_tb,CLK_tb,SET_tb,LOAD_tb,MOD_tb,CE_tb,Sh_dir_tb);
always #10 CLK_tb = ~CLK_tb;
initial
begin
CLK_tb=1'b0;
#5 CLR_tb=1'b1;
#20
CLR_tb=1'b0;SET_tb=1'b1;
#20
SET_tb=1'b0;
#20
PS(Pin_tb,LOAD_tb,MOD_tb,CE_tb);Sh_dir_tb=1'b0;
#20
Sh_dir_tb=1'b1;
#20
CLR_tb=1'b1;
#20
CLR_tb=1'b0;
#20
SS(Pin_tb,LOAD_tb,MOD_tb,CE_tb,Sin_tb);Sh_dir_tb=1'b0;
#20
Sh_dir_tb=1'b1;
#1000
$stop;
end
task PS (output reg [15:0]pin,output reg load,mod,ce);
begin
pin=16'd24;
ce=1'b1;
load=1'b1;
mod=1'b0;
end
endtask
task SS (output reg [15:0]pin,output reg load,mod,ce,sin);
begin
ce=1'b1;
pin=16'd24;
load=1'b1;
mod=1'b1;
sin=1'b1;
end
endtask
endmodule
65
Test wave form:
66
Exercise No. 20
N bit full adder

Date:
Type: Combinational design with generate
Aim : To design N bit full adder with generate statement using verilog and verify the
functionality.
Block diagram:
67
Verilog program:
//Full adder using generate
module FA_gen (sum,cout, A,B,cin);
parameter N=4;
output [N-1:0]sum; output cout;input [N-1:0]A,B; input cin;
wire [N:0] carry;
assign carry[0]=cin;
genvar i;
generate for(i=0;i<N;i=i+1)
begin: fa
FA x0(sum[i],carry[i+1],A[i],B[i],carry[i]);
end
endgenerate
assign cout=carry[N];
endmodule
//Full adder
module FA (output sum, cout,input A,B,cin);
assign sum = A^B^cin;
assign cout =(A&B)|(B&cin)|(A&cin);
endmodule
68
Test wave form:
69
Exercise No. 21
User Defined Primitives

Date:
Type: primitive design
Aim : To design UDP for 4 to 1 multiplexer, D latch, T flip flop, and D flip flop using verilog and
Circuit diagram:
70
Verilog program:
//UDP Mux4_1
primitive UDP_Mux4_1 (output out,input i0,i1,i2,i3,s1,s0);
table
//i0 i1 i2 i3 s1 s0 : out
1 ?
? ? 0 0 : 1;
0 ?
? ? 0 0 : 0;
? 1
? ? 0 1 : 1;
? 0
? ? 0 1 : 0;
? ?
1 ? 1 0 : 1;
? ?
0 ? 1 0 : 0;
? ?
? 1 1 1 : 1;
? ?
? 0 1 1 : 0;
? ?
? ? x ? : x;
? ?
? ? ? x : x;
endtable
endprimitive
//UDP d latch
primitive UDP_dlatch (output reg q, input d,clk,clr);
initial q = 0;// sequential UDP initialization (optional)
table //state table
// d clk clr : q : q+;
? ? 1 : ? : 0;
1 1 0 : ? : 1;
0 1 0 : ? : 0;
? 0 0 : ? : -;
endtable
endprimitive
//UDP T flip flop
primitive UDP_TFF (output reg q, input clk,clr);
//state table
table
// clk clr : q : q+;
? 1 : ? : 0;
? (10) : ? : -;
(10) 0 : 1 : 0;
(10) 0 : 0 : 1;
(0?) 0 : ? : -;
endtable
endprimitive
71
//UDP D flip flop

primitive UDP_DFF (output reg q, input d,clk,clr);
table //state table
// d clk clr : q : q+;
? ? 1 : ? : 0;
? ? f : ? : -;
1 f 0 : ? : 1;
0 f 0 : ? : 0;
? p 0 : ? : -;
* ? 1 : ? : 0;
endtable
endprimitive
//4 to1 UDP mux test bench
module UDP_mux4_1_tb ();
reg [5:0] mux_in;
wire out_tb;
//4*1 mux instance
UDP_Mux4_1 m0 (out_tb,mux_in[5],mux_in[4],mux_in[3],mux_in[2],mux_in[1],mux_in[0]);
begin
mux_in = 6'b100000;
#10
mux_in = 6'b010010;
#10
mux_in = 6'b001001;
#10
mux_in = 6'b000111;
#10
mux_in = 6'bx;
end
endmodule
//UDP T ff test bench
module UDP_TFF_tb();
wire q_tb;
reg clk_tb,clr_tb;
UDP_TFF u0(q_tb,clk_tb,clr_tb);
begin
clk_tb=1'b0;clr_tb=1'b0;
#5 clr_tb=1'b1;
#20
clr_tb=1'b0;
#100
$stop;
end
endmodule
72
Test wave form:

//4 to 1 UDP mux
//UDP T flip flop
73
Exercise No. 22
4 bit counter using UDP

Date:
Type: primitive design
Aim : To design 4 bit counter using UDP T flip flop in verilog and verify the functionality with
test bench.
Block diagram:
74
Verilog program:
//4 bit counter using UDP_TFF
module udp_counter_4bit (output [3:0]count,input rst,clk);
UDP_TFF t0 (count[0],clk,rst);
UDP_TFF t1 (count[1],count[0],rst);
endmodule
//UDP TFF
primitive UDP_TFF (output reg q, input clk,clr);
table //state table
// clk clr : q : q+;
? 1 : ? : 0;
? (10) : ? : -;
(10) 0 : 1 : 0;
(10) 0 : 0 : 1;
(0?) 0 : ? : -;
endtable
endprimitive
//UDP Counter test bench
module UDP_counter_tb();
reg rst_tb,clk_tb;
wire [3:0]count;
//Counter instance
udp_counter_4bit u0(count,rst_tb,clk_tb);
//Clock initialization
initial
begin
clk_tb=1'b0;
forever #10 clk_tb = ~clk_tb;
end
initial
begin
rst_tb=1'b0;
#5 rst_tb = 1'b1;
#20 rst_tb = 1'b0;
#1000 $stop;
end
initial $monitor ($time,,, rst_tb,,,clk_tb,,,count);
endmodule
75
Test wave form:
76
Exercise No. 23
Switch level modeling

Date:
Type: Transition gate design
Aim : To design 2 to1 multiplexer, D latch ,And gate, Not gate, Or gate, Xor gate and Full adder
in switch level modeling with transition gates using verilog and verify the functionality .
Circuit diagram:
77
Verilog program:
//2 to 1 mux
module sl_mux2_1(output out,input i0,i1,s);
wire sbar;
cmos(out,i0,sbar,s);
cmos(out,i1,s,sbar);
sl_not n0(sbar,s);
endmodule
//Switch level not gate
module sl_not (output out,input in);
supply1 pwr;
supply0 gnd;
pmos(out,pwr,in);
nmos(out,gnd,in);
endmodule
//Switch level d latch
module sl_latch(output q,qbar,input d,clk);
wire nclk,e;
cmos(e,d,clk,nclk);
cmos(e,q,nclk,clk);
sl_not n0(nclk,clk);
sl_not n1(qbar,e);
sl_not n2(q,qbar);
endmodule
//Full adder using switch level gates;
module fa_sl(output sum,cout,input a,b,cin);
wire p,g1,g2;
sl_xor x0(p,a,b);
sl_xor x1(sum,p,cin);
sl_and a0(g1,a,b);
sl_and a1(g2,p,cin);
sl_or o0(cout,g1,g2);
endmodule
78
//switch level xor

module sl_xor(output out,input a,b);
wire abar,bbar,w0,w1;
sl_and a0(w0,abar,b);
sl_and a1(w1,a,bbar);
sl_or o0(out,w0,w1);
sl_not n0(abar,a);
sl_not n1(bbar,b);
endmodule
//switch level and
module sl_and(output out,input a,b);
wire w0,w1;
supply1 pwr;
supply0 gnd;
pmos(w0,pwr,a);
pmos(w0,pwr,b);
nmos(w1,gnd,b);
nmos(w0,w1,a);
sl_not n0(out,w0);
endmodule
//switch level or
module sl_or(output out,input a,b);
wire w0,w1;
supply1 pwr;
supply0 gnd;
pmos(w0,pwr,a);
pmos(w1,w0,b);
nmos(w1,gnd,a);
nmos(w1,gnd,b);
sl_not n0(out,w1);
endmodule
79
Test wave form:

//Full adder using switch level gates
//Switch level 2 to 1 mux
//Switch level d latch
80
Exercise No. 24
32 byte RAM
Date:
Type: Memory design
Aim : To design 32 byte RAM using verilog in behavioral modeling and verify the functionality
with test bench.
Block diagram:
81
Verilog program:
//32 RAM
module ram32 (output reg[7:0]dout,input [7:0]din,input [4:0]addr,input rw,rst,clk);
reg [7:0]ram[0:31];
always@(clk or rst)
if (rst)
dout<=8'b0;
else if (rw)
dout<=ram[addr];
else if (~rw)
ram[addr]<=din;
else dout<=dout;
endmodule
//RAM32 test bench
module ram32_tb();
reg [7:0]din_tb;
reg [4:0]addr_tb;
reg rw_tb,rst_tb,clk_tb;
reg [7:0]i;
wire [7:0]dout_tb;
ram32 r0(dout_tb,din_tb,addr_tb,rw_tb,rst_tb,clk_tb);
initial
begin
clk_tb=1'b0;
#5 rst_tb=1'b1;
#20
rst_tb=1'b0;rw_tb=1'b0;
for(i=0;i<32;i=i+1)
begin
#20
din_tb=i; addr_tb=i[4:0];
end
#20
rw_tb=1'b1;
for(i=0;i<32;i=i+1)
begin
#20 addr_tb=i[4:0];
end
#1000 $stop;
end
endmodule
82
Test wave form:
83
Exercise No. 25
24 bit Efficient Carry look ahead adder

Date:
Type: Combinationl design
Aim : To design Efficient Carry look ahead adder in structural modeling using verilog and verify
the functionality .
Block diagram:
84
Verilg program:
//Modified CLA
module E_CLA24 (sum,cout,a,b,cin);
output [23:0]sum;
output cout;
input [23:0]a,b;
input cin;
wire [3:1]c;
//6bit CLA instance
E_CLA6 cla1 (sum[5:0],c[1],a[5:0],b[5:0],cin);
E_CLA6 cla2 (sum[11:6],c[2],a[11:6],b[11:6],c[1]);
E_CLA6 cla3 (sum[17:12],c[3],a[17:12],b[17:12],c[2]);
E_CLA6 cla4 (sum[23:18],cout,a[23:18],b[23:18],c[3]);
endmodule
//6bit CLA
module E_CLA6 (sum,cout,a,b,cin);
output [5:0]sum;
output cout;
input [5:0]a,b;
input cin;
wire [5:0]g,p;
wire [14:0]z;
wire [6:1]c;
xor (p[0],a[0],b[0]);
xor (p[1],a[1],b[1]);
xor (p[2],a[2],b[2]);
xor (p[3],a[3],b[3]);
xor (p[4],a[4],b[4]);
xor (p[5],a[5],b[5]);
and (g[0],a[0],b[0]);
and (g[1],a[1],b[1]);
and (g[2],a[2],b[2]);
and (g[3],a[3],b[3]);
and (g[4],a[4],b[4]);
and (g[5],a[5],b[5]);
//c1
and (z[0],p[0],cin);
or (c[1],g[0],z[0]);
//c2
and (z[1],p[1],c[1]);
85
or (c[2],g[1],z[1]);
//c3
and (z[2],p[2],p[1],c[1]);
and (z[3],p[2],g[1]);
or (c[3],g[2],z[2],z[3]);
//c4
and (z[4],p[3],p[2],p[1],c[1]);
and (z[5],p[2],g[1]);
or (z[6],g[2],z[5]);
and (z[7],p[3],z[6]);
or (c[4],g[3],z[7],z[4]);
//c5
and (z[8],p[4],p[3],p[2],p[1],c[1]);
and (z[9],p[4],p[3],z[6]);
and (z[10],p[4],g[3]);
or (c[5],g[4],z[10],z[9],z[8]);
//c6
and (z[11],p[5],p[4],p[3],p[2],p[1],c[1]);
and (z[12],p[5],p[4],p[3],z[6]);
or(z[13],g[4],z[10]);
and (z[14],p[5],z[13]);
or(c[6],g[5],z[14],z[12],z[11]);
//sum
xor (sum[0],p[0],cin);
xor (sum[1],p[1],c[1]);
xor (sum[2],p[2],c[2]);
xor (sum[3],p[3],c[3]);
xor (sum[4],p[4],c[4]);
xor (sum[5],p[5],c[5]);
assign cout=c[6];
endmodule
86
Test wave form:
87
Exercise No. 26
Self checking test bench

Date:
Type: Self checking test bench
Aim : To design 4 bit counter in behavior modeling using verilog and verify the functionality
with self checking test bench.
Block diagram:
88
Verilog program:
//Counter top
module counter_4bit_top;
wire [3:0] count_top;
wire clk_top,rst_top;
counter_4bit_tb t0 (clk_top,rst_top);
counter_4bit t1(count_top,rst_top,clk_top);
counter_4bit_ch t2(count_top,rst_top,clk_top);
initial $monitor ($time,,,"rst_top = %b,clk_top = %b ,count_top =%h
",rst_top,clk_top,count_top);
endmodule
//Counter test bench
`timescale 1ns / 1ns
module counter_4bit_tb (output reg clk_tb,rst_tb);
initial
begin
clk_tb=1'b0; //clock initialization
forever #10 clk_tb = ~clk_tb; //clock generator
end
initial //test stimulus
begin
rst_tb=1'b0;
#5 rst_tb = 1'b1;
#20 rst_tb = 1'b0;
#1000 $stop;
end
endmodule
//4 bit counter using TFF
module counter_4bit (output [3:0]count,input rst,clk);
TFF t0 (count[0],rst,clk);
TFF t1 (count[1],rst,count[0]);
endmodule
//TFF
module TFF (output reg q,input rst,clk);
always @ (negedge clk or posedge rst)
if (rst)
q<=4'b0;
else
q<=~q;
endmodule
89
//4 bit counter checker

module counter_4bit_ch (input [3:0]count_ch,input rst_ch,clk_ch);
reg [3:0]count;
//counter logic
always @ (negedge clk_ch, posedge rst_ch)
if (rst_ch)
count<=4'b0;
else count<=count+1;
//comparator logic
always @ (count_ch && ~clk_ch)
begin $display ($time,,,"count_ch = %h, count = %h", count_ch,count);
if (count_ch == count)
$display ("Pass");
else
$display ("Fail");
end
endmodule
90
Display results:
91
92
Exercise No. 27
Finite State Machines

Date:
Type: Finite State Machine
Aim : To design Sequence detector (101) with melay and moore method in behavior modeling
using verilog and verify the functionality .
Block diagram:
93
Verilog program:
//Sequence detector 101 with over lap
//moore machine
module sqn_dtr_moore(output reg out,input in,clk,rst);
parameter A=2'b00;
parameter B=2'b01;
parameter C=2'b10;
parameter D=2'b11;
reg [1:0]crnt_state;
reg [1:0]nxt_state;
always@(*)
case (crnt_state)
A:if(in)nxt_state=B;
else nxt_state=A;
B:if(in)nxt_state=B;
else nxt_state=C;
C:if(in)nxt_state=D;
else nxt_state=A;
D:if(in)nxt_state=B;
else nxt_state=C;
default:nxt_state=A;
endcase
if(rst)
crnt_state<=A;
else
crnt_state<=nxt_state;
always@(*)
case(crnt_state)
A:out=1'b0;
B:out=1'b0;
C:out=1'b0;
D:out=1'b1;
default:out=1'b0;
endcase
endmodule
94
//mealy machine
module sqn_dtr_mealy(output reg out,input in,clk,rst);
parameter A=2'b00;
parameter B=2'b01;
parameter C=2'b10;
reg [1:0]crnt_state;
reg [1:0]nxt_state;
always@(*)
case (crnt_state)
A:if(in)nxt_state=B;
else nxt_state=A;
B:if(in)nxt_state=B;
else nxt_state=C;
C:if(in)nxt_state=B;
else nxt_state=A;
default:nxt_state=A;
endcase
if(rst)
crnt_state<=A;
else
crnt_state<=nxt_state;
always@(*)
case(crnt_state)
A:out=1'b0;
B:out=1'b0;
C:if(in)out=1'b1;
else out=1'b0;
default:out=1'b0;
endcase
endmodule
95
Test wave form:

//Moore machine
//Mealy machine
96

Verilog Lab

Cargado por

Información del documento

Derechos de autor

Formatos disponibles

Compartir este documento

Compartir o incrustar documentos

Opciones para compartir

¿Le pareció útil este documento?

¿Este contenido es inapropiado?

Copyright:

Formatos disponibles

Verilog Lab

Cargado por

Copyright:

Formatos disponibles

Exercise No.

Test wave form:

Single bit full adder

//Full adder test bench

Test wave form:

Test wave form:

Test wave form:

Test wave form:

Test wave form:

Test wave form:

Test wave form:

Test wave form:

Test wave form:

Test wave form:

Arithmetic and Logic Unit

// ALU test bench

Test wave form:

Test wave form:

Test wave form:

//T flip flop

//T flip flop using D flip flop

//JK Flip flop

SISO Shift register

Test wave form:

Barrel shift register

Test wave form:

//Counter test bench

Test wave form:

Task and Function

Test wave form:

//Full adder using task

//Parity generator using functions

Universal Shift Register

//USR test bench

Test wave form:

N bit full adder

Test wave form:

User Defined Primitives

//UDP D flip flop

Test wave form:

//UDP T flip flop

4 bit counter using UDP

Test wave form:

Switch level modeling

//switch level xor

Test wave form:

//Switch level 2 to 1 mux

//Switch level d latch

Test wave form:

24 bit Efficient Carry look ahead adder

Test wave form:

Self checking test bench

//4 bit counter checker

Finite State Machines

Test wave form:

También podría gustarte