ECE480/580 Digital Systems Design

Lab 1: QUARTUS II VHDL Design and Simulation for

Combinational and Sequential Circuits

1. INTRODUCTION

In this lab you will use the QUARTUS II software package to design and simulate several simple
combinational and sequential logic circuits. The requirements for this lab consist of completing QUARTUS
II designs and printing the VHDL files, functional simulation results and completing the laboratory report.
All simulations should be done using the ModelSim-Altera Simulator. Before beginning the laboratory
designs, you should familiarize yourself with the simulation of VHDL designs using the ModelSim Graphical
Waveform Editor. The tutorial (ModelSim_GUI_Introduction.pdf) is available on the course website. A more
extensive discussion (Using_ModelSim.pdf) of simulation using the ModelSim simulator is provided in the
tutorial Using ModelSim to Simulate Logic Circuits for Altera Devices.

2. DESIGN

Implement the following circuits using VHDL. Provide a functional simulation for each design. Devise a set
of test vectors to verify each circuit. DE2-115 boards available for your use are located in SERC 2005.
Table 1 gives selected Cyclone IV EP4CE115F29C7 FPGA I/O pin assignments necessary for this lab.

Table 1. Selected DE2-115 Cyclone IV EP4CE115F29C7 FPGA I/O pin assignments.

Pin Name FPGA Pin Number Pin Name FPGA Pin Number
SW[0] PIN_AB28 KEY[0] PIN_M23
SW[1] PIN_AC28 KEY[1] PIN_M21
SW[2] PIN_AC27 KEY[2] PIN_N21
SW[3] PIN_AD27 KEY[3] PIN_R24
SW[4] PIN_AB27 LEDG[0] PIN_E21
SW[5] PIN_AC26 LEDG[1] PIN_E22
SW[6] PIN_AD26 LEDG[2] PIN_E25
SW[7] PIN_AB26 LEDG[3] PIN_E24
LEDR[0] PIN_G19 LEDG[4] PIN_H21
LEDR[1] PIN_F19 LEDG[5] PIN_G20
LEDR[2] PIN_E19 LEDG[6] PIN_G22
LEDR[3] PIN_F21 LEDG[7] PIN_G21
LEDR[4] PIN_F18 CLOCK_50 PIN_Y2
LEDR[5] PIN_E18
LEDR[6] PIN_J 19
LEDR[7] PIN_H19

A 4-bit comparator circuit that compares two 4-bit unsigned numbers A and B producing three
outputs AeqB, Al tB and AgtB.

o Design the comparator circuit using VHDL. There are numerous constructs in VHDL that
can be used to model this circuit. In addition to the constructs and operators discussed in
class, you may consider use of VHDL relational operators (<, <=, >, >=, =, and /=). See
the Quartus Help for more information.
o Perform a functional simulation of your design using the ModelSim simulator. Include a
printout of the simulation waveform in your lab report.
o Download your design to the Cyclone IV EP4CE115F29C7 device on the Altera
development board. Switches (SW[3]-SW[0]) should be used for the A input and switches
SW[7]-SW[4] should be used for the B input to the circuit. LED outputs LEDR[2]-LEDR[0]
should be used for the AltB, AeqB, and AgtB outputs respectively.

A 4-bit up/down counter

o Write a behavioral VHDL description for the design.
o Perform a functional simulation of your design using the ModelSim simulator. Include a
printout of the simulation waveform in your lab report.
o Download your designs to the Cyclone IV EP4CE115F29C7 device on the Altera
development board. Push button KEY[0] should be used as the clock input to the counter.
Push button KEY[1] should be used for the up/down count direction control input. If KEY[1]
is not pushed, the counter should count up. LED outputs LEDG[3]-LEDG[0] should be
used for the output.

A 32-bit up counter with enable

o Write a behavioral description for the design.
o Perform a functional simulation of your design using the ModelSim simulator. The
simulation should show a change in the least significant five bits of the counter. Include a
printout of the simulation waveform in your lab report.
o The upper four bits of the counter should be displayed on LED outputs LEDG[3]-LEDG[0].
Note the frequency at which each of these four bits changing and explain this behavior in
your lab report.
o Download your designs to the Cyclone IV EP4CE115F29C7 device on the Altera
development board. The 50 MHz clock (CLOCK_50) should be used as the clock input to
the counter. Push button KEY[0] should be used as the enable input. If KEY[0] is not
pushed, the counter should be enabled.

74164 Serial-In Parallel-Out Shift Register

o Write a behavioral VHDL description for this design. A datasheet for the 74164 device may
be located using an Internet search.
o Perform a functional simulation of your design using the ModelSim simulator. Include a
printout of the simulation waveform in your lab report.
o Download your design to the Cyclone IV EP4CE115F29C7 device on the Altera
development board. Push button KEY[0] should be used as the clock input to the shift
register. Choose appropriate bits for the remaining inputs for the 74164 device. Display the
eight data output bits on LED outputs LEDG[7]-LEDG[0].

(Required for ECE580, extra credit for ECE480) General FSM design

o Design an FSM that, upon device programming, will enter an initial (RESET) state. The
FSM should transition into a wait (WAIT) state upon first transition of the KEY[0]
pushbutton. The FSM should remain in the wait state until a 4-bit up counter reaches its
maximum count value. Push button KEY[1] should be used as the clock input to the
counter. The FSM should then transition to a ready (READY) state. After entering the ready
state, the FSM should function as the 74164 Serial-In Parallel-Out Shift Register previously
designed. Outputs from the shift register should be as in the previous design.
o Perform a functional simulation of your design using the ModelSim simulator. Include a
printout of the simulation waveform in your lab report.
o Download your design to the Cyclone IV EP4CE115F29C7 device on the Altera
development board and test.
Instructions for Preparing Laboratory Reports

1. Your lab report should consist of the following:

a) Cover Sheet
b) Abstract
f) Body of the Report (in appropriately named sections)
g) References
h) Appendices (lengthy code, multipage timing diagrams, etc.)

2. Cover Sheet: The cover sheet should follow the format of the sample cover sheet that is attached.
3. Abstract: The abstract is a brief (50-150 words) summary of your report. The project goals, major
results, and/or conclusions should be stated in the abstract. The abstract should occupy a single
page with the centered title, "ABSTRACT".
4. Body of the Report: The body of the report should begin with an INTRODUCTION and end with a
CONCLUSIONS section. The remainder of the report should be divided into several named
sections as appropriate. You should have sections titled according to what is described in that
section, e.g. Design of a 4-bit Comparator Circuit, Test of a 4-bit Comparator Circuit, etc. Note:
You should never have a section titled Body of the Report.
5. References: As appropriate, include a list of reference material used in preparing your report.
References should be listed in the order they were cited in the report and should be in standard
IEEE format (see the IEEE Information for Authors document on the course website). The
Preparation of Papers for IEEE TRANSACTIONS and JOURNALS document on the course website
also provides good examples. The references should occupy a one or more separate pages with
the centered title "REFERENCES". References that do not follow these conventions will be
graded as compl etel y incorrect.
6. Appendi ces: Diagrams, programs, tabular data, etc. may be included as appendices or may be
contained within the body of the report. Any data that spans more than one page should be
included in an appendix. Construct multiple, titled and lettered appendices as appropriate, e.g.
Appendix A VHDL Code for a 4-bit Comparator, Appendix B Timing diagram for a 4-bit up/down
counter, etc.
7. Figures: Figures should be legible and have an appropriate figure number and caption. Logic
diagrams and timing diagrams may be screen captured and imported as figures where appropriate.
Logic and/or timing diagrams may appear in landscape mode to enhance readability. All information
in logic diagrams and timing diagrams should be labeled appropriately. The IEEE Information for
Authors document on the course website is the source for describing proper formatting and
referencing of figures. Figures that do not follow these conventions or are unreadable will be
graded as compl etel y incorrect.
8. VHDL Source Code: All VHDL source code must follow coding conventions presented in class.
Code that does not follow these conventions will be graded as completel y incorrect.
9. Timing diagrams: Remember, timing diagrams are meant to convey information to your reader about
the functionality of a given design. Related signals should be grouped together to enhance
readability. For example, cl ock and clock rel ated signals should be grouped together and placed
at the top of the timing diagram. Controls signals should also be grouped together with the data
signals they control. Timing diagrams should be sized so that it is easy to read appropriate
information from the timing diagram. Long timing diagrams should be split into multiple figures as
appropriate. Timing diagrams that do not follow these conventions or are unreadable will be
graded as compl etel y incorrect.
10. All pages are to be numbered with the exception of the cover sheet and abstract page.
11. All reports must be typed and printed on a quality printer.
12. All reports should be stapled or placed in a binder and not folded when submitted.
13. All reports should be free of grammatical and typographical errors. Use an appropriate word
processor with spell and grammar check capabilities.
14. All reports are to be double-spaced with appropriate margins (one inch on all sides).



Title








First Laboratory Report for ECE481
Digital Systems Design








Submitted by

Name
Student number







Department of Electrical & Computer Engineering
The University of Alabama
Tuscaloosa, Alabama 35487







Date