Full Custom Design With Cadence and Ams Hit-Kit

https://www.microlab.ti.bfh.
ch/wiki/huce:microlab:tutorials:soc:cadence:introduction_tutorial
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Full Custom Design with Cadence and AMS HIT-Kit
Author: Michael Nydegger (HuCE-microLab)
The following Cadence tutorial is based on the Full-Custom Design with Cadence Tutorial from the Instituto Superior Tcnico. Some
parts of the original tutorial were changed to fit the Cadence IC version used in our institute.
Introduction
This tutorial aims to introduce Cadence Virtuoso by building a CMOS inverter. It covers the schematic creation, the layout design
according to the process specific rules and the simulation of the schematic and the layout extracted parasitic resistances and
capacitances.
Starting Cadence
Cadence IC Package runs on the HuCE microLab server triton.bfh.ch. Connection can be established with the following command:
ssh -Y triton.bfh.ch
Before you start Cadence you have to change to your desired project directory. For this tutorial you have to create a new project
directory (e.g. ~/VirtuosoTutorials/cds_tutorial):
mkdir -p ~/VirtuosoTutorials/cds_tutorial
cd ~/VirtuosoTutorials/cds_tutorial
Now start the IC development environment for the AMS 0.35um process with the following command:
icenv_ams35
Start Cadence Virtuoso with the AMS HIT-Kit (C35B):
cadence&
If you start cadence in an empty directory, it creates a new project. Select the ic process in the appearing process option menu (the
process were going to use in this tutorial is called C35B3C3 and is a 0.35um process with three metal layers):
https://www.microlab.ti.bfh.ch/wiki/huce:microlab:tutorials:soc:cadence:introduction_tutorial
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Main window and library manager
If you have started Cadence you will see the Virtuoso main window. Here you can launch the different Cadence tools and make essential
settings. Since you started Cadence with the AMS HIT-Kit, everything should already be configured. One important component is the log
file. Here you can see errors or warnings which occured during your work with Virtuoso.
Next we need to start the library manager by selecting
Tools - Library Manager
in the Virtuoso main window. The library manager lets you organize your project and browse the already installed default libraries.
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Creating the Schematic
Creating a library and a schematic cell view
At first, a new library that will contain the data for the implemented cell must be created. From the menu bar of the Library Manager
select
File - New - Library
and enter a name for the new library, e.g. STUDENTS. In the next window we choose to attach the library to an existing technology
library. After pressing OK the technology library can be selected: Set Technology Library to TECH_C35B3 and press OK.
Now we can start to create the schematic of our cell. Select the newly made library and choose
File - New - Cell View
from the menu bar of the Library Manager. Enter a name for the cell in the appearing form (e.g. inverter1) and check whether the correct
options are selected: Library Name must be set to STUDENTS, View Name must be set to schematic and Open with must be set to
Schematics L in order to start the schematic editor. After pressing OK the schematic editor should start automatically (if a window Next
License appears, just click yes).
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Drawing the schematic
The following schematic for a CMOS inverter has now to be entered into the Schematic Composer:
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Before adding instances or wires in the inverter schematic, briefly read the Miscellaneous part below this section.
Adding the MOS transistors
First, add the pMOS and nMOS transistors. Select from the Composer menu bar
Create - Instance (or use the shortcut )
Fill out the form by hand or press the Browse button to search the libraries for the appropriate cell. The MOS transistors are in the
library PRIMLIB and are called pmos4 and nmos4 respectively. To place them in a schematic the selected View must be symbol. After
choosing the right cell, parameters of the cell can be set in the form. Change the default values of the transistor width (wpmos = 4 m
and wnmos = 1 m) and place each symbol in the schematic using the left mouse button.
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To hide the Add Instance form during placing press the Hide button. To rotate the cell press <r>, to flip the cell vertical press <shift+r>, to
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flip the cell horizontal press <cntrl+r>.
Placing VDD and GND supply
Add instances of vdd and gnd supply cells which can be found in the library analogLib.
Adding input and output pins
To add input and output pins select
Create - Pin (shortcut )
from the menu bar and fill out the appearing form. Give a list of Pin Names separated by spaces, e.g. IN OUT, and select the direction of
the first pin in the list (IN is an input pin). Now place the first pin. To hide the Add Pin form, press the Hide button. After placing the
first pin its name is automatically deleted from the Pin Names list and the next pin direction can be changed and the pin placed. Place
the input pin IN and the output pin OUT.
Adding wires and wire names
To add wires select
Create - Wire (narrow) (shortcut <w>)
from the menu bar and place wires by clicking on the begin and end point of a wire. Connect the objects via their connection ports.
If the mouse pointer is moved near to a connection port and the port is marked with the diamond symbol the wire can be
quick-connected to that port by pressing <s>.
Don't forget to connect the bulk-ports of the pMOS transistors with VDD and the bulk- ports of the nMOS transistors with GND!
To name a wire select
Create - Wire Name (shortcut <l>)
and fill in a list of wire Names in the appearing form. To hide the Add Wire Name form during naming press the Hide button. Add the
wire names in the order as they appear on the Names list by clicking the appropriate wire. Note that wires given the same name are
connected implicitly. The wires connected to the vdd cell are automatically named vdd! and the wires connected to the cell gnd are
automatically named gnd!.
Miscellaneous
To zoom in on the schematic right click and draw the rectangle.
To fit the schematic window to the current design select Window - Fit (shortcut <f>).
To move an object: Select the object and move the mouse pointer over it until the pointer changes to a move-object symbol. Press the
left mouse button and move the object.
To move an object: Select Edit - Move (shortcut <shift+M>) from the menu bar and select the object to move.
To edit cell instance properties select the cell and choose Edit - Properties - Objects (shortcut <q>) from the menu bar.
In the Schematic Editor window you can see which command is currently activated and how many instances are currently selected. In
the lower status bar you can see the current actions assigned to the mouse buttons according to the currently activated command.
Multiple objects can be selected by: Holding down the <shift> key and selecting the objects.
Multiple objects can be selected by: Draging a box around them with the mouse pointer while pressing the left mouse button.
Creating the Symbol
Creating a symbol of the cell is necessary if the cell should be instantiated in another schematic (i.e. the simulation schematic). The
symbol defines the shape your cell will take in another schematic.
To create the symbol, open the cell schematic in the Virtuoso Composer and select
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Create - Cellview - From Cellview
and check whether the appearing form is filled in correctly: The View Name must be set to symbol and Tool / Data Type must be set to
schematicSymbol. After hitting OK the form Symbol Generation Options appears where the initial positions of the pins can be chosen.
Press OK after assigning the pins to the desired lists.
The Virtuoso Symbol Editor will open and a default symbol will be created for the cell. Now the symbol can be edited. You can leave the
symbol as it is by default or you can try to draw an inverter like the one shown below:
After finishing the design of the symbol check and save it with: File - Check and Save.
Schematic Simulation
Creating a test bench (schematic for simulation)
The first step to simulate the inverter is to create a test-bench as a schematic with the new inverter1 (symbol) as unit-under-test (UUT) -
similar as you always did in the digital world using VHDL. This procedure is best-practice, as you strictly seperate the circuitry to be
integrated into an ASIC and the test environment, which will be composed of laboratory equipment and not be realized into the ASIC.
To create a schematic refer to the section Creating the Schematic. The schematic of the test bench must be created in the library
STUDENTS and the cell should be named tb_inverter1.
The inverter gate in the simulation schematic is of course the cell inverter1 from the library STUDENTS.
Add a instance () of a DC voltage source between vdd and gnd. Use the cell vdc from the library analogLib and set the parameter DC
Voltage to vdd_val V. By connecting this voltage source to the cells vdd and gnd, from the library analogLib, you are defining vdd and
gnd for all the cells that use these labels.
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In order to generate the input signal for the simulation use a voltage source of type vpulse (rectangular signal) from the library
analogLib. Define the voltage source with the following parameters:
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We also have to name the input wire (e.g. IN) and the output wire (e.g. OUT) so that we can select them during simulation and plot their
voltage curves.
Add a capacitor (cap) of 1pF to the output pin from the library analogLib.
You should end up with the following test bench:
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Don't forget to do the Check and Save.
Simulating the schematic
After creating the simulation schematic you are ready to simulate the inverter gate. Select from the Schematic window of the simulation
schematic
Launch - ADE L
The following settings have to be made:
Setup - Simulator/Directory/Host
- Set Simulator to spectre
- Also the Project Directory could be changed here
Setup - Temperature - Set Degrees to 25
Setup - Environment
- Switch View List should be set to spectre cmos_sch schematic
- Stop View List should be set to spectre ahdl
Analyses - Choose
- Set Analysis to tran
- Set Stop Time to 200n
- Accuracy Defaults should be set to conservative
Variables - Copy From Cellview
- Variables in the simulation schematic will be identified and will be listed in the field
Design Variables of the Virtuoso Analog Environment tool
- To edit the Design Variables entries either double-click on an entry or select
Variables - Edit from the menu bar
- Set vdd_val to 3.3V
Outputs - To Be Plotted - Select On Schematic
- Select the signals to be ploted in the simulation schematic: net (must be named!) =>
voltage; object node => current into the object through this node
- Selected signals will be listed in the field Outputs of the Virtuoso Analog Environment
tool
- To edit the Outputs entries either double-click on an entry or select Outputs - Setup
from the menu bar
After configuring the simulator it should look like this
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To build the netlist and run the simulation select
Simulation - Netlist and Run
First the simulator output log window appears and shows the simulation progress. After the simulation has finished the waveform
window appears and the selected signals are plotted.
Expressions
It is possible to enter expressions in the field Outputs of the Virtuoso Analog Design Environment to calculate parameters of the cell
(propagation delay, output slew, ) from the simulation results directly or to plot modified signal curves.
Select Outputs - Setup from the menu bar of the Virtuoso Analog Environment and add the following expression:
Name = propagation delay
Expression:
delay(v("/IN" ?result "tran") 1.65 1 "rising" v("/OUT" ?result "tran") 1.65 1 "falling")
The expression propagation delay gives the propagation delay of the gate when the input value changes from IN = 0 to IN = 1.
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After plotting the expression with Results - Plot Outputs - Expressions the result of the expression for the propagation delay is displayed
in the field Outputs of the Virtuoso Analog Design Environment.
Parametric analysis
It is very important to evaluate the circuit behaviour with different temperatures, supply voltages and technological parameters.
Parametric analysis is used in this tutorial to sweep the temperature. In the Virtuoso Analog Environment select
Tools Parametric Analysis
Set the sweep according to the following figure
Start the analysis with
Analysis - Start All
Have a look at the influence of the temperature variation influence: what do you observe? Close the simulation windows.
Creating the Layout
Starting the layout tool
Open the schematic view of the inverter1 cell (you can also double click into your inverter1 symbol at your test-bench) and select
Launch - Layout XL
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from the menu bar. Selecting this option will first open a small dialog box that will let the user create a new layout or open an existing
one. We opt for Create New. The next dialog gives us the possibility to change the properties of the new cellview. Check whether the
Name and the Type fields are set to layout. After pressing OK the Virtuoso Layout XL Editor will start.
Layer Selection Window (LSW)
The layer selection window (LSW) is located on the left boarder of the editor window. Each LSW entry is divided in three categories
which are color, abbreviated name and purpose. Color shows the appearance of the layer in the layout. The abbreviation is the official
name of the layer for Virtuoso, it can appear in messages, etc.
The Layer Selection Window is used to select the active layer (left mouse-button), to set whether a layer is selectable or not (right
mouse-button) and to set whether a layer is visible or not (middle mouse-button). After the visibility status of a layer has been changed
press the <F6> key to refresh the screen.
Each layer appears in the LSW window with purpose drawing and pin, you will almost always need drawing.
Initialize the layout
To initialize the layout according to the schematic (i/o pins, device instances, ) select
Connectivity - Generate - All From Source
in the Virtuoso Layout XL Editor menu bar. Fill out the appearing form to set some properties of the components in the layout: set the
boundary width to 3 m and the boundary height to 13 m. Check the I/O Pins - Create Label As box and enter the Pin Label Options
dialogue window. Set the Layer Name to PIN and Layer Purpose to metal1.
The Configuration is shown below:
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After hitting OK the Virtuoso Layout XL Editor creates the chosen components in the layout window.
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Settings for the Virtuoso Layout XL Editor
Select Options - Display and, in the new opened window, assign X Snap Spacing and Y Snap Spacing to 0.025, and Display Levels: From
= 0, To = 2. Click ok. As you have choosen a deeper Display Level, you should now see all layers of the two transistors and not just a
bounding box as before.
Useful commands are:
command menu bar command shortcut
save the layout File - Save <F2>
fit complete layout in the layout window View - Zoom To Fit All <f>
redraw layout window View - Redraw <ctrl+r>
create ruler Tools - Create Ruler <k>
delete all rulers Tools - Clear All Rulers <shift+k>
undo last action Edit - Undo 
move object Edit - Move <m>
stretch object Edit - Stretch <s>
delete object Edit - Delete <DEL>
edit object properties Edit - Basic - Properties <q>
terminate any command <ESC>
Layout creation - placing the components
A first placement iteration can be obtained by selecting
Connectivity Generate Place as in Schematic
In more complex cells, the commands Connectivity Nets Show/Hide all incomplete nets may be of interest.
When a pin or MOS transistor is selected in the Layout Window, the corresponding device is also highlighted in the Schematic Window.
This works also when a component is selected in the Schematic Window.
When the Drain or Source contacts of two similar transistors are connected directly, Virtuoso XL will chain these transistors
automatically after shifting the according areas over each other. Furthermore Virtuoso XL determines the necessity for an additional
connection to this area.
To rotate a transistor select the command Edit - Move, select the transistor you want to rotate and press the middle mouse button.
While a command is activated its detailed behavior can be customized by pressing the <F3> key (e.g. set snap mode).
Very useful is Virtuoso XL's status bar just above the menu bar:
X: and Y: indicate the actual mouse pointer's position.
The letter enclosed by parenthesis indicates whether partial selection mode (P) or full selection mode (F) is activated. Toggle
between these two settings by pressing <F4>.
The Select: entry shows how many objects are currently selected.
When moving components, dX:, dY: and Dist: show the difference between starting point and end point.
In the Cmd: field one can determine the currently active command.
Also very useful is the mouse function indicator at the bottom of the Layout Window. There the currently assigned functions to the
mouse buttons according to the active command are indicated.
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Gnd and vdd rectangles
Zoom in the bottom of the prBoundary (light blue rectangle).
Select the layer metal 1(MET1) of type drawing (drawing), clicking in the corresponding layer in the LSW.
Draw a ruler (<k>) from coordinates (0, 0) to (0, 1.8). The ruler is probably not yet forced to the grid you have defined. You can do it by
right-click (when the ruler is active) and in the new window choose Center Line.
Starting at coordinates (0, 0), draw a rectangle (<r>) of metal 1 with the total width of the prBoundary (that will be the limit of the cell)
and 1.8 m of height:
Copy this metal 1 rectangle to the top of the prBoundary box (for vdd usage).
Place the gnd pin and label over the metal 1 rectangle in the bottom of the cell. The vdd pin and label should be placed over the metal 1
rectangle in the top of the cell. The following picture shows the placed power pins:
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For simulation purpose, the pin can be placed anywhere. If the cell would be used in an automatic placement and routing process, two
rectangles of metal 1 of type pin should be overlapped to the metal 1 drawing, at each access of the ground rectangle. Each metal 1 pin
rectangle points to an access to the net and therefore its properties must include the directions from where the access is allowed.
The placement of the global pins gnd! and vdd! needs some additional setting. Their properties have to be edited. After selecting them
and pressing <q> the Edit Instance Properties dialog box opens. Here Connectivity has to be checked. Terminal Name is displayed (gnd!
or vdd!). Net Expression Property and its Default value has to be defined as gnd and gnd! as well as vdd and vdd! respectively. If this
property is missing then everything will run correctly with the only exception of the simulation of the extracted netlist. The LVS will not
be influenced, but the simulator will not be able to connect the power supply to the power rails of the layout and, therefore, the circuit
will not function at all.
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Placing the transistors
Place the pmos and nmos according to the following picture by moving and rotating. The source of both mosfets should be located on
the right.
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Use the ruler <k> to align and center the mosfets.
Show incomplete nets to identify the transistors sources (Connectivity Nets Show/Hide All Incomplete Nets)
When drawing layout, always use a large zoom-in in order to draw and place layers precisely.
Substrate and n-well connection
In order to connect the ground metal 1 rectangle to the substrate a contact can be automatically generated selecting:
Create Via
and selecting PD_C (Via Definition, see table below for explanation). Place the bottom-left corner of the contact at coordinates (0, 0).
This contact includes the active area (diff), p+select (pplus), metal 1 (met1), and the contact (cont). It performs a good ohmic contact
between metal 1 and the substrate.
In order to connect the n-well to vdd, the n-well included in the pmos transistor must be extended to include the vdd line. Select the
layer NTUB of type drawing and draw a rectangle starting from the top of the pmos n-well and ending 0.9 m above the vdd line.
Similarly to the gnd contact to substrate, select the ND_C and place the top-left corner of the contact at coordinates (0, 13). This contact
includes the active area (diff), n+select (nplus), metal 1 (met1), and the contact (cont). It performs a good ohmic contact between metal
1 and n-well.
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Possible via types:
Via Definition Connects ... ... with
PD_C PPLUS MET1
ND_C NPLUS MET1
P2_C POLY2 MET1
P1_C POLY1 MET1
VIA1_C MET1 MET2
VIA2_C MET2 MET3
Routing between the components
The next step in layout creation is to connect the components electrically according to the schematic. Connections can be drawn in
three different ways:
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type of connection menu bar command shortcut
rectangle Create - Shape - Rectangle <r>
polygon Create - Shape - Polygon <Shift+p>
path Create - Shape - Path 
Before activating a command select the desired layer in the Layer Selection Window (LSW)!
When the path command is activated and the path has been started at an identifiable connection Virtuoso XL highlights the geometries
and terminals of other components which should be connected. To change the path options use the menu invoked by pressing <F3>.
Inter-layer contacts can be created explicitly through Create - Via (shortcut <o>). To establish a connection between the metal layer 2
and the poly layer 1, for example, two of these contacts have to be placed: MET2 MET1 (VIA1_C) and MET1 POLY1 (P1_C). They can
be placed right over each other.
The following figure shows the gates and drains interconnections and the OUT pin placement over the corresponding metal 1
connection. For the input pin a poly-metal 1 via that allows connectivity in metal 1 has been placed (Create Via P1_C).
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The sources of the transistors must be connected to vdd! and gnd!.
The IN pin and label must be moved to the top of the metal 1 connected to the inverter input (overlapping the P1_C via)
The P1_C via must be placed as shown in the picture to avoid metal 1 clearance problems between the IN and OUT pin.
Design-Rule-Check (DRC)
The layout of a cell must be drawn according to a set of strict design rules. During the Design-Rule-Check a program checks the design
against the design rules and reports any violations.
Starting DRC
To start the DRC for the layout select
Assura - Run DRC
from the menu bar of the Virtuoso Layout XL Editor. In the appearing form, the DRC can be parameterized. Set the no_coverage switch
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in the Set Switches Dialog shown in the following picture (this check only makes sense for a full chip DRC). There is no need to change
any other settings.
After hitting OK the DRC is carried out you will be asked if you want to see the results - click Yes. The VLW and the Error Layer
Window will open.
Processing DRC errors
The Error Layer Window shows a list of all the design rule violations in the layout and is shown in the following image:
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In this example there are four messages, a minimum spacing violation, two generated layer notifications and a notification about the
DRC check itself. The Generated Layers notification means that Assura has automatically created a layer which is required for
fabrication. The number in square brackets (in front of the rule name) shows how often the error exists in the layout.
The only real DRC error in this example is the spacing violation on metal 1. To locate the problem on the layout, click on the error in the
left window panel and change between the different locations where the error occurs by clicking on the right or left arrow button
located in the right half of the window. The spacing problem in this example can easily be solved by moving the input pad and via away
from the metal 1 path of the output pin.
Layout-versus-Schematic Check (LVS Check)
After the mask layout design of the cell is completed, it should be checked against the schematic of the cell created earlier. The
Layout-versus-Schematic check (LVS check) will compare the circuit given by the schematic with that one extracted from the mask
layout and tries to prove that both networks are equivalent.
The LVS step provides an additional level of confidence for the integrity of the design and ensures that the mask layout is a correct
realization of the intended circuit.
The LVS check only guarantees topological match: A successful LVS check will not guarantee that the mask layout of the cell will
actually satisfy the performance requirements.
Any errors that may show up during the LVS check (such as unintended connections between transistors, missing connections/devices,
) should be corrected in the mask layout. Note that the extraction step must be repeated every time the layout of the cell is modified.
Starting LVS checking
To start the LVS check select
Assura - LVS
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from the menu bar of the Virtuoso Layout Editor. In the appearing form, the options for the LVS check can be set: It can be specified
which cell views should be compared and where to find the LVS rules file. There should be no need to change the default settings which
are given in the following picture.
The LVS check can be started by clicking OK. At the end of the check, a summary of the results will appear. If the layout and the design
match, there should be no error and the values in the summary should be 0.
In case of an error: First check that all the connections are drawn and that there are no gaps between adjacent polygons on the MET1
and the POLY1 layers.
Extraction
Circuit extraction is performed after the mask layout design of the cell is completed. It creates a detailed netlist (extracted netlist) of
the cell which includes the parasitic elements introduced by the cells layout. The circuit extractor is capable of identifying the
individual transistors and their interconnections as well as the parasitic resistances and capacitances that are inevitably present in the
cell. Thus, the extracted netlist provides a very accurate model of the cell.
Prepare extraction
Before the extraction can be done, we need to rerun the LVS check to generate additional connectivity information of the layout. The
LVS check can be done like before but this time with a additional switch called resimulate_extracted. The settings for LVS are given in
the following picture:
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After the LVS check there should be no new errors in the design.
If Assura asks about existing files or LVS checks which are already running, just click on Yes/OK.
Starting extraction
To start the extraction select
Assura - Run QRC
from the menu bar of the Virtuoso Layout XL Editor. In the appearing form, the options for the extractor can be given. Set the following
options:
panel option set to comment
Setup View extracted name of extracted view
Setup Extract MOS Diffusion Res enabled
Extraction Extraction Type RC extract both parasitic R and C
Extraction Cap Coupling Mode Coupled
Extraction Ref Node gnd! define the name of the reference node (common ground)
Netlisting Auto Substrate Stamping Off disabled
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After hitting OK the extraction is carried out and a new view called extracted is generated for the cell (Library Manager).
Post-Layout Simulation
It is now easy to simulate the layout (more exactly the extracted netlist) with the Virtuoso Analog Circuit Design Environment. Close the
layout editor window and open the test bench for the simulation of the cell schematic (section Schematic Simulation). The same test
bench can be used for the extracted simulation. Open the test bench schematic and select
Launch - ADE L
Configure the simulation conditions as described in section Schematic Simulation and choose:
Setup - Environment
and set Switch View List to spectre cmos_sch extracted schematic. As a result of this, if the simulator now creates the netlist of the
simulated circuit it uses the extracted netlist of the cell rather than the schematic.
As in the first simulation, measure the delay time. Probably you will not see much difference as some conditions are set to an
unrealistic extreme - think why and re-simulate the circuit. What is the difference you can see between the two simulations: schematic
and post-layout. Quantify it.
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