Bonfring International Journal of Power Systems and Integrated Circuits, Vol. 2, No.

3, September 2012 10
ISSN 2277-5072 | 2012 Bonfring
Abstract--- This paper presents how to generate high
frequency quadrature sinewave signals by selection topology
and its active and passive components. Also, presents how to
choose the value of inductor by different ways followed by
performance comparison of various VCO topologies. The
overall performance is displayed by all-pMOS VCO in terms
of supply voltage and tuning range. The performance
comparison of all-pMOS LC-VCO using various capacitive
loads is discussed. All-pMOS LC-VCO with MOS capacitor
switched capacitor array (SCA) followed by divider using
CML latch without fixed tail current source is used for
generation of high linearity quadrature signals. A three
2.4/4.8 GHz CMOS Quadrature Voltage Controlled
Oscillators (QVCOs) tuned by a diode varactor, inversion-
mode pMOS varactor and an accumulation-mode nMOS
varactor, respectively. The performance comparison of
different varactors QVCO is simulated in terms of frequency
range, tuning range, harmonic distortion and power
consumption. The overall performance is displayed by
inversion mode pMOS varactor QVCO. However, all the
performances of varactor QVCOs are significantly closer
with all-pMOS LC VCO compared with other VCO topologies
like all-nMOS LC-VCO and complementary cross coupled LC-
VCO, due to low dc impedance path between the varactor to
ground terminal. It displayed the power consumption of all
varactor QVCOs are equal. The QVCOs were implemented
in a 0.18 m standard CMOS technology as the supply voltage
is 1 V. The pre and post layout simulation results are
compared in terms of tuning range, phase noise, power
dissipation, and harmonic distortion, self oscillation frequency
of divider and reference voltage of inversion mode pMOS
varctor QVCO.
Keywords--- VCO Topologies, S-parameter, Inductor,
MOS Capacitor SCA, Poly Capacitor SCA, Types of
Varactors, CML Divider, CML Buffer

I. INTRODUCTION
HE VCO is one of the major critical blocks in RF
transceiver and it will limit the overall performance of
transceiver in terms of power consumption and phase noise.

P. Arivazhagan, Master of Science, Department of Electrical and

Electronics Communication Engineering, Indian Institute of Technology,
Kharagpur, West Bengal, India. E-mail: arivazhaganiitkgp@gmail.com
TarunKanti Bhattacharyya, Associate Professor, Department of
Electrical and Electronics Communication Engineering, Indian Institute of
Technology, Kharagpur, West Bengal, India. E-mail: tkb@ece.iitkgp.ernet.in

DOI: 10.9756/BIJPSIC.2015
Each wireless standard has different specification to design a
VCO, including phase noise and tuning range. In addition,
VCO needs to generate quadrature signals, since transceivers
are highly integrated architectures [1], such as direct
conversion and low-IF. Quadrature signals are generated by
all-pMOS LC-VCO with either poly (or) MOS capacitor SCA
followed by divider using current mode logic latches without
fixed current source. As, this topology occupies low area and
fabrication cost than other [2], as it suitable in todays wireless
communications. Performance [2] using different varactors are
compared [3] and tabulated. This work further improvement
changes in design level, replacing source degeneration resistor
in CML Latch into conventional CML latch QVCO.The
designing of QVCO should meet overall standard
specifications in terms of power and phase noise, as this
applicable for 2.4 GHz short range wireless transceivers like
ZigBee, Bluetooth, WLAN etc., This work presents a CMOS
QVCO tuned by a reverse biased diode varactor, pMOS
capacitor working in the depletion and inversion regions,
nMOS capacitor working in the accumulation and depletions
regions and shows the overall performance comparison in
terms of phase noise, frequency range, harmonic distortion
and tuning range.
The section 2 describes the diode acts as capacitance by
varying the reverse bias voltage. The section 3 describes about
MOS varactor operating in different regions whereas section 4
describes about 2.4 GHz QVCO design includes VCO
generates at 4.8 GHz with various loads followed by divider.
Section 5 describes about performance comparison of different
varactors followed by pre and post layout results discussed in
section 6.
II. DIODE VARACTOR
A reverse biased diode used as a capacitor [4] and its
simplified electrical model are shown in [5]. This simplified
model considers the parasitic resistance in series with the
capacitance. The capacitance C
j
is the reverse p-n junction
capacitance, R
s
is the series parasitic resistance [6] and R
par
is
the parallel resistance due to substrate losses as shown in Fig.
1. The capacitance can be varied because C
j
has a dependence
on the reverse bias voltage V
rev
(i.e., potential difference
between V
out1
and V
ctr
) of the p-n junction given by equation
1. Any one node behaves like variable voltage with respect to
reference voltage, hence in our design V
ctr
acts as variable
than fixed V
out1
.Therefore, V
ctr
is equal to V
rev
. Equation 1
shows,

m
ctr
j j
V V
V
C C

+
=
0
0
0
(1)
Quadrature Sine Wave Signals Generated by
Selection Topology and its Components
P. Arivazhagan and Tarun Kanti Bhattacharyya


T
Bonfring International Journal of Power Systems and Integrated Circuits, Vol. 2, No. 3, September 2012 11
ISSN 2277-5072 | 2012 Bonfring


A. Derivations of Quality Factor of Diode Varactor
Figure 1 shows the conversion from parallel RC network
into series RC network to find the quality factor of the diode
varactor. The quality factor of series RC network [1],
V
1
o
u
t
R
s
R
par
C
j
V
c
t
r
V
1
o
u
t
R
s
R
C
j
V
c
t
r
s1
V
1
o
u
t
R
C
j
V
c
t
r
equ.

Figure 1: Conversion from Parallel RC Network into Series
RC Network


.
1
equ j
j C
R C
Q

=
(2)
Where,

( )
( )
2
2
. Re
par j
par par s j s
R C
R R R C R
qu

+ +
=
(3)

Substitute equation (3) in equation (2),

s j
cj
R C
Q

(4)
Equation (4), is the approximately quality factor of diode
varactor operating under reverse bias condition.
III. MOS VARACTOR
MOS acts as a capacitor when its drain, source and bulk
(D, S, B) are connected together to form one capacitor
terminals, and the polysilicon gate forms the other capacitor
terminal as shown in Fig. 2 (a). The capacitance varies
depending on the potential difference between the bulk and the
gate V
BG
(i.e., potential difference between the V
out1
and V
ctr
))
and the operating region in which the MOS structure stays as
shown in Fig. 3. The variation is non-monotonic as the device
goes from the accumulation region to the inversion region
through the depletion region. Two ways to make the variation
monotonic are to force the device operate in either the
accumulation region or in the inversion region. In order to
make accumulation mode MOS capacitor (A-MOS), in a
standard pMOS transistor, the p+ diffusions of the drain and
source are replaced with n+ regions [8]. This suppresses the
injection of minority carriers (holes) into the channel and
prevents inversion. The device stays always in accumulation
region, which can be used to give highly nonlinear and
monotonic capacitance. This structure has high C
max
/ C
min

ratio, which can be used to achieve a high tuning range. Low
parasitic resistance (high Q) gives low phase noise
performance and furthermore as change in capacitance is less
steep, K
VCO
is low. Hence, this type of structure is generally
preferred to achieve a low phase noise and high tuning range
performance.
But due to lack of A-pMOS model support in authors
laboratory, inversion mode structure has been chosen in the
present design. PMOS based inversion mode (I-pMOS)
structure as shown in Fig. 2 (b) is used because it has low 1/f
noise and has a higher tuning range than an nMOS based
accumulation structure shown in Fig. 2 (c).

Figure 2: Schematic of (a) MOS Varactor. (b) I-pMOS
Varactor. (c) A-nMOS Varactor

Figure 3: Capacitance per Unit Area C gb Versus VBG
IV. 2.4 GHZ QVCO DESIGN
The design of 2.4 GHz QVCO is used for generation of
high linearity quadrature sinewave signals by combination of
VCO with various capacitive loads followed by CML divider
without fixed tail current source.

Figure 4: Asymmetric Structure of Spiral Inductor
A. Choose the Inductor Size
Bonfring International Journal of Power Systems and Integrated Circuits, Vol. 2, No. 3, September 2012 12
ISSN 2277-5072 | 2012 Bonfring
Before, going into actual transistor level design, first
choose the inductor value at 4.8 GHz from the given S-
parameters [9]. The modeled six parameter values shown in
Figure 4 using MATLAB is not fit our design considering in
terms of area, parasitic capacitance, which affects the
operating frequency and supply voltage. Another choice to
find the values using ASITIC (circuit simulator) [10] (or)
based on your assumption by the value of quality factor
(standard). Spiral inductor is suitable in todays applications
like On-chip, as it occupy low area. The quality factor of these
inductor around 5 ~10 is low compared with others like
bondwire etc., It affects the phase noise, but while considering
in 2.4 GHz short range applications phase noise is not major
issue than cost and power. Assume Q and inductor values at
4.8 GHz to find the parasitic series resistance of inductor by
Equation 5. Finally, square

s
s
L
R
L
Q

(5)
(or) octagonal type spiral inductor is used, which is best
suited for on-chip solutions related with quality factor. The
value of each inductor is 1 nH. The parasitic resistance of the
spiral inductor was found approximately 4.5 ohm providing a
(Q) value of 6.7 at 4.8 GHz estimated using ASITIC. With
this inductance value, the total capacitance on each node must
be approx. 1.1 pF to obtain a 4.8 GHz oscillation frequency.
B. Performance Comparison of Different VCO Topologies
Three different topologies of LC-VCO based on
complementary cross-coupled (VCO_CC), all-nMOS and all-
pMOS transistors are shown in Figure 5 (b) and Figure 5 (c)
respectively. These topologies are compared for their
performance characteristics in terms of phase noise, supply
voltage and tuning range to choose the appropriate VCO
topology for designing a power-efficient low noise QVCO.
Phase Noise
The topology based on all-pMOS transistors shows better
phase noise performance compared to all nMOS transistors.


Vdd
Vctr
M M
M
M
2
4 3
0 180
M
M 1
2
L R
S
Vctr
M
M
6
5
M
4 M
3
Vdd
Vctr
M
M
4 3
M
2
M
1
Vdd
180
180
0
0
I
bias
I
bias
I
bias
1
C
s1
s2
C
R
s1
s2
R
s R
s
2
R
s
2
L
s
2
L
s
2 C
s1
R
s1
C
s2
R
s2
C
s1
R
s1
C
s2
R
s2 R
s
2
L
s
2
R
s
2
L
s
2
V
out1
V
out1
V
out1
V
out2
V
out2
V
out2

(a) VCO_CC (b) All-nMOS VCO (c) All-pMOS LC-VCO
Figure 5: Different Types of LC-VCOs Using On-Chip Spiral Inductor (Six Parameter Model)

In a typical 0.18 m digital CMOS technology pMOS
transistors have approximately 10 dB lower 1/f noise
compared to that for nMOS transistors [7]. This is because
pMOS transistors have buried channel whereas, nMOS
transistors have surface channel. Moreover, PMOS transistors
have lower drain current thermal noise compared to nMOS
transistors. Thus, pMOS VCOs (replace the bias current into
pMOS tail current source) gives better phase noise
performance than nMOS VCOs in deep-submicron CMOS
technologies. Also, noise fluctuations on the varactor terminal
at node V
out1,2
, affects varactor gain due to fluctuations in I
bias

in both VCO_CC and all-nMOS VCO than all-pMOS VCO.
Because, low impedance DC path between nodes and ground.
The overall performance in terms of phase noise is all-pMOS
VCO than VCO_CC and all-nMOS VCO.
Supply Voltage
The voltage at node V
out1, 2
required to operate the entire
transistor in saturation region used as shown in Fig. 5 without
causing any non-linearity. That term is called voltage
headroom.
Bonfring International Journal of Power Systems and Integrated Circuits, Vol. 2, No. 3, September 2012 13
ISSN 2277-5072 | 2012 Bonfring
Replace the bias source into MOS tail current source.
From Figure 5 (a):
The minimum and maximum voltage at nodes are shown
below,

1 2 7 5 sg DD out od gs
V V V V V + (6)
Figure 5 (b) & (c):

1 2 3 1 th T D DD out od gs
V R i V V V V + + (7)
If spiral inductor has Symmetric structure then

2 1 out out
V V = (8)
If spiral inductor has asymmetric structure then

2 1 out out
V V (9)
Due to asymmetric, there is variation in amplitude (p-p).
But this is not major issue for considering short range
applications than close-in phase noise. Voltage headroom is
higher in all-pMOS VCO than VCO_CC and all-nMOS VCO
due to body effect.
Tuning Range
To achieve a same transconductance (g
m
) for a given
current, nMOS transistors have smaller size than pMOS
transistors [11]. Because of this, all-nMOS VCO core can
achieve a wide tuning range than all-pMOS VCO and
VCO_CC core due to less parasitic capacitance.
Based on the above discussion, all-pMOS VCO topology
is chosen for designing a power efficient low noise QVCO
with higher voltage headroom in deep submicron technology.
Switched capacitor array (SCA) is used to achieve a wide
tuning range [11] while maintaining the constant VCO tuning
gain (K
VCO
), in all-pMOS VCO topology. Hence, in our
design finally we have chosen the all-pMOS LC-VCO
topology.
B. 4 .8 GHz All-pMOS LC-VCO Design
The all-pMOS LC-VCO is designed in 0.18 m CMOS
technology and the supply voltage is 1 V instead of maximum
supply voltage is 1.8 V. From Fig. 6, M
1
and M
2
form a pMOS
current mirror, whereas M
3
and M
4
are coupled in a positive
feedback to provide negative resistance in order to compensate
the losses occur due to parasitic resistance of both inductor
and capacitor [2]. C
var
are variable capacitance either diode or
MOS varactor, whose value is dependent on the control
voltage (V
ctr
). Bias current (I
bias
) is chosen such that to reduce
the power consumption, which is identified from whether the
oscillator operating in current (or) voltage limited regime [12].
Load is used either poly (Or) MOS capacitor switched
capacitor array (SCA) as shown in Fig. 7 in addition with
interfacing load between two circuits. Figure 7 (a) shows the
fixed poly capacitor based SCA. Drawbacks for these load, it
required additional step for fabrication [1] than MOS
capacitor SCA as shown in Figure 7 (b). But, it will affect the
close in phase performance than Fig. 7 (a). Based on the
requirements, choose the load for external tuning. D
0
, D
1
, D
2

and D
3
are discrete switches controlled by externally shown in
Fig. 7 (a) & 7 (b).
Vdd
M M
M
M
L
R R
L
s s
1 2
3
4
0 180
R
C
V
ref bias
l
o
a
d
l
o
a
d
V
out1
V
out2
V
ctr
C
var var
C
V
cm
I

Figure 6: Schematic of All-p MOS LC-VCO with Different
Loads
C 2C 4C 8C
W
2W 4W
8W W
2W 4W
8W
W
2W 4W 8W
V
out1 out1
V
D
0
D
0
D
1
D D D D D
1 2 3 2 3

(a) Fixed Poly Capacitor SCA. (b) MOS Capacitor SCA
Figure 7: Two Different Variable Capacitor Loads SCA
C. Performance Comparison of All-p MOS LC-VCO using
Various Loads
The performance comparison of various loads like ideal
capacitor, poly (practical) capacitor, poly capacitor SCA and
MOS capacitor SCA are interchanges step by step shown in
Fig. 6 for analyzing the performance in terms of close in phase
noise, harmonic distortion and amplitude swing (p-p) showed
in Fig. 8 and Table 1. Only major difference as shown in Fig.
8 and Table 1 is close in phase noise due to difference in poly
gate resistance. It will affect the overall quality factor and
magnitude of LC-VCO. However, it can further reduce by
increasing the number of gate fingers to reduce the poly gate
resistance but based on the required tuning range
specifications.








Bonfring International Journal of Power Systems and Integrated Circuits, Vol. 2, No. 3, September 2012 14
ISSN 2277-5072 | 2012 Bonfring

Table 1: Comparison of Different Load by Differential
Amplitude (p-p), Harmonic Distortion and Phase Noise


Figure 8: Simulated Phase Noise at 4.8 GHz All-p MOS LC-
VCO with Various Loads
D. Divider using CML Latch without Fixed Tail Current
Source
The schematic of CML divider latch using resistive load
without fixed tail current source are shown in Fig. 9. D-latch
consists of a cross-coupled pair (M
n3
, M
n4
) connected in
positive feedback configuration to provide negative trans
conductance to maximize the operating frequency. M
1
-M
4

operates in saturation region and M
5
-M
6
operates in triode
region.


Vdd
clk+
clk-
R
load
M
M M
M
M
M
1
2 3
4
5
6
Vdd
clk+
R
load
M
M M
M
M
M
1
2 3
4
5
6
Z
e
r
o
O
p
p
T
w
o
s
e
v
e
n
t
y
.
N
i
n
t
y
R
load
R
load
V
ref1 ref1
V

Figure 9: CML Divider with Resistive Load for Quadrature Signals
typical
corner @ 27 C
Differential
amplitude
(p-p)
(mV)
Harmonic
Distortion
3
rd
(dBc)
Phase Noise
@ 10 kHz,
100kHz, 1
MHz and 3
MHz
(dBc/Hz)
C
load
(ideal) 845.70 36.32
69.9,
95.2,
116.4,
126.3
C
load

(Practical)
847.66 36.26
75.5,
96.7,
116.8,
126.4
Fixed poly-
capacitor SCA
with C
load

(ideal)
837.90 36.58
71.2,
95.4,
116.3,
125.7
Fixed poly-
capacitor SCA
with C
load

(Prac.)
836.60 36.59
73.2,
95.87,
116.4,
125.9
MOS-Capacitor
SCA with
Cload

(ideal)
833.56 36.27
69.9,
94.9,
116.0,
125.6
MOS-Capacitor
SCA with C
load

(Practical)
831.80 36.30
72.5,
95.8,
116.4,
126.0
Bonfring International Journal of Power Systems and Integrated Circuits, Vol. 2, No. 3, September 2012 15
ISSN 2277-5072 | 2012 Bonfring

E. Theoretical Analysis
The transfer function and maximum operating frequency
of conventional CML latch are determined as follows. Figure
10 shows the equivalent of small- signal conventional CML
latch half circuit.
r d
s
g
m
1
V
R
l
o
a
d
-1
g
m4
C
V
1
T
d
q

Figure 10: Latch Equivalent Small-Signal Half Circuit
1 1 gd T
C C C + =

Where, C
gd1
is the gate-drain overlap capacitance of MOS
transistor M
1
.
Let us estimate the transfer function of D-latch by
associating one pole with each node as shown in Figure 10.
At node V
q
, the sum of the currents is equal to zero,
When input V
d
and V
Clk+
is equal to 1, total charge
accumulated in (C
T
) starts to discharge through resistance.
Hence,
At node
q
V

0
4 1
= + + +
q T q m
load
q
ds
q
d m
V sC V g
R
V
r
V
V g
(10)
=
d m
V g
1

+
T m
load ds
q
sC g
R r
V
4
1 1
(11)
T m
load ds
m
d
q
sC g
R r
g
V
V
+
=
4
1
1 1
(12)
Equation (12) is the transfer function of D-latch.
Now, let us calculate the approximation value of maximum
operating frequency when the voltage gain becomes unity.
Neglect body effect and channel length modulation while
considering in worst case analysis.
0
1 1
4 1
= + + +
T m
load ds
m
sC g
R r
g
(13)

+ =
4 1
1 1
m
load ds
m T
g
R r
g sC
(14)

Simplify the equation (14), replace s=j
0
,
( ) ( )
T
m
load ds
m m
load ds
m
out
C
g
R r
g g
R r
g
f

2
1 1 1 1
2
2
4
1
2
1 4
1
1
max ,
(15)
The maximum operating frequency is derived from
equation (15), when g
m4
reaches the 1/r
ds1
+ 1/R
load
by varying
the nMOS gate width.
To estimate the self oscillation frequency of latch, the
necessary condition is g
m4
R
load
is equal to 1 to get the
transfer function goes to infinity in equation (12) without
considering the total capacitance.
V. COMPARISON OF QVCO USING DIFFERENT
VARACTORS AND RESULTS
The main objective of the work was to make the behavior
of QVCOs perceptive to the different varactors. The parasitic
resistance of different varactors is not equal; it will affect the
performance of whole QVCO in terms of quality factor.
Therefore, performance of QVCO using different varactors
have been compared in terms of frequency range, tuning
range, harmonic distortion and phase noise as shown Table II.
All the outputs are shown below is taken from buffer with
combination of LC-VCO with MOS capacitor SCA followed
by divider without tail source. All simulations have been
performed with a power supply voltage V
dd
= 1 V. The tuning
characteristics of the VCO
s
are shown in Fig. 11 and
summarized in Table II. Fig. 10 shows the phase noise of the
QVCOs at 2.4 GHz carrier frequency. Table II presents the
phase noise at different offset frequencies from the carrier. At
offset frequencies lower than 1 MHz the phase noise behavior
of three QVCOs is approximately same with current
Table II: Performance Comparison in Terms of Frequency, Tuning Range, Phase Noise and Harmonic Distortion


Consumption of all these QVCOs are equal comparing
with [13]. The overall performance is displayed by inversion-
mode pMOS varactor comparing with other types, in terms of
frequency range, tuning range, phase noise and harmonic
distortion. If dc bias on the varactor varies, it will modulate
the varactor capacitance. Hence, it will affect the varactor gain
Varactor
f
L
f
H

(GHz)
f
c

(GHz)
C
max
/
C
min

Ratio
Tuning
Range
without
SCA
Tuning
Range
with SCA
I
dd
(mA)

Harmonic
Distortion
(3rd) (dBc)
Phasenoise@10kHz,
100kHz,1 MHz, 3 MHz
offset from carrier ( dBc /
Hz)
Diode
2.40
2.45
2.425 1.33 2.06% 5.36% 2.8 37.41 75, 102, 124, 134
I-pMOS
2.39
2.48
2.435 1.69 3.69% 6.99% 2.8 37.48 78, 104, 126, 134
A-
nMOS
2.39
2.43
2.410 1.15 1.66% 4.98% 2.8 37.10 75, 102, 124, 134
Bonfring International Journal of Power Systems and Integrated Circuits, Vol. 2, No. 3, September 2012 16
ISSN 2277-5072 | 2012 Bonfring
(K
VCO
) as it linearly proportional to phase noise performance.
But, in all-pMOS LC- VCO topology compared with others,
there is no dc bias variation on the varactor due to low dc
impedance path at node V
out1
(Figure 7) to ground [14]. As,
shown in Fig. 12, inversion mode pMOS varactor have
smoothness of slope around 0.25 V to 0.75 V, which means
that varactor gain, will decreases, while increasing the tuning
range of QVCO compared with others types of varactor.

Figure 11: Phase Noise for Different Varactor QVCOs at 2.4
GHz Carrier Frequency

Figure 12: Tuning Characteristics of Three Varactor QVCOs
at 2.4 GHz Carrier Frequency
VI. LAYOUT DESIGN AND ITS RESULTS
The overall performance is displayed by all-pMOS VCO
with MOS capacitor SCA followed by divider without tail
current source using inversion mode pMOS varactor shown in
table II. Bandgap reference is used to generate the reference
voltage for all the sub blocks like VCO followed by divider
then followed by buffer is independent of temperature and
supply independent. Hence, the comparison of pre and post
layout simulation results is described as follows. The pre and
post simulation results of the tuning range, phase noise, power
dissipation, harmonic distortion, self oscillation frequency of
divider, and reference voltage are analyzed over temperature
and process corner variation is shown in table III. There is a
possibility of threshold voltage variations by discarding wafers
that fall out of the envelope [1]. Based on those reason the
carrier frequency shifts by gate delay of the transistor. By
using SCA will bring back to the carrier frequency. The
simulated results the QVCO can be tuned from 2.38 to 2.51
GHz when all the discrete switches of SCA are 4b1000. The
overall performance of phase noise shows 133.6 dBc / Hz at
3 MHz offset from the carrier frequency, while consuming
5.17 mA of total current. Monte Carlo statistical simulations
have been undertaken over the QVCO extracted view shown
in Fig. 13. The number of samples N is 500. During
simulations, component mismatches are considered. The scale
X-axis is replace into frequency (GHz), whereas Y-axis is
replace into number of samples.

Figure 13: Monte Carlo Simulations
The layout design of proposed selection topology and its
components for generation of quadrature sine wave signals is
shown in Figure 14. The results are compared with pre layout
as shown in table III.

Figure 14: Layout Design of Conventional QVCO



Bonfring International Journal of Power Systems and Integrated Circuits, Vol. 2, No. 3, September 2012 17
ISSN 2277-5072 | 2012 Bonfring
Table III: Simulation Results of Conventional QVCO with Different Process Corners


VII. CONCLUSION AND FUTURE ENHANCEMENT
A 1 V 2.4 / 4.8 GHz CMOS QVCO using selection
topology and its components has been designed and presented
up to layout with performance comparison. The future scope is
to design the divider with and without tail current source
followed by buffer only p MOS device using either active or
passive load. Also, the circuit level design for targeted
applications try with only p MOS device using either active or
passive load rather than n MOS device.
VIII. ACKNOWLEDGEMENT
The authors would like thanks to advanced VLSI design
laboratory, Indian Institute of technology, Kharagpur for
accessing the IC tools.
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Arivazhagan, S/O V Perumal, krishnapuram,
TamilNadu India-614902 and 28-07-1981. School life
upto twelfth standard studied nearby town and
villages from my birth place. Gone to Madras in the
year 2000 (now Chennai) and did Bachelor of
electronics and Instrumentation Engineering, Madras
University, Madras, TamilNadu, India in the year
2004. Gone to Chandigarh in 2006 and did Advanced
PG Diploma in VLSI Design under Cadence
University Program at Semiconductor Complex
Limited, Vedant. Gone to kharagpur, West Bengal, India and did Master of
Science in Department of Electrical and Electronics Communication
Engineering, Indian Institute of Technology (IIT), kharagpur in the year 2012.
Achievements like gold medalist in government public Examination, students
best project award, best paper award in international conference etc., Also,
Worked as senior project assistant in advanced VLSI Design laboratory, IIT-
Kharagpur and Assistant professor in Oxford Engineering College,
Tiruchirappalli, TamilNadu, India. (E-mail: arivazhaganiitkgp@gmail.com).
Temperature (40 C ~ 85 C) FF TT SS
Tuning

Range
(GHz)

Pre Layout 2.49 ~ 2.36 2.51 ~ 2.38 2.50 ~2.38
Post Layout 2.29 ~ 2.16 2.31 ~ 2.18 2.30 ~2.18
Phase Noise
@3 MHz dBc/Hz
Pre Layout 136 ~ 134 136 ~ 133 135 ~ 132
Post Layout 124 ~ 126 125 ~ 128 123 ~ 125
Power Dissipation
(mW)
Pre Layout 7.26 ~ 7.09 5.71 ~ 5.64 4.1 ~ 4.47
Post Layout 6.30 ~ 5.59 5.08 ~ 5. 09 4.05 ~ 3.36
Harm. distortion
(3
rd
) (dBc)
Pre Layout 29 ~ 33 33 ~ 30 39 ~ 34
Post Layout 24 ~ 29 28 ~ 38 33 ~ 42
Self Osc. freq.of divider (GHz) Pre Layout 4.25 ~ 3.47 4.04 ~ 3.28 3.83 ~ 3.08
Post Layout 2.27 ~ 1.87 2.17 ~ 1.76 2.08 ~ 1.65
Reference Voltage
(mV)
Pre Layout 553 ~ 530 551 ~ 527 550 ~ 524
Post Layout 552 ~ 535 551 ~ 531 549 ~ 529