2004 Fairchild Semiconductor Corporation RFP50N05L Rev.

C
RFP50N05L
50A, 50V, 0.022 Ohm, Logic Level,
N-Channel Power MOSFETs
These are logic-level N-channel power MOSFETs
manufactured using the MegaFET process. This process,
which uses feature sizes approaching those of LSI
integrated circuits gives optimum utilization of silicon,
resulting in outstanding performance. They were designed
for use with logic-level (5V) driving sources in applications
such as programmable controllers, automotive switching,
switching regulators, switching converters, motor relay
drivers and emitter switches for bipolar transistors. This
performance is accomplished through a special gate oxide
design which provides full rated conductance at gate bias in
the 3V - 5V range, thereby facilitating true on-off power
control directly from integrated circuit supply voltages.
Formerly developmental type TA09872.
Features
50A, 50V
r
DS(ON)
= 0.022
UIS SOA Rating Curve (Single Pulse)
Design Optimized for 5V Gate Drive
Can be Driven Directly from CMOS, NMOS, TTL Circuits
Compatible with Automotive Drive Requirements
SOA is Power Dissipation Limited
Nanosecond Switching Speeds
Linear Transfer Characteristics
High Input Impedance
Majority Carrier Device
Related Literature
- TB334 Guidelines for Soldering Surface Mount
Components to PC Boards
Symbol
Packaging
JEDEC TO-220AB
Ordering Information
PART NUMBER PACKAGE BRAND
RFP50N05L TO-220AB F50N05L
NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-263AB variant in the tape and reel, i.e., RFP50N05L9A.
D
G
S
GATE
DRAIN (FLANGE)
SOURCE
DRAIN
Data Sheet August 2004
2004 Fairchild Semiconductor Corporation RFP50N05L Rev. C
Absolute Maximum Ratings T
C
= 25
o
C, Unless Otherwise Specified
RFP50N05L UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
50 V
Drain to Gate Voltage (R
GS
= 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
50 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
DM
50
130
A
A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
10 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Above T
C
= 25
o
C, Derate Linearly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
0.88
W
W/
o
C
Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to UIS SOA Curve -
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 150
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . .T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
DSS
I
D
= 250A, V
GS
= 0V (Figure 10) 50 - - V
Gate Threshold Voltage V
GS(TH)
V
GS
= V
DS
, I
D
= 250A (Figure 9) 1 - 2 V
Zero Gate Voltage Drain Current I
DSS
V
DS
= Rated BV
DSS
, V
GS
= 0 - - 25 A
V
DS
= 0.8 x Rated BV
DSS
, V
GS
= 0, T
C
= 150
o
C - - 250 A
Gate to Source Leakage Current I
GSS
V
GS
= 10V, V
DS
= 0V - - 100 nA
Drain to Source On Resistance (Note 2) r
DS(ON)
I
D
= 50A, V
GS
= 5V (Figure 7) - - 0.022
I
D
= 50A, V
GS
= 4V - - 0.027
Turn-On Time t
(ON)
V
GS
= 5V, R
GS
= 2.5, R
L
= 1
(Figures 12, 15, 16)
- - 100 ns
Turn-On Delay Time t
D(ON)
- 15 - ns
Rise Time t
r
- 50 - ns
Turn-Off Delay Time t
D(OFF)
- 50 - ns
Fall Time t
f
- 15 - ns
Turn-Off Time t
(OFF)
- - 100 ns
Total Gate Charge Q
G(TOT)
V
GS
= 0 to 10V V
DD
= 40V, I
D
= 50A
R
L
= 0.8
(Figures 17, 18)
- - 140 nC
Gate Charge at 5V Q
G(5)
V
GS
= 0 to 5V - - 80 nC
Threshold Gate Charge Q
G(th
) V
GS
= 0 to 1V - - 6 nC
Thermal Resistance Junction to Case R
JC
- - 1.14
o
C/W
Thermal Resistance Junction to Ambient R
JA
- - 80
o
C/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage (Note 2) V
SD
I
SD
= 50A - - 1.5 V
Diode Reverse Recovery Time t
rr
I
SD
= 50A, dI
SD
/dt = 100A/s - - 1.25 ns
NOTES:
2. Pulsed: pulse duration = 300s maximum, duty cycle = 2%.
3. Repititive rating: pulse width limited by maximum junction temperature.
RFP50N05L
2004 Fairchild Semiconductor Corporation RFP50N05L Rev. C
Typical Performance Curves
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SAFE
OPERATING AREA
FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS
1.2
1.0
0.8
0.6
0.4
0.2
0
P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N

M
U
L
T
I
P
L
I
E
R
0 25 50 75 100 125 150
T
C
, CASE TEMPERATURE (
o
C)
50
40
30
20
10
0
25 50 75 100 125 150
T
C
, CASE TEMPERATURE (
o
C)
I
D
,

D
R
A
I
N

C
U
R
R
E
N
T

(
A
)
100
10
1
0.1
1 10 100
I
D
S
,

D
R
A
I
N

T
O

S
O
U
R
C
E

C
U
R
R
E
N
T

(
A
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
T
C
= 25
o
C
OPERATION IN THIS
AREA LIMITED
BY r
DS(ON)
I
D
MAX CONTINUOUS
DC OPERATION
T
J
= MAX RATED
1000
100
10
I
A
S
,

A
V
A
L
A
N
C
H
E

C
U
R
R
E
N
T

(
A
)
IF R = 0
t
AV
= (L) (I
AS
) / (1.3 RATED BV
DSS
- V
DD
)
IF R = 0
T
AV
= (L/R) IN [(I
AS
*R) / (1.3 RATED BV
DSS
- V
DD
) + 1]
0.01 0.1 1 10
t
AV
, TIME IN AVALANCHE (ms)
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
I
DM
140
120
100
80
60
40
20
0
I
D
S
,

D
R
A
I
N

T
O

S
O
U
R
C
E

C
U
R
R
E
N
T

(
A
)
0 1.5 3.0 4.5 6.0 7.5
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 10V
V
GS
= 4V
V
GS
= 3V
V
GS
= 2V
PULSE DURATION = 80s
T
C
- 25
o
C
DUTY CYCLE = 0.5% MAX.
V
GS
= 5V
0 1.5 3.0 4.5 6.0 7.5
V
GS
, GATE TO SOURCE VOLTAGE (V)
140
120
100
80
60
40
20
0
150
o
C
-55
o
C
25
o
C
V
DS
= 15V
I
D
(
O
N
)
,

D
R
A
I
N

T
O

S
O
U
R
C
E

C
U
R
R
E
N
T

(
A
)
PULSE DURATION = 80s
T
C
- 25
o
C
DUTY CYCLE = 0.5% MAX.
RFP50N05L
2004 Fairchild Semiconductor Corporation RFP50N05L Rev. C
FIGURE 7. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs GATE VOLTAGE
FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Typical Performance Curves (Continued)
3.0
2.5
2.0
1.5
1.0
0.5
0
N
O
R
M
A
L
I
Z
E
D

D
R
A
I
N

T
O

S
O
U
R
C
E
-50 0 50 100 150
T
J
, JUNCTION TEMPERATURE (
o
C)
PULSE DURATION = 80s
V
GS
= 5V
I
D
= 50A
O
N

R
E
S
I
S
T
A
N
C
E
DUTY CYCLE = 0.5% MAX.
2.0
1.5
1.2
0.8
0.4
0
N
O
R
M
A
L
I
Z
E
D

D
R
A
I
N

T
O

S
O
U
R
C
E
4 5 6 7
V
GS
, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80s
I
D
= 50A, V
GS
= 5V
O
N

R
E
S
I
S
T
A
N
C
E
DUTY CYCLE = 0.5% MAX.
2.0
1.8
1.2
0.8
0.4
0
-50 0 50 100 150
T
J
, JUNCTION TEMPERATURE (
o
C)
N
O
R
M
A
L
I
Z
E
D

G
A
T
E
T
H
R
E
S
H
O
L
D

V
O
L
T
A
G
E
V
GS
= V
DS
, I
D
= 250A
2.0
1.8
1.2
0.8
0.4
0
-50 0 50 100 150
T
J
, JUNCTION TEMPERATURE (
o
C)
N
O
R
M
A
L
I
Z
E
D

D
R
A
I
N

T
O

S
O
U
R
C
E
B
R
E
A
K
D
O
W
N

V
O
L
T
A
G
E
I
D
= 250A
6000
5000
4000
3000
2000
1000
0
C
,

C
A
P
A
C
I
T
A
N
C
E

(
p
F
)
0 5 10 15 20 25
V
DS
, DRAIN TO SOURCE (V)
C
ISS
C
OSS
C
RSS
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
C
DS
+ C
GD
50
37.5
25
12.5
0
D
R
A
I
N

T
O

S
O
U
R
C
E

V
O
L
T
A
G
E

(
V
)
0
5
10
G
A
T
E

T
O

S
O
U
R
C
E

V
O
L
T
A
G
E

(
V
)
R
L
= 0
I
G(REF)
= 1.25mA
DRAIN TO SOURCE VOLTAGE
GATE TO
SOURCE
VOLTAGE
V
DD
= BV
DSS
V
DD
= BV
DSS
0.75BV
DSS
0.75BV
DSS
0.50BV
DSS
0.25BV
DSS
TIME-MICROSECONDS 20
I
G(REF)
I
G(ACT)
80
I
G(REF)
I
G(ACT)
0.25BV
DSS
0.50BV
DSS
RFP50N05L
2004 Fairchild Semiconductor Corporation RFP50N05L Rev. C
Test Circuits and Waveforms
FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 14. UNCLAMPED ENERGY WAVEFORMS
FIGURE 15. SWITCHING TIME TEST CIRCUIT FIGURE 16. RESISTIVE SWITCHING WAVEFORMS
FIGURE 17. GATE CHARGE TEST CIRCUIT FIGURE 18. GATE CHARGE WAVEFORMS
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50% 50%
10%
PULSE WIDTH
V
GS
0
0
R
L
V
GS
+
-
V
DS
V
DD
DUT
I
G(REF)
V
DD
Q
g(TH)
V
GS
= 1V
Q
g(5)
V
GS
= 5V
Q
g(TOT)
V
GS
= 10V
V
DS
V
GS
I
G(REF)
0
0
RFP50N05L
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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