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FORMAT NO: FM02 /Issue: 01/Revision: 00

Srinivasan Engineering College, Perambalur


Department Of Computer Science and Engineering
Even Semester 2013 2014
DATE: 25.11.2013
Course Handout
L T P C
Course No : CS 2253 3 0 0 3
Course Title : COMPUTER ORGANIZATION AND ARCHITECTURE
Course Instructor : Nilutpal Bose
Instructor-in-charge : Nilutpal Bose
COURSE OBJECTIVES
To define the function units of computer architecture,
To find the various instruction types and addressing modes used for programming
To understand the basic processing unit and execution of instruction.
To understand how computer hardware has evolved to meet the needs of multi-Processing systems.
To understand the Issues affecting modern processors(caches ,pipeline etc)
To understand how computers are designed and build.
COURSE OUTCOME
Upon successful completion of this course, a student will be able to
To understand the major components of a computer including CPU, memory, I/O and
storage.
To understand the uses for cache memory.
To understand a wide variety of memory technologies both internal and external.
To understand the role of the operating system in interfacing with the computer hardware.
To understand the basic components of the CPU including the ALU and control unit.
To understand design principles in instruction set design including RISC architectures.
To understand parallelism both in terms of a single processor and multiple processors
TEXT BOOK(S) [TB]
1. T1. Carl Hamacher, Zvonko Vranesic and Safwat Zaky, Computer Organization, 5th Edition,
Tata Mc-Graw Hill, 2002.
2. T2. Heuring, V.P. and Jordan, H.F., Computer Systems Design and Architecture, 2nd Edition,
Pearson Education, 2004.
COURSE PLAN / SCHEDULE
S.No Topics to be covered Learning objectives Ref. to Text
Book
No. of
lectures
1
Computer and its type
Functional units
Define the function units of
computer architecture
T1[1.1,1.2] 2
2
Basic operational concepts , Bus
structure
The interconnect functional unit
and approach T1[1.3]
1
3 Performance and metrics
How quickly a program be
executed
T1[1.6] 1
4 Instruction and its sequence
Basic principles of addressing
techniques and instruction
T1[2.4] 2
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sequencing
5 Hardware and software interface
Hardware and software
interfaces and execution
T1[2.4] 1
6 Instruction set architecture
Find the various instruction
types
T1[3.1-3.3] 2
7
Addressing modes
What an instruction set does
and how to specify the
operands
T1[2.5] 2
8
RISC CISC, Fixed point and
Floating point operation
Execution behavior of high
level language program and
new processor architecture
T2[13.8] 2
9
ALU design
The designing of new
computer architecture
T2[6.3] 2
10 Fundamental Concepts Organization of computers
central processing unit
T1[7.1] 3
11 Execution of complete
instruction
Internal functional units of a
processor and how they are
interconnected
T1[7.2]
1
12 Multiple bus organization Data transfer with reduced
number of
Clock cycle
T1[7.3]
2
13 Hardwired control . Hardware for generating
internal control signals T1[7.4]
1
14 Microprogrammed control Approaches for
microprogramming
T1[7.5]
1
15 Nano programming Organization of micro program.
T2[7.5]
2
16
Basic concepts
What is pipelining and need for
pipelining
T1[8.1] 2
17
Data hazards
Define data hazard and
handling them
T1[8.2] 2
18
Instruction hazards
Branch and Conditional branch
prediction
T1[8.3] 1
19
Influence on instruction sets
Addressing modes and
condition codes
T1[8.4] 2
20
Data path and control
considerations
Modification made in pipeline
execution
T1[8.5] 1
21
Performance considerations
Indicate instruction through put
T1[8.8] 2
22
Exception handling
Handling exceptions
T2[9.1] 1
23
Basic concepts Basic memory circuits
T1[5.1] 2
24
Semiconductor RAM Internal organization of
memory chips. DRAM details
T1[5.2]
1
25
ROM ROM, EPROM, EEPROM,
flash memory
T1[5.3] 1
26
Speed , Size and Cost Discussion on the effectiveness
of cost and speed
T1[5.4] 1
27
Cache memories , Improving
cache performance
Cache memory concepts, which
shortens the effective memory
T1[5.5,5.6] 2
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access time
28
Virtual memory Mechanism which increases
the apparent size of main
memory
T1[5.7] 1
29
Memory management
requirements
A part of operating system.
Defines user space and system
space
T1[5.8] 1
30
Associative memories To discuss about associative
memories
T2[7.5] 1
31
Secondary storage devices
Magnetic disks, optical disks
and magnetic tapes
T1[5.9] 2
32
Accessing I/O Devices Input/output arrangements and
device connections
T1[4.1] 1
33 Programmed I/O
To learn about the concept of
programmed i/o
T1[4.1]
2
34
Interrupts The idea of interrupts and the
hardware and software needs to
support
T1[4.2]
2
35
Direct memory access I/O mechanism for high-speed
devices
T1[4.4]
1
36 Interface circuits The design of them T1[4.6] 2
37
Standard I/O interfaces (PCI,
SCSI, USB)
Commercial bus standards T1[4.7]
1
38 I/O devices and processors. Detail of the I/O interfacing T2[7.6] 2
39
Review of Unit 5 and previous
units.
Revision
1
Total number of classes planned: 59
FORMAT NO: FM02 /Issue: 01/Revision: 00
EVALUATION SCHEME INTERNAL ASSESSMENT
LINKS:
Question Bank : www.sriengg.com/Kindly include the respective link
University Question Paper : www.sriengg.com/Kindly include the respective link
HOD Instructor-In-Charge Instructor
(S.Jayanthi) (Nilutpal Bose) (Nilutpal Bose)
EC
No.
Evaluation
Components
Duration Weightage Date & Time Venue
1
Slip Tests 40 min 20%
Monday-Friday
&
8.30am to 9.15am
T
o

b
e
a
n
n
o
u
n
c
e
d

l
a
t
e
r
2 Cycle Test 1 1.30hr
30%
27-01-2014 To 01-02-2014
&
8.30am to 10.00am
3 Cycle Test 2 1.30hr
17-02-2014 To 24-02-2014
&
8.30am to 10.00am
4 Cycle Test 3 1.30hr
10-03-2014 To 15-03-2014
&
8.30am to 10.00am
5 Model Exam 3hr 30%
05-04-2014 To 11-04-2014
&
1.00pm to 4.00pm
6
Attendance
Percentage
Continuous 20%

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