Design Flows for the Microelectronics Industry

The term microelectronics describes the group of technologies used to integrate multiple devices
into a small physical area such as a microchip used in computers or mobiles. Every example
spans several technologies, each with their own goals and challenges. The microelectronics
industry is dynamic and rapidly changing. Design flows (the rigorous engineering methods used
for quality assurance) must evolve just as rapidly to embrace new technological advancement.
Despite the small physical size of the systems in microelectronics, complexity can be very high.
In order to accommodate this engineering methods have developed that allow details to be
hidden, or abstracted to lower levels of the design process. This allowed larger systems to be
created with building blocks, which are small systems themselves.
Analysing the phases involved in the design process is the first step in understanding the
challenges facing the microelectronics industry in Australia. The rising demand for smaller,
smarter chips has the knock-on effect of increasing levels of design integration, and the level of
design automation must also increase to manage the inherent complexity. The use of Electronic
Design Automation (EDA) tools are an integral part of implementing design flows, but its influence
varies across sectors of the industry.
These are the various design flows or sectors, with a brief explanation and the key issues
involved with each.
1. Field Programmable Gate Array (FPGA) Design Flow
A FPGA is an array of regular logic blocks, which may be configured to operate within a particular
logical function. Digital logic functions can be synthesized onto the logic blocks of the FPGA and
it is then programmed with the configuration information to perform that function. FPGA devices
are economical at small volumes because the non-repetitive engineering (NRE) costs are lower
than with an Application Specific Integrated Circuit (ASIC). (As production volumes rise, the
longer-term cost efficiency of ASIC outweighs the increased NRE to make custom
implementation viable.) FPGAs can also offer a time to market advantage, as the device can be
programmed and tested after the design phase more quickly than an ASIC takes to synthesise.
Design modification and re-programming costs are also low compared to re-fabrication.
Design tool costs for FPGA development are traditionally lower than for ASICs, making FPGAs a
viable training and prototyping vehicle and opening the FPGA market to smaller organizations.
FPGA part vendors have traditionally provided FPGA design software. However, advances in
fabrication technology have seen an explosion in FPGA logic capacity, and this has moved the
complexity beyond software provided by FPGA tool vendors. ASIC tool vendors have now
moved into the market place to provide very high quality front-end tools to the FPGA market at a
reduced cost.
With front-end procedures being similar to digital ASIC and System on Chip development, FPGAs
are a low cost proof of concept or training tool. EDA tools are also more financially accessible to
small organizations and educational facilities.
User Constraints File
Test Bench
Synthesis Libraries
Timing Constraints
Module Generator/Library
Specification
Simulation/Timing
RTL
Synthesis
Gate Level Simulation
FPGA Place & Route
Simulation/Timing
Post Layout
Bit JEDEC file
System Level Modeling
Architectural Exploration
RTL Description
Meet
Specification?
Yes
No

FPGA Design Flow
Place & Route
Floorplan
Scan Chain Reordering
Pass?
Yes
No
Physical Rules
Pass?
Yes
No
Fault Simulation
ATPG
Test Vectors
Test Bench
Simulation Library
Synthesis Libraries
Module Generator/Library
Physical Constraints
Timing Libraries
Physical Libraries
Scan/BIST configuration
Constraints
Specification
RTL description
Initial Floorplan
Simulation/Timing
Logic Synthesis &
Scan Insertion
Power Analysis
Clock Tree Synthesis
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RC Extraction
Gate Level Simulation
Timing Verification
Post-Layout Verification
(LvS, DRC, ERC)
Tape Out
System Level Modeling
Architectural Exploration
2. Digital Application Specific Integrated Circuits (ASIC) Design Flow
Timing driven design flow for digital ASIC
Digital Application Specific Integrated Circuits (ASIC) Design Flow (continued)
ASIC developments in digital CMOS (complimentary metal oxide semiconductor) technologies
are the most common microelectronics pursuit. They are suited to medium to high levels of
production where NRE costs may be recouped by production cost savings due to lower
component counts or lower per part costs.
A timing driven design flow (TDD) is suitable for fabrication technologies of 0.25 micron and
above. The Register Transfer Language (RTL) is synthesised to a symbolic implementation in
terms of logic gates and a netlist, which is then implemented with a separate physical place and
route stage. The separation of these activities means that estimates of wire delays need to be
supplied to the synthesis tool. Satisfying timing constraints becomes more difficult if this
methodology is employed for finer line, deep sub-micron technologies.
A deep sub-micron (DSM) design flow addresses a number of physical effects that arise as the
fabrication technology moves below 0.18 micron. Signal integrity becomes the central issue
because the inter-line capacitance (that is wire to wire) becomes more dominant than the line to
substrate capacitance, causing cross talk and interference between signals. At the same time the
fine line technology produces narrower wires, which are more resistive, and the drive strength of
the transistors in the logic gates is reduced as less transistor area is used. The net result is that
interconnect can no longer be considered as ideal and the signal propagation delay due to
interconnect can be more significant than the gate delay.
Design complexities rise as larger, more complex systems can be integrated into fine line
technologies. This complexity has a large impact on design testability and practices that Design
for Test (DFT) must be employed. Demands for faster clock speeds and lower power push
design techniques to the limit of the time.

(see over for deep sub-micron digital design flow)
Physical Rules
Pass?
Yes
No
Pass?
Yes
No
Fault Simulation
ATPG
Module Generator/Library
Timing Constraints
Area Constraints
Power Constraints
Scan/BIST configuration
Synthesis Libraries
Physical Constraints
Floorplan
Scan Insertion
Placed-Gate Synthesis
Clock Tree Synthesis
Power Analysis
Detailed Route
Scan Chain Connections
RC Extraction
Synthesis:
Test Vectors
Simulation Library
Test Bench
Simulation/Timing
RTL Description
Initial Floorplanning
Specification
Post-Layout Verification
(LvS, DRC, ERC)
Tape Out
back-annotation
Timing Verification
Architectural Exploration
System Level Modeling

Deep Sub-Micron Digital Design
Flow
3. Analog Integrated Circuit (Analog IC) Design Flow
An analog design flow can be broken into two parts; one for large analog systems where analog
modules are assembled, and another for generation of the individual analog modules. Issues
such as reduced noise immunity, a greater dependence on device matching and process
variation means that most analog implementations require manual design (no synthesis) and
manual layout. With less automation available, analog design practises turn to hierarchy
management and modular design practices to cope with increasing complexity.
The physical implementation affects circuit performance to a far greater extent than in digital
circuits. Consequently, synthesis of analog circuits has not progressed very far and analog
implementations are substantially manual pursuits.
Process variation in manufacture can impact heavily on performance and yield. Circuit design
needs to use process tolerant topologies and process variation needs to be allowed for during
simulation. Design portability (between fabrication facilities) is reduced for the same reason.
Design Rules
Test Bench
Cell Library
Cell Models
Test Bench
Cell models
Specification
Physical Verification
RC Extraction
Meet
Specification
Yes
No
Post-Layout
AMS Simulation
Tape Out
Module Specification
AMS Simulation
System level Modeling
Floorplan

Analog System Development
Design Rules
Test Bench
Simulation models
Test Bench
Simulation models
Schematic Capture
Topology Selection
Layout
Design Simulation
Physical Verification
RC Extraction
Post-Layout Simulation
Meet
Specification
Yes
No
Callibrated AMS Model
Module
Specification

Analog Module Development
4. Mixed Signal Integrated Circuit (Mixed Signal IC) Design Flow
A Mixed Signal IC is appropriate for small and medium sized chips (<250,000 transistors), where
a combination of analog and digital circuitry is integrated. Such designs are generally partitioned
into analog and digital sections and then handled with design flows appropriate for each section.
The analog module design flow is usually appropriate for analog sections of the chip and includes
the generation of AMS models, which can be used in full chip verification suites.
The digital section of the chip can then proceed using a timing driven design flow or a deep sub
micron design flow as appropriate. To differentiate it from SoC development, this mixed signal
design flow refers to chips up to 250,000 transistors and, as such, a timing driven digital design
flow has been featured.
The Mixed Signal IC inherits the key issues involved with both digital and analog design flows.
System level verification of a mixed signal design requires specialised techniques and tools,
especially at the interface boundary between analog and digital circuits.
Test Vectors
Test Bench
Constraints
Scan/BIST configuration
Synthesis Library
Simulation Library
Cell Library
Physical Constraints
Test Bench
Test Vectors
Timing Information
Timing Estimates
Implementation Netlist
Logic Synthesis
with test insertion
Floorplan
and simulation
RTL description
Specification
Detailed Route
Layout Database
Physical Verification
(LvS, DRC, ERC)
Pass?
No
Yes
Scan path reordering
Clock Tree synthesis
Architectural Exploration
Schematic Capture
Topology Selection
Layout
Design Simulation
Physical Verification
RC Extraction
Post-Layout Simulation
AMS description
Gate level & AMS
AMS Models
Timing Estimates
Timing Verification
Formal Verification
Placement
RC Delay estimation
Simulation
Analog / Digital Partitioning
System level modelling
Calibrated AMS Models

Mixed Signal Design Flow


5. Radio Frequency Integrated Circuit (RFIC) Design Flow
RFIC design covers the development of integrated wireless communication and signal processing
devices. Typical RFIC design involves a high frequency RF front end, and a lower frequency
back end responsible for modulation or decoding of a signal. However, RF developments range
from predominantly digital systems with an RF front end, to those almost entirely analog RF
designs in the case of Microwave Monolithic Integrated Circuits. (When systems become
particularly large or contain multiple technology domains the term RF SoC may be applied.)
RFIC design often requires a considerable amount of signal processing. Algorithm design at the
system level is critical to achieving noise immunity and high system performance. RF systems
often merge digital signal processing and analog RF techniques in the one system. Future
developments will call for MicroElectro Mechanical Systems devices, further broadening the skill
base required for development.
System-level design and verification is required. Packaging and loading effects need to be
considered through the whole design cycle to ensure that system performance targets are met.
Significant complexity is introduced by the high frequency of operation. Specialised simulators
and analysis methods have been developed for RF design. Sections of an RF system that
operate at high frequency or have an analog nature have a high reliance on the physical
implementation. They may also be sensitive to process variation and require considerable effort
to optimise for a new fabrication process.
Design Rules
Test Bench
Cell Library
Test Bench
Behavioural Models
Behavioural models
Specification
Algorithm Design
Physical Verification
RC Extraction
Post-Layout
Floorplan
RF Simulation
verification / RF Simulation
System Behavioural
Architecture exploration
System partitioning

RF IC Design Flow
Design Rules
Test Bench
Simulation models
Test Bench
Simulation models
Schematic Capture
Topology Selection
Layout
Design Simulation
Physical Verification
RC Extraction
Post-Layout Simulation
Meet
Specification
Yes
No
Module
Specification
Calibrated Behavioural
model

RF Module Design Flow

6. Microwave Monolithic Integrated Circuit (MMIC) Design Flow
MMIC development is a form of RFIC development that tends to occupy the high frequency end
of the spectrum. In general MMIC circuits are low density (10s of transistors) and tend to operate
at a higher frequency (1GHz and above). At the lower frequency range MMIC devices can be
fabricated in standard silicon technologies, while higher performance can be obtained by moving
to SiGe, GaInP or GaAs processes.
The high frequency range of MMIC devices introduces significant complexity. Microwave design
principles are required and transmission line structures are often employed for interconnect.
Specialised simulators and analysis methods have been developed for RF design, their use
important to model transmission line and distributed effects within the circuit. Electromagnetic
simulators may also be used to analyse the physical structure of particularly complex circuits.
Considerable Intellectual Property is contained in RF device models. These may not always be
available from the fabrication facility and may require significant development resources.
Sections of an RF system that operate at high frequency or have an analog nature have a high
reliance on the physical implementation. They may also be sensitive to process variation and
require considerable effort to optimise for a new fabrication process. Prototype runs and design
iteration are an accepted part of the design flow for MMIC and high frequency analog
implementations. As simulation and RF modelling techniques mature, the need for this may
reduce.
Design Rules
Package model
System loading
System loading
Package model
Device models
Layout
Design Simulation
Physical Verification
RC Extraction
Post-Layout Simulation
Specification
Schematic Capture
Topology Selection
Prototype Fabrication
and packaging
Device Testing
Device models
Meet
Specification
Yes
No
Device production

MMIC Design Flow

7. System on Chip (SoC) Design Flow
SoC development is distinguished from traditional integrated development by the marked
increase in system complexity and the integration of several technology domains. For example,
SoC designs will incorporate traditional digital systems like microprocessors (once a chip in their
own right) with embedded memory and RF analog devices. In the future MicroElectro Mechanical
Systems, Optical Systems and Electro-Biological Systems will find their way into SoC designs.
SoC development falls into two main categories:
Cost based SoC (C-SoC) is characterized by large volume production directed at the
consumer electronics market. Systems are integrated on chip to reduce manufacturing
costs and power consumption for hand held devices. Device packaging tends to be as
inexpensive as possible and pin counts are reduced to assist this. A major emphasis for
C-SoC is the reduction of engineering development times to reduce time to market and
extend a products life in an environment of decreasing product life cycles.
Performance based SoC (P-SoC) is characterized by smaller volumes of high
performance, high value products. SoC is employed in these applications as the only
means available to meet project specifications (such as high speed or low power). P-SoC
occurs at or near the upper technological limits of the time. Military and aerospace
applications are classic candidates for P-SoC.
SoC developments occur in deep sub-micron technology, therefore key issues affecting deep
sub-micron affect SoC, including signal integrity and need for physical synthesis and system level
planning to meet timing constraints. As system complexity is rising exponentially, design
practices need to integrate design for test (DFT) and design for verification (DFV). Verification of
modern deep sub-micron projects consumes up to 70% of development time. Unless design
techniques embrace testing and verification from system level, time to market of SoC devices will
blow out to unsustainable levels.
Effective reuse of previous designs and Intellectual Property (IP) is critical to building complex
systems while reducing time to market. To achieve this, standards for IP development must be
developed to ensure integration and verification can occur in a timely fashion. Robust,
standardised interface and bus models are vital to avoid significant re-work of IP in order to
integrate it. The reuse of general purpose, programmable cores (like microprocessors) shifts
functionality from the hardware to the software domain. As software content increases, its design
complexity rises rapidly and software verification becomes an important issue, thus SoC design
flows must allow for hardware/software co-design and co-verification at all levels of the design
process.
Integration of multiple technologies on a single chip introduces new range of design challenges.
SoC developments already incorporate embedded memories. The International Technology
Road-map for Semiconductors (ITRS) predicts emergence of FPGA technology in SoCs in 2001,
MEMS, FRAM and Chemical sensors in 2002, electro-optical devices in 2004 and electro-
biological in 2006.
IP Core models
Cell Library
IP Core layout / box
Test Bench
IP Core models
Cell models
Design Rules
Timing/Power Constraints
Scan / BIST etc
Design Rules
Test Bench
Test Bench
IP Core models
Specification
System level
algorithm development
Architecture exploration
System level
Timing Verification
Physical Verification
HDL Design entry
and simulation
Tape Out
Block based Floorplan
Synthesis

SoC Block Based Development is evolving from digital ASIC methodologies like Timing Driven
Design (TDD). This diagram shows an abbreviated TDD flow evolving into a physical synthesis
stage, removing the need for iterations in the design flow.
Test Bench
Virtual Component library
Test Bench
Design Rules
Timing/Power Constraints
Scan / BIST etc
Design Rules
Virtual Components
Virtual component models
Specification
System level
algorithm development
Architecture exploration
System level
Tape Out
Virtual component
functional verification
Physical Verification
Floorplan
Synthesis

SoC Platform Based Development (PBD)

8. Bipolar Process
Bipolar integrated circuits provide some specialised features that have seen them in use over a
very long period. The power rating of the devices is one of most important properties, and they
have wide spread applications in power and automotive electronics. Their power sinking
capability also makes them more immune to switching spikes and inductive fly back than CMOS
technology. This has seen bipolar technology take up an important role as an interface between
sensitive CMOS circuitry and harsh high voltage or mechanical environments
The bipolar process is predominantly an analog design process. Technology provides medium-
scale integration and integration of traditional passive components. High currents can produce
thermal effects, which must be carefully modelled. The level of integration and feature size
allows prototype designs to be internally probed and tested effectively.
Physical Constraints
Prototype
Simulation Models
Design Rules
(LvS, DRC)
Floorplan
Layout
Simulation
Physical Verification
Schematic Capture
System Level Modelling
System Tests
Pass?
Specification
No
Yes
No
Meet
Specification?
Final Circuit for
Production
Yes

Bipolar System Development

9. MicroElectro Mechanical Systems (MEMS) Design Flow
MEMS are small electrical/mechanical devices utilised for their functionality in electrical systems
as sensors and switches. MEMS applications range from on-chip RF components, as antenna
structures, to micro-mirrors in optical systems. Current examples of MEMS technology are found
in devices like inkjet-printer heads, and accelerometers for the deployment of car airbags. The
widespread application possibilities give massive growth potential to development of the
technology and its market
MEMS devices are primarily a mechanical structure, but a variety of physical domains impact on
their behaviour. The mechanical, electrostatic, electromagnetic, thermal and fluidic domains all
require consideration and simulation at differing levels of accuracy.
Electrical models are often used as an analysis technique to leverage off more advanced
electrical design tools, but this technique requires careful interpretation on designers behalf.
The match between simulation results and device performance is poor by other microelectronics
standards. Prototype and design iteration is an accepted reality.
Process definition
Stimulus / test bench
Environment (package)
Specification
Schematic Entry &
2D Mask layout
Physical Verification
(LvS + limited DRC)
No
Yes
Device for
analysis & modelling
3D Visualization
Simulate FEA model
Simulate electrical analog
Production
Specification?
Meet
Device Tests
Fabrication & Packaging
Finite element

MEMS Design Flow
10. Integrated Optoelectronic Devices (Opto)
These devices range from laser/light sources, detectors, modulation devices, amplifiers,
multiplexers and demultiplexers. A large area for these chip-integrated optical systems is in the
communications industry, for applications such as switching devices and connectors.
The design flow for opto-electronic devices is concentrated on the physical characteristics of
structures. Complexity lies in developing and modelling the physical structures to produce the
required function rather than in sheer system size. Wavelength of operation is in the order of a
micron and below, so packaging must be included as an integral part of the design. Differing
material systems are used for various functional groups, but the design process used is similar.
Fabrication techniques are still maturing and manufacturing limits are currently a major factor in
performance and functionality.
2D Cross-Section
Design Rules
Mask Exports
Prototype
Device Tests
Meet
Specification?
Production
Specification
(LvS, DRC, ?)
Physical Verification
Simulation
Pass?
No
No
Yes
Yes
Device for
Package Design
Integration &
Floorplan & 3-D Layout
2-D Physical
Characteristic Modelling

Optoelectronic Device Development