Bo co lp trnh Verilog

Bi tp Lab2

Sinh vin thc hin: Nguyn Don Tun-K56.

Hng dn: Nguyn Sn Lm K54

1. Bi 1
a. Yu cu ca bi ton.
- Thit k mch gii m hin th cc s 4 bit (0-9) ln led 7 thanh.
b. Input, Output.
- Input: SW15-0
- Output: LEDR15-0, HEX3, HEX2, HEX1, HEX0
c. Thit k h thng.
- S khi:

Tuanbk | Bi tp Lab s 2

d. Trin khai.
- Code Verilog:
module part1(SW,LEDR,HEX3,HEX2,HEX1,HEX0);
input [15:0]SW;
output [15:0]LEDR;
output [0:6]HEX3,HEX2,HEX1,HEX0;
assign LEDR = SW;
display d3 (SW[15:12],HEX3);
display d2 (SW[11:8],HEX2);
display d1 (SW[7:4],HEX1);
display d0 (SW[3:0],HEX0);
endmodule
//Khoi hien thi led 7 thanh tu 1 so 4 bit
module display(A,B);
input [3:0]A;
output [0:6]B;
assign B[0] = (~A[1])&(A[2]|((~A[3])&(~A[2])&A[0]));
assign B[1] = A[2]&((~A[1])&A[0]|(~A[0])&A[1]);
assign B[2] = (~A[2])&A[1]&(~A[0]);
assign B[3] =
A[2]&((~A[1])&(~A[0])|A[1]&A[0])|((~A[3])&(~A[2])&(~A[1])&A[0]);
assign B[4] = A[0]|(A[2]&(~A[1]));
assign B[5] = A[1]&A[0]|(~A[2])&A[1]|(~A[3])&(~A[2])&A[0];
assign B[6] = (~A[3])&(~A[2])&(~A[1])|A[2]&A[1]&A[0];
endmodule

e. Kt qu.
- Code Testbench:
module Testbench21();
reg [15:0] sw;
wire [0:6]hex3,hex2,hex1,hex0;
wire [15:0]ledr;
part1 test1(sw,ledr,hex3,hex2,hex1,hex0);
initial
#0; sw
#10; sw
#10; sw
#10; sw
#10; sw
end
endmodule

begin
= 15'h1028;
= 15'h2345;
= 15'h7924;
= 15'h1155;
= 15'h6590;

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- Kt qu m phng Testbench (u vo v u ra hin th h hexa):

Tuanbk | Bi tp Lab s 2

2. Bi 2
a. Yu cu bi ton.
- Thit k mch t hp hin th s 4 bit (0-15) ln 2 led 7 thanh hin th hng
chc v hng n v ca s ny.
b. Input, output.
- Input: SW3-0
- Output: LEDR3-0, HEX1, HEX0
c. Thit k h thng.
- S khi :

Tuanbk | Bi tp Lab s 2

d. Trin khai.
module part2(SW,LEDR,HEX1,HEX0);
input [3:0]SW;
output [3:0]LEDR;
output [0:6]HEX1,HEX0;
wire z;
wire [2:0]n;
wire [3:0]m;
assign LEDR = SW;
comparator comp1(SW,z);
circuitA cirA (SW[2:0],n);
mux2to1 mux3 (SW[3],1'b0,m[3],z);
mux2to1 mux2 (SW[2],n[2],m[2],z);
mux2to1 mux1 (SW[1],n[1],m[1],z);
mux2to1 mux0 (SW[0],n[0],m[0],z);
circuitB cirB (z,HEX1);
display d1 (m,HEX0);
endmodule
//Khoi so sanh co chuc nang: if(in>10) out = 1 else out = 0
module comparator(in,out);
input [3:0] in;
output out;
assign out = in[3]&in[2]|in[3]&in[1];
endmodule
module circuitA(a,b);
input [2:0]a;
output [2:0]b;
assign b[2] = a[2]&a[1];
assign b[1] = a[2]&(~a[1]);
assign b[0] = a[0];
endmodule
// Manh B co chuc nang:
// a = 1 hien thi so 1 voi ma hien thi 4Fh
// a = 0 hien thi so 0 voi ma hien thu 01h
module circuitB(a,b);
input a;
output [0:6]b;
assign b = {a,1'b0,1'b0,a,a,a,1'b1};
endmodule
//Khoi hien thi Led 7 thanh tu 1 so 4 bit
module display(A,B);
input [3:0]A;
output [0:6]B;
assign B[0] = (~A[1])&(A[2]|((~A[3])&(~A[2])&A[0]));
assign B[1] = A[2]&((~A[1])&A[0]|(~A[0])&A[1]);
assign B[2] = (~A[2])&A[1]&(~A[0]);
assign B[3] =
A[2]&((~A[1])&(~A[0])|A[1]&A[0])|((~A[3])&(~A[2])&(~A[1])&A[0]);
assign B[4] = A[0]|(A[2]&(~A[1]));
assign B[5] = A[1]&A[0]|(~A[2])&A[1]|(~A[3])&(~A[2])&A[0];
assign B[6] = (~A[3])&(~A[2])&(~A[1])|A[2]&A[1]&A[0];
endmodule
//Khoi mux-2to1: s = 1 thi c = b; s = 0 thi c = a
module mux2to1(a,b,c,s);
input a,b,s;
output c;
assign c = (~s)&a|s&b;
endmodule

Tuanbk | Bi tp Lab s 2

e. Kt qu.
- Code Testbench:
module Testbench22();
reg [3:0] sw;
wire [0:6]hex1,hex0;
wire [3:0]ledr;
part2 test2 (sw,ledr,hex1,hex0);
initial
#0; sw
#10; sw
#10; sw
#10; sw
#10; sw
end
endmodule

begin
= 4'h1;
= 4'h5;
= 4'hB;
= 4'h2;
= 4'hA;

- Kt qu m phng (u vo v u ra hin th vi h hexa):

Tuanbk | Bi tp Lab s 2

3. Bi 3
a. Yu cu bi ton.
- Thit k b cng hai s 4 bit t 4 b FA (Full Adder)
b. Input, Output.
- Input: SW8-0
- Output: LEDR8-0, LEDG4-0
c. Thit k h thng.
- S khi:

d. Trin khai.
- Code Verilog:
module part3(SW,LEDR,LEDG);
input [8:0]SW;
output [8:0]LEDR;
output [4:0]LEDG;
wire [2:0]c;
wire [4:0]s;
assign LEDR = SW;
FA fa1 (SW[8],SW[0],SW[4],s[0],c[0]);
FA fa2 (c[0],SW[1],SW[5],s[1],c[1]);
FA fa3 (c[1],SW[2],SW[6],s[2],c[2]);
FA fa4 (c[2],SW[3],SW[7],s[3],s[4]);
assign LEDG = s;
endmodule
module FA(ci,a,b,s,c0);
input ci,a,b;
output s,c0;
wire v;
assign v = a^b;
assign s = ci^v;
assign c0 = v&ci|(~v)&b;
endmodule

Tuanbk | Bi tp Lab s 2

e. Kt qu.
- Code Testbench:
module Testbench23();
reg [8:0] sw;
wire [8:0]ledr;
wire [4:0]ledg;
part3 test3 (sw,ledr,ledg);
initial
#0; sw
#10; sw
#10; sw
#10; sw
#10; sw
end
endmodule

begin
= 9'h012;
= 9'h136;
= 9'h0B2;
= 9'h028;
= 9'h1AA;

- Kt qu m phng (u vo h c s 8 v u ra h nh phn):

Tuanbk | Bi tp Lab s 2

4. Bi 4
a. Yu cu h thng.
- Thit k mach t hp c chc nng cng hai s BCD l: A+B = S1S0 sau hin th
S1 v S0 ln led 7 thanh.
b. Input, output.
- Input: SW8-0 (Tng ng vi c2, c1, c0).
- Output: : LEDR8-0, LEDG8-0, HEX5, HEX4, HEX1, HEX0
c. Thit k h thng.
- S khi:

Tuanbk | Bi tp Lab s 2

d. Trin khai.
- Code Verilog:
module part4(SW,LEDR,LEDG,HEX5,HEX4,HEX1,HEX0);
input [8:0]SW;
output [8:0]LEDR;
output [8:0]LEDG;
output [0:6]HEX5,HEX4,HEX1,HEX0;
wire [4:0]x,m;
wire [3:0]z;
wire cout;
assign LEDR = SW;
adder add1 (SW[3:0],SW[7:4],SW[8],x);
assign LEDG[4:0]=x;
assign LEDG[8] = (SW[7]&SW[6]|SW[7]&SW[5])|(SW[3]&SW[2]|SW[3]&SW[1]);
led7 L5 (SW[7:4],HEX5);
led7 L4 (SW[3:0],HEX4);
assign cout = x[4]|(x[3]&x[2]|x[3]&x[1]);
led7 L1 ({3'b000,cout},HEX1);
adder add2 (x[3:0],4'b0110,1'b0,m);
assign z = ({4{cout}}&m[3:0])|({4{~cout}}&x[3:0]);
led7 L2 (z,HEX0);
endmodule
module led7(A,B);
input [3:0]A;
output [0:6]B;
assign B[0] = (~A[1])&(A[2]|((~A[3])&(~A[2])&A[0]));
assign B[1] = A[2]&((~A[1])&A[0]|(~A[0])&A[1]);
assign B[2] = (~A[2])&A[1]&(~A[0]);
assign B[3] =
A[2]&((~A[1])&(~A[0])|A[1]&A[0])|((~A[3])&(~A[2])&(~A[1])&A[0]);
assign B[4] = A[0]|(A[2]&(~A[1]));
assign B[5] = A[1]&A[0]|(~A[2])&A[1]|(~A[3])&(~A[2])&A[0];
assign B[6] = (~A[3])&(~A[2])&(~A[1])|A[2]&A[1]&A[0];
endmodule
module adder (sw1,sw2,sw,leg);
input [3:0]sw1;
input [3:0]sw2;
input sw;
output [4:0]leg;
wire [2:0]c;
wire [4:0]s;
FA fa1 (sw,sw1[0],sw2[0],s[0],c[0]);
FA fa2 (c[0],sw1[1],sw2[1],s[1],c[1]);
FA fa3 (c[1],sw1[2],sw2[2],s[2],c[2]);
FA fa4 (c[2],sw1[3],sw2[3],s[3],s[4]);
assign leg = s;
endmodule
module FA(ci,a,b,s,c0);
input ci,a,b;
output s,c0;
wire v;
assign v = a^b;
assign s = ci^v;
assign c0 = v&ci|(~v)&b;
endmodule

Tuanbk | Bi tp Lab s 2

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e. Kt qu.
- Code Testbench:
module Testbench24();
reg [8:0] sw;
wire [8:0]ledr;
wire [8:0]ledg;
wire [0:6]hex5,hex4,hex1,hex0;
part4 test4 (sw,ledr,ledg,hex5,hex4,hex1,hex0);
initial begin
#0; sw = 9'h098;
#10; sw = 9'h136;
#10; sw = 9'h0B2;
#10; sw = 9'h028;
#10; sw = 9'h1AA;
end
endmodule

- Kt qu m phng:

Tuanbk | Bi tp Lab s 2

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5. Bi 5
a. Yu cu h thng.
- Thit k mch t hp hin th cng hai s BCD: A1A0+B1B0 = S2S1S0. S dng
mch t hp bi 4 thc hin. V kt qu S2, S1, S0 hin th ln Led 7 thanh.
b. Input, Output.
- Input: SW15-0
- Output: LEDR15-0, HEX7, HEX6, HEX5, HEX4, HEX2, HEX1, HEX0
c. Thit k h thng.
- S khi:

Tuanbk | Bi tp Lab s 2

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d. Trin khai (code verilog thc hin)

module part5(SW,LEDR,HEX7,HEX6,HEX5,HEX4,HEX2,HEX1,HEX0);
input [15:0]SW;
output [0:6]HEX7,HEX6,HEX5,HEX4,HEX2,HEX1,HEX0;
output [15:0]LEDR;
wire [4:0]s1,s2,s3,s4;
wire [3:0]c0,c1,c2;
wire cout1;
assign LEDR = SW;
FA4bit fa4bit1(SW[11:8],SW[3:0],1'b0,s1);
assign cout1 = s1[4]|(s1[3]&s1[2]|s1[3]&s1[1]);
FA4bit fa4bit2(s1[3:0],4'b0110,1'b0,s3);
assign c0 = ({4{cout1}}&s3[3:0])|({4{~cout1}}&s1[3:0]);
FA4bit fa4bit3(SW[15:12],SW[7:4],cout1,s2);
assign c2[3] = 0;
assign c2[2] = 0;
assign c2[1] = 0;
assign c2[0] = s2[4]|(s2[3]&s2[2]|s2[3]&s2[1]);
FA4bit fa4bit4(s2[3:0],4'b0110,1'b0,s4);
assign c1 = ({4{c2[0]}}&s4[3:0])|({4{~c2[0]}}&s2[3:0]);
display d4 (SW[3:0],HEX4);
display d5 (SW[7:4],HEX5);
display d6 (SW[11:8],HEX6);
display d7 (SW[15:12],HEX7);
display d0 (c0,HEX0);
display d1 (c1,HEX1);
display d2 (c2,HEX2);
endmodule
module display(A,B);
input [3:0]A;
output [0:6]B;
assign B[0] = (~A[1])&(A[2]|((~A[3])&(~A[2])&A[0]));
assign B[1] = A[2]&((~A[1])&A[0]|(~A[0])&A[1]);
assign B[2] = (~A[2])&A[1]&(~A[0]);
assign B[3] =
A[2]&((~A[1])&(~A[0])|A[1]&A[0])|((~A[3])&(~A[2])&(~A[1])&A[0]);
assign B[4] = A[0]|(A[2]&(~A[1]));
assign B[5] = A[1]&A[0]|(~A[2])&A[1]|(~A[3])&(~A[2])&A[0];
assign B[6] = (~A[3])&(~A[2])&(~A[1])|A[2]&A[1]&A[0];
endmodule
module FA4bit(sw1,sw2,sw,leg);
input [3:0]sw1;
input [3:0]sw2;
input sw;
output [4:0]leg;
wire [2:0]c;
wire [4:0]s;
FA fa1 (sw,sw1[0],sw2[0],s[0],c[0]);
FA fa2 (c[0],sw1[1],sw2[1],s[1],c[1]);
FA fa3 (c[1],sw1[2],sw2[2],s[2],c[2]);
FA fa4 (c[2],sw1[3],sw2[3],s[3],s[4]);
assign leg = s;
endmodule
module FA(ci,a,b,s,c0);
input ci,a,b;
output s,c0;
wire v;
assign v = a^b;
assign s = ci^v;
assign c0 = v&ci|(~v)&b;
endmodule

Tuanbk | Bi tp Lab s 2

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e. Kt qu.
- Code Testbench:
module Testbench25();
reg [15:0] sw;
wire [15:0]ledr;
wire [0:6]hex7,hex6,hex5,hex4,hex2,hex1,hex0;
part5 test5 (sw,ledr,hex7,hex6,hex5,hex4,hex2,hex1,hex0);
initial begin
#0; sw = 16'h1365;
#10; sw = 16'h2354;
#10; sw = 16'h0545;
#10; sw = 16'h1894;
#10; sw = 16'h0163;
end
endmodule

- Kt qu m phng (u vo v u ra hin th s hexa):

Tuanbk | Bi tp Lab s 2

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6. Bi 6
a. Yu cu h thng.
- Yu cu tng t nh bi 5 nhng ta s s dng If else thc hin.
b. Input, output.
- Input: SW15-0
- Output: LEDR15-0, HEX7, HEX6, HEX5, HEX4, HEX2, HEX1, HEX0
c. Thit k h thng.
- S khi:

d. Trin khai.
- Code Verilog:
module part6 (SW,LEDR,HEX7,HEX6,HEX5,HEX4,HEX2,HEX1,HEX0);
input [15:0]SW;
output [0:6]HEX7,HEX6,HEX5,HEX4,HEX2,HEX1,HEX0;
output [15:0]LEDR;
wire [4:0]T0,T1;
wire c1,c2;
wire [3:0]Z0,Z1,S0,S1,S2;
assign T0 = SW[3:0]+SW[11:8];
assign Z0 = (T0>5'b01001)?4'd10:4'd0;
assign c1 = (T0>5'b01001)?1'b1:1'b0;
assign S0 = T0-Z0;
assign T1 = SW[7:4]+SW[15:12]+c1;
assign Z1 = (T1>5'b01001)?4'd10:4'd0;
assign c2 = (T1>5'b01001)?1'b1:1'b0;
assign S1 = T1-Z1;
assign S2 = c2;
assign LEDR = SW;
display d1 (SW[3:0],HEX4);
display d2 (SW[7:4],HEX5);

Tuanbk | Bi tp Lab s 2

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display
display
display
display
display
endmodule

d3
d4
d5
d6
d7

(SW[11:8],HEX6);
(SW[15:12],HEX7);
(S0,HEX0);
(S1,HEX1);
(S2,HEX2);

module display(A,B);
input [3:0]A;
output [0:6]B;
assign B[0] = (~A[1])&(A[2]|((~A[3])&(~A[2])&A[0]));
assign B[1] = A[2]&((~A[1])&A[0]|(~A[0])&A[1]);
assign B[2] = (~A[2])&A[1]&(~A[0]);
assign B[3] =
A[2]&((~A[1])&(~A[0])|A[1]&A[0])|((~A[3])&(~A[2])&(~A[1])&A[0]);
assign B[4] = A[0]|(A[2]&(~A[1]));
assign B[5] = A[1]&A[0]|(~A[2])&A[1]|(~A[3])&(~A[2])&A[0];
assign B[6] = (~A[3])&(~A[2])&(~A[1])|A[2]&A[1]&A[0];
endmodule

e. Kt qu.
- Code Testbench:
module Testbench26();
reg [15:0] sw;
wire [15:0]ledr;
wire [0:6]hex7,hex6,hex5,hex4,hex2,hex1,hex0;
part6 test6 (sw,ledr,hex7,hex6,hex5,hex4,hex2,hex1,hex0);
initial begin
#0; sw = 16'h1365;
#10; sw = 16'h2354;
#10; sw = 16'h0545;
#10; sw = 16'h1894;
#10; sw = 16'h0163;
end
endmodule

Tuanbk | Bi tp Lab s 2

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- Kt qu m phng (u vo v u ra hin th s hexa):

Tuanbk | Bi tp Lab s 2

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7. Bi 7
a. Yu cu h thng.
- Thit k mch t hp thc hin chc nng chuyn mt s 6 bt thnh s thp phn
dng BCD v hin th s ny ln Led 7 thanh.
b. Input, Output.
- Input: SW5-0
- Output: LEDR5-0, HEX1, HEX0
c. Thit k h thng.
- S khi:

d. Trin khai.
- Code Verilog:
module part7 (SW,LEDR,HEX1,HEX0);
input [5:0]SW;
output [5:0]LEDR;
output [0:6]HEX1,HEX0;
wire [3:0]d1,d2,d3;
wire [3:0]c1,c2,c3;
assign LEDR = SW;
assign d1 = {1'b0,SW[5:3]};
assign d2 = {c1[2:0],SW[2]};
assign d3 = {c2[2:0],SW[1]};
add3 m1 (d1,c1);
add3 m2 (d2,c2);
add3 m3 (d3,c3);
display disp1 ({1'b0,c1[3],c2[3],c3[3]},HEX1);
display disp2 ({c3[2:0],SW[0]},HEX0);
endmodule
module add3(in, out);

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input [3:0]in;
output [3:0]out;
assign out[3] = in[3]|(in[2]&(in[1]|in[0]));
assign out[2] = in[2]&(~in[1])&(~in[0])|in[3]&in[0];
assign out[1] = in[1]&in[0]|in[3]&(~in[0])|(~in[2])&in[1];
assign out[0] =
(~in[3])&(~in[2])&in[0]|in[2]&in[1]&(~in[0])|in[3]&(~in[0]);
endmodule
module display(A,B);
input [3:0]A;
output [0:6]B;
assign B[0] = (~A[1])&(A[2]|((~A[3])&(~A[2])&A[0]));
assign B[1] = A[2]&((~A[1])&A[0]|(~A[0])&A[1]);
assign B[2] = (~A[2])&A[1]&(~A[0]);
assign B[3] =
A[2]&((~A[1])&(~A[0])|A[1]&A[0])|((~A[3])&(~A[2])&(~A[1])&A[0]);
assign B[4] = A[0]|(A[2]&(~A[1]));
assign B[5] = A[1]&A[0]|(~A[2])&A[1]|(~A[3])&(~A[2])&A[0];
assign B[6] = (~A[3])&(~A[2])&(~A[1])|A[2]&A[1]&A[0];
endmodule

e. Kt qu.
- Code Testbench:
module Testbench27();
reg [5:0] sw;
wire [5:0]ledr;
wire [0:6]hex1,hex0;
part7 test7 (sw,ledr,hex1,hex0);
initial begin
#0; sw = 6'd10;
#10; sw = 6'd25;
#10; sw = 6'd60;
#10; sw = 6'd35;
#10; sw = 6'd50;
end
endmodule

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- Kt qu m phng (u vo v u ra hin th s hexa):

Tuanbk | Bi tp Lab s 2

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