Chap 2Lesson06EmsysNew

2008
Chapter-2 L6: "Embedded Systems - Architecture, Programming and Design",

Raj Kamal, Publs.: McGraw-Hill Education
1
8051 AND ADVANCED PROCESSOR
ARCHITECTURES
Lesson-6: REAL WORLD INTERFACING -
Part 1
2008
2
1. Interfacing Using System Bus
1. Interfacing Using System Bus
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3
Interfacing of processor, memory and IO devices
using memory system bus
System bus ! interconnections for a simple
bus structure has three sets of signals
System bus ! defines by address bus, data
bus, and control bus
A system-bus interfacing-design is
according to the timing diagrams of
processor signals, speed, and word length
for instructions and data.
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4
Processor internal
Processor internal
bus(es
bus(es
) and external
) and external
bus(es
bus(es
).
).
Characteristics differ in the system
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5
Interconnections for a simple bus structure
RAM
Processor
Input-Output Ports and
Devices
ROM
Address bus
Data bus
Control bus
Interfacing of processor, memory and
IO devices using memory system bus
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6
Address Bus
Address Bus
Processor issues the address of the
instruction byte or word to memory system
through the address bus.
Processor execution unit, when required,
issues the address of data (byte or word) to
be read or written using the memory system
through address bus.
The address bus of 32-bits used to fetch the
instruction or data from an address specified
by 32-bit number.
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7
EXAMPLE
Let a processor at the start reset the program
counter at address 0. Then the processor
issues address 0 on the bus and the
instruction at address 0 is fetched from
memory on reset
Let a processor instruction be such that it
needs to load register r1 from the memory
address M. The processor issues address M
on the address bus and data at address M is
fetched.
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8
Data Bus
Data Bus
Instruction fetch! Processor issues the
address of the instruction, it gets back the
instruction through the data bus.
Data Read! When it issues the address of
the data, it loads the data through data bus.
Data Write! When it issues the address of
the data, it stores the data in the memory
through the data bus. A data bus of 32-bits
fetches, loads, or stores the instruction or
data of 32-bits.
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9
EXAMPLE
Processor issues address m for an instruction, it
fetches the instruction through data bus from
address m. [For a 32-bit instruction, word at data
bus from addresses m, m + 1, m + 2, and m + 3.]
Instruction executes for store of register r1 bits to
the memory address M, the processor issues
address M on the bus and sends the data at address
M through the data bus. [For 32-bit data, word at
data bus sent to the memory addresses M, M + 1,
M + 2, and M + 3.]
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10
Control Bus
Control Bus
Issues signals to control the timing of
various actions during interconnection.
Signals synchronize all the subsystems.
address latch enable (ALE)[ Address
Strobe (AS) or address valid, (ADV)],
memory read (RD) or write (WR) or IO
read (IORD) or write,(IOWR) or data
valid(DAV)
Other control signals as per the processor
design.
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11
Interrupts and DMA Control Signals
Interrupts and DMA Control Signals
Interrupt acknowledge (INTA) [on a request for
drawing the processor attention to an event]
INT (Interrupt) from external device interrupt to
the system
Hold acknowledge (HLDA) [on an external hold
request for permitting use of the system buses]
HOLD when external device sends a hold request
for direct memory access (DMA).
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12
EXAMPLE
Processor issues the address, it also issues a
memory-read control signal and waits for
the data or instruction.
Memory unit must place the instruction or
data during the interval in which memory-
read signal is active (not inactivated by the
processor).
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13
EXAMPLE
Processor issues the address on the address bus,
and (after allowing sufficient time for the all
address bits setup) it places the data on the data
bus, it also then issues memory-write control
signal (after allowing sufficient time for the all
data bits setup) for store signal to memory.
Memory unit must write (store) the data during the
interval in which memory-write signal is active
(not inactivated by the processor).
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14
Program memory access and data buses
Program memory access and data buses
multiplexed for memory access in
multiplexed for memory access in
Harvard Architecture
Harvard Architecture
Address and data buses are multiplexed
Control signal PSEN active when accessing
program memory using the address and data
buses
Control signal Read or Write active when
accessing data memory using the address
and data buses
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15
Time division multiplexed (TDM) address
Time division multiplexed (TDM) address
and data bits for the memories
and data bits for the memories
TDM ! Different time slots, there are is a
different set sets (channel) of the signals.
Address signals during one time slot t. and
data bus signals in another time slot.
Interfacing circuit for the demultiplexing of
the buses uses a control signal in such
systems.
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Time division multiplexed (TDM)
Time division multiplexed (TDM)
address and data bits for the memories
address and data bits for the memories
Control signal Address Latch Enable (ALE)
in 8051, Address Strobe (AS) in 68HC11
and address valid (ADV) in 80196.
ALE or AS or ADV demultiplexes the
address and data buses to the devices
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Interfacing circuit using Latch and decoders,
Interfacing circuit using Latch and decoders,
ALE for latching the address
PSEN for program memory read using address-
data buses
Each chip of the memory or port that connects the
processor has a separate chip select input from a
decoder.
Decoder is a circuit, which has appropriate signals
of the address bus at the input and control circuit
signals to generate corresponding CS (chip select)
control signals for each device (memory and
ports)
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18
Interfacing
Interfacing
-
-
circuit
circuit
Consists of latches, decoders and demultiplexers
Designed as per available control signals and
timing diagrams of the bus signals.
Circuit connects all the units, processor, memory
and the IO device through the system buses.
Also called glue circuit used as it joins the devices
and memory with the system bus and processor
Can be designed using a GAL (generic array
logic) or FPGA
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68HC11 Bus signals and Interfacing to
68HC11 Bus signals and Interfacing to
memory
memory
68HC11
E Clock for 8 MHz XTAL
T = 0.25 8 m
0.25 s m 2t1
A8...A15
A8
AD0-AD7
D0-D7
(during write)
D0-D7
(during read
amd write)
Read
0x0000
a.
b.
0xFFFF
Write
6
8
H
C
1
1
A8,A9,A15
AD0,AD1,....AD7
A0,A1,...AD7
A8
D0-D7
A0-A7
R/W
R/W
R/W =1
t1
t2
t3
t1
T = 0.25 8 m
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2. Interfacing Using System and IO
2. Interfacing Using System and IO
Buses
Buses
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21
System Bus and IO Bus
System Bus and IO Bus
System bus interconnects
processor
memory systems and
subsystems
Another set of signals called I/O bus
Interfacing of processor with system
bus at first level and IO bus at second
level
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22
Popular IO buses and wireless communication
PCI Bus interfaces to devices designed to
meet the PCI standard.
USB interfaces to devices designed to meet
the USB IOs
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23
PCI Bus interfaces to devices designed to
meet the PCI standard.
USB interfaces to devices designed to meet
the USB IOs
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24
Memory system bus and I/O bus interconnections in
a bus structure
Processor
Input-Output Bus Controller,
for example, PCI or USB
Address bus
RAM ROM
IO
Device
IO
Device
IO
Device
IO bus
Memory bus
Data bus
Control bus
System Bus
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25
3. Multilevel Buses
3. Multilevel Buses
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26
Separate memory and I/O buses using PCI and USB bus
controllers and a separate disk I/O bus
Processor
Input-Output Bus Controller,
for example, PCI or SCSI
Address bus
RAM ROM
USB
Port
IO
Device
Hard disk
controller
IO bus
Memory bus
Data bus
Control bus
System Bus
USB
Controller
USB
Port
Display
Controller
Display
unit
Disk bus
Disk 1 Disk 2
LCD or
Touch
Screen
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27
Summary
Summary
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We learnt
Interfacing processor with memory,
ports and devices using system bus
System bus consisting of Address, data
and control buses
Latches, decoders and multiplexers
Interfacing using system bus at first
level and IO bus at second level
Multilevel interfacing
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29
End of Lesson 6 of Chapter 2
End of Lesson 6 of Chapter 2

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2008

Chapter-2 L6: "Embedded Systems - Architecture, Programming and Design",

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