1234

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 31, NO 6, NOVEMBEFUDECEMBER 1995

Space Vector Modulated Three-phase to
Three-phase Matrix Converter with
Input Power Factor Correction
LBsz16 Huber, Member, IEEE, and Du3an BorojeviC, Member, IEEE
Abstruct- Analysis, design, and implementation of the space
vector modulated three-phase to three-phase matrix converter
with input power factor correction are presented. The majority
of published research results on the matrix converter control
is given an overview, and the one, which employs s h e-
ous output-voltage and input-current space vector modulation,
is systematically reviewed. The modulation algorithm is theo-
retically derived from the desired average transfer functions,
using the indirect transfer function approach. The algorithm is
verified through implementation of a 2-kVA experimental matrix
converter driving a standard induction motor as a load. The
switching frequency is 20 kHz. The modulator is implemented
with a digital signal processor. The resultant output voltages and
input currents are sinusoidal, practically without low-frequency
harmonics. The input power factor is above 0.99 in the whole
operating range.
I. INTRODUCTION
N MANY ac drive applications, it is desirable to use a
compact voltage source converter to provide sinusoidal
output voltages with varying amplitude and frequency, while
drawing sinusoidal input currents with unity power factor from
the ac source, and having high regulation bandwidth, figh
efficiency, and noise above the audio range. In recent years,
matrix converters (MC s) have become increasingly attractive
for these applications because they fulfill all the requirements,
having the potential to replace the conventionally used recti-
fier/dc linWinverter structures. Matrix converters are single-
stage converters; they need no energy storage components
except small ac filters for elimination of switching ripples. Of
greatest practical interest are the MCs with three input and
three output phases (3@-3@). The 3@-3@ MC with an input
LC filter and an ac motor load is shown in Fig. 1.
Paper IPCSD 9540, approved by the Industrial Power Converter Com-
mittee of the IEEE Industry Applications Society for presentation in part at
the 1991 IEEE Industry Applications Society Annual Meeting, Dearbom, MI,
September 28-October 4, in part at ,IECON 92 - 18th Annual Conference
of IEEE Industrial Electronics, San Diego, CA, November 9-13, and in part
at the 1993 IEEE Applied Power Electronics Conference and Exposition -
APEC 93, San Diego, CA, March 7-12, with different titles. This work was
supported in part by theVirginia Center for Innovative Technology and the
Virginia Power Electronics Center University-Industry Partnership Program.
Manuscript released for publication May 12, 1995.
L. Huber is with Delta Power Electronics Lab., Inc., Blacksburg, VA 24060
USA.
D. BorojeviC is with the Bradley Department of Electrical Engineering,
Virginia Power Electronics Center, Virginia Polytechnic Institute and State
University, Blacksburg, VA 24061 USA.
IEEE Log Number 9414387.
The basic MC configuration with high-frequency (HF) con-
trol was originally introduced in 1980 [l]. Since then, MCs
have been subject of intensive research which mostly con-
centrated on two aspects: implementation of the MC switches
and the MC control.
The switches of the MC are four-quadrant switches
(4QSWs). As 4QSWs are not available to date, they have
to be implemented either by anti-parallel connection of two
voltage-two-quadrant switches (2QSWs) or by anti-series
connection of two current-2QSWs [23]. Safe commutation of
2QSWs cannot be achieved in only one step: A multi-stepped
switching procedure is recommended [5], [7], [23]. It requires
independent control of each 2QSW, as well as detection of
the load current or source voltage direction.
In t!is paper, most of the published research results on
the 3@3@ MC control [1]-[22] are given an overview. Only
a few of those provide for sinusoidal output voltages and
sinusoidal input currents without low-frequency (LF) har-
monics, with maximal voltage gain of &/2, and adjustable
input displacement factor (IDF). One of them, which uses
simultaneous output-voltage and input-current space vector
modulation ( S W) [lo], is systematically reviewed. A simple
geometric representation in complex plane of the modulation
process, used for the first time in [24], is given. The algorithm
is verified through implementation of an experimental MC [25]
with the following characteristics:
maximum output power 2 kVA,
9 output frequency range 0-167 Hz,
0 switching frequency 20 Wz,
* input r ms line voltage 3 x 208 V, 60 Hz, and
* input power factor above 0.99.
11. MC CONTROL PRINCIPLES
The simplified 3G-34, MC topology is shown in Fig. 2.
Since the MC is supplied by the voltage source, the input
phases must never be shorted, and due to the inductive nature
of the load, the output phases must not be left open. If the
switching function of a switch, s 3k in Fig. 2, is defined as
the constraints can be expressed as
0093-9994/95$04.00 0 1995 IEEE
HUBER AND BOROJEVIC: SPACE VECTOR MODULATED THREE-PHASE TO THREE-PHASE MATRIX CONVERTER 1235
a c c - v C ~ 0 v,, i A 0 - i A 1 0 0 0 0 1 0 0 1
b C C V bc 0 -Vbc 0 i A - i A 0 1 0 0 0 1 0 0 1
b a a -Vat,
0 vab - ! A
i A 0 0 1 0 1 0 0 1 0 0
'I-* c a a vca o -vca - 1 A o ! A o o 1 1 o o I o o
C b b -Vbc 0 V bc 0 -! A 1~ 0 0 1 0 1 0 0 1 0
a b b Vat, 0 - Vab i A - 1 ~ 0 1 0 0 0 1 0 0 1 0
c a c Vca - v C ~ 0 i g O - i g 0 0 1 1 0 0 0 0 1
C b C 'vbc vbc 0 0 i e- i e 0 0 1 0 1 0 0 0 1
a b a vab 'vab 0 - i g i g 0 1 0 0 0 1 0 1 0 0
b a b 'vab vab 0 i g - i B 0 0 1 0 1 0 0 0 1 0
a c a -vCa vca o - i g o i B 1 o o o o 1 1 o o
b C b V bc -Vbc 0 O - i B i e 0 1 0 0 0 1 0 1 0
c c a 0 vca -vca i c 0 - f c 0 0 1 0 0 1 1 0 0
a a b 0 vab 'vab - i c i c 0 1 0 0 1 0 0 0 1 0
'I-' a a c 0 .-vca vca - i c 0 i c 1 0 0 1 0 0 0 0 1
b b c 0 vbc 'vbc 0 - i c i c 0 1 0 0 1 0 0 0 1
b b a 0 'Vab vab i c - i c 0 0 1 0 0 1 0 1 0 0
a a a 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0
I 1 1 b b b 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0
c c c 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1
c c b 0 'vbc vbc 0 i C- I C 0 0 1 0 0 1 0 1 0
Fig. 2. Simplified 3@- 3@ MC topology.
phase currents. The switching combinations can be classified
into three groups. The first group includes six combinations
where each output phase is connected to a different input
phase. In the second group, there are 3 x 6 =18 combinations
with only two output phases shorted. The third group includes
three combinations with all three output phases shorted.
From Table I and Fig. 2, the following expressions for
the output line voltages and input phase currents are directly
Fig. 1. 36-3T MC topology
With these constraints, the 3@3@ MC switches from Fig. 1
can assume only 27 allowed combinations (see Table I). The
table also shows which input and output phases are mutually
connected for each allowed switching combination, as well as
the resulting output line (phase-to-phase) voltages and input
1236 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 31, NO 6, NOVEMBEFUDECEMBER 1995
obtained:
VOL =
and
where the superscript T denotes a transpose and the matrix
T phL is the instantaneous input-phase to output-line transfer
function matrix of the 3Q-34, MC. Alternatively, the output
phase voltages referenced to the input neutral and the input
phase currents can be expressed as
and
t i ] =TFhph ' i oPh (6)
i C
where the matrix T phph is the instantaneous input-phase
to output-phase matrix. In order to use the HF-synthesis
methodology, the switching frequency must be much higher
than the frequencies of the input voltages and output currents,
which are assumed to be continuous LF functions. Then, the
HF components of the variables in (3)-(6) can be neglected.
The low-frequency or local-averaged value of a switching
function silk is the duty cycle of the switch S3k, and it is
denoted as d 3 k . The LF equivalents of (1)-(6) are
respectively, where
are the LF input-phase to output-line and input-phase to
output-phase transfer matrices.
Let the input phase voltages be given by
if it is desired that the local-averaged output line voltages be
sinusoidal, i.e.
1
C OS ( W, ~ - po +30" +120") !
COS( W, ~ - +30")
C O S ( U , ~ - po i- 30" - 120")
(16)
C O S ( L J ~ ~ - yo 4- 30" +120")
then with the LF input-phase to output-line transfer matrix
chosen as
(17)
cos(wzt - cpz)
where 0 5 m 5 1 is the modulation index and pz is an
arbitrary angle, (15)-(17) satisfy (9) with
(18)
In this case, due to the inductive nature of the load, the output
line currents can be assumed sinusoidal, and hence given by
8
V,, =- . v,, ' m . cos(p,).
2
COS(^,^- yo - p~+30")
C O S ( W ~ ~ - p0 - ' p ~ +30" +120")
cos(w,t - yo - pL +30" - 120')
where ( pL is the load displacement angle at the output fre-
quency f,. If (17) and (19) are substituted into (lo), the
local-averaged input phase currents are obtained as
where
fi
4, =- . I,, . m ' C0 S ( c p L )
2
It follows from (18) that one can make a trade-off between
the modulation index, m, the voltage gain, Vo,/V,,, and
the input displacement angle, cpz, independently of the load
displacement angle. Unity input displacement factor is ob-
tained for cpz =0, which from (18), with m =1, also results
in the maximum voltage gain of 612. Physically, the only
restriction is the equality of the input and output active powers,
because from (18) and (21) it follows that:
n
6
2
(22)
-
- - . V", . I,, * COS(CpL) =Po.
By rewriting (16), (17), and (19) without 8 and 30"
and writing m/2 instead of m in (17), equations for
synthesis of output phase voltages can be obtained. In
HUBER AND BOROJEVIC: SPACE VECTOR MODULATED THREE-PHASE TO THREE-PHASE MATRIX CONVERTER
TABLE I1
OVERVIEW OF 3@-3@ MC CONTROL ALGORITHMS
INDIRECT TRANSFER FUNCTION APPROACH
Diode-Bridge-Rectifia / PWM-Inverter
(IDF =1)
Without compensation of
full-wave-rectified input-
line-voltages ripple
Sine-PWM with triangu-
lar carrier in VSI [4]
0 Modified Sine-PWM witl
triangular carrier in VSI
121, PI
With compensation of
full-wave-rectified input-
line-voltages ( Vd ripple
(A,, =&I21
Sine-PWM with amplitude-modu-
lated triangular carrier in VSI 151
VSI with Sine-PWM (or PWM wit
harmonic elimination) with duty
cycle proportional to 1 " [61
(includes also adjustableIDF)
0 VSI with space-vector-modulation
with duty cycleproportional to
1 " [71
VSI with hysteresis current control
l a 181
VSI with predictive current control
laP I
PWM-R~tifier /
SquareWave-Inv
0 VSRwith
modified Sine-
PWM [21, E31
DIRECT TRANSFER FUNCTION APPROACH
PWM-Rectifier I PWM-Inverter
(A,, =&I21
Adjustable IDF
- Simultaneous output-voltage and
input-current space-vector-
modulation [ 101
IDF=1
- Modified Sine-PWM in both
VSR and VSI 121, [3]
- Hysteresis current controller in
both VSR and VSI E111
- VSR with six-step PWM and VSI
with ramp-comparison current
controller [12]
Synthesis of output phase-voltages I Synthesis of output line-voltages
Output neutral connected
to input neutral
(A,,, =0. 3
RestrictedIDF
(IDF <ODF) [l]
Output neutral modulated
with respect to input neutral
(A.,,, =$1 2)
AdjustableIDP
- Injection of input and output 3rd
harmonics [131, [141, [151, [161
- Six-step PWM with extension to
unity duty-cycle [181
I DF=1
(Injection of input and output 3rd
harmonics) C171
Six-step PWM using two input line-voltages
(A,, = &/ 2 , IDF=1) [19]
Six-step PWM using threeinput line-voltages
Unrestricted frequency changers (UFC [20]) with PWM
(A,, =3/4, IDF =1) [19]]
( A.,,, <& / 2, IDF =f ODF, LF harmonics)
- UniformPWM with triangular carrier [21,[31
- Sine-PWM with triangular carrier [21]
- Clipped-Sine-PWM with triangular carria [21]
- PWM with selective harmonic elimination [22]
1237
this case, the maximal voltage gain is 314. Obviously, the
whole procedure from this section Can be repeated starting
from the input line voltages.
To make final a 3@3@ MC control algorithm using the
HF-synthesis methodology, two additional steps are needed.
A. Indirect Transfer Function Approach
Equation (17) presents an indirect transfer function (ITF)
approach. The transfer matrix is equal to the product of two
matrices
First, the switch duty cycles, d7k, which implement a desired TPhL =TVsI (uo) TTSR(wz). (23)
LF transfer matrix (e.g., (17)) and satisfy (7) and (8), have to
be determined. Second, the position of the switching pulses
within the switching cycle has to be defined.
By multiplication of the matrix T$SR(~,) with the input
voltage vector (15), a constant voltage is obtained
n
111. OVERVIEW OF 3@-3@ MC CONTROL ALGORITHMS
An overview of the published 3@-3@ MC control algorithms
is presented in Table 11. For the MC control, indirect and direct
transfer function approaches [2], [3] can be distinguished.
This is equivalent to the operation of a voltage source rectifier
(VSR). By multiplying the voltage (24) with the matrix
Tvs~(u,), the operation of a voltage source inverter (VSI)
1238 LEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 31, NO. 6, NOVEMBERDECEMBER 1995
Fig. 3. Emulation of VSR-VSI conversion
is performed. Therefore, the ITF approach emulates a VSR-
VSI conversion, as shown in Fig. 3. It follows from Fig. 3 that
at any instant the 3@-3@ MC reduces to one of the six possible
VSI subtopologies with V p n E {Vab, U&, Vca, vba, Vcb, Vac} .
It can be easily verified that for each allowed switching
combination in Fig. 3, there is only one switching combination
in Table 1 that results in the same output voltages and input
currents. This correspondence includes all combinations from
the second and third groups in Table I, and none from the first
group. The ITF approach enables application of well-known
standard VSI and VSR PWM techniques for MC control. In
the case of output line-voltage synthesis, the maximal VSI
voltage gain is equal to unity, and hence from (24) the maximal
MC gain is &/2. When sinusoidal output phase voltages are
synthesized, the maximal phase voltage amplitude is one half
of the dc link voltage, and from (24) the maximal MC gain is
314. In this case, the output neutral point voltage is equal to the
dc link midpoint voltage which varies as (V,,/4) . cos(3w,t)
with respect: to the input neutral.
The ITF control algorithms are distinguished according
to the place where PWM is used [2], [3]. En the Diode-
Bridge-Rectifier/PWM-Inverter group, the input characteris-
tics resemble the diode bridge characteristics (only in [6], the
IDF is adjustable). As a result, the rectified input voltage, vp,,
contains the 6f , ripple. If this ripple is not compensated, the
output voltages contain harmonics at 6f, f fo. With ripple
compensation, sinusoidal output line-voltages can be obtained
without LF harmonics and with maximal voltage gain of
a / 2 . In the group PWM-Rectifier/Square-Wave-Inverter
only the modified-sine PWM is analyzed in [2] and [3] as
an example within the ITF classification. It was shown that
the weak spectral characteristics of the square-wave inverter
also appear in the MC output Sinusoidal output voltages
with maximal voltage gain of 4 1 2 and sinusoidal input
currents, both without LF harmonics, can be obtained only by
employing PWM in both VSR and VSI. Control algorithms
[2], [3], [ll], and [12] are llmited to unity IDF. Only the
simultaneous output-voltage and input-current space-vector-
modulation [lo], presented in this paper, yields adjustable IDF.
B. Direct Transfer Function Approach
By multiplication of the VSI and VSR transfer matrices in
(17), a single matrix is obtained whose elements are sinusoidal
functions of (wo w,) . t. This leads to the direct transfer
function (DTF) approach. When synthesizing sinusoidal output
phase voltages with respect to the input neutral, the maximal
volltagegain is inherently limited to 0.5 (with adjustable IDF,
although in [l], it was restricted). The gain can be increased
to 3/4 by injecting the third harmonic of the input frequency,
(~,/4)-cos(3w2t), into the desired output phase voltages, and
it can be fwrther increased to &/2 by additional injection of
the third harmonic of the output frequency, (Vo/6). cos(3w0t)
[14], [26]. However, this is related to significant amount of
additional calculations, which is the principal drawback of
the DTE approach with synthesis of output phase voltages: It
synthesizes complex, nonsinusoidal output phase voltages and
then uses the output line voltages which are sinusoidal, instead
of directly synthesizing the output line voltages. When starting
from the input line voltages, by using all three of them in each
switching cycle, the maximal voltage gain is limited to 3/4
[19]. In order to achieve the maximal voltage gain of &/ 2,
~ d y two input line voltages should be used in a switching
cycle [19], which is also true for the ITF. However, unlike
the I TF, the DTF control algorithms employ the switching
combinations from all three groups in Table I, which makes
the essential difference between the two.
For the sake of completeness, one should mention a special
group of DTF control methods, called unrestricted frequency
changers (UFC), which employ the switching combinations
only from the first and third groups in Table I. The LF transfer
function of PWM UFCs contaips sinusoidal functions either
of (wo +w,) . t or of (wo - U,) . t , but not both, unlike the
normal DTF. As a result, LF harmonics exist in both output
voltage and input current spectra, and the IDF is restricted to
the positive or negative value of the output displacement factor
(ODF). Therefore, the UFCs are inferior to other control
methods.
Possibly the most satisfactory DTF control algorithm is the
six-step P W from [ 191, which also enables compensation
of asymmetrical and distorted input voltages, but the IDF is
limited to uni ty. With Sa-balanced input voltages, [ 191 yields
the same expressions for the duty cycles as the ITF control
algorithm [lo] with (pz =0. However, [lo] and [19] differ in
the distribution of the switching intervals within a switching
cycle. The control algorithms [ 101 and [ 191seem to be superior
to other control methods. The algorithm introduced in [lo] is
systematically reviewed below.
IV. SPACE VECTOR MODULATION
in this section, based on the ITF approach, the space
vector modulation is simultaneously employed in both VSR
and VSI parts of the MC. First, the VSI-SVM and VSR-
SVM procedures are reviewed, and the respective LF transfer
functions are derived. Then, the three steps of the HF-synthesis
of the simultaneous output-voltage and input-current SVM for
control of the 3@-3@ MC are performed. Finally, a simple
geometric representation in complex plane of the modulation
process is given.
A. VSI Output Voltage SVM
Consider the VSI part of the circuit in Fig. 3 as a stand-
alone VSI supplied by a dc voltage source, vpn =Vdc . The
HUBER AND BOROJEVIC: SPACE VECTOR MODULATED THREE-PHASE TO THREE-PHASE MATRIX CONVERTER
1239
Fig. 5. VSI SVM vector addition.
VSI switches can assume only six allowed combinations which
yield nonzero output voltages, and two combinations with zero
output voltages. Hence, the resulting output line-voltage space
vector defined by
can assume only seven discrete values, Vo - Vs in Fig. 4,
called voltage switching state vectors (SSV's).
The space vector of the desired output line voltages (16)
VoL =fi. V", . e3( wot - %+30)
(26)
can be approximated by two adjacent SSV's, V, and Vp, and
the zero voltage vector, VO, using PWM as shown in Fig. 5,
where V o ~ is the sampled value of V,L at an instant within
the switching cycle T,. Using the law of sines, the duty cycles
of the SSV's are
d, =T,/Ts =mu . sin(60' - e,,),
dp =Tp/Ts =mu . sin(O,,),
dou =To, / Ts =1 - d, - dp
(27)
where m, is the VSI modulation index
o I mu =(d3. Vom)/Vdc L I. (28)
The sectors of the VSI hexagon in Fig. 4 correspond directly
. . . .
-180 -120 -90 -30 30 90 150 180
w0t-cpO+30 [ O ]
Fig. 6. Output line voltage 60'-segments.
"CA t
Fig. 7. Synthesis of VSI output line voltages.
output line voltages shown in Fig. 6. The synthesis of the
output line voltages for a switching cycle within the first
60"-segment is shown in Fig. 7, as an example. The local-
averaged output line voltages are
GAB d, +dp
[5:] =[ 1; ] . v d c
- sin(O,,)
For the first 60"-segment
-30" 5 w,t - po +30" 5 +30' and
B,, =(w,t - p0 +30') +30".
(30)
By substitution of (30) in (29)
(31)
The matrix Tvs~, defined in (31), is the LF transfer matrix of
the VSI. Substituting the modulation index from (28) in (31),
1
COS ( U, ~ - +30")
C O S ( L J , ~ - 9, +30' - 120')
COS(U, t - p0 +30" +120')
- mu .
. Vd , [;;I - [
=TvsI ' vdc.
to the six 60"-segments within a period of the desired 3@ the desired output line voltages (16) are obtained.
1240 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 31, NO 6, NOVEMBER'DECEMBER 1995
The VSI local-averaged input current is determined as
&-
i, =TCSI . i,L F - ' I,, . m, . cOs(cpL) =const. (32)
B. VSR Input Current SVM
Consider the VSR part of the circuit in Fig. 3 as a stand-
alone VSR loaded by a dc current generator, i, =Id,. The
VSK input-current SVM is completely analogous to the VSI
output-voltage SVM. The VSI subscripts Q, /3, and SU are
replaced with the VSR subscripts p , U, and sc, respectively.
The VSR hexagon is shown in Fig. 8. The VSK duty cycles are
d, =T,/Ts =m, . sin(60" - Os,).
d, =T,/T, =m, . sin(@,,),
do, =Toc/Ts =1 - d, - d,
0 5 m, =Itm/Idc 5 1.
(33)
where m, is the VSR modulation index
(341
Examples of the local-averaged input phase currents, for a
switching cycle within the first sector of the VSR hexagon,
are
COS(O,~ - 30")
- sin(@,,)
By substitution of
Os, 1 ( wt t - yZ) +30, -30" 5 w,t - (pZ 5 +30"
(36)
for - the first sector in (35), the LF transfer matrix of the VSR,
TVSR, is defined as
(37)
Replacing the modulation index from (34) in (37), the de-
sired input phase currents (20) are obtained. The VSR local-
averaged output voltage is determined as
cos(w,t - Pz)
cos(w,t - cp, - 120") . Idc =TVsR . Id, .
cos(w,t - 9% +120")
- T
u p n TVs, ' VzPh
3
2
(38)
-
- - . m, . V,, . cos(p,) =const.
C. MC Output-Voltage and Input-Current SVM
As the local-averaged output voltage of the SVM VSR, (38),
and the local-averaged input current of the SVM VSI, (32), are
constant, from the local-averaged point of view the SVM VSR
and the SVM VSI can be directly connected. Substituting
from (38) for v d c in (31) and using TVSR from (37, the
same expression for the LF transfer matrix of the 3@-34, MC
is obtained as (17) with m =m, m,. For simplicity, it is
convenient to choose m, =1 and m =m,. This completes
the first step of the HF-synthesis procedure.
.-
Re
IO (ad or (b,b) or (c,c)
Fig. 8. VSR hexagon.
In the second step of the HF-synthesis procedure, the
modulation algorithm is derived from the LF transfer matrix
(17) in the same way as for the SVM VSI, (29)-(31), and
SVM VSR, (35)-(37), only in the opposite direction. Since
both the VSI and the VSR hexagons contain six sectors, there
are 6 x 6 =36 combinations or operating modes. If at a
particular instant, the first output-voltage 60O-segment and the
first input-current 60O-segment are active, then by using (30)
and (36), the LF transfer matrix (17) becomes
T
COS(O~, - 30") COS(@,, - 30')
(39)
Substituting (27) and (33) in (39), with m =mu . m,, the
local-averaged output line-voltages from (9) are
using
(41) 'vab =V,O - 2160
and
U,, =W,O - v,o
it is finally obtained
AB d,, +4, de, +dp,
[: E: ] [ 1;;; 1 ' " J a b +[ 1;;; ] . vue (42)
where
d,, =d, . d, =m . sin(60" - QSu ) . sin(60' - Os,)
dp, =dp . d, =m . sin(O,,) . sin(60" - e,,) =Tp,/T,,
d,, =d , . d, =m . sin(60" - QS,) . sin(@,,) =T,,/Ts,
dp, =dp . d, =m . sin(O,,) . sin(O,,) =Tp,/T,.
=T a p ITS,
(43)
As can be seen, the output line voltages are synthesized inside
each switching cycle from samples of two input line voltages,
"Jab and U,, for the above example. By comparison of (42) and
(29), it can be concluded that simultaneous output-voltage and
input-current SVM can be obtained by employing the standard
HUBER AND BOROJ EVIC: SPACE VECTOR MODULATED THREE-PHASE TO THREE-PHASE MATRIX CONVERTER
1241
TABLE 111
SWITCHING SEQUENCE EXAMPLE
Swi t c hi ng out put Input
SSV Combi nat i on ON Li ne Vol t age Phase Current S wi t c h St a t e s
Ti me
Pai r p n A B c V A B V B C V C A i a i b i c S Aa S Ab S Ac S Ba S Bb S Bc SCasCbS
11-V6 a c a c c dpv- Ts V a c 0 -vac i~ 0 -iA 1 0 0 0 0 1 0 0
I l - Vl a c a c a da, - Ts v a c - vac 0 - i ~ 0 iB 1 0 0 0 0 1 1 0
Io-Vo a a a a a d0-T. 0 0 0 0 0 0 1 0 0 1 0 0 I O
paper, the switching sequence d,, -+dp, + dp, + d,, --i
do is used, and the optimum zero SSV is chosen for each of
the 36 operating modes.
The synthesis of the output line voltage VAB waveform for
cpz =0' and cpz =30' is illustrated in Fig. 9. The waveforms
of the other two output line voltages, with opposite sign, are
also shown in the figure.
The input phase currents, for the above example, are syn-
thesized according to the following:
'- Tap
:: : r
4 - Tci"
5- To
E]
[ ' ! : , I ' ( - i B> + ['ii,] ' i A
+
[
] ' i A +[ d;" ] ' ( - i B) . (45)
-+U -&U
Fig, 9. Synthesis of 3@-3@ MC output ]]ne voltages for (a) p, =0 and
A Particular set Of five switching combinations is
(b) yt =30'. depending on the actual operating mode. By simultaneous
observation of the desired LF voltage vector in the MC inverter
VSI SVM sequentially in two VSI-subtopologies of the 3@-
3@ MC. When the standard VSI SVM is applied in the first
VSI-subtopology, where vpn =nab, the duty cycles of the two
adjacent voltage SSV's are d,, and dp,, as defined in (43).
The standard VSI SVM in the second VSI-subtopology, with
vpn =vac, results in the SSV duty cycles d,, and dp,, also de-
fined in (43). During the remaining part of the switching cycle
do =1 - d,, - dp, - d,, - dp, To/T, (44)
the output line voltages are equal to zero, by employing a
zero SSV. It is easily verified that with (38), the conditions
(7) and (8) are also satisfied. The duty cycle expressions (43)
remain the same for all operating modes. This completes the
second step of the HF-synthesis procedure.
In the third step, a switching sequence within one switching
cycle is defined. This requires decisions on which of the three
switching combinations from Group I11in Table I is used for
the zero SSV, and on how the five switching combinations
are ordered within the switching cycle. Among the possible
combinations, those which require switches to change state
only once during a switching cycle should be used. In this
hexagon, and the desired LF current vector in the MC rectifier
hexagon (see Fig. IO), the MC SVM procedure can be easily
followed. Note that the desired LF current vector magnitude
(21) is equal to the local-averaged input current of the fictitious
VSI, ( 32) , because m =m,.
For example, if at an instant V,L is in the first sector
of the MC inverter hexagon, the actual voltage SSV's are
V, =Vg and Vp =VI; and if i zph is in the first sector of the
MC rectifier hexagon, the actual current SSV's are I, =I6
and I, =11. Voltage-current SSV pairs are applied in the
following sequence: I6 - Vg, 16 - VI, I1 - VI, 11 - VS,
and Io - VO. To each voltage-current SSV pair corresponds a
switching combination with the on-time determined by (43), as
shown in Table 111. For example, while applying 16, it follows
from Fig. 10(a) that p =a and n =b. With simultaneous
application of v6, from Fig. 10(b), A =p , B =n, and C =p .
Therefore, the voltage-current SSV pair 16 - V6 is realized
with the switching combination A =a, B =b, and C =a,
which is kept ON for the time interval d,, . T,. On-times of
the individual MC switches can be determined from Table 111.
The table also shows the resulting output line-voltages and
input phase-currents.
1242
EEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 31, NO 6, NOVEMBERBECEMBER 1995
--c
Re
+
Re
V5 ( nm)
(b)
" CA
Fig. 10. 3&3@ MC: (a) rectifier hexagon and (b) inverter hexagon.
V. MODULATOR IMPLEMENTATION
The space vector modulator for control of the 3@-3@ MC
has to perform the following tasks:
synchronization with input phase voltages,
generation of phase angle of desired input phase cur-
rents,
generation of phase angle of desired output line voltages,
calculation of switching times (43),
conversion of switching times data to switching pulses,
and
distribution of switching pulses to 4QSW's.
The modulation algorithm can be most efficiently implemented
using a digital processing system.
Due to the nature of the SVM, all phase angles are repre-
sented with two variables: the code of the 60"-segment, s, and
the angle from the beginning of the 60-segment, 6'.
The block diagram of the modulator is shown in Fig. 11.
Through the three-phase step-down transformer, the input
supply voltages are interfaced with the comparators, which
generate the code of the input phase voltage 60O-segment
( s Wz ) . The tasks b) through e) are implemented within the
digital signal processor (DSP) block. The DSP block has three
input signals: svz, the input displacement angle cpz, and the
output voltage command. In general, cp, may be adjusted on-
line by a closed-loop control system in order to compensate the
phase shift caused by the input filter. In this work, cpz is given
as independent input data. The three-phase output voltage
command is normally provided by an external controller as
INPUT 3-PHASE 3-PHASE
VOLTAGE INPUT
PROT
PROTECTION
U
o V T [ ~ ~ ~ ~ . ~ E FROM OVER-CURRENT
Fig. 11. Modulator block diagram.
a two-dimensional vector, e.g., instantaneous amplitude and
phase (or frequency). In this work, a simple open-loop, V / f =
constant type of induction motor controller was implemented
within the DSP itself. It receives the motor speed command as
independent input data and provides the normalized amplitude
(rnodulation index), m, and the output frequency, f o , as the
output voltage command to the modulation process. The output
signals of the DSP block are: the PWM pulses, the operating
mode code, and the clock signal for the switch sequencers.
Finally, the decoder implements task f).
Input Voltage Comparators: The input voltage compara-
tors operate as sign detectors. The outputs of the compara-
tors directly represent the code of the input phase voltage
60"-segment, s,, . Standard integrated comparators are used.
Digital Signal Processor (DSP): In the development phase
a commercial, personal-computer based, DSP development
system [27]--containing a TMS320E14 processor, four A/D
converters, RAM, and additional circuitry-was used. The
TMS320Ef4 unit [2X] has a 16 x 16-b hardware multiplier
antdsix built-in PWM generators. All the tasks b) through e),
as well as the motor controller, are implemented in software
by using the assembly language.
The successive functional units of the DSP software are:
F1 initialize;
F2 read phase angle 9%;
. F3
F4
F5
F6
F7
F8
F9
F10 generate phase angle of desired input phase currents:
F11 calculate sin(B,,), sin(60" - Bsc) ;
F12 calculate switching times
wait for timer interrupt;
read motor speed command from AD;
implement V/ f =constant control;
generate phase angle of desired output line voltages:
calculate sin(B,,), sin(60" - Os u ) ;
multiply m . sin(@,,), m . sin(60" - Os,);
input s,, from input voltage comparators;
svo, o m ;
s a , Os&
Tl =Tm, ,
T2 =TcY/Lt Tpp,
T3 =Tap +Tp, t Tpv,
T4 =Tap t TpjL +Tpv +Tau; (46)
F13 output scr, s,, to decoder;
HUBER AND BOROJEVIC: SPACE VECTOR MODULATED THREE-PHASE TO THREE-PHASE MATRIX CONVERTER 1243
U
(a) (b)
Fig. 12. Flowchart of desired (a) output line voltage and (b) input phase
current angle generation.
F14 output TI through T4 and T, to PWM generators; and
F15 jump to F3.
The software is implemented as a single interrupt service rou-
tine, driven by the timer associated with the PWM generators.
The period of the PWM generators is equal to the desired
switching period, T5 =50 ps. The duration of the program
loop is about 35 ps. In the following, some details of the
modulator software are described.
The desired output line voltage phase angle e,, is coded as
osv =k . 3" +ae,,; k =0, 1, . . . 19,
AOs, =mod(O,,, 3"). (47)
The flowchart of the modulator software unit F6 is shown
in Fig. 12(a). Calculation of sinusoidal functions ( F7) is
achieved by using a look-up table with 3" resolution and by
linear interpolation between the table entries.
The phase angle of the input phase voltages and the input
displacement angle are coded as
Bs 0 =j . AOsz, j =1,2,. . , 56. (48)
and
cpZ =p . AB,,,
p 10, $1,. . . , zt55
(49)
respectively, where AOsz =360' . f , . T, =1.08'. The
flowchart of the modulator software unit F10 is shown in
Fig. 12(b). The sinusoidal functions 8'11are obtained by using
look-up tables, without interpolation.
Decoder: The switching pulses corresponding to the
switching intervals Tap, Top, Tovl T,,, and To are generated
from the PWM pulses synthesized by the DSP, using basic
logic operations. These pulses are distributed to the appropriate
TO MODULATOR INPUT
1 FILTER 1
PROT
c
OVER-VOLTAGE OVER-CURRENT
CURRENT DIRECTION
DETECTOR C
DETECTOR B
CURRENT DIRECTION
h A
- B
- C
m o
FROM MODULATOR
Fig. 13. 3@3@ MC block diagram.
4QSW's, depending on the operating mode code. The signal
PROT in Fig. 11 represents the overcurrent protection bit.
The decoder is implemented with one EP910 erasable PLD
chip [29].
VI. MATRIX CONVERTER
The block diagram of the 3@-3@ matrix converter is shown
in Fig. 13. Each block is described below.
Four-Quadrant Switches: The 4QSW's of the 2-kVA HF
matrix converter are realized with two anti-parallel voltage-
2QSW's which are implemented by series connection of the
BUK437 power MOSFET (600 V, 9 A) and the BYR29
fast recovery diode, as shown in Fig. 1. Across the input
connections of every three 4QSW's connected to the same
output phase, three 82-nF metallized polypropylene film HF
capacitors are connected in delta in order to eliminate the
wiring inductance influence.
Gate Drives: Each of the 18 2QSW's has its own gate
drive circuit, shown in Fig. 14. The control pulses from a
switch sequencer are transmitted through a high-speed opto-
coupler. An integrated MOSFET-gate-drive circuit amplifies
the opto-coupler signal to the appropriate level. The opto-
coupler and the 4429 circuit are supplied by on-board linear
voltage regulators. Only six isolated dc voltages are needed to
supply the 18 gate drives, as three 2QSW's are connected to
the same output or input phase. The common mode chokes,
L1 and L2, proved essential for the proper circuit operation.
Switch Sequencers: As the MC does not contain free-
wheeling diodes, whlch normally accomplish safe commuta-
tion of the converter switches, the effect of the free-wheeling
diodes has to be achieved by using the existing switches.
For safe control of the 4QSWs, a multi-stepped switching
procedure [ 5] , [7], [23] is used, which requires independent
control of each 2QSW, as well as detection of the load current
1244 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 31, NO. 6, NOVEMBEmECEMBER 1995
t Li
Fig. 14. Gate drive circuit schematic.
direction, but it operates without additional snubber circuits.
The safe commutation algorithm encompasses three 4QSW's
connected to the same output phase, and it is implemented
within the three switch sequencers. Three EP610 erasable PLD
chips [29] are used, one for each output phase. Each switch
sequencer has four inputs: Two represent the code of a switch
which has to be turned on, as requested by the modulator; one
is the clock signal from the modulator ( f c ~ ~ =6.25 MHz);
the last one is the current direction bit from the current
direction detector. The current-sign validity bit, proposed in
[7] is not used, because in this case experimentally it was
found unnecessary.
Current Direction Detectors: Through-hole type Hall cur-
rent sensors (100 A) are used with ten turns. The sensitivity
of the sensors was selected so that they can provide signals
which could be also used in a more complex closed-loop motor
control algorithm. The current direction signal is obtained with
standard voltage comparators.
Overvoltage Protection: A three-phase full-bridge diode
rectifier with a clamp-capacitor is connected across the output
phases. It acts as a voltage clamp for possible voltage spikes at
the output lines. A small resistor between the diode-bridge and
the capacitor provides critical damping to the circuit comprised
by the clamp capacitor and the wiring inductance, and limits
the maximum clamping current. A resistor in parallel with the
capacitor acts as "bleeding" element for the clamp capacitor.
Overcurrent Protection: Connection type Hall current sen-
sors (20 A) are used. Two three-phase half-bridge diode
rectifiers produce dc voltages proportional to the instanta-
neously most positive and most negative three-phase input
currents. Positive and negative overcurrents are detected with
two standard comparators. To make the overcurrent protection
circuit insensitive to very short overcurrent spikes, a delay
circuit and a third comparator are added. The overcurrent is
registered by a flip-flop, which causes the modulator to shut
down the matrix converter by forcing it into zero input current
and zero output voltage state, until resetting.
Znput Filter: A 3@ single-stage LC filter is used. It consists
of three 5-pF (400 Vdc) metallized polypropylene capacitors
in star-connection, and three 5-mH inductors. As in any buck-
type converter, the input currents are discontinues, so that
high-quality capacitors with low ESR and high current rating
are required.
2 ms/div 2 ms/dlv
Fig. 15 Experimental waveforms with unloaded dc generator (fo =80 Hz)
(a) input phase voltage (SO V/div), (b) filtered input phase current (1 Aldiv),
(cl output line voltage (200 V/div); and (d) output phase current ( 5 A/div).
The matrix converter output is fed to a standard
3 x 208 V/11 A (60 Hz) squirrel-cage 3-hp induction
motor, which is mechanically coupled to a low-inertia
permanent magnet dc generator used for loading.
VII. EXPERIMENTAL RESULTS
The experimental steady-state waveforms with unloaded dc
generator are shown in Fig. 15. The input and output phase
currents are mostly sinusoidal. Without the input displacement
factor correction ( c p , =OO) , the filtered input phase current
leads the input phase voltage due to the capacitive nature of
the input filter at 60 Hz. The phase angle between the first
hamonics of the input phase current and input phase voltage
is 16O, the total harmonic distortion of the input phase current
is THD, =8.5%, and the input power factor is PF, =0.958.
The input displacement factor can be corrected by introducing
a ]phase lag cpz =16" at the modulator input, which results in
THD, =10.5% and PF, =0.995.
The experimental waveforms for 75% load are shown in
Fig. 16. The input and output phase currents are again mostly
sinusoidal, and the input phase current is practically in phase
with the input phase voltage. The input power factor is PF, =
0.997. In general, when the load is above 50%, the capacitive
component of the input filter current is negligible compared
to the total input current so that the input displacement factor
correction is not necessary, i.e., cp, =0" can be used.
Hence, if the input current phase shift cp, is adjusted
according to the load level, input power factor PF, >0.99
is achieved in the whole operating range.
The measured efficiency is between 90 and 93% in the
load range 50-100%. The power density of the experimental
prototype is 8.5 kVA/ft3 including input filter.
VIII. CONCLUSION
In this paper, control and design of the 3@-3@ MC are
described. The 3@-3@ MC output-voltage and input-current
SVM algorithm is systematically reviewed. A simple geomet-
HUBER AND BOROJEVIC: SPACE VECTOR MODULATED THREE-PHASE TO TI
(a)
( b)
2 ms/dlv
Fig. 16. Experimental waveforms with 75% load: (a) input phase voltage
(100 V/div); (b) filtered input phase current (2.5 A/div); and (c) output phase
current (5 A/div).
ric presentation in complex plane of the 3@-3@ MC SVM
procedure is given. This schematic approach enables clear
comprehension of the modulation algorithm. Implementation
of a compact, high-performance, high-frequency 3@3@ MC
for ac drive applications is presented. The MC switches are
realized with power MOSFETs and fast recovery diodes.
For safe control of the MC switches, a multi-stepped switch-
ing procedure is used, which does not require any snubber
circuits. The space vector modulator is implemented using
a commercial, personal-computer based, DSP development
system. However, the modulator could be implemented using
no more than three integrated circuits: a data acquisition
circuit, a DSP, and a PLD for implementation of the decoder.
Since the duration of the active program loop is about 35 ps
within a sampling period of 50 ps, additional protection and
diagnostics can be built in. A closed-loop input-displacement-
factor correction can be easily achieved by adjusting the
input current phase shift according to the load level. The
experimental output voltages and input currents, obtained with
balanced and undistorted input source voltages, are sinusoidal,
practically without LF harmonics. Maximal voltage gain of
&/ 2 is achieved, and the input power factor is above 0.99
in the whole operating range.
Further work can include:
investigation of the MC operation with unbalanced and/or
9 investigation of transient behavior, and
investigation of parallel operation of several MCs for
nonsinusoidal input voltages,
higher power applications.
ACKNOWLEDGMENT
The authors would like to thank Prof. X. F. Zhuang for
building the experimental matrix converter, and Dr. F. C.
Lee, without whose support this work would never have been
completed.
3REE-PHASE MATRIX CONVERTER
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L6szl6 Huber (M86) received the B S degree
fromthe Umversity of Novi Sad, Yugoslama, the
M S degree from the Umversity of NiS, and the
Ph D degree from the Umversity of Novi Sad, in
1977, 1983, and 1992, respectively, in electncal
engineenng
From 1977 to 1992, he was an Instructor at the
Institute for Power and Electromcs, Umversity of
Nom Sad In 1992, he joined the Virgima Power
Electronics Center, Virgima Polytechnic I nst
and State University, Blacksburg, as a visitlng pro-
fessor From 1993 to 1994, he was employed as a research scienbst at the
Virginia Power Electronics Center Since 1994, he has been working as a
senior design engineer at Delta Power Electronics Lab., Inc., Blacksburg, VA.
His experience includes dc-dc converter circuits, three-phase direct power
conversion, and digital control electronics His current research is focused
on power conversion and management issues for portable equipment, and
design optimzahon for low-voltage power supplies He has published over
40 technical papers
DuSan BorojeviC (S80-M86) received the B S
degree fromtheUniversity of Belgrade, Yugoslavia,
the M.S. degree from theUniversity of Novi Sad,
Yugoslavia, in 1976 and 1982, respectively, and
the Ph.D degree from Virginia Power Electron-
ics Center, Virginia Polytechnic Institute and State
Umversity, Blacksburg, in 1986, all in electrical
engineering
From 1976 to 1982, he was an Instructor at the
Institute for Power and Electronics at the University
of Novi Sad. Between 1986 and 1990, he was
an Assistant Professor and founder of the power and industrial electronics
research program, and served as the Acting Department Head Since 1990, he
has been an Associate Professor at Virginia Polytechnic Institute and State
Umversity, and a member of the Virginia Power Electronics Center His
research interests include multi-phase power converters, high-power PWM
conversion, applied control, and electncal drives He has published over 60
technicd papers, has oneU.S. patent and two patents pending, and has led
over 20 sponsored research projects
Dr. Borojevit is a member of IEEE Power Electronics Society AdCom,
IEEE Industry Applicallons Society Industrial Drives Comttee, and Phi
Kappa Phi