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Doppler Systems
111 E. Moon Valley Drive
Phoenix AZ 85022
A U.S. Patent is pending on the direction-finding system described in this article. For further information, contact the author.
adio direction-flnding phase modulation, Doppler- built one of the earliest and utilized the more so-
* (RDF) systems tend to type systems generally are adaptations of this system phisticated TTL and CMOS
fall into two general cate- less sensitive to site errors for amateur use. That sys- integrated circuits then
gories depending on than amplitude measure- tem employed 16 switched becoming available.
whether or not they use the ment systems. The first antennas housed i n a
known RDF based on de-
A serious drawback to
Doppler shift principle 4-foot-diameter wooden
these systems was the dras-
Most non-Doppler RDFs tecting the Doppler shift "hat box" and was used suc-
tic loss in sensitivity which
employ directional anten- was p a t e n t e d b y H.T. cessfully in local trans-
occurred during operation.
nas which produce peaks or Budenbom and used a mitter hunts during 1970-
A second problem which
nulls in the received signal motor driven antenna. Dop- 1972. The antenna itself
was equally vexing was the
amplitude as they are rotat- pler RDFs today do not was heavy (115 pounds) and
appearance of mysterious
ed. Doppler-type systems, mechanically rotate an the system required an ex-
false bearing vectors appar-
on the other hand, detect antenna, but instead rely on ternal oscilloscope for dis-
ently due t o off-channel fre-
the phase modulation im- sequential switching be- play. DTL logic was used.
quencies being shifted onto
parted t o the received tween a series of antennas Other systems were subse-
the received frequency by
signal by translational mo- placed in a circular array t o quently built in the Phoenix
something in the commuta-
tion of the receiving anten- approximate the continu- area which operated on
ously rotating single ele- tion (electrical rotation)
na. As a consequence of the essentially the same basis
"capture effect" of the FM ment. process. Both of the above
but incorporated improved
problems would disappear
receiver which detects the In 1969, W7KWB and I mechanical construction
whenever the antenna com-
mutation was halted, i.e.,
on-channel stations would
immediately regain their
signal strength into the
receiver and off-channel
carriers would disappear.
Several techniques were
tried unsuccessfully to
eliminate these problems.
Theorizing that the sw~tch-
ing transients related to
turning on and off the
various antennas were
causing receiver desen-
sitizat~onand, in additron,
were m o d u l a t i n g off-
channel signals into the
receiver passband, several
methods were investigated
t o smooth out the sw~tching
transients These included:
Photo A. Fully expanded version of the electronics available in kit form from Doppler (1) overlapping the anten-
Systems. na selection so that at least
OPTIONAL
SERIAL
INTERFACE -
-FSK OUTPUT
FSK INPUT
I
EQUATIONS I
I
I I
I
, Equation (1): ER = A sin (wct + Y) Equation (8): Phase at S = Ys = Yc + ( Y or~B -Yc or D)
+TO
TO FET
By combining the MOSFET Fig. 70. R f gain variation with control gate voltage for four
rf gain characteristic of Fig. typical field-effect transistors. The curve is a seventh-order
Rd S.,mmer
10 with the desired antenna polynomial fit to the measured data.
?\.;2 circuit to be used for gain variation given in Fig.
antenna summing should 5, the control voltage wave-
provrde a low insertion loss, form for antenna A can be are modified by adding a 0, converter is used with a
pro..;ide a stable and elec- found. This is plotted in Fig. I , 2, and 3 sequentially t o CA3240 BlMOS operational
tronically-controlled gain 11. The control waveforms each of the PROM ad- amplifier t o minimize off-
characteristic, have negligi- for channels 6, C, and D are dresses using a CD4008 full set and noise. The CD4051
ble phase-shift variation i d e n t i c a l in shape, b u t adder. The resulting ad- is an 8-channel analog de-
with the control voltage, be delayed by 90,180, and 270 dress is held temporarily in multiplexer which directs
compatible with a 50-Ohm degrees respectively. the 8-bit 74LS273 latch the converter output into
unbalanced input, and lend which synchronizes the one of the four dual-gate
itseif to operating into a otherwise skewed output of MOSFETs. A small RC filter
50-Ghm unbalanced out- Control Voltage the ripple counter. formed by the 10-kilohm re-
put. Waveform Generator Together, the two 745287 sistors and 470-pF capaci-
P i N diodes and voltage- Two inexpensive PROMs PROMs provide an 8-bit ad- tors in the rf summer is suf-
controlled FET resistor are used t o store the wave- dress by &bit output mem- ficient to hold the demulti-
devices were tried and form plotted in Fig. 11. The ory for the control wave- plexed control voltage be-
eventually rejected for one PROM address is multi- form. Each address corre- tween updates. N A N D
or inore incompatibilities plexed in multiples of 90 sponds to 3601256 or 1.40625 gates A and B are used t o in-
with the above require- degrees commutation an- degress of commutation, hibit the demultiplexer ex-
mer;is. The dual-gate MOS- gle, and the PROM output, while the output is scaled cept during that portion of
FE'T operating in a com- after conversion t o an t o cover the range - 2.5 t o the cycle when the D/A out-
mon-source configuration analog voltage, is demulti- +3.5 volts dc which pro- put is stable. They also pro-
waz found t o provide an ex- plexed at the same time so vides a resolution of 6.01256 vide the synchronizing
ceiient choice. Fig. 8 shows that the entire PROM mem- = 0.0234 volts/step. The pulse to the 74LS273 octal
the circuit configuration. ory is utilized t o generate MC1408 digital-to-analog latch.
-- each of the four control
i he rf equivalent circuit
voltages. Fig. 12 shows the
is given in Fig. 9. Each
schematic of the control
MOSFET acts as a current
voltage waveform genera-
source into a common out-
tor.
put impedance. The single,
tapped inductor is used t o The CD4040 is a 12-stage
cancel the combined out- ripple-carry binary counter
put susceptance of the four that produces an &bit incre-
MCSFETs. Device input im- menting address t o the
pedance is extremely high, PROMs. When driven at a
and the circuit is broad- frequency of 1,228,800 Hz,
banded by the use of rela- the PROM address will cy-
tively low value resistors cle at a rate of 300 Hz,
for iine impedance termina- which is the commutation
tion at all inputs and the frequency of the system. To
output. Some gain is lost, multiplex the PROM, the Fig. 11. FET control voltage required to produce the ampli-
but i t is quite acceptable two most significant bits tude variation shown in Fig. 5.
Audio Signal Processor to the phase of this signal and t o blank the display t o 10. Frequencies below
Fig. 13 shows the circuitry for the display generator. when no signal is present. 142 Hz are attenuated by
used t o extract the 300-Hz Threshold detectors are the input filter and frequen-
Doppler modulation fre- also provided t o give an Preamplifier A is ac cou- cies above 664 Hz are
quency from the receiver's overload i n d i c a t i o n t o pled t o the receiver and reduced by the feedback
audio output and generate assist in setting up the contains a gain adjustment compensation. Amplifier B
a logic signal synchronized audio gain of the circuit variable over the range 0.2 provides an additional gain
Fig. 13. Audio signal processor circuit schematic. Notes: A l l op amps are 112 LM1458 except H, which is 112 CA3240.
diodes are 1N4148. Logic power is Vdd = +5, Vee = - 6, Vss = Op amp power is $ 5 and - 6 V dc.
74C903.
NOR gates are 1/4 CD4001. Inverters are 116
blanking delay of approxi-
cuit determines the speed mately I 0 0 milliseconds i s
of response of the system as provided by the electrolytic place of Fig. 14. This circuit Selection of the system
weii as the selectrvity, a capacitor. is designed for compatibil- clock frequency and divid-
track-off can be made in the ity with the optional serial ers was made so as t o pro-
selection of resistor R. The Display interface t o be described duce compatible binary
value shown provides a The circuitry required for below and uses a 4-bit data and BCD counter frequen-
g o d compromise, but indi- a simple LED display is bus to transfer data be- cies. Over a complete com-
vidual users may prefer a shown in Fig. 14. Two one- tween temporary holding mutation interval of 11300
somewhat faster or slower shot circuits are used t o registers and the display second, the 4-bit binary in-
responding display. The convert square wave sync latches. If the serial inter- put to register R will incre-
one-shot f o r m e d w i t h signal S to a short positive face is omitted, the two sig- ment through 24001300 X 2
NAiiiD gate L is used to in- clock pulse which is used t o nals SEND and MS must be = 16 counts. Each of these
hibit switching of the l a t c h the binary clock tied to logic ground. counts then corresponds to
muitiplexer during transi- count into the 74LS75 quad BCD counter latches H, I, 1116th of a revolution on
tior; of its logic-select in- latch. The first one-shot has and j are driven by a the LED circular display.
puts. an adjustable delay time t o 108,026-Hz clock signal and Over the same time inter-
i?mplifier F provides an permit calibration of the their contents are latched val, the clock input t o the
ditional gain of 10 and display over a 90-degree into tri-state latches 0, P, BCD counters generates
Ips t o attenuate harmon- bearing angle. (Rotation of and Q by the delayed sync 108026.3736/300 = 360.
produced in the com- the four antenna inputs is pulse. The binary clock 0879 counts, or approxi-
utative filter above 796 used for greater correction.) count is simultaneously mately one count per de-
z. Ac coupling is used t o The second one-shot gener- strobed into latch R by the gree. Although the error is
tenuate frequencies be- ates the 10-microsecond same sync pulse. Since the very small (less than 0.1
%rai I 6 9 Hz because the latching pulse. maximum count is (deci- degree), it will accumulate
ornmutative filter does mal) 359, the maximum rapidly unless the BCD
A 74154 decoder drives
ass dc. Amplifier H i s used BCD count required for the counter is periodically syn-
the 16-LED circular display
s a comparator t o produce hundreds digit is 3 (binary chronized back t o the
directly. Two additional
square wave sync signal 0011). Since the two most binary counter. The circuit
LEDs are used to indicate
or the display generator. A significant bits of this digit consisting of flip-flop A and
audio overload in the signal
83240 operational amplifi- are always zero, these bits the surrounding gates i s
processing circuit and the
is used here instead of are used to transfer the used to reset the three BCD
power-on status.
LMl458s used else- overload (MSB) and the counters every complete
ere for its very high slew When b o t h LED and display enable (MSB-I) in- cycle (as defined by the bi-
ate. Ac coupling is em- three-digit decimal bearing formation. A one-shot is nary counter) so that the
loyed t o remove any dc readouts are required, the used t o stabilize the over- BCD and binary counts re-
ffsets from the previous circuit of Fig. 15 i s used in load flag for sampling. main synchronized.
Fig, 15. Schematic of the circuit used to provide circular LED display and a threedigit decimal display. A data bus tech-
nique is employed which is compatible with the optional serial interface. Notes: Connect Cbit data bus *. All LED§
+
MIL32 R. Digital logic power is Vdd = Vcc = 5, Vss = CND = V A l l NOR gates are 1/4 CD4001. All inverters are
CD4069 e x c e p t b are 116 74C903. Schematic is drawn for operation with serial interface. For no serial interface, add
jumpers SEND t o p MS t o v
776. Optional seriai interface circuit schematic. Notes: NOR gates are 7/4 CD4007. Inverters are 716 74CW3. Digital logic
Power is k c = Vdd = +5, Vss = C N D = v A m p l i f i e r H power is 1- 73 switched (sw]; ground s
iv
73 Magaz~ne June, 1981 41
1200 Hz when the UART coupled through the RC cir- 74LS197 i s used t o divide mately - 8 V dc at the in-
output is "0" or 2400 Hz cuit shown to the second the 9.8304-MHz clock fre- put t o a 7906 regulator. The
when the UART output is a channel for simultaneous quency by 8 t o generate - 6 V dc is used as the
"1". Sine-wave distortion is recording. On playback, 1.2288 MHz for the antenna negative analog supply
below 5% with this arrange- this audio is amplified by control waveform genera- voltage.
ment, and the FSK frequen- the LM380 (amplifier H) to tor and binary display. Two Operational amplifier K
cies are as accurate as the drive a loudspeaker so that 74LS193 counters are con- generates the +2.0 V dc
system clock (which is bearing data can be easily nected t o divide the clock reference used for D/A con-
crystal controlled). correlated w i t h the re- frequency by 91 t o generate version and threshold com-
When the system is in the ceived signal. 108026 Hz for the BCD dis- parison.
remote data display mode, play. Gates F and C and the
FSK input i s demodulated 74LS74 flip-flop are used t o Electronics Construction
Power Supply and Clock
in the XR2211 decoder, C. load a count of 256-91 = If you wish t o build the
The c o m p o n e n t values The entire system is de- 165 into the two 4-bit count- electronics from scratch,
shown are optimized for signed to operate from a ers. If the BCD display is not your best bet is t o use wire-
300-baud, 1200/2400-Hz op- single unregulated supply used, ICs D, E, and H may wrap sockets for all of the
eration using the procedure voltage between 11.5 and be omitted. DIP integrated circuits and
given in EXAR's specifica- 14.5 V dc negative ground A 7805K regulator pro- the discrete components
tion sheet for the XR2211. for mobile operation. Total
input current is approxi-
vides + 5 V dc for the digi- (resistors, diodes, and small
The audio c i r c u i t r y tal logic, operational ampli- capacitors). Individual wire-
shown at the top of Fig. 16 is mately one Ampere with fiers, and the displays. The wrap pins may be used for
included as a convenience the display enabled. Fig. 17
shows the power supply
7808 regulator provides + 8 the larger components such
when using the system with V dc for the MOSFETs used as the electrolytic capaci-
a two-channel tape record- and clock circuits. in the rf summer. tors. All circuitry except the
er FSK data can be placed Gates A and B are con- Negative voltage is gen- rf summer may be con-
on one channel, and the nected for linear operation erated by a switch~ngIn- structed on open perforated
rece~vedaudio out of pre- and form a crystal-con- verterlvoltage doubler cir- board w ~ t h0 1 " spacing t o
a m p l ~ f ~ e rinAFig 13 can be t r o l l e d o s c i l l a t o r The cult that produces approxi- accept the wire-wrap
sockets Be sure to bypass
+5
the + 5 V dc using 047- o
I-uF disc ceramic ca
74LS197 51K
114 74LS02 tors near each of the
ICs a n d t h e CD45
to use 5% resistors an
either mylar or dipped mic
capacitors for all of th
a u d ~ of ~ l t e r ~ nand
g dig~ta
must be mounted In
shielded enclosure usln
=v
Fig. 77. Schematic of the power supply and clock circuitry. Notes: Power to LM74.58 is + 5 and - 6 V dc. Logic power is
Vcc = +5, CND
L 4
Fig. 19. Construction detail o f the short radial. Four are re- DRILL
5/32
HOLE
A 10 5/16
q::ired. 11/64 B
17/64 C
Antenna Construction
The antenna array must
contain four identical ele-
ments located in the cor-
ners of a sauare arrav hav-
ing sides less than on'e-half
wi.,velength. Analysis shows,
ho~vvever,that the best per-
formance can be expected
with an array size between
1/14 and 5/16 wavelength.
Each element must be ver- DRILL HOLE
5/32 A 1 518
ticaily polarized and non- 11/64 B
17/64 C
directional in t h e hori- 112 D
& LOCKWASHERS
K;
"4(i) 8 - 3 2 H E X NUTS
4 !-,I.
1 112
SHORT RADIAL
II!!~ SPACER
FLAT WASHER
( 3 ) X 6 LOCKWASHERS
( 3 ) 6 - 3 2 H E X NUTS
Fig. 28. Radial element assembly. 'The eye bolt and suction
cups are required only for car mounting. Allow the receiver and di- The direction-finder bear-
rection finder to warm up ing coutrol should then be
before making final calibra- adjusted so that the correct
i$Aark the phono jack indicated in Figs. 31 and 32. adjustments, however. bearing is displayed for a
ends of the coax cable "A", Bearing data and receiver After setting the re- known transmitted signal,
"B", "C", and "D" accord- audio may be recorded si- ceiver~s volumecontrol,the D~ not use a nearby handie-
i &! to Fig. 29. Mark antenna
n multaneousl~as shown in direction-finder gain adjust- talkie for this calibration as
"A" also for ease in aligning Fig. 31. Virtually any audio merit is made, Increase the local reflections are sure t o
tape recorder is adequate gain until the overload LED result in an error. A repeater
Installation and Adjustment this because flashes on voice peaks. (If station which is within the
the low baud rate and this adjustment is very low, line of sight of the antenna
primary power require- wide FSK shift used for the display will remain makes the best calibration
ments for the electronics i s serial data transmission. A blanked,) setting isnot criti- source, changing channels
11.5 to 13.5 V dc negative stereo system i s recom- cal, but the overload LED will have very little effect
at 1 Ampere maxi- mended so that the m r m a l should blink with a duty cy- on system calibration, so
mum. Ordinary 12-V dc receiver audio (voice) infor- ,-le between about 10 and any convenient station
automobile battery power mation may be recorded 50 percent during normal within the band may be
ma.4 be used, or, for fixed with the bearing data. speech. used. The display should be
operation, an inexpensive , ,T systemsmay be con-
12.5-V dc power supply nected as shown in Fig. 32
be used, such as Radio for remote data display, A
Shack Model 22-127. switch could be installed at
System interconnection the central site to enable a
without the serial interface single monitor point t o
is particularly simple as in- display the bearing data
dicated in Fig. 30. While the received at two or more ELECTRONICS
external speaker connec- remote sites for triangula-
------------
calibrated t o display bear- D; or Ant. D, Ant. A, Ant. B, cur, then set the control were generally well within 5
ing relative t o magnetic Ant. C; or Ant. C, Ant. D, midway between these set- degrees except when the
North in a fixed station set- Ant. A, Ant. B; or Ant. B, tings. I f valid data is re- transmitted audio was un-
u p and should correspond Ant. C, Ant. D, Ant. A. See ceived u p to one of the u s u a l l y l o u d o r deep-
t o straight ahead in a Fig. 8 for definition of an- ends of the control adjust- voiced. Even in those cases,
m o b i l e application. The tenna inputs to rf summer ment, use the end point as better bearing data could
calibration range of the and Fig. 29 for the defini- the invalid data point. The be obtained by mentalby
bearing control is approxi- tion of antenna elements. setting of this control i s not averaging the displayed
mately 90 degrees. I f the very critical. data.
system needs further cor- If the serial interface op- Accuracy tests have been Field testing has occured
rection, either rotate the an- tion is t o be used, the performed using fixed-sig- over the past year using the
tenna physically or switch receive frequency adjust- nal sources and a fixed-re- system competitively in lo-
the antenna inputs t o the ment can be made b y re- ceiving site t o eliminate cal transmitter hunting. The
electronics. Be sure not t o cording a few minutes of changing reflection paths. success record achieved t o
reverse the order of anten- data, then playing i t back in The antenna was rotated o n date has been very impres-
na rotation, however. The the Remote Display Mode a calibrated turnstile and sive considering the highex-
acceptable combinations while making this adjust- errors measured between pertise in transmitter hunt-
for inputs A, B, C, and D are: ment. Note the control set- the true bearing and the ing which exists in the
Ant. A, Ant. B, Ant. C, Ant. tings where invalid data oc- displayed bearing. These Phoenix area. B
46 73 M a g a z ~ n e* June, 1981