UNIVERSITY OF GUYANA

FACULTY OF TECHNOLOGY
DEPARTMENT OF ELECTRICAL ENGINEERING







Name: Frederick Cort
Reg.#: 11/0935/2437
Course: ELE 3204
Lecturer: Mr. Jomo Gill
2013/27
th
/Mar.
Aim : To Design and Simulate a Sample and Hold Circuit using a sinusoidal input to
observe the operation

Theory: The sample and hold circuit, as its name implies, samples an input signal
and holds on its last sampled value until the input is sampled again. For an analog
signal to be processed by a digital system, it must be converted to a digital signal
(discrete-time and discrete-amplitude). A sample and hold circuit makes it easier
for us to record the amplitude at each sample by holding the signal for a short
period of time at a given amplitude. Two important properties of a sample-and-
hold circuit are the highest possible sampling rate and how constant the sample
remains during the hold interval. Sample and hold circuits are commonly used in
analogue to digital converts, communication circuits, PWM circuits etc.

Components used:
Voltage Sources (Sinusoidal Input and Sample Signal)
2 100 Resistor
1 0.1F Capacitor
1 741 OpAmp
1 N-channel EMOSFET (BS170)
1 Oscilloscope







Sample and Hold Circuit





Diagram showing the sample and hold circuit with oscilloscopes connected




Simulation Results:

Diagram of Input Waveform

Diagram of Output Waveform

Diagram of the Input and Output Waveform

Sampler and Capacitor Waveform
Discussion :
In the above shown circuit the MOSFET(BS170) works as a switch while the
opamp 741 is wired as a voltage follower, the signal to be sampled (Vin) which
has a peak voltage of 1V is applied to the drain of MOSFET while the pulse voltage
(Vs) having a state of either 5V or 0V to turn on and off (respectively) the MOSFET
is applied to the gate of the MOSFET. The source pin of the MOSFET is connected
to the non inverting input of the opamp through the resistor R1. The capacitor
(C1) serves as the charge storing device and resistor (R2) serves as the load
resistor.
During the positive half cycle of the Vs, the MOSFET is ON which acts like a closed
switch and the capacitor C1 is charged by the Vin and the same voltage (Vin)
appears at the output of the opamp. When Vs is zero the MOSFET is switched off
and the only discharge path for C1 is through the inverting input of the opamp as
a result the voltage Vin is retained and it appears at the output of the opamp.
The time periods of the Vs during which the voltage across the capacitor (Vc) is
equal to Vin are called sample periods (Ts) and the time periods of Vs during
which the voltage across the capacitor C1 (Vc) is held constant are called hold
periods (Th).









Conclusion
To conclude this exercise the lab experiment done I better understood the
principle operation behind the sample and hold circuit as a result of designing the
circuit. Also learnt from this experiment it was experience that varying the
component values altered the output waveform to a great extent and as such
precise calculations are needed in the design or the trial and error method to
which I resorted to obtain the expected output. This experiment was very
beneficial in understanding how the circuit works in a practical basis.
















References

http://www.circuitstoday.com/sample-and-hold-circuit

http://www.ece.vt.edu/ece3274/compare_sh.pdf

http://s.eeweb.com/members/floy_viola/answers/1355193178-SAMPLE-AND-
HOLD-CIRCUIT-USING-OP-AMP-741-_-MY-CIRCUITS-9.pdf