UNIVERSIDAD NACIONAL AUTNOMA DE MXICO

FACULTAD DE INGENIERA
Arquitectura de computadoras
PROYECTO: Simulacin e Implementacin de una mquina de estados.




Carta ASM propuesta


Memoria de microprograma
Estado Actual Liga Prueba MI Salida
000 *** ** 000 0001
001 *** ** 001 0100
010 010 00 010 1001
011 001 11 100 0101
100 000 ** 110 1111
101 011 01 010 1100
110 011 11 101 0001
111 110 10 011 0010

Simulacin




Cdigo fuente
Placa.vhd
----------------------------------------------------
-- Arquitectura de computadoras
-- Proyecto: Simulacin e implementacin de una
-- mquina de estados de tercer estado.
-- Grupo:
-- Integrantes:
-- Pajarito Vargas Antonio
-- Zurita Garca Fernando Daniel
----------------------------------------------------
-- Placa.vhd
-- Inplementa las entradas y salidas fsicas
-- de la mquina de estados.
----------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.paquete.all;

entity Placa is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : in STD_LOGIC;
int : in STD_LOGIC;
switch1 : in STD_LOGIC_VECTOR (2 downto 0);
switch2 : in STD_LOGIC_VECTOR (2 downto 0);
relojEnt : in STD_LOGIC;
reset : in STD_LOGIC;
habD7S : out STD_LOGIC_VECTOR (3 downto 0);
D7S : out STD_LOGIC_VECTOR (6 downto 0);
salida : out STD_LOGIC_VECTOR (3 downto 0));
end Placa;

architecture Behavioral of Placa is
signal entrada_sel: STD_LOGIC;
signal cont,lig,inter,trans : STD_LOGIC;
signal relojDiv : STD_LOGIC; --Comente/Descomente para la
activacin del divisor
signal G : STD_LOGIC_VECTOR (1 downto 0);
signal MI, estado_actual, liga, regIncr : STD_LOGIC_VECTOR (2 downto 0);

begin

relojDiv <= relojEnt;
habD7S <= "1110";

--Memoria de microprama
mem: Memoria port map(estado_presente => estado_actual,
prueba => G,
microinstruccion => MI,
liga => liga,
salida => salida
);

--Multiplexor de 4x1
mp: Multiplexor port map(Selector => G,
Entrada(0) => x,
Entrada(1) => y,
Entrada(2) => z,
Entrada(3) => int,
Salida => entrada_sel
);

--Decodificador de 3x7 para display de siete segmentos
dcd: decodificador port map (entrada => estado_actual,
salida => D7S
);

--Registro de interrupciones
regInt: registro port map(hab => inter,
reloj => relojDiv,
reset => reset,
entrada => switch1,
salida => estado_actual
);

--Registro de transformacin
regTr: registro port map(hab => trans,
reloj => relojDiv,
reset => reset,
entrada => switch2,
salida => estado_actual
);

--Registro de Liga
regLi: registro port map(hab => lig,
reloj => relojDiv,
reset => reset,
entrada => liga,
salida => estado_actual
);

--Registro de incrementador
regI: registro port map(hab => cont,
reloj => relojDiv,
reset => reset,
entrada => regIncr,
salida => estado_actual
);

--Divisor de frecuencia
--rel: reloj port map(reloj => relojEnt,
-- divisor => relojDiv
-- );

increm: incrementador port map(entrada => estado_actual,
salida => regIncr
);

sec: secuenciador port map(cc => entrada_Sel,
microinstruccion => MI,
habilitadores(0) => trans,
habilitadores(1) => inter,
habilitadores(2) => lig,
habilitadores(3) => cont
);

end Behavioral;

Memoria.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Memoria is
Port ( estado_presente : in STD_LOGIC_VECTOR (2 downto 0);
prueba : out STD_LOGIC_VECTOR (1 downto 0);
microinstruccion : out STD_LOGIC_VECTOR (2 downto 0);
liga : out STD_LOGIC_VECTOR (2 downto 0);
salida : out STD_LOGIC_VECTOR (3 downto 0));
end Memoria;

architecture Behavioral of Memoria is
signal int : std_logic_vector(11 downto 0);
begin
process(estado_presente)
begin
case estado_presente is
when "000" => int <= "000000000001";
when "001" => int <= "000000010100";
when "010" => int <= "010000101001";
when "011" => int <= "001111000101";
when "100" => int <= "000001101111";
when "101" => int <= "011010101100";
when "110" => int <= "011111010001";
when "111" => int <= "110100110010";
when others => int <= "000000000000";
end case;
end process;
liga <= int(11 downto 9);
prueba <= int(8 downto 7);
microinstruccion <= int(6 downto 4);
salida <= int (3 downto 0);
end Behavioral;

Multiplexor.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Multiplexor is
Port ( Selector : in STD_LOGIC_VECTOR (1 downto 0);
Entrada : in STD_LOGIC_VECTOR (3 downto 0);
Salida : out STD_LOGIC);
end Multiplexor;

architecture Behavioral of Multiplexor is
begin
process (Selector,Entrada)
begin
case Selector is
when "00" => Salida <= Entrada(0);
when "01" => Salida <= Entrada(1);
when "10" => Salida <= Entrada(2);
when "11" => Salida <= Entrada(3);
when others => Salida <= '0';
end case;
end process;
end Behavioral;

Decodificador.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decodificador is
Port ( entrada : in STD_LOGIC_VECTOR (2 downto 0);
salida : out STD_LOGIC_VECTOR (6 downto 0));
end decodificador;

architecture Behavioral of decodificador is
begin
process(entrada)
begin
case entrada is
when "000" => salida <= "0000001";
when "001" => salida <= "1001111";
when "010" => salida <= "0010010";
when "011" => salida <= "0000110";
when "100" => salida <= "1001100";
when "101" => salida <= "0100100";
when "110" => salida <= "0100000";
when "111" => salida <= "0001111";
when others => salida <= "1111111";
end case;
end process;
end Behavioral;

Registro.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity registro is
Port ( hab : in STD_LOGIC;
reloj : in STD_LOGIC;
reset : in STD_LOGIC;
entrada : in STD_LOGIC_VECTOR (2 downto 0);
salida : out STD_LOGIC_VECTOR (2 downto 0));
end registro;

architecture Behavioral of registro is
begin
process (reloj)
begin
if reloj'event and reloj='1' then
if hab ='0' then
if reset = '0' then
salida <= entrada;
elsif reset = '1' then
salida <= "000";
end if;
elsif hab = '1' then
salida <= "ZZZ";
end if;
end if;
end process;
end Behavioral;

Incrementador.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity incrementador is
Port ( entrada : in STD_LOGIC_VECTOR (2 downto 0);
salida : out STD_LOGIC_VECTOR (2 downto 0));
end incrementador;

architecture Behavioral of incrementador is
begin
process(entrada)
begin
salida <= entrada + 1;
end process;
end Behavioral;

Secuanciador.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity secuenciador is
Port ( cc : in STD_LOGIC;
microinstruccion : in STD_LOGIC_VECTOR (2 downto 0);
habilitadores : out STD_LOGIC_VECTOR (3 downto 0));
end secuenciador;
-- Microinstrucciones:
-- Paso Continuo 000
-- Salto de Transformacion 001
-- Salto Condicional con 0 010
-- Salto Condicional con 1 011
-- Salto por Interrupcion con 0 100
-- Salto por Interrupcion con 1 101
-- Salto incondicional por liga 110
-- Orden de los habilitadores: Incrementador,Liga,Interrupcion,Transformacion
architecture Behavioral of secuenciador is
begin
process(cc,microinstruccion)
begin
case microinstruccion is
when "000" => habilitadores <= "0111";
when "001" => habilitadores <= "1110";
when "010" =>
if cc = '0' then habilitadores <= "1011";
elsif cc = '1' then habilitadores <= "0111";
end if;
when "011" =>
if cc = '1' then habilitadores <= "1011";
elsif cc = '0' then habilitadores <= "0111";
end if;
when "100" =>
if cc = '0' then habilitadores <= "1101";
elsif cc = '1' then habilitadores <= "0111";
end if;
when "101" =>
if cc = '1' then habilitadores <= "1101";
elsif cc = '0' then habilitadores <= "0111";
end if;
when "110" => habilitadores <= "1011";
when others => habilitadores <= "0111";
end case;
end process;
end Behavioral;

Reloj.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity reloj is
Port ( reloj : in STD_LOGIC;
divisor : out STD_LOGIC);
end reloj;

architecture Behavioral of reloj is
begin
process(reloj)
variable cuenta : std_logic_vector(27 downto 0);
begin
if reloj='1' and reloj'event then
cuenta := cuenta +1;
end if;
divisor <= cuenta(27);
end process;
end Behavioral;