NHM 4 10DTLT

N VI X L V MY TINH
TRNG H BCH KHOA NANG
KHOA IJN T - VIEN THNG
LAB3: THIET KE B X
L MIPS SINGLE CYCLE
Yu cu thit k

Thit k b 32-bit MIPS Single-Cycle CPU n gin.

CPU thc hin c c!c lnh " #$% S$% &% '()% *+,I%
-..% SU'. &, /0 S#T.

*1y 2ng 3456ect 3 c7 89 2:ng ,egi8te4 ;ile c<= 3456ect >

/0 MIPS -#U c<= 3456ect 2.

S9 2:ng ?ile @2=t=AeA./B /0 @in8t4AeA./B C D1y 2ng

A52Ele 2=t= AeA54y /0 in8t4Ecti5n AeA54y.

' C5nt45l l5gic c7 thC c /it the5 kiCE beh=/i54=l.

Quan di m hiu sut
ChFng t= G bit hiE 8EHt c<= At A!y tInh
c JEyt Knh bLi 3 yE tM chInh"
SM lnh Nin8t4Ecti5n c5EntO
ThPi gi=n At chE kQ DEng Rng b Ncl5ck
cycle tiAeO
SM chE kQ DEng Rng b ch5 ASi lnh NCPIO
I-Count
CPI Cycle

T45ng 7% t4Tnh biUn 2Kch /0 cHE t4Fc tV3 lnh NIS-O JEyt
Knh 8M lnh yUE cWE Mi /Xi At chng t4Tnh 8Yn c7. TEy
nhiUn JE! t4Tnh thc hin c<= b D9 lZ l[i JEyt Knh c
4ng c<= At cl5ck cycle /0 8M cl5ck cycle t4Un ASi lnh.
32-bit MIPS Single-Cycle CPU

\hMi D9 lZ t4Eng t1A NCent4=l P45ce8854 UnitO c7 kh

n]ng thc thi tV3 lnh MIPS 32-bit t45ng At chE kQ A!y.

CPU c7 kh n]ng thc hin c!c lnh c bn c<= tV3 lnh

MIPS b=5 gRA"

C!c lnh th=A chiE b nhX" l5=2 ^542 Nl^O /0 8t54e

^542 N8^O

C!c lnh 8M h_c-lEVn lZ" =22% 8Eb% 8lt% D54i

C1E lnh 4` nh!nh b4=nch n5t eJE=l NbneO /0 lnh nhy

6EA3 N6O h5ac 6EA3 4egi8te4 N64O.
32-bit MIPS Single-Cycle CPU
b=i th0nh 3hWn chInh c<= CPU" .=t=3=th /0 C5nt45l Unit.

\hMi icE khiCn b=5 gRA"

C!c ngd /05% c!c ngd 4=.

'iUn 2Kch lnh e n[3 lnh% gii AG /0 thc thi lnh.

.=t=3=th b=5 gRA"

C!c khMi chfc n]ng e -#U% c!c b nh1n% b chi= g

C!c th=nh ghi e ' A chng t4Tnh NP45g4=A C5Ente4O% c!c

th=nh ghi 2Kch% c!c th=nh ghi lE t4h.
(g50i c!c th=nh ghi% 2=t=3=th cin chf= c!c l5gic 8M h_c b=5 gRA
c!c bE8% c!c b MU*% c!c b gii AG /0 c!c A[ch D9 lZ.
Cac thanh phn cua Datapath
Data
Memory
Address
Data_in
Data_out
MemRead MemWrite
32
32
32
A
L
U
ALU control
ALU result
zero
32
32
32
overflow
cout
negative
m
u
x
0
1
select
32
Address
nstruction
Instruction
Memory
32
Registers
RA
R!
!usA
RegWrite
!us!
RW
"
"
"
32
32
32
!usW
#loc$
%
#
32 32
&'tend
32
1(
)ign&'t

Ph1jn tk tlkng hm3

-#U% -22e4

IAAe2i=te eDten2e4

MElti3leDe48

Ph1jn tk lE t4n

In8t4Ecti5n AeA54y

.=t= AeA54y

PC 4egi8te4

,egi8te4 ?ile
Cac tp l nh co ban cua Mips
Tng quan qua trinh thuc hin

oMi /Xi ASi c1E lnh% h=i bXc WE tiUn l0 Rng nhHt"

p9i PC n b nhX lnh C n[3 lnh.

o_c At h5ac h=i th=nh ghi% 89 2:ng c!c t4Png c<= c1E lnh C ch_n
th=nh ghi cWn _c.

S=E h=i bXc n0y% c!c bXc cin l[i C h50n tHt At c1E lnh tqy thEc /05
khEln 2[ng lnh.

oMi /Xi tHt c c!c khEln 2[ng lnh ng5[i t4r lnh nhy cE 89 2:ng -#U
thc hin c!c chfc n]ng 8=E"

C!c c1E lnh 8M h_c" tInh t5!n c!c t5!n h[ng.

C!c c1E lnh 4` nh!nh" thc hin 85 8!nh.

C!c c1E lnh th=A chiE b nhX" tInh t5!n K= chs c<= b nhX 2h liE.

Mat kh!c% PC 8` t]ng lUn t C g9i K= chs n c1E lnh ti3 the5
Phuong phap dng b du liu

ChFng t= gi 89 DEng cl5ck kIch h5[t 8Pn lUn N358iti/e e2ge-t4igge4e2

cl5ckingO. T45ng At chE kQ DEng cl5ck"

'ut WE _c ni 2Eng c<= c!c 3hWn t9 t4[ng th!i.

p9i c!c gi! t4K JE= c!c A[ch l5gic tv h3.

wit kt JE n At h5ac nhicE 3hWn t9 t4[ng th!i khi kt thFc chE

kQ cl5ck cycle.

Phng 3h!3 Rng b DEng cl5ck ch5 3hx3 At 3hWn t9 t4[ng th!i c
_c /0 ghi t45ng cqng At cl5ck cycle Nng5[i t4r c!c bE8 chf= 2h liE tfc
thPiO.
Thit k datapath ring phn

TV3 lnh MIPS c bn c7 thC c chi= th0nh 3 kiCE lnh

chInh

\iCE th=nh ghi N,O y chs 2qng th=nh ghi l0A Mi 8M.

\iCE tfc thT NIO y 2qng th=nh ghi /0 c!c 8M l0A Mi 8M.

\iCE nhy N&O y 2qng K= chs l0A Mi 8M.

oMi /Xi ASi kiCE lnh thT JE! t4Tnh thc thi lnh l0 giMng nh=E
/Vy nUn t= czng chi= 3hWn thit k 2=t=3=th th0nh 3 3hWn
tng fng.
Datapath - Qu trnh np lnh

oUk tijA lUmnh chE{ng t= c1jn "

Th=nh ghi b A chng t4Tnh NP45g4=A C5Ente4 y PCO

' nhX lnh NIn8t4Ecti5n MeA54yO

' cng t]ng PC lUn t N-22e4O

%
#
32
Address
nstruction
Instruction
Memory
32
32
32
4
A
d
d
next PC
.=t=3=th n0y khlng
Dxt n c1E lnh 4`
nh!nh.
2 bit thH3 nhHt c<= PC l0
|}}~ 25 7 PC l0 bi c<= t.
Ci thin" C7 thC 89 2:ng
PC y 3} bit /0 t]ng PC lUn >
8=E ASi lnh.
32
Address
nstruction
Instruction
Memory
32
30
P
C
0
0
*1
30
Datapath sau
khi cai thin
next PC
Datapath cua khun dng lnh R
+,
(
Rs
"
Rt
"
Rd
"
funct
(
sa
"
A
L
U
32
32
ALU#trl
RegWrite
Registers
RA
R!
!usA
!us!
RW
!usW
" Rs
" Rt
" Rd
ALU result
32

,- ,' U{n tj t4j ng ,8 ,t

,$ U{ n tj t4jng ,2

b=i 1jE /=j5 -#U U{n tj 'E8- 'E8' cEk= ,egi8te48

o1jE 4= cEk= khl{i -#U mc kU{t nl{i /{i 'E8$ cEk= 4egi8te48

Ti{n hiUmE iUjE khiUk n "

o
-#UCt4l mc iUjE khiUk n bki t4jng ?Enct bki /ij +3e} l{i /{i
khEln 2=mng lUmnh ,.
o
,eg$4ite mc 8k 2Emng Uk ki{ ch h5=mt ghi cEk= kU{t JE=k -#U
32
Address
nstruction
Instruction
Memory
32
30
%
#
0
0
*1
30
Datapath cua khun dng lnh I
+,
(
Rs
"
Rt
"
immediate
1(
ALU#trl
RegWrite
32
"
Registers
RA
R!
!usA
!us!
RW
!usW
" Rs
" Rt
)ign&'t
32
ALU result
32
32
A
L
U
&'tender
mm1(

'1y gij ,$ U{n tj t4jng ,t

o1jE /=j5 th{ h=i cEk= -#U U{n tj t4jng Ak 4lmng 21{E .

,' 'E8' khlng 8k 2Em ng.

Ti{n hiUmE iUjE khiUkn "

-#UCt4l mc iUjE khiUkn tj t4jng +3.

,eg$4ite mc 8k 2Emng Uk ki{ ch h5=mt ghi kU{t JE=k -#U /05 th=nh ghi.

Sign)Dt mc 8k 2Emng Uk iUjE khiUkn t4jng Ak 4lmng 21{E > bit th=jnh 32
bit.
32
Address
nstruction
Instruction
Memory
32
30
%
#
0
0
*1
30
T hp Datapath cua khun dng R v I
ALU#trl
RegWrite
)ign&'t
m
u
x
0
1
RegDst
ALU)rc
m
u
x
0
1
'lm AED Uk ch5mn ,$ l=j
,t h=y l=j ,2
Mlmt blm AED kh={c Uk
ch5mn 1jE /=j5 cEk=
-#U m c l1{y tj
ngEljn 2n liUmE cEk=
th=ng ghi ,t t4Un
'E8' h5]mc tj t4j ng
Ak 4lmng 21{E

Ti{n hiUmE iUjE khiUkn "

-#UCt4l mc iUjE khiUkn bki t4jng +3 h=y t4jng ?Enct.

,eg$4ite ki{ch h5=mt ghi 2h liE /05 tj kU{t JE=k cEk= -#U.

Sign)Dt iUjE khiUkn t4jng Ak 4lmng 21{E > bit 8=ng 32 bit.

,eg.8t ch5mn th=nh ghi i{ch ,t h5]mc ,2.

-#US4c ch_n h=i ngEljn 1jE /=j5 -#U tj 'E8' h5]mc tj t4jng Ak 4lmng 21{E.
A
L
U
ALU result
32
32
Registers
RA
R!
!usA
!us!
RW
"
32
!usW
32
Address
nstruction
Instruction
Memory
32
30
%
#
0
0
*1
30
Rs
"
Rd
&'tender
mm1(
Rt
32
"
Controlling ALU Instructions
ol{i /{ i khEln lUmnh , %
,eg.8t i8 |>~ Uk ch5mn ,2
t4Un ,$ /=j -#US4c i8
|}~ Uk ch5mn t 'E8' l=j ng5k
/=j 5 th{ h=i cEk= -#U.
Ph1jn h5=mt lmng m c
biUkE 2iUn n b]jng A=j E *=nh
ol{i /{ i khEln 2=mng lUmnh
I % ,eg.8t i8 |}~ Uk ch5mn
,t t4Un ,$ /=j n2
-#US4c i8 |>~ Uk ch5mn
t4j ng Ak 4lmng 21{ E l=j
1jE /=j5 th{ h=i cEk= -#U.
Ph1jn h5=mt lmng m c
biUkE 2iUn n b]jng A=j E *=nh
RegDst - 1
ALU)rc - 0
A
L
U
ALU#trl
ALU result
32
32
Registers
RA
R!
!usA
RegWrite - 1
!us!
RW
"
32
!usW
32
Address
nstruction
Instruction
Memory
32
32
%
#
0
0
*.
32
Rs
"
Rd
&'tender
)ign&'t
mm1(
Rt
32
m
u
x
0
1
"
m
u
x
0
1
RegDst - 0
ALU)rc - 1
A
L
U
ALU#trl
ALU result
32
32
Registers
RA
R!
!usA
RegWrite - 1
!us!
RW
"
32
!usW
32
Address
nstruction
Instruction
Memory
32
30
%
#
0
0
*1
30
Rs
"
Rd
&'tender
)ign&'t
mm1(
Rt
32
m
u
x
0
1
"
m
u
x
0
1
Cc chi tit cua khi mo rng 32-bit

C7 h=i kiUk E Ak 4lmng 32-bit"

Mk 4lmng 21{E. " ML 4ng >-bit c=5 the5 bit MS' c<= t4Png IAA>

Mk 4lmng e45 " ML 4ng >-bit c=5 l0 bit }

Ti{n hiUmE iUj E khiUk n Sign)Dt D={ c imnh kiUkE Ak 4lmng.

Thmc hiUmn Ak 4lmng "

)ign&'t - 0 U,,er1( - 0
.
.
.
)ign&'t
U33e4
> bit8
#5^e4
> bit8
.
.
.
IAA>
MS'
Sign)Dt e >
U33e4> e 8ign bit
Datapath cua cu lnh tham chiu b nh

.=t= AeA54y mc thUA /=j 5 Uk t4EyUjn t=ki /=j lE t4n 2h liE.

Data
Memory
Address
Data_in
Data_out
32
32
A
L
U
ALU#trl
32
Registers
RA
R!
!usA
RegWrite
!us!
RW
"
!usW
32
Address
nstruction
Instruction
Memory
32
30
%
#
0
0
*1
30
Rs
"
Rd
&'tender
)ign&'t
mm1(
Rt
m
u
x
0
1
"
RegDs
t
ALU)rc
m
u
x
0
1
32
MemRead MemWrite
32
ALU result
32
m
u
x
0
1
MemtoReg
-#U ti{nh t5={n im= chik 2=t= AeA54y
'lm AED th{ b= 2Ejng Uk ch5mn 2n liUE t4Un
'E8$ l=j kU{ t JE=k cEk= -#U h=y 1j E 4= cEk=
AeA54y 2=t=.
'E8' m c kU{t nl{i /{ i .=t=in cEk= .=t=
MeA54y l{i /{ i lUmnh #^.

ThUA ti{ n hiUmE iUjE khiUkn"

MeA,e=2 iUjE khiUkn l{i /{i lUmnh #^

MeA$4ite iUjE khiUkn l{i /{i lUmnh S^.

MeAt5,eg Uk ch5mn 2n liUmE t4Un 'E8$ l=j -#U 4e8Elt h5]mc MeA54y
.=t=5Et
Tn hiu diu khin lnh LW
Sign)Dt e |8ign~ Uk thm c hiUm n Ak
4lmng 21{ E > t5 32 bit8
-#UCt4l e |-..~Uk ti{nh t5={n im= chik cEk= .=t=
AeA54y l=j ,egN,8O 8ign-eDten2NIAA>O
-#US4c e |>~ ch5mn t4j ng Ak 4lmng 21{E nh 1jE
/=j 5 th{ h=i cEk= -#U.
MeA,e=2 e |>~ Uk 5mc 2n liUmE tj 2=t=
MeA54y
,eg.8t e |}~ ch5mn ,t l=j
th=nh ghi i{ch
,eg$4ite e |>~ Uk /iU{t 2n liUmE t4Un 2=t=
MeA54y t4Un 'E8$ U{ n th=nh ghi ,t
MeAt5,eg e |>~ l=j ni Uk 5mc 2n liUmE tj
blm nh{ /Uj 'E8$
Data
Memory
-224e88
.=t=in
.=t=5Et
32
32
-
#
U
-#UCt4l
e -..
-#U 4e8Elt
32
32 Registers
,-
,'
'E8-
,eg$4ite
e >
'E8'
,$

'E8$
32
-224e88
In8t4Ecti5n
Instruction
Memory
32
3}
P
C
}
}
>
3}
,8

,2
)Dten2e4
Sign)Dt
e 8ign
IAA>
,t
m
u
x
}
>

m
u
x
}
>
m
u
x
}
>
32
MeA,e=2
e >
MeA$4ite
e }
,eg.8t
e }
-#US4c
e >
MeAt5,eg
e >
32
Tn hiu diu khin lnh SW
-#UCt4l e |-..~ Uk ti{nh t5={n im= chik cEk= 21t
AeA54y l=j ,egN,8O 8ign-eDten2NIAA>O
-#US4c e |>~ Uk ch5mn t4j ng Ak 4lmng 21{E l=j 1jE
/=j 5 th{ h=i cEk= -#U.
MeA$4ite e |>~Uk /iU{t 2n liUmE /=j 5 2=t=
AeA54y
,eg.8t e |D~ bk i /ij
khlng c5{ th=nh ghi i{ch.
Sign)Dt e |8ign~ Uk Ak 4lmng 21{E
> t5 32 bit8
,eg$4ite e |}~ bk i /ij khlng c5{ th=nh ghi
n=j 5 m c /iU{t bk i lUmnh 8t54e.
MeAt5,eg e |D~ bk i /ij chE{ng t= khlng
c1jn ni /iU{t 2n liUmE t4Un 'E8$ .
Data
Memory
-224e88
.=t=in
.=t=5Et
32
32
32
-
#
U
-#UCt4l
e -..
-#U 4e8Elt
32
32 Registers
,-
,'
'E8-
,eg$4ite
e }
'E8'
,$

'E8$
32
-224e88
In8t4Ecti5n
Instruction
Memory
32
3}
P
C
}
}
>
3}
,8

,2
)Dten2e4
Sign)Dt
e 8ign
IAA>
,t
m
u
x
}
>

,eg.8t
e D
m
u
x
}
>
m
u
x
}
>
32
MeA,e=2
e }
MeA$4ite
e >
MeAt5,eg
e D
-#US4c
e >
Datapath cua cu lnh nhay v lnh r nhnh

ThUA c={ c ti{ n hiUmE iUjE khiUkn.

&% 'ne l=j c={ c t1m3 lUmnh cEk= nh=ky /=j 4en nh={nh.

e45 Uk kiUkA t4= tij nh t4=mng cEk= -#U

&EA3 e > ch5mn &EA3 '4=nch mc thmc

hiUmn.
)Dt
Data
Memory
-224e88
.=t=in
.=t=5Et
MeA,e=2 MeA$4ite
32
-
#
U
-#UCt4l
-#U 4e8Elt
32 Registers
,-
,'
'E8-
,eg$4ite
'E8'
,$

'E8$
32
-224e88
In8t4Ecti5n
Instruction
Memory
P
C
}
}
>
3}
,8

,2
IAA2
,t
m
u
x
}
>

,eg.8t
-#US4c
m
u
x
}
>
m
u
x
}
>
MeAt5,eg
m
u
x
}
>
3}
e45
3} &EA3 54 '4=nch T=4get -224e88
3}
&EA3 IAA>
&% 'ne
(eDt
PC
'1y gij CPU 8en ti{nh t5={n im=
chik cEk= lUmnh nh=ky h5]mc im= chik
cEk= lUmnh 4en nh={nh.
ol{i /{i lUmnh 4en nh={nh thij
-#U thm c hiUmn Almt lUmnh t4j .
Controlling the Execution of 1ump
)Dt
Data
Memory
-224e88
.=t=in
.=t=5Et
32
-#U 4e8Elt
32

Registers
,-
,'
'E8-
'E8'
,$ 'E8$
32
-224e88
In8t4Ecti5n
Instruction
Memory
P
C
}
}
3}
,8

,2
IAA2
,t
m
u
x
}
>

m
u
x
}
>
m
u
x
}
>
m
u
x
}
>
3}
3} &EA3 T=4get -224e88
3}
IAA>
(eDt
PC
,eg$4ite
e }
MeA,e=2
e }
MeA$4it
e
e }
& e >
,eg.8t
e D
-#UCt4l
e D
-#US4c
e D
MeAt5,eg
e D
)Dt+3
e D
&EA3
e >
>
e45
-
#
U
ChE{ ng t= khlng c1jn ,eg.8t% )Dt+3%
-#US4c% -#UCt4l% =n2 MeAt5,eg
MeA,e=2% MeA$4ite ,eg$4ite b]jng }
& e > mc ch5mn% IAA2 l0
im= chik i{ch cEk= lUmnh nh=ky.
&EA3 e > Uk ch5mn im= chik
i{ch cEk = lUmnh nh=ky.
t bit c=5 n tr PCt
.=t=3=th n0y ch= Dxt n c1E lnh 64% 8` c7 thUA b AED2-> /Xi tIn hiE icE khiCn &EA34eg C ch_n
K= chs PC ti3 the5 l0 tr c1E lnh & h=y &,
Tn hiu diu khin thc thi cu lnh r nhnh
)Dt
Data
Memory
-224e88
.=t=in
.=t=5Et
32
-#U 4e8Elt
32

Registers
,-
,'
'E8-
'E8'
,$ 'E8$
32
-224e88
In8t4Ecti5n
Instruction
Memory
P
C
}
}
3}
,8

,2
IAA2
,t
m
u
x
}
>

m
u
x
}
>
m
u
x
}
>
m
u
x
}
>
3}
3} '4=nch T=4get -224e88
3}
IAA>
(eDt
PC
,eg$4ite
e }
MeA,e=2
e }
MeA$4ite
e }
'ne e >
-#UCt4l
e SU'
-#US4c
e }
,eg.8t
e D
MeAt5,eg
e D
)Dt+3
e D
&EA3
e >
>
e45
-
#
U
,eg.8t e )Dt+3 e MeAt5,eg e D
MeA,e=2 e MeA$4ite e ,eg$4ite e }
'ne e>
-#US4c e |}~ Nngd /05 thf 2 c<= -#U l0 'E8'O
-#UCt4l e |SU'~ t[5 cP e45
PC ti3 the5 D={c imnh &EA3
2m = /=j5 cj e45.
oK= chs Ich c1E lnh 4` nh!nh l0 ngd 4= ti3 the5 c<= PC
Main Control v ALU Control
In3Et"

-bit t4Png 53c52e ?iel2 tr c1E lnh

+Et3Et"

tIn hiE icE khiCn ?54 2=t=3=th

-#U+3 ?54 -#U C5nt45l

In3Et"

-bit t4Png ?Encti5n ?iel2 tr c1E lnh

-#U+3 tr A=in c5nt45l

+Et3Et"

TIn hiE -#UCt4l n -#U

> tIn hiE icE khiCn &EA34eg ch5

2=t=3=th
-#U
C5nt45l
M=in
C5nt45l
.=t=3=th
32
-224e88
In8t4Ecti5n
Instruction
Memory
-
#
U
+3

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8
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2
M
e
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t
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-#U+3
-#UCt4l
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&
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A
3
&
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A
3
4
e
g
TIn hiE icE khiCn &EA34eg c D!c Knh tr 2 t4Png 53c52e /0 ?Encti5n c<= c1E lnh &, nUn c
t!ch 4iUng C thEVn tin ch5 /ic thit k.
Single-Cycle Datapath + Control
/um,
&'t
Data
Memory
Address
Data_in
Data_out
32
A
L
U
ALU result
32
"
Registers
RA
R!
!usA
!us!
RW !usW
32
Address
nstruction
Instruction
Memory
%
#
0
0
*1
30
Rs
"
Rd
mm2(
Rt
m
u
x
0
1
"
m
u
x
0
1
m
u
x
0
1
m
u
x
0
1
30
30
/um, or !ranc0 1arget Address
30
mm1(
2e't
%#
zero
ALU
#trl
ALU#trl
ALU+,
func
RegDst ALU)rc RegWrite
/3 !ne
MemtoReg
MemRead
MemWrite
)ign&'t
Main
#ontrol
+,
Y nghia cua cac tin hi u di u khin
(5. TIn hi E n T!c ng A fc } T!c ng A fc >
> ,eg.8t Th=nh ghi Ich 8 ` lHy K=
ch s tr t4 Png 4t Nc!c bit t r
2}>O
Th=nh ghi Ich 8 ` lHy K=
ch s tr t4 Png 42 Nc!c bit t r
> >>O
2 ,eg$4ite \hlng ch5 3hx3 ghi 2 h li E
/05 t 3 th=nh ghi.
Ch5 3hx3 2 h li E t r
$4ite2=t= c ghi /05
th=nh ghi.
3 -#US4c T5!n h [ng th f h=i c <= -#U
c l Hy t r ngd 4= th f h=i
c<= t 3 th=nh ghi N,e=2
2=t= 2O.
T5!n h [ng th f h=i c <= -#U
l0 k t JE c A L 4ng
e452 HE t r > bit th H3 c <=
c1E l nh NIAA>bitO
t '4=nch PCe PCt PCePCtSign
eDtNIAA>O2
MeA,e=2 \hlng ch5 3hx3 _c t r b
nh X 2h li E.
(i 2Eng b nh X 2h li E ch s
Knh b Li K= ch s ngd /05
c at /05 ngd 4= ,e=2
2=t=.
MeA$4ite \hlng ch5 3hx3 ghi /05 b
nh X 2h li E.
(i 2Eng b nh X 2h li E ch s
Knh b Li K= ch s ngd /05 8 `
c th=y th bLi gi! t4 K L
ngd /05 $4ite 2=t=.
MeAt5,eg pi! t4 K L ngd /05 $4ite 2=t=
c<= t 3 th=nh ghi c l Hy
tr kt JE ngd 4= c <= -#U.
pi! t4 K L ngd /05 $4ite 2=t=
c<= t 3 th=nh ghi c l Hy
tr b nh X 2h li E.
&EA3 PCePCt h5 ac
PCePCtSign
eDtNIAA>O2
PCePC3>"2%t=4get%}}.
&EA34 eg PCePCt
b5 ac PCePCtSign
eDtNIAA>O2
b5 ac
PCePC3>"2%t=4get%}}.
PCe,eg48
>} Sign)Dt ML 4ng e45 ML 4ng 2 HE

Main Control Signal Values
ALU Control Truth Table
Tr #=b2% T= G thit k khMi -#U c7 kh n]ng thc hin t 3hx3 tInh c
bn" -22% SEb% *54 /0 S#T /Xi 2 bit icE khiCn -#Uct4l>"}. Tqy /05 chfc
n]ng c<= ASi c1E lnh A0 -#U 8` thc hin > t45ng t 3hx3 tInh n0y. C: thC
nh 8=E"
In8t4Ecti5n8 +3e4=ti5n -#Uct4l>"}
=22% l^% 8^ -22 }}
D54i *54 }>
8Eb%bne SEb >}
8lt Slt >>

Ng vo: bit thH3 c<= AG lnh h=y ;Encti5n"} /0 2 bit icE khiCn tr
khMi icE khiCn chInh h=y -#U+3>"}.
T45ng 7 2 bit icE khiCn -#U+3> /0 -#U+3} c Knh ngh= nh 8=E"
-#U+3>"} Chfc n]ng -#U
}} -22
}> SEbt4=ct
>} Ph: thEc t4Png ;Encti5n
>> *54 trng bit

ALU Control Truth Table
Ng ra: -#Uct4l>"} 8` icE khiCn chfc n]ng -#U.

I+ Sign=l n=Ae =22 8Eb 8lt D54i l^ 8^ bne 6 64
I
;Enct >
>
>
D D D D D
0
;Enctt }
}
}
D D D D D
0
;Enct3 }
}
>
D D D D D
1
;Enct2 }
}
}
D D D D D
0
;Enct> }
>
>
D D D D D
0
;Enct} }
}
}
D D D D D
0
-#U+3> > > > > } } } D D
-#U+3} } } } > } } > D D
+
-#Uct4l> } > > } } } > D D
-#Uct4l} } } > > } } } D D

Nhuoc dim cua b xu ly Singcle Cycle

'lm Dk ly{ Single Cycle ch5 3he{ 3 thmc hiUm n t1{ t c=k c={c lUm nh t45mng > chE kyj.

T1{ t c=k c={ c t1m 3 lUm nh A1{ t nhiUj E thji gi=n.

In8t4Ecti5n ;etch ,eg ,e=2 -#U ,eg $4ite
MeA54y ,e=2 In8t4Ecti5n ;etch
l5nge8t 2el=y
-#U ,eg ,e=2 ,eg $4ite
In8t4Ecti5n ;etch -#U MeA54y $4ite ,eg ,e=2
In8t4Ecti5n ;etch ,eg ,e=2 -#U
In8t4Ecti5n ;etch .ec52e
-#U
#5=2
St54e
'4=nch
&EA3

'lm Dk ly{ Single Cycle thiU{ t kU{ n gi=k n nhng khlng hiUm E JE=k .
MIPS
Quartu
s
ModelSim
NGUYEN HNG QUAN
L THJ NI NA
MAI XUAN HONG
NGUYN MINH HO
TRAN NGC TRNG
L THJ HNG DUNG
TRAN V QUANG HNG
L THJ KIM CAM