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9, SEPTEMBER 2013

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A High-Efciency Wide-Input-Voltage Range Switched Capacitor Point-of-Load DCDC Converter

Vincent W. Ng, Member, IEEE, and Seth R. Sanders, Fellow, IEEE
AbstractThe traditional inductor-based buck converter has been the default design for switched-mode voltage regulators for decades. Switched capacitor (SC) dcdc converters, on the other hand, have traditionally been used in low-power (<10 mW) and low conversion ratio (<4:1) applications where neither regulation nor efciency is critical. This study encompasses the complete successful design, fabrication, and test of a CMOS-based SC dcdc converter, addressing the ubiquitous 121.5 V boardmounted point-of-load application. In particular, the circuit developed in this study attains higher efciency (92% peak, and >80% over a load range of 5 mA to 1 A) than surveyed competitive buck converters, while requiring less board area and less costly passive components. The topology and controller enable a wide input range of 7.513.5 V. Controls based on feedback and feedforward provide tight regulation under worst case line and load step conditions. This study shows that the SC converter can outperform the buck converter, and thus, the scope of SC converter application can and should be expanded. Index TermsDC-DC power converters, switched capacitor circuits, switched-mode power supply.

I. INTRODUCTION

S discussed in [1] and [2], a number of SC converter topologies are very effective in their utilization of switches and passive elements, especially in relation to the ever popular buck converter. In terms of switches, the power switches in the buck converter each block the full input voltage and support the full output current. For a large or even moderate conversion ratio, this leads to a high switch total volt-ampere product, and causes the buck converter to suffer from poor power device utilization. In contrast, the switches in a ladder or Dickson SC converter only block a fraction of the input voltage, while supporting a fraction of the output current. This not only enables utilization of native low-voltage CMOS transistors in a modern low-cost CMOS process, but also leads to a low total switch volt-ampere product, allowing these SC converters to sustain high efciency with a high conversion ratio. In terms of passive elements, SC converters benet from the signicantly higher energy density of capacitors over inductors. As discussed in [2] and [3], surveyed surface mount scale capacitors have a volumetric energy density that is over 1000 times higher than that

Fig. 1.

Circuit schematic of a converter.

of surveyed inductors. This can lead to a considerable reduction in printed circuit board (PCB) area and in cost by replacing one bulky inductor with several smaller capacitors. This study builds a moderate conversion ratio (121.5 V) SC converter in a 0.18 m/0.6 m process to realize these advantages of the SC converter. II. ARCHITECTURE Fig. 1 shows the schematic of the Dickson SC converter implemented in this study [12], [14]. In contrast to Dicksons original work on a voltage step-up converter [10], this study utilizes the Dickson topology as a step-down converter. The input voltage may range from 7.5 to 13.5 V, while the converter outputs a nominal voltage of 1.5 V, dened by an on-chip bandgap reference. Capacitors C1 C9 are the power-train capacitors, and they are implemented with off-chip ceramic capacitors. When compared to [11], this converter utilizes a ladder type capacitor conguration in contrast to a star type capacitor conguration for quicker line transient response [12]. The Dickson converter operates in two phases, and achieves voltage conversion through charge transfers among capacitors C1 C9 [10]. Switches S1 S12 are the power switches, and the phase in which they are turned ON is indicated by the number in bracket next to the switch label in the gure; the switch is turned OFF in the other phase. Switches S13 S18 are also power switches, but they may turn ON in either clock phase depending

Manuscript received May 31, 2012; revised September 12, 2012; accepted September 29, 2012. Date of current version February 15, 2013. This work was supported by National Semiconductor. Recommended for publication by Associate Editor Y.-F. Liu. V. W. Ng is with Volterra Semiconductor, Fremont, CA 94538-6537 USA (e-mail: vwng@eecs.berkeley.edu). S. R. Sanders is with the Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA 94720 USA (e-mail: sanders@eecs.berkeley.edu). Digital Object Identier 10.1109/TPEL.2012.2224887

0885-8993/$31.00 2012 IEEE

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TABLE I STATE OF SWITCHES TO SUPPORT VARIOUS CONVERSION RATIOS

on the conversion ratio of the converter. The timing sequence of switches S13 S18 allows the converter to attain seven different conversion ratios, ranging from 5-to-1 to 8-to-1 with half-integer steps. Table I shows the states of switches S13 S18 in each clock phase to support these various conversion ratios. The whole integer conversion ratios are obtained by connecting the input terminal to either the top or bottom plate of capacitor C7 in one of the two clock phases. The half-integer step conversion ratios are obtained by connecting capacitor C9 in series with the input terminal. Since an SC converter is most efcient when operating close to its nominal conversion ratio, a ner conversion ratio step topology allows higher efciency across the input voltage range. The integrated circuit implementation, in a 0.18-m triplewell CMOS process, is subdivided into various voltage domains to allow the usage of low-voltage transistors (blocking a maximum of 4 V) to accommodate a moderate voltage input (as high as 13.5 V). Level-shifter circuits are implemented to convey signals across voltage domains, while protection clamps and startup helper circuits are implemented to support safe shutdown and self-startup [11]. Startup of the converter is realized by operating the circuit in charge-pump (boost) mode at powerup. During startup, the SC converter is initially isolated from the input source with a single full-voltage-rated pass transistor while an auxiliary linear regulator charges up the output rail. The SC converter then operates in charge-pump (boost) mode to charge up all the capacitors and internal nodes to predetermined values. The pass transistor is then activated, followed by turn-off of the auxiliary linear regulator. III. REGULATION The SC converter can be modeled as an ideal transformer in series with an equivalent output resistance, ROUT [1]. The conversion ratio of the ideal transformer is given by the unloaded conversion ratio of the SC converter, whereas ROUT is dependent on the conductance of the power switches, sizes of the power-train capacitors, and the switching frequency [1]. This converter achieves regulation by rst adjusting its nominal conversion ratio, and then by modulating the switch conductance of switches S1 , 4 , 5 . Switch conductance modulation [13] allows tight regulation for line and load variation whereas changing conversion ratio allows the converter to attain a high efciency throughout the operating space. Further, the converter also modulates switching frequency to attain high efciency under lightload conditions. The control action is divided into an inner loop and an outer loop; the inner loop regulates switch conductance

Fig. 2.

Conceptual diagram of the controller.

Fig. 3.

Overall block diagram of the controller.

and switching frequency, whereas the outer loop chooses the nominal conversion ratio. Fig. 2 shows a conceptual diagram of the two-loop controller implemented in this converter, and Fig. 3 shows a more detailed structure of the controller. A. Inner Loop Controller The inner loop controller modulates ROUT in Fig. 2 through switch conductance modulation, and at the same time

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chooses switching frequency roughly proportional to switch conductance. Switch conductance modulation is achieved through modulating the gate drive voltages of the three output switches, S1 , 4 , 5 . These three switches all block 1.5 V and are implemented using 0.18-m PMOS transistors. This choice of device allows the three switches to be in the same voltage domain when they are ON, and thus, only one controlled supply rail, with voltage VGD , is needed to provide their gate drive voltages. Voltage VGD is maintained by an error amplier that compares the output voltage with a reference voltage generated on-chip. On-chip decoupling capacitors are also added to reduce the uctuations on this controlled supply rail. The output voltage is sensed differentially with a pair of Kelvin sense wires to eliminate the effects of voltage drops on the bondwire resistances, RW IRE . A low-pass lter composed of RLPF and CLPF is inserted to reduce the noise associated with remote sensing. The pole frequency of this low-pass lter is chosen to be approximately the ESR corner frequency of the output capacitor so as to roughly cancel the zero associated with it. The inner loop switch conductance modulator involves controlling VDROP in Fig. 2 and operates very similarly to a linear regulator. For simplicity, only proportional feedback is used in this controller, and thus, loop dynamics design involves making sure that the nondominant poles of the system are beyond the maximum gain bandwidth product of the loop. The lowest frequency nondominant pole of the system is the closed-loop pole of the error amplier shown in Fig. 3. Due to the use of ceramic capacitors, the zero associated with the capacitor ESR is beyond the gain bandwidth product of the loop and can be ignored. The pole associated with the voltage sensing low-pass lter approximately cancels this ESR zero, in any case. The gain bandwidth product of the loop is given by AEA GM /COUT , where AEA is the closed-loop gain of the error amplier shown in Fig. 3, GM is the transconductance of the controlling action, and COUT is the output capacitor. The value of all three terms can be determined or estimated by other specications of the converter. Capacitor COUT is chosen based on the target ripple voltage of the converter, while gain AEA is picked based on the target tightness of regulation. In order to maintain gain precision, gain AEA is implemented using resistive feedback around an operational amplier to give a nominal value of 75, as shown in Fig. 3. Transconductance GM can be approximated by the transconductance of the output switches S1 , 4 , 5 , which is dependent on operating conditions, and thus, the maximum value has to be used for stability design. The switching frequency of the converter is designed to roughly track the conductance of switches S1 , 4 , 5 such that the total output resistance of the converter is dominated by the resistances of switches S1 , 4 , 5 . This allows coarse frequency binning without destabilizing effects since a change in switching frequency has negligible impact on the total converter output resistance. Further, to avoid discontinuous transition in switching frequency, the controller uses lower bound hysteretic control to obtain a smooth and continuous transition from one frequency bin to another [12]. This choice of switching frequency not only smoothes the impulsive transfer of charges to the output capacitor and reduces the output voltage ripple, but also results in

lower power loss under light-load conditions. Since the controller maintains a constant VDROP through modulating ROUT in Fig. 2, conductance of switches S1 , 4 , 5 are set proportional to output current when no conversion ratio change is initiated by the outer loop controller. The action of the outer loop controller is discussed in the next section. Thus, by setting switching frequency roughly proportional to conductance of switches S1 , 4 , 5 , the switching frequency scales roughly proportional to output current as well. Since switching loss associated with gate drive is the dominant loss under light-load conditions, this choice of switching frequency allows the converter to maintain high efciency under light-load conditions. In terms of implementation, the gate drive voltage of switches S1 , 4 , 5 , VGD , is digitized using a simple ash analog-to-digital converter (ADC) and is used as a proxy for switch conductance. The controller then uses the digitized VGD to determine the switching frequency of the converter. The controller runs on a 50 MHz clock generated by an on-chip oscillator, and is capable of generating a switching frequency ranging from a maximum value of 2.5 MHz to virtually 0 Hz. The converter stops switching if switches S1 , 4 , 5 are in a cut-off region and yet the output voltage is higher than the reference level. Clocking is only initiated when the stored charge in the output capacitor is reduced, and the output recovers to its reference value. B. Outer Loop Controller The outer loop controller chooses the optimal conversion ratio such that the converter maintains regulation and attains maximum efciency under all line and load conditions. The outer loop controller bases its decision on the output conductance of the converter, GOUT in Fig. 2, and an estimate voltage drop across the virtual output resistor of the converter, VDROP . Conductance GOUT is approximated by the digitized gate drive voltage VGD as developed in the inner loop controller. The value VDROP = (VIN /n VOUT ) is estimated by rst dividing VIN using a voltage divider, and then converting to the digital domain using a ash ADC. The voltage divider has a variable division ratio chosen to be n by the controller, where n is the conversion ratio, and the ash ADC uses a reference voltage proportional to VOUT . The outer loop controller changes the conversion ratio by both feedback action and feedforward action. Feedforward action is used when VDROP drops to below 20 mV due to a change in input voltage. When this happens, the converter is closed to being unable to maintain regulation, and thus, a reduction in conversion ratio is needed. Depending on the measured VDROP value, the outer loop controller changes the conversion ratio by one or more steps. Since the optimal conversion ratio depends on both VDROP and GOUT , this feedforward action can only get the conversion ratio to roughly the optimal value. Feedback action is used to allow the conversion ratio to converge close to its optimal value. Feedback action of the outer loop controller reduces the conversion ratio when GOUT approaches its maximum value, GM AX , and increases the conversion ratio when VDROP is high and GOUT is low. When GOUT approaches GM AX , the inner

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Fig. 5.

Control law of an outer loop controller.

Fig. 4. ratio.

Contour plot showing expected efciency and optimal conversion

loop is closed to saturation, and the converter requires a larger VDROP to supply the needed load current. This condition is detected by comparing VGD to a reference 100 mV since PMOS switches S1 , 4 , 5 are fully ON at this gate drive voltage level. In this scenario, the outer loop controller reduces the conversion ratio by one step to increase VDROP and maintain regulation. On the other hand, the outer loop controller increases the conversion ratio by one step when VDROP is high and GOUT is low. Although the converter is under regulation in this scenario, a high VDROP limits the maximum achievable efciency of the converter due to series loss. While the exact condition to increase the conversion ratio can be derived and calculated [12], this converter uses a simplied condition of VDROP > 220 mV and GOUT < 0.05 GM AX . Fig. 4 shows the expected efciency of the converter and corresponding conversion ratio when the optimal conversion is achieved by the outer loop controller. Besides maintaining regulation and maximizing efciency, the outer loop controller also performs overcurrent protection. Instead of measuring output current directly, this converter uses a combination of large VDROP and large GOUT to simplify an overcurrent condition. When VDROP > 300 mV and GOUT = GM AX , the output current is determined to be too high, and the outer loop controller does not allow any further reduction in the conversion ratio. Without a reduction in the conversion ratio, the output voltage drops, and will eventually shut down the controller as it is powered OFF from the output terminal. The converter will stop switching and protection clamps [11] will protect the low-voltage transistors in each voltage domain from overvoltage stress. Fig. 5 summarizes all the various conditions implemented in the outer loop using the GVDROP space. IV. RESULTS Fig. 6 shows the expected efciency and measured efciency of the converter versus IOUT at around VIN = 8.7 V. As shown in the gure, this converter attains a peak efciency of 92% and maintains efciency higher than 80% over an output current range from 5 mA to 1 A. The efciency of the converter reduces

Fig. 6. Expected and measured efciency versus output current at an input voltage around 8.7 V.

Fig. 7. Expected and measured efciency versus input voltage at output current around 50 and 220 mV.

for IOUT > 700 mA because a reduction in the conversion ratio is needed to maintain regulation. When a conversion ratio is reduced, VDROP , which equals the voltage drop across the output referred resistance of the converter, increases, and thus, efciency of the converter is reduced. Fig. 7 shows the expected efciency and measured efciency of the converter versus VIN with IOUT at 220 and at 50 mA. As shown in the gure, this converter maintains efciency higher than 85% from 7.5 to 13 V with a nominal VOUT of 1.5 V. The expected efciency curve is calculated assuming that switching frequency is scaled linearly with switch conductance. Due to an approximation implemented in the inner loop frequency modulation

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Fig. 8. Oscilloscope plot of loading and unloading output current step of 1 A at input voltage equals 9 V. Timebase 20 s/div. TABLE II COMPONENTS USED AND CONTRIBUTION TO POWER LOSS Fig. 9. Die photo of the fabricated silicon chip.

Fig. 10.

Comparison of efciency between this work and similar works.

block, the converter may switch faster (reduces efciency) or slower (increases efciency) than the expected frequency. Fig. 8 shows the load transient response of the converter during loading and unloading steps of 1 A. On the loading transient, after rst increasing switch conductances to their maximum values, the controller decreases the conversion ratio from 5.5 to 5, in order to meet the load. On the unloading transient, the controller immediately stops clocking, and then adjusts the conversion ratio back to 5.5 to be prepared to continue operation. Clocking is only initiated when the stored charge in the output capacitor is reduced, and the output recovers to its regulated value. The output voltage is regulated to within 30 mV during the transient. Table II shows the components used in this converter and the contributing factors to power loss. Off-chip X5R EIA size code 0603 ceramic capacitors are used due to their high-density capacitance and low cost. A maximum switching frequency of 2.5 MHz is chosen for this converter based on the approximate ESR corner frequency of 5 MHz of these power train capacitors. The widths of the power train switches are chosen such that they contribute roughly half of the fast switching limit output resistance, RFSL . In the asymptotic fast switching limit, the

voltages on the power train capacitors remain constant, and current ows are represented by square waveforms within each phase of conduction. In this case, the output referred resistance is determined by the resistancesswitch, metal, ESR, bond-wire, etc., [1]. In contrast, in the slow switching limit (SSL), the output referred resistance is determined by the values of the power-train capacitors [1]. In the asymptotic SSL, capacitors are allowed to fully equilibrate after each clock edge, and consequently, output resistance is determined only by capacitor values in this limit. Table II also shows the output referred resistance, ROUT , at 2.5 MHz switching frequency, at which the circuit output resistance is dominated by the fast switching limit impedance. As evidenced from Table II, power loss at 1 A load is dominated by conduction loss of bond-wire and on-chip metal resistances, rather than conduction loss due to on-chip MOS channel or power-switch gate-drive loss. Fig. 9 shows the die photo of the fabricated silicon in a 0.18-m CMOS process. The total die area of this experimental converter is 11.55 mm2 , but only

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TABLE III COMPARISON BETWEEN THIS WORK AND SIMILAR WORKS

V. CONCLUSION The traditional inductor-based buck converter has been the default design for switched-mode voltage regulators for decades. Switched capacitor (SC) dcdc converters, on the other hand, have traditionally been used in low-power (<10 mW) and low conversion ratio (<4:1) applications where neither regulation nor efciency is critical. This study encompasses the complete successful design, fabrication, and test of a CMOS-based SC dcdc converter, addressing the ubiquitous 121.5 V boardmounted point-of-load application. In particular, the circuit developed in this study attains higher efciency (92% peak, and >80% over a load range of 5 mA to 1 A) than surveyed competitive buck converters, while requiring less board area and less costly passive components. The topology and controller enable a wide input range of 7.513.5 V. Controls based on feedback and feedforward provide tight regulation under worst case line and load step conditions. This study shows that the SC converter can outperform the buck converter, and thus, the scope of SC converter application can and should be expanded. ACKNOWLEDGMENT The authors would like to thank National Semiconductor for manufacturing the test silicon. REFERENCES
[1] M. Seeman and S. Sanders, Analysis and optimization of switchedcapacitor dcdc converters, IEEE Trans. Power Electron., vol. 23, no. 2, pp. 841851, Mar. 2008. [2] M. Seeman, V. Ng, H.-P. Le, M. John, E. Aton, and S. Sanders, A comparative analysis of switched-capacitor and inductor-based dcdc conversion technologies, in Proc. IEEE Workshop Control Model. Power Electron. (COMPEL), Jun. 2010. [3] M. Seeman, A design methodology for switched-capacitor dc-dc converters, Ph.D. dissertation, UC Berkeley, Berkeley, CA, May 2009. [4] High Efciency, 250 mA Step-Down Charge Pump, Texas Instruments (TPS60503), Dallas, TX, 2002. [5] 500 mA High Efciency, Low Noise, Inductor-Less Step-Down DC/DC Converter, Linear Technology (LTC3251), Milpitas, CA, 2003. [6] 1A Simple Switcher Power Module With 20V Maximum Input Voltage, National Semiconductor Inc. (LMZ12001), Santa Clara, CA, Jun. 2010. [7] 1.5A, 15V Monolithic Synchronous Step-Down Regulator, Linear Technology (LTC3601), Milpitas, CA, 2009. [8] 2A, 16V, Non-Synchronous Step-Down, DC/DC Regulator, Fairchild Semiconductor Inc. (FAN8301), San Jose, CA, Nov. 2008. [9] 4.5V to 18V Input, 2-A Synchronous Step-Down Swift Converter With Eco-Mode, Texas Instruments (TPS54226), Dallas, TX, Feb. 2011. [10] J. F. Dickson, On-chip high-voltage generation in nmos integrated circuits using an improved voltage multiplier technique, IEEE J. Solid-State Circuits, vol. 11, no. 3, pp. 376378, Jun. 1976. [11] V. Ng, M. Seeman, and S. Sanders, Minimum PCB footprint point-ofload dcdc converter realized with switched capacitor architecture, in Proc. IEEE Energy Convers. Congr. Expo., Sep. 2009, pp. 15751581.

Fig. 11.

Comparison between this work and similar works.

about 20% of the die area is occupied by active power train devices. Rather, die area is dominated by bond pads and other conservative design considerations for this experimental chip. Solder bump interconnect and a thick on-chip metal layer would allow a substantial performance improvement, manifested in reduced diesize. Fig. 10 shows a graph comparing the peak efciency of this converter with that of similarly rated converters. All the surveyed buck and SC converters achieve respectable efciency, but show a general trend of reduced efciency as conversion ratio increases. This study shows a signicant increase in efciency when compared to similarly rated SC and buck converters. Table III and Fig. 11 compare critical performance metrics of this work with other existing technologies. In addition to higher peak efciency, the reported device achieves high efciency for a wider range of load currents than in other competitive designs. Peak-to-peak output voltage transient during a full-load current step is also respectable while using similar values of input and output capacitances. Signicantly, this study also achieves an overall reduction in PCB area, passive component height, and passive component cost when compared to dcdc converters with similar ratings. This comparison only considers input/output capacitors, inductors and power-train capacitors because other auxiliary passives required for compensation, start-up, etc., are not fundamental and are eliminated or minimized in leading modern designs. The estimated cost of capacitors or inductors is based on large-volume purchase perunit prices from Digikey. This study shows that the SC converter provides a new direction for performance and cost advantages with respect to the conventional buck converter.

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[12] V. Ng, Switched capacitor dcdc converter: superior where the buck converter has dominated, Ph.D. dissertation, UC Berkeley, Berkeley, CA, Dec. 2011. [13] L. Salem and R. Jain, A novel control technique to eliminate outputvoltage-ripple in switched-capacitor dc-dc converters, in Proc. IEEE Int. Symp. Circuits Syst., Jun. 2011, pp. 825828. [14] V. Ng and S. Sanders, A 92% efciency wide-input voltage range switched-capacitor dc-dc converter, in Proc. IEEE Solid State Circuit Conf., Feb. 2012, pp. 282284.

Vincent W. Ng (M10) received the B.S. degree in electrical and computer engineering from Cornell University, Ithaca, NY, and the Ph.D. degree in electrical engineering from UC Berkeley, Berkeley, in 2005 and 2011, respectively. His Ph.D. research was focused on designing switched-capacitor dcdc converter for point-of-load applications. Since 2010, he has been with Volterra Semiconductor, Fremont, CA, as a Design Engineer on voltage regulators in solar power application. His research interests include integrated circuits for power electronics, renewable energy, dcdc conversion circuitries, and control systems.

Seth R. Sanders (F10) received the S.B. degrees in electrical engineering and physics in 1981, and the S.M. and Ph.D. degrees in electrical engineering from the Massachusetts Institute of Technology, Cambridge, in 1985 and 1989, respectively. Following an early experience as a Design Engineer at the Honeywell Test Instruments Division in 19811983, he joined the UC Berkeley faculty in 1989. He is a Professor of electrical engineering in the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley. His research interests include high-frequency power conversion circuits and components, design and control of electric machine systems, and nonlinear circuit and system theory as related to the power electronics eld. He is presently or has recently been active in supervising research projects in the areas of ywheel energy storage, novel electric machine design, renewable energy systems, and digital pulse-width modulation strategies and associated IC designs for power conversion applications. During the 19921993 academic year, he was on industrial leave with National Semiconductor, Santa Clara, CA. Dr. Sanders received the NSF Young Investigator Award in 1993 and multiple Best Paper Awards from the IEEE Power Electronics and the IEEE Industry Applications Societies. He has served as the Chair of the IEEE Technical Committee on Computers in Power Electronics, and as a Member-At-Large of the IEEE PELS Adcom.