CD4010C Hex Buffers (Non-Inverting)

October 1987 Revised June 2000

CD4010C Hex Buffers (Non-Inverting)

General Description
The CD4010C hex buffers are monolithic complementary MOS (CMOS) integrated circuits. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage. This results in high noise immunity over a wide supply voltage range. No DC power other than that caused by leakage current is consumed during static conditions. All inputs are protected against static discharge. These gates may be used as hex buffers, CMOS to DTL or TTL interface or as CMOS current drivers. Conversion ranges are from 3V to 15V providing VCC VDD. The devices also have buffered outputs which improve transfer characteristics by providing very high gain.

Features
I Wide supply voltage range: I Low power: 100 nW (typ.) 8 mA (min.) at VO = 0.5V 3.0V to 15V I High noise immunity: 0.45 VDD (typ.) I High current sinking: capability: and VDD = 10V

Applications
Automotive Data terminals Instrumentation Medical electronics Alarm system Industrial controls Remote metering Computers

Ordering Code:
Order Number CD4010CM CD4010CN Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram
Pin Assignments for DIP and SOIC

Schematic Diagram

Hex COS/MOS to DTL or TTL converter (inverting). Connect VCC to DTL or TTL supply. Connect VDD to COS/MOS supply.

Top View

2000 Fairchild Semiconductor Corporation

DS005945

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CD4010C

Absolute Maximum Ratings(Note 1)

Voltage at Any Pin (Note 2) Operating Temperature Range Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) Operating Range (VDD) 260C VSS + 3V to VSS + 15V 700 mW 500 mW
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Note 2: This device should not be connected to circuits with the power on because high transient voltage may cause permanent damage.

VSS 0.3V to VSS +15.5V

45C to +85C 65C to +150C

DC Electrical Characteristics
Test Conditions Symbol Characteristics VO ICC PD Quiescent Device Current Quiescent Device Dissipation/Package Output Voltage VOL VOH LOW Level HIGH Level Noise Immunity (All Inputs) VNL VNH Output Drive Current IDN IDP IIN N-Channel (Note 3) P-Channel (Note 3) Input Current VO 1.5 VO 3.0 VO 3.5 VO 7.0 0.4 0.5 2.5 9.5
Note 3: IDN and IDP are tested one output at a time.

Limits 40C +25C Min Typ 0.03 0.05 0.15 0.5 0 0 4.99 9.99 5 10 Max 3 5 15 50 0.01 0.01 4.95 9.95 Min +85C Max 42 70 210 700 0.05 0.05 A A W W V V V V Units Min Max 3 5 15 50 0.01 0.01 4.99 9.99

(Volts) VDD 5 10 5 10 5 10 5 10

5 10 5 10 5 10 5 10

1.6 3.2 1.4 2.9 3.6 9.6 1.5 0.72

1.5 3 1.5 3 3 8 1.25 0.6

2.25 4.5 2.25 4.5

1.4 2.9 1.5 3 2.4 6.4 1 0.48

V V V V mA mA mA mA pA

10

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CD4010C

AC Electrical Characteristics
Symbol tPHL tPLH Characteristics Propagation Delay Time: HIGH-to-LOW Level (tPHL)

(Note 4)
Test Conditions VDD (Volts) Min 5 10 5 10 5 10 Limits Typ 15 10 10 50 25 15 20 16 80 50 5 Max 70 40 35 100 70 40 60 50 160 120 pF ns ns ns ns Units

TA= 25c, CL= 15 pF, unless otherwise noted. Typical Temperature coefficient for all values of VDD= 0.3%/C

VCC = VDD VDD = 10V VCC = 5V

5 10

LOW-to-HIGH Level (tPLH)

VCC = VDD VDD = 10V VCC = 5V

tTHL tTLH

Transition Time: HIGH-to-LOW Level (tTHL) LOW-to-HIGH Level (tTLH) Input Capacitance (CI)

VCC = VDD VCC = VDD Any Input

Note 4: AC Parameters are guaranteed by DC correlated testing.

Typical Application

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CD4010C

Physical Dimensions inches (millimeters) unless otherwise noted

16-Line Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A

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CD4010C Hex Buffers (Non-Inverting)

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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