Ball Grid Array Performance Characteristics; A User's Design Guide

Thomas S. Tarter Advanced Micro Devices Sunnyvale, CA Martin P. Goetz and Marc Papageorge ASAT, Inc. Palo Alto, CA
ABSTRACT The popularity of array packages, especially ball grid array (BGA) formats, is increasing rapidly and is of great interest to integrated circuit (IC) manufacturers. High pin counts in compact form factors are key features for microprocessors, ASICs, and other I/O intensive products. Benefits of the BGA format include ease of surface mounting due to relaxed lead pitch, relatively low cost, and enhanced performance options. Due to the multitude of BGA package styles, many users are unsure of which package may be best suited for their specific application. This paper describes options for BGA packages and discusses advantages and disadvantages of the various styles available. The performance specifications consider BGA capabilities in terms of thermal and electrical characteristics pulled from industry sources, as well as measured parameters and theoretical models. Thermal characteristics of BGAs vary greatly with package style and application environment. Electrical parameters can be designed in while taking into account cost and manufacturability. Performance capabilities of various formats are compared with reference to cost considerations, applicability, and infrastructure for assembly and rework. Physical representations are included for many current BGA types including overmolded plastic (PBGA), cavity plastic (CPBGA), ceramic (CBGA), and tape (TBGA) types. Die mounting and dieto-package interconnects are investigated with emphasis on flip-chip and wire-bond processes as well as applications for few-chip or multi-chip modules using BGA formats. Performance enhancements include internal and external heat sinking methods, power planes in the BGA substrate as well as the mounting surface, and signal routing effects. This work will help the package user to select a range of packages based on performance and cost and will increase the understanding of internal and external effects on BGA packaging performance. INTRODUCTION Due to the BGA formats popularity, the volume of packages being manufactured are rising, especially for lead counts of 256 and higher. BGAs are attractive for these applications as an alternative to packaging styles such as plastic quad flat packs (PQFPs) which require more board space. Moreover, high pin count PQFPs have lead pitches of less than 0.4 mm which can be difficult to handle and surface mount. In fact, most U.S. manufacturers are not inclined to use components with outer lead pitches less than 0.4 mm which is helping to drive the application of array packaging. Thermal and electrical performance parameters for IC packaging are primary design variables that can offer tradeoffs for cost and manufacturability and determine the market segment into which a particular package-device combination will fit. Electronic systems are becoming ever smaller and ultra-compact thereby increasing the density of components on the printed circuit board (PCB). This not only leads to physical dimension limitations, but it increases concerns about system-level thermal performance. With increasing clock and data transfer rates, package electrical and thermal performance can become bottlenecks in the design cycle. By using good design practices, the optimum cost-performance needs can be satisfied. This paper presents a set of relationships along with generalized rules to follow when selecting package options during the design process. References to published papers, books and other pertinent documents are included for more in-depth study. Performance capabilities and limitations associated with geometry, material properties and configuration alternatives are also discussed to assist the design team in identifying the best package to satisfy their application requirements. BGA PACKAGE FORMATS BGA packages are available in several formats. The selection criteria should aim towards the best performance while maintaining an allowable cost. Table 1 lists several typical BGA package types. Thermal performance for BGAs is roughly equivalent to PQFPs, and can be easily enhanced, provided the proper design guidelines are followed. Electrical performance is usually also enhanced. Plastic Ball Grid Array (PBGA) Package A cross-section of a typical PBGA is shown in Figure 1. The PBGA package design utilizes a single or multilayer, bismaleimidetriazine (BT) resin-glass-cloth substrate. The die is attached to the substrate with silver-filled epoxy, and gold wire bonds are used for die-to-package interconnects. The die is encapsulated by a transfer molding process using

a low-stress molding compound. The BT substrate is processed using fine-line PCB manufacturing techniques. Traces are typically fanned-out from the bond fingers to the periphery of the substrate and fed through the board with vias (plated through holes). The vias are routed to the array of pads. Low melting point solder balls (63Sn37Pb) are attached to the substrate on Ni-Au plated pads. Table 1. Ball Grid Array Package Configurations PBGA (Plastic Ball Grid Array) [1] Encapsulation Styles Overmolded Globtop Lid Seal (B-Stage) Ball Material Low Temperature Solder (63Sn37Pb) CPBGA (Cavity Plastic Ball Grid Array) [2] Encapsulation Styles Globtop Lid Seal (B-Stage) Ball Material Low Temperature Solder (63Sn37Pb) CBGA (Ceramic Ball Grid Array) [3] Multilayer Ceramic Frit Seal Solder Seal Ball Composition High Temperature Solder (10Sn/90Pb) TBGA (Tape Ball Grid Array) [4] Single Layer / Two-Layer Tape Encapsulation Lid Attachment Heat Sink Attachment Ball Composition High Temperature Solder (10Sn/90Pb)

bonding tiers. The die is attached with silver-filled epoxy and gold wire is used for bonding the chip to the package. The cavity is filled with liquid encapsulant to protect the die and wire bonds. Low melting point (63Sn37Pb) solder balls are attached around the cavity to the substrate. Other references to this type of package are enhanced ball grid array (EBGA) and SuperBGA [2].
Die Copper Slug Die Attach Via

Solder Ball

Lid or Liquid Encapsulant

Wire Bond

Laminate

Figure 2. Cavity Plastic Ball Grid Array (CPBGA) Ceramic Ball Grid Array (CBGA) This package format is manufactured using typical ceramic cofire processes. Tungsten traces are used for conductors, and multiple layers are common. High performance can be obtained by the use of multiple power/ground planes, coupled with stripline signal layers. The die is either die attached using silver-glass or cyanite-ester compounds, and wire bonded using aluminum wire, or flip-chip techniques can be used for device interconnection. The use of flip-chip methods improves electrical performance and can enhance the CBGAs thermal performance capability. Solder balls are usually high temperature solder and are connected to the substrate and mounting surface using 63Sn37Pb solder. A generic representation of a CBGA package is shown in Figure 3.
Cap Thermal Grease Die Flip-chip attach Underfill

Die Attach

Molding Compound

Die

Wire Bond Solder Ball (10Sn90Pb) Eutectic solder Multi-layer Ceramic Substrate

Trace

Substrate

Figure 3. Ceramic Ball Grid Array (CBGA) Tape Ball Grid Array (TBGA) TBGA packages are constructed using standard tapeautomated-bonding (TAB) materials. The tape is typically a two-layer design and is made of copper-polyimide film. High melting point (10Sn90PB) solder balls are reflowed to plated through holes in the tape on 1.27 mm centers. The die is attached to the tape using TAB inner-lead bonding and stiffeners are added to the tape to increase rigidity. The die down configuration allows direct attachment of a heat sink to the backside of the die. Electrical properties are enhanced due to the short electrical paths and close

Solder Mask

Solder Ball

Plated Through Hole

Figure 1. Plastic Ball Grid Array (PBGA) Cavity Plastic Ball Grid Array (CPBGA) This package is designed to be a relatively low-cost, highperformance package for which there has been a proliferation of design options. A cross-section of a typical construction is shown in Figure 2. Construction is of a laminate design, allowing the option of multiple layers and

proximity to a ground plane when two-layer tape is used. A typical cross-section of a TBGA package is shown in Figure 4. Other Ball Grid Array Packages Many other types of BGA packages are available. These include variations on the basic configurations shown here as well as chip-size or near chip-size packages. Although these packages are not detailed herein, Table 2 provides an overview of their construction.
Heat Sink Thermal Grease Die Underfill

JX =

TJ TX PH

(1)

Where; JX = thermal resistance, junction to reference (C/W) Tj = steady-state junction temperature (C) Tx = reference temperature (C) PH = power dissipation (W) The most common thermal metric is JA (thermal resistance junction-to-ambient) but many other resistances and symbols are commonly used. See Table 3. Table 3. Common Junction-To-Environment Symbols Symbol Definition; Thermal Resistance, JA junction-to-ambient JB junction-to-board JC junction-to-case JL junction-to-liquid JMA junction-to-moving air JP junction-to-pin JR junction-to-reference JX junction-to-defined environment (x) Thermal resistance can be influenced dramatically by the environment, mounting surface, and neighboring heatdissipating elements. Due to typical BGA design, the system board becomes a fundamental part of the cooling mechanism, disallowing component-only considerations. This system-level effect is pronounced and must be evaluated simultaneously with the package. Other enhancements to thermal performance can be made, both internal and external to the package, by the selection of appropriate materials and with the addition of heat sinks. BGA THERMAL PERFORMANCE The following information is helpful in choosing a BGA technology and determining if thermal enhancement is needed to satisfy the design rules. Several BGA packages are compared with ja as the metric. Table 4 provides a list of the BGA package types with a description of each configuration. The table describes the package, vias in the substrate, if any, the mounting surface, and any heat sinking applied to the package. Included in the table are references for more information and a key number is supplied to be used to identify the particular format in reference graphs and tables. Graph 1 shows thermal resistance ranges for a variety of BGA packages. The data shows that there is a wide range of thermal resistance capability in the BGA package family. Graph 2 presents the same data, sorted by thermal resistance. Here we see that the pin count (thus the overall geometry) of a BGA package does not limit the performance that can be gained by the addition of various thermal enhancements.

Adhesive

Stiffener Solder Ball (10Sn90Pb) TAB Tape Frame Flip-chip attach

Figure 4. Tape Ball Grid Array (TBGA)

Table 2. Other BGA Package Types Mini BGA (Sandia Labs) [5, 6] Chip size package Array pads for solder balls or adhesive attach BGA (Tessera) [7, 8, 9] Chip size package Peripheral die pads to array 85 m Ni-Au bumps 20 mil (0.5 mm) and 30 mil pitch (0.75 mm) SLICC (Motorola) [10] Slightly larger than chip size Flip chip to organic substrate 15 mil (0.375 mm) solder balls 35 mil pitch C2BGA (SGS Thompson) [11] Conduction Cooled Ball Grid Array Chip attached directly to copper slug Wire bond interconnect BT epoxy substrate THERMAL PERFORMANCE METRICS Performance characteristics are best determined by a combination of measurements and models of the parameters desired, or one can use package supplier data to compare various packaging options. The most common method of reporting thermal performance data is in the form of a thermal resistance, specified as the steady-state temperature difference between the junction and the reference point. The mathematical definition is shown in equation (1).

Table 4. BGA Package Configuration Table Key Package Body Cavity 1 169 PBGA 23 mm Up 2 169 PBGA 23 mm Up 3 169 PBGA 23 mm Up 4 169 PBGA 23 mm Up 5 169 PBGA 23 mm Down 6 240 CBGA 25 mm Up 7 240 CBGA 25 mm Up 8 240 CBGA 25 mm Up 9 240 CBGA 25 mm Up 10 240 CBGA 25 mm Up 11 240 CBGA 25 mm Up 12 225 PBGA 27 mm Up 13 225 PBGA 27 mm Up 14 225 PBGA 27 mm Up 15 225 PBGA 27 mm Up 16 225 PBGA 27 mm Up 17 225 PBGA 27 mm Up 18 256 PBGA 27 mm Up 19 256 SBGA 27 mm Down 20 400 CBGA 32 mm Down 21 400 CBGA 32 mm Down 22 320 CPBGA 40 mm Down 23 320 CPBGA 40 mm Down

Chip Attach Wire bond Wire bond Wire bond Wire bond Wire bond Wire bond Wire bond Flip chip Flip chip Flip chip Flip chip Wire bond Wire bond Wire bond Wire bond Wire bond Wire bond Wire bond Wire bond Wire bond Wire bond Wire bond Wire bond

Vias 8 8 24 24 -------28 28 64 64 16 16 -------

PCB 2 layer 4 layer 2 layer 4 layer -------2 layer 4 layer 2 layer 4 layer 2 layer 4 layer 2 layer 2 layer --6 layer 6 layer

Pd 1.2W 1.2W 1.2W 1.2W -------1W 1W 1W 1W 1W 1W 2W 2W --3W 3W

Comments
No planes Vias connected to plane No planes Vias connected to plane Top mount heat sink 10 mm fin heat sink Cap cooling, th. grease Cap,10mm fin heat sink Flat plate cooling Capless, 10mm fin h/s No planes Vias connected to plane No planes Vias connected to plane No planes Vias connected to plane No planes No planes 10mm fin heat sink 23 mm slug 38 mm slug

Ref. (12) (12) (12) (12) (13) (14) (14) (14) (14) (14) (14) (15) (15) (15) (15) (15) (15) (16) (16) (15) (15) (17) (17)

BGA Thermal Resistance

60.00

50.00

40.00

30.00 ja C/W 20.00

10.00

0.00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Key

Graph 1. BGA Thermal Resistance (sorted by package)

BGA Thermal Resistance

60.00

50.00

40.00

30.00 ja C/W 20.00

10.00

0.00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Key 20 21 22 23

Graph 2. BGA Thermal Resistance (sorted by JA) Printed Circuit Board (PCB) Considerations When selecting a package, be sure to keep in mind the end- use mounting surface. The PCB has a major effect on the thermal resistance of BGA packages. In fact, thermal enhancements such as vias in the BGA substrate are not effective unless the PCB is designed to take advantage of them. The thermal conductivity of the PCB is increased as layers are added. Ground or power planes add more copper to the board, thereby increasing thermal conductivity and decreasing the thermal resistance of the component. Table 5 shows the calculated thermal conductivity of typical FR-4/Cu laminate circuit boards[18, 19, 20, 21]. Table 5. Calculated Thermal Conductivity of PCB Board Description ~k (w/mC) Two-Layer, 5% Cu content 0.75 Two-Layer, 25% Cu content 3.0 Two-Layer, 50% Cu content 5.6 Four-Layer 13.4 Eight-Layer 17.6 The effect of the PCB on the systems thermal capability is further illustrated in Graph 3. In this graph, the significance of increasing the thermal conductivity of the PCB is clearly evident on 169- and 225- lead packages. The enhancement due to higher PCB thermal conductivity is directly related to the number of vias in the BGA substrate. For example, in Graph 3 three of the packages show an approximate 46% decrease in thermal resistance due to PCB enhancement. These packages are 169 PBGA #3, 225 PBGA #12, and 225 PBGA #14, which have thermal via counts of 24, 28, and 64 respectively. The 169 PBGA #1, on the other hand, has 8 vias and 225 PBGA #16 has 16 vias. These lower via count packages show an approximate 35% decrease in thermal resistance because of the additional layers in the PCB. In these examples, the PCB has filled vias that are connected to copper planes within the PCB. POWER DISSIPATION CONSIDERATIONS Graph 4 shows the relationship between power dissipation and thermal resistance. This information can be used to judge the package thermal capability needed to satisfy design requirements. The chart shows power dissipation capability based on thermal resistance at ambient temperatures of 25C, 55C, and 70C. The temperature of the mounting surface must also be taken into account due to the dependence of the BGA package thermal performance on the PCB. A discussion of this phenomenon is documented by Mulgaonker, et. al. [22]. Graph 5 shows the BGA packages listed in Table 4, sorted by power dissipation capability for ambient temperatures of 25, 50, and 70C.

PC B Th e rm a l C o n d u c tivity Effe c ts o n Th e rm a l Re sista n c e o f Se le c te d BG A Pa c k a g e s

169 PBG A #1 169 PBG A #3 50 45 225 PBG A #12 225 PBG A #14 225 PBG A #16 40 35 30 25 20 2-la y e r (k ~ 3.0 w / m C )
PC B La y e rs

55

JA - C/W

4-la y e r (k ~ 13 w / m C )

Graph 3. Effect of PCB Thermal Conductivity

Th e rm a l Re sist a n c e Re q u ire m e n t s - Pd = 0 W t o 1 0 0 W 100

Ta = 7 0 Ta = 5 5 Ta = 2 5 10

ja C / W

0.1 1 10 Pd - W 100

Graph 4. Power Dissipation and Thermal Resistance

BGA Power Dissipation Capability

14.00

12.00

10.00

8.00 Pd - W 6.00 Pd(70C) Pd(55C) Pd(25C)

4.00

2.00

0.00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Key 23

Graph 5. BGA Power Dissipation Capability ELECTRICAL PERFORMANCE METRICS Electrical performance of microelectronic packages is another fundamental concern. Typically, the electrical characteristics of the package are described by the inductance (L), capacitance (C), and resistance (R) of the interconnects. These parameters are frequency dependent and are affected by proximity of the conductors to ground planes and to each other. Mutual coupling effects can help or hinder in the design. Electrical performance can also be defined by time delay (td) and characteristic impedance (Z0). Z0 can be approximated by equation (2) for a uniform transmission line. Inductance is most problematic for power supply interconnects, as power or ground noise is generated by the combination of simultaneous switching output currents and the interconnect inductance (Ldi/dt effects). If the magnitude of this noise is above the allowable device thresholds, non-switching or false switching can occur. Graph 6 shows the frequency vs. inductance between various packages of a similar body size. Self inductance of BGA package interconnects range from less than 2nH to over 11nH. Although there is a wide range of values, most BGA package designs can hold up to 50% of the signal line inductances to less than about 6nH. Using well defined return paths can drastically reduce inductance in PBGA designs. Mutual inductance of signal lines is reported to be very low, typically 100pH to 400pH in CBGA. Plane inductance can be very low due to the ability to have several planes in the substrate, and to assign specific pins to the planes. Published data shows power plane inductances ranging from 300pH to 400pH, and power supply loop inductances as low as 60pH, making the package attractive from a ground bounce perspective. Graph 7 shows signal line self inductances for package types shown in Table 6. Capacitance is related to loading and time delay effects, especially when coupled with resistance (RC time constant). Data indicates typical capacitances to be in the range of 0.4 pF to 6.0 pF depending on the geometry and materials used in the package design. Graph 8 plots signal

Z0
Where;

L0 C0

(2)

Z0 = characteristic impedance L0 = per unit length inductance C0 = per unit length capacitance L, C, and R values are typically generated for a given frequency range such as 1Mhz and 10Mhz, or at the typical frequency that the device is expected to operate at. Although all packages have these properties, they are, for the most part, unwanted and cause problems. The values are therefore commonly referred to as parasitics.

line bulk capacitance for package types listed in Table 6. .Most of the materials used for interconnects have low resistance so this property is usually the least destructive to the signal integrity. Only at high frequency is this parameter of concern due to skin effects. Graph 9 shows the frequency vs. resistance between various packages of a similar body size. Electrical performance can be enhanced by adding ground and power planes, intelligent routing, and attention to decoupling and impedance parameters. Low-cost, two-layer substrates in PBGA packages can be electrically enhanced by routing traces to take advantage of mutual coupling [24]. Graph 10 shows the frequency vs. coupling percentage between various packages of similar body size. An interposer ring can be an effective design enhancement in the two (metal) layer BGA substrate design. Incorporating the interposer ring reduces lead inductance in both power and ground interconnects. Figure 5 shows the difference between two designs, one with a traditional die attach pad, the other with an interposer ring.

Typical BG A S i g n a l L i n e I n d u c t a n c e
6 5 4
Pkg. Ke y

3 2 1 0 0 1 2 3 4 5 6
Ls(nH )

10

11

12

Graph 7. Inductance ranges for selected packages. See Table 5 for legend.
T ypical BGA Signal line Capacitance
6 5 Pkg. 4 Key 3 2 1 0 0 2 C(pF) 4 6

10 Inductance (nH) 8 6 4 2 0 0 200 400 600 800 Frequency (MHz) 1000

256 PBGA 256 TBGA 225 PBGA

Graph 8. Capacitance ranges for selected packages. See Table 5 for legend.

500 Resistance (mOhms) 400 300 200 100 0 0 200 400 600 800 Frequency (MHz) 1000
256 PBGA 256 TBGA 225 PBGA

Graph 6. Frequency vs. inductance of various BGA packages (shortest lead) in the 27x27 mm body size. Table 6. Key for Graph 7 and Graph 8. Key Type Ref. 1 140 PBGA [13] 2 Custom TBGA [14] 3 361 CBGA [23] 4 225 PBGA [24] 5 Custom CBGA [25] 6 Custom C4/CBGA [14] The difference in lead inductance between the two designs can be seen in Graph 11. This conveys not only the decrease in self inductance, Lxx, but also of the mutual inductances as well, Lxy. Three leads were analyzed running parallel on the topside using standard routing, and again using the interposer ring to connect to backside solder balls for power and ground connection.

Graph 9. Frequency vs. resistance of various BGA packages (shortest lead) in the 27x27mm body size. BALL GRID ARRAY PERFORMANCE SUMMARY The trade-offs of choosing the correct ball grid array product for the final system based on electrical and thermal performance is not the only analysis that is needed. Other trade-offs include: cost, reliability, space constraints, and manufacturability. The general summary set of relationships are shown in Graph 12. This chart reveals that each array package has its own characteristics and advantages for a proper selection. The graph is based on

30 25 Coupling (%) 20 15 10 5 0 0 200 400 600 800 Frequency (MHz) 1000

2L PBGA ML CD PBGA ML CU PBGA 1L TBGA 2L TBGA

Graph 10. Frequency vs. maximum coupling between lines for a 256 BGA, 27x27mm body size at 1.27 mm pitch. 1L = single (metal) layer, 2L = 2 (metal) layer, ML = multilayer, CD = cavity down configuration, and CU = cavity up.
14 12 Standard Interposer

Inductance (nH)

10 8 6 4 2 0 L11 L22 L33 L12

L23

L13

Matrix Number
Graph 11. Matrix relationships vs. inductance for a 225 PBGA package, 27x27mm body size. todays information regarding process and assembly technologies. For example, if the trade-offs are based on product performance and product cost and not product area, the obvious choice would be the TBGA or PBGA over the CSP. This would hold true for the CPBGA as well which is not shown in the figure. Further, it is quite obvious that the CBGA is more expensive, but if reliability and hermeticity is a must then the CBGA would be the proper selection. As improvements are made in substrate technology, such as cost and routability , Graph 12 will change accordingly. The eight variables shown are the most common concerns regarding package selection. These variables will always present trade-offs. The key is to understand what package is important for the total system design and the end-user.

Figure 5. 225 PBGA two (metal) layer board layout. Top drawing shows traditional union jack die attach pad design. Bottom design utilizes complete die attach pad design with surrounding power/ground interposer ring. CONCLUSION Thermal, electrical, and cost-performance issues for most popular BGA packages have been presented. This data, along with the references, has provided a comprehensive set of design guidelines that can be used to determine which BGA type is best suited for silicon performance while attaining comparable cost with other package technologies. The effect of the system on package thermal performance has been highlighted. This helps to clarify

thermal resistance metrics and further increases the understanding of the end-user. Electrical parametrics presented show the relative benefits of design options for enhanced electrical performance. The tradeoffs associated with cost vs. performance have been summarized for typical BGAs.
cost 4 power dissipation CSP PBGA TBGA CBGA clock frequency 3 2 1 0 height area ratio (die/pkg)

[7]

[8] [9]

[10]

[11]

[12]

[13]
board assembly reliability

ball count

[14] [15]

Graph 12. Multi-parameter comparison between various configurations of ball grid array packages. As time goes on, more BGA variations will be designed and the cost-performance tradeoffs will improve. This is due to an increasingly solid infrastructure and general acceptance of BGA reliability. BGAs are ideal for few-chip and multichip applications because of the PCB construction, intrapackage interconnects, and multiple cooling options. Because of its flexibility and performance capability, the BGA package has a bright future. Continuing technology advancements and cost reductions will surely make the BGA the package of choice well beyond the year 2000. REFERENCES [1] B. Freyman and R. Pennisi, Overmolded Plastic Pad Array Carriers (OMPAC): A Low Cost, High Interconnect Density IC Packaging Solution for Consumer and Industrial Elecctronics,1991 ECTC Proceedings, pp. 176 - 182 [2] Super BGA Advanced Products Operations Presentation, B. Marrs, April, 1995 [3] D. Banks, et. al., Second-Level Assembly of Column Grid Array Packages, Surface Mount International Proceedings, Aug. 1993, pp. 92 - 98 [4] F. Andros and R. Hammer, Area Array TAB Package Technology, ITAP 93 Proceedings, Feb. 1993 [5] A. Bindra, Sandia shrinks size of BGA packages, Electronic Engineering Times, May 1994, p. 57 [6] R. K. Treece, Technology Overview, mBGA Commercialization Project Workshop, April 1994

[16]

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[22]

[23]

[24]

[25]

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