INSTITUTE OF TECHNOLOGY, NIRMA UNIVERSITY, AHMEDABAD 382 481, 08-10 DECEMBER, 2011

Implementation of Software Defined Radio on FPGA

A. I. Mecwan, N. P. Gajjar
Abstract--The next generation of communication will be driven by the technology called Cognitive Radio that can adapt the environment around it. It adjusts to the changes in the communication medium, modulation schemes, coding method etc. Design of the radio on the reconfigurable platform makes it more flexible in adapting the demand of communication system. The paper covers the design of transmitter and receiver on the reconfigurable platform like FPGA, so that the modulation scheme can be dynamically adapted depending on the noise in the communication medium. The FPGAs can be configured partially when in use. This advantage makes it more useful in the SDR applications. Paper discusses the design and development of SDR on virtex 5 FPGA. The results are obtained and compare at simulation level. Index Terms--SDR, FPGA, Partial Reconfiguration

(transmitter side), Modulator, Demodulator, Encoder, Decoder, Error Counter and Decision Generator. II. BLOCKS OF SDR 1) Digital Down/Up Converter A fundamental part of any communications system is Digital Up/Down Converter (DUC/DDC). The DUC converts the IF band of frequency to move up the spectrum so that it can be transmitted efficiently. On the other hand the DDC allows the frequency band of interest to be moved down the spectrum so the sample rate can be reduced; filter requirements and further processing on the signal of interest become more easily realizable [23]. In this paper the DUC and DDC designs using FPGA are discussed. The main advantage of using an FPGA to implement the Digital Up/Down Converter is the speed, but it also has advantages associated with any digital signal processing system is that once it is defined it is fixed relative to the sample frequency, and will not change with time or temperature. 2) Block Diagram of DUC and DDC Figure 1 shows the basic block diagram of Digital Down Converter. Digital Up Converter is similar to DDC the only difference is that the CIC is an interpolation filter instead of a decimation filter.

I. INTRODUCTION Reconfigurability in radio development is not such a new technique as one might think. Already during the 1980s reconfigurable receivers were developed for radio intelligence in the short wave range. These receivers included interesting features like automatic recognition of the modulation mode of a received signal or bit stream analysis. An SR transceiver comprises all the layers of a communication system. An ideal SR directly samples the antenna output. A Software Defined Radio (SDR) is a practical version of an SR: the received signals are sampled after a suitable band selection filter. Fact is that the digitization of an unnecessary huge bandwidth filled with many different signals of which only a small part is determined for reception is neither technologically nor commercially desirable. However, there is no reason for a receiver to extremely oversample the desired signals while respecting extraordinary dynamic range requirements for the undesired in-band signals at the same time. Furthermore, the largest portion of the generated digital information, which stems from all undesired in band signals, is filtered out in the first digital signal processing step. The system presented in the paper basically works on Partial Reconfiguration of FPGA. The main requirement of the SDR is to adapt itself with the changing environment. For this adaptation, reconfiguration of FPGA is required. The system developed consists two main blocks namely Transmitter and Receiver. Both are consisting of modulator and demodulator. The modulator and demodulator are the part of the system which needs to be changed with the changing requirement. All the other parts of the system remain same even after the reconfiguration of the system. The main parts of the system are Digital Down Converter (receiver side), Digital Up Converter

Fig.1. Block diagram of DDC

The heart of DUC/DDC is Direct Digital Frequency Synthesizer or DDS. DDS is similar to the local oscillator. The next block is Cascaded Integrated Comb filter or CIC filter. It is a special type of filter to lower down the band of the received signal, after mixing with the DDS output. The next block is Compensation FIR filter or CFIR. The CIC does not provide the flat band response and it also has more ripples in the pass band. To compensate the effect of CIC, the compensation filter is added after CIC. It also provides further decimation to the

978-1-4577-2168-7/11/$26.00 2011 IEEE

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signal. It also adjusts the gain of the signal at particular frequency by narrowing the pass band. Different sections instead of only one section reduce the computational complexity of the system [17]. 3) Modulator and Demodulator Implementation No communication system is complete without modulation and demodulation process. Simple definition of modulation can be given as the modification in the carrier signal with respect to the amplitude of the modulating signal. The demodulation is the reverse process of the modulation. Modulation can be categories in two broad classes namely: analog modulation and digital modulation [7]. The implementation of various modulators and demodulators based on digital modulation techniques is carried out using MATLAB Simulink, Xilinx System Generator and VHDL also. 4) Encoder and Decoder The CRC encoder presented in the paper takes 4 bit input and appends 3 extra bits to it to make it 7 bits. The generator polynomial used in the coder is "1011". The decoder works exactly reverse of the encoder. It takes 7 bits of input and gives 4 bit of output. Decoder block also provides an extra error signal, which goes high when an error is detected. 5) Error Counter and Decision Generator The error output of the decoder at the receiver side is given to the Error Counter block. Error Counter is nothing but a simple counter which is triggered on the input error count. The error is continuously checked and the count number is sent to the Decision Generator block. Decision Generator block is a very simple design. The input to it is the number counted by the Error Counter. If the number is less than 70 (10 percent data is erroneous as number of transmitted bits are 700) then two bits output "00" is generated. If error number is more than 70 and less than 140 (20 percent error) then "01" is generated. If error is more than 140 (more than 20 percent error) then "10" is generated. Depending on the number generated by the Decision generator block, 50 bits of data is transmitted as a response from receiver to the transmitter. III. IMPLEMENTATION OF SDR SYSTEM The Software Defined Radio consists two main parts transmitter and receiver. Both the parts are capable of transmitting as well as receiving, but as far as data communication is concern the communication is simplex. The various blocks discussed so far in the paper are parts of transmitter and receiver. The blocks of DDC and DUC are first blocks in the systems. The working of both transmitter and receiver is as follows. 1) Transmitter Figure 2 shows the block diagram of transmitter section. The first block is Serial to Parallel Converter. The assumption is that the data coming to the transmitter block is serial, but the

processes applied to it in the transmitter block require parallel data. So it is necessary to convert the data in parallel. The output of the Serial to Parallel Converter is of 4 bits. If one wants to work with parallel data then 4 bits of parallel data can directly be given to the next block. The other output of the block is RDY which is given to the next block. When four bits of data is converted to the parallel stream, the RDY pin goes high momentarily. This pin works as a clock signal for the next block

Fig. 2. Transmitter Block Diagram

The next block is Counter1 block. As the data is converted to serial to parallel, after every four clock cycle one clock cycle is left when four parallel bits are supplied to the next block. This leads to unsynchronized communication between two blocks. To properly synchronize the data Counter1 and Counter2 block are required. Counter1 block counts four clock cycles as four parallel bits are required. After four clock cycles it generates load signal as output. The next block is Encoder block. It generates the CRC checksum and appends the same with the input data. Input to this block is of 4 bit and the output is of 7 bits. The CRC generation process is triggered by the RDY output of Serial to Parallel Converter block. Encoder also generates its own RDY signal, which is generated at every output sample. The 7 - bit output of Encoder is given to the Arrange block and RDY is supplied to the Counter2 block. The Counter2 block counts 100 clocks, which are RDY output of Encoder block. After such 100 RDY signals it generates load signal. This means, after every 700 bits of data, load is generated by Counter2 block. The load signals from both Counter1 and Counter2 are logically anded to generate the main load signal, which allows the next data block to be loaded to the system. Counter2 block also receives one bit signal from the final Parallel to Serial block which helps it to generate the load signal. Counter2 does one more important work which is to supply the counted number to the next block at every RDY signal from Encoder block. The Arrange block is required to gather the data block of 700 bits so that it can be transmitted

INSTITUTE OF TECHNOLOGY, NIRMA UNIVERSITY, AHMEDABAD 382 481, 08-10 DECEMBER, 2011

serially. It receives input data from Encoder block. It also receives Count numbers from the Counter2 block. The RDY signal from Counter2 block is also given to the Arrange block. Arrange block is nothing but a array of 100 locations, each of 7 bits. The addresses of this array are nothing but the number supplied from the Counter block and the data stored at this addresses are nothing but the data supplied by the encoder block. The 700 bits of output is supplied to the Parallel to Serial block when Counter completes the 100 number count. The next block is Parallel to Serial Converter. It receives 700 bits of data block and supplies it to the modulator for serial transmission on every clock cycle. It also generates RDY signal which indicates that full 700 bits are supplied to the modulator. This signal is given to the Counter2 block as well as Control block. The modulator modulates the data and transmission is completed by the transmitter. Once the transmission of 700 bits is over the transmitter comes into receiver mode and waiting for the response from the receiver. It will receive 50 bits of data block serially once the response is sent by the receiver block. If all received 50 bits are received as zeros then it assumes that the noise level in the communication medium is very less and the modulator should be the ASK modulator. If it receives all 1's then it changes the modulator to PSK because the level of noise in the medium is moderate and ASK is no longer capable of dealing with this amount of noise. If the received data is alternate 1's and 0's then the modulator is changed to QPSK because the noise level is very high and it requires a robust system. The change of modulator is performed by Partial Reconfiguration of FPGA. The extra block of Stuffing can be added to the system if more than one block of data is transmitted. Stuffing will provide start and end of frame delimiter. 2) Receiver

erroneous. To detect the error and to perform the change in modulator depending on the noise level in the medium it is necessary to perform the error detection in the receiver block. So the demodulated data is given for the further processing. The next block is Serial to Parallel converter. The process applied to the data in the Receiver block requires parallel data. So it is necessary to convert the data in parallel stream. The output of the serial to parallel converter is of 7 bits. The other output of the block is RDY which is given to the next block. When seven bits of data is converted to the parallel stream, the RDY pin goes high momentarily. The Counter block counts 100 clocks, which are RDY output of Serial to Parallel Converter block. After such 100 RDY signals it supplies the counted number to the next block. The Arrange block is required to supply the data of 700 bits to the Decoder in the block of 7 bits. Arrange is nothing but can be viewed as an array of 100 addresses each of 7 bits. It receives count number from the counter. This number is the address from which the data is to be supplied to the Decoder. The next block is Decoder block. It computes the CRC checksum from the input data. The input to this block is of 7 bits and the output is of 4 bits. It also generates one error signal as output when the CRC check sum does not match with the received data. The process is triggered by the RDY output of Serial to Parallel Converter block. Decoder also generates its own RDY signal, which is generated at every output sample. This signal provided to the error counter, which counts the error depending on the error signal supplied by the same Decoder block. The Error counter and Decision block is discussed in the previous chapter. The decision is applied to the Demodulator as well. The response is generated as per the decision and demodulator changes with modulator as discussed in chapter 4. The Response Generator generates the data as stream of 0's or 1's or alternate 1's and 0's as per the decision supplied by Decision Generator. This response is modulated and transmitted using PSK modulator. Response Generator also triggers the Control block when it completes the generation process. The extra block of Destuffing can be added to the system if stuffing is added to the transmitter. The Control block is the block which enables the transmission and reception process at both the transmitter as well as receiver. It is similar block at both the side. IV. RESULTS Figure 4 shows the output waveform of transmitter block. The code is written in VHDL and output is obtained in the Modelsim. Figure 5 shows the output waveform of receiver block.

Fig. 3. Receiver Block Diagram

Figure 3 shows the block diagram of Receiver section. The first block is Demodulator. This block changes the demodulator when the transmitter modulator changes. The output is the demodulated data stream. The received output may be

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Fig. 4. Output waveform of transmitter block

Fig. 7. Output on the hyper terminal 2

V. CONCLUSION The design of Digital Up and Down Converter is implemented in VHDL. Direct Digital Synthesizer is designed and implemented and the real time results are observed. The design is carried out using Sparten 3E with speed grade of -4. Various Modulators and Demodulators are designed and simulated in high level simulation and synthesis tools (MATLAB Simulink and Modelsim). Cyclic Redundancy Code are studied and implemented in VHDL. All the blocks are successfully integrated to design the SDR system. The Software Defined Radio System has been tested for adaptive modulation. The full adaptive modulation and coding scheme can be developed using the system presented here. The partial reconfiguration of FPGA can be efficiently used to dynamically reconfigure the SDR. The use of built in IP cores reduces the resource requirement of the system and improves the overall performance in terms of speed and area. Xilinx Virtex 5, xc5vls110t-1fi1136 is used to implement the full transmitter and receiver system. The results are obtained and observed at the simulation level VI. REFERENCES [1] [2] [3] [4]
Fig. 6. Output on the hyper terminal 1

Fig. 5. Output waveform of receiver block

The final design is combination of transmitter and receiver blocks. The modulator and demodulators are partially reconfigured on FPGA as and when required. After the reconfiguration process the output can be seen on the hyper terminal of the computer. Figure 6 and 7 show the final output of SDR system on the hyper terminal of the computer.

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INSTITUTE OF TECHNOLOGY, NIRMA UNIVERSITY, AHMEDABAD 382 481, 08-10 DECEMBER, 2011

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