The analog challenge of nanometer

Maarten Vertregt
NXP Semiconductors Research, Eindhoven, The Netherlands
maarten.vertregt
nxp.com

CMOS

Abstract:
Nanometer CMOS technology offers the required integration density for advanced products such as home theatre equipment and personal communication devices. The system solutions inside these products demand highly integrated systems-on-silicon, blending highdensity digital functions with analog interface circuits. These integrated solutions have to cope with high datarates, and thus require high speed and high dynamic range circuits, without compromising power consumption. Novel choices on circuit and system level are required to handle the increased number of devices subject to high variability, running at higher intrinsic speeds with a constraint power supply. 1. Introduction

The semiconductor industry prospers on its ability to introduce more versatile product solutions, exploiting Moore's Law with ever increasing numbers of devices, at an approximately constant price level. Until the first submicron CMOS technology nodes this trend went along with combined improvements in the factors speed (clock and data-rate) and power efficiency. For this reason that period of technology succession is referred to as the "Golden Years of Scaling".
5-

still very much in demand. People want access to, and exchange, tens of gigabytes of stored data as easily and quickly as possible. For the nanometer CMOS technology nodes, it is only the density scaling that remains. And the conditions for circuit operation become tighter especially due to the increased impact of dope fluctuations [1], as illustrated in Figure 1. The technology discussion for the digital domain focuses on the Ion/Ioff ratio. The solutions offered by technology resulted in a process complexity increase: multiple supply and threshold levels, multi gate-oxides, vast increase in number of metal levels etc. The application needs, power efficiency combined with operational speed, have to be met by design architecture optimisation and adding design complexity (e.g. clock gating, multicore parallel computation, voltage islands by supply gating). Revolutionary device concepts that maintain the traditional high Ion/Ioff ratio promise a turn-around. This enhances flexibility at the expense of process architecture and fabrication complexity, illustrated in Figure 2. m High

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Figure 2 Technology solutions and design solutions to cope with digital system challenges

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Technology Node [nm]

1000 800 500 350 250180 130 90 65 45 32

reducing available dynamic range

Figure 1 Supply voltage and threshold mismatch trends,

Nowadays, speed and power efficiency are attributes that no longer come for free with technology scaling, but are

The second axis on which CMOS device optimisation is performed is in the RF domain. The need for cheap system solutions in the upcoming GHz communications has fuelled the demand for RF System-on-Chips. The focus here is especially on the RF performance of single transistors in the low-noise amplifier, RF-transmitter, the local oscillator and frequency synthesis blocks. These devices are biased in regimes with high drain and gate voltages, enabled by the specific electronic design of these RF stages.

Consequently RF performance is optimised and measured at bias settings corresponding to this use, see Figure 3.
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Figure 4 Power efficiency progress at the analog-digital interface (and data-rates @100mW), with the enabled application fields

100 150 Gate length, nm

Figure 3 Cut-off frequencyft versus physical gatelength for 90-nm LP and GP devices, from [11]
However, optimising technology for digital design and for RF design does not necessarily create the optimum operating conditions for the majority of devices that forms the heart of the analog interface electronics.

2.

System level analysis

For digital (signal) processor circuits, data throughput is increased by implementing parallelism (multi-core processors with multi-instruction and/or multi-data slots). Running more streams in parallel at individually limited clock rates enhances data-rate and improves power efficiency [2]. Part (if not all) of the reduction factor of a new technology node is traded for area by increasing the number of devices in parallel signal paths to satisfy the increased speed/power demands of a next generation function. At first glance adding more devices seems wasteful; however the flexibility and versatility of the functionality offer are greatly enhanced. A similar trend is observable for analog interface electronics as well. Also here, data-rate and power efficiency are key aspects to new solutions. On a coarse time-scale, Figure 4 shows the improvement in conversion efficiency for the analog-to-digital conversion function [3]. From the sixties by digitization of the plain old telephone service (converting a few kHz bandwidth speech signal), power efficiency improvements at a pace of 1Ox per decade have led to (ultra-) wideband conversion possibilities beyond 1GHz-level per mW.

The applications that can afford the technology cost still need to develop, but recent publications [4, 5] already show power efficiencies beyond 2GHz-levels/mW in the 90nm technology node. This is identical to consuming 0.5pJ of energy for converting a single level in a sample. All analog processing from antenna to clean bits including analog supporting circuitry requires today several hundreds of nanoJoules. This is an amount of energy sufficient for 104-105 digital operations per second. This growing gap between analog and digital signal processing efficiency requires enhanced attention for power efficient optimisation of analog CMOS implementation. The following section presents a method to analyze the MOS device properties for power efficiency in analog design, as an alternative to the digital focus for Ion/Ioff, and the RF focus on small-signal peakf at extreme drive voltages.
3. Device analysis method

The scaling trend for successive technology nodes is assessed on the basis of the actual electrical device behaviour. The operating point is not imposed as the result of a scaling scenario [6] but follows from the simulated electrical device properties. These simulations are done with the surface-potential based Philips MOS model Model 11 (MM1 1), the predecessor of the new Compact Model Council standard MOS Model PSP [7]. This provides a dependable view of the MOS transistor behaviour. The key device properties are not taken from the input parameters of the MOS model, but derived from the simulated drain current and its derivatives in saturation (the very quantities available to the designer for circuit creation). Figure 5 graphically illustrates the procedure on a 1/0.13ptm NMOS device from a 0.13ptm CMOS technology.

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Usable beta
v

intercept

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a function of the technology node as well as device type. Also note that the efficiency by which transconductance g. is created per unit drain current improves for lower

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Figure 5 Key device property estimation for circuit design (at Vd,=0.5V, V,b=OV); the square-law operation spans from the Vgs intercept Vt,sat to the Vgs corner
In this procedure the square-law approximation of the transistor drain current in saturation, as given by equation (1),
'drain =I2(Vgs Vth2)
(1)

0.0
-0.1 0.0 0.1 0.2 0.3 0.4

0.5

0.6

0.7

0.8

Vgt

Figure 6 gm/Idrain vs. Vgs-Vt,sat at fixed Vds=0.5V, for L=Lmin of several technology nodes; N- and PMOS

is exploited for identification of relevant device operation boundary conditions. The gm tangent at the Vgs where agm/aVgs is at its maximum is used as a linear approximation for gm (increasing linear-with-Vgs beyond threshold, as prescribed by the "square-law" model). The peak value of agm/aVgs is picked as an estimator for the current factor, and called the "usable f3". This usable f3 approximation is applicable between two intercept points. The first intercept point, where the maximum-slope gm tangent crosses with gm=0, is used as a threshold estimator Vgs =Vt,sat. It marks the onset of the approximated square-law operation of the device. The second boundary Vgs =Vgs,comer is found at the corner intercept of the maximum-slope gm tangent, and the (velocity-saturated), horizontal, gm tangent at maximum gm. For Vgs>Vgs,comeri the MOS transfer characteristic is best approximated by linear behaviour. These approximations are used to establish relevant operating boundaries, and determine the so-called square-law operation span between the Vgs intercept Vt,sat and Vgs,comer (the Vgs at the gm corner intercept). The usable f3 parameter enables the design-centric interpretation of results across different device geometries and technology generations. The usable f3 marks the Vgs range that is preferred by analog designers: it combines a reasonable current modulation without running in headroom problems or leaving the saturation regime. For all analyses, the variation in bias condition is conducted by sweeping the variable Vgt=Vgs-Vt,sat, the gateoverdrive voltage. These bias sweeps start (for all technologies and all lengths) at each respective Vt,sat voltage. The gate-overdrive variable Vgt is a true common reference throughout the device-level investigation. Figure 6 shows gm/ldrain for 0.18pim, 90nm, 65nm, 45nm, and 32nm technology flavours (with varying threshold levels), plotted vs. a common Vgt x-axis. The validity of the normalized gate-overdrive approach is convincingly demonstrated through indifference of the gm/ldrain ratio as

Trend analysis can now be done on basis of a comparable operating point for all device types across multiple technology nodes
4. Device trend analysis
Several device behaviour properties are explored against channel length, with technology node (and gate oxide thickness flavour) as a parameter. All properties are normalized per pim device width or per pim2 device area.

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0.5

NMOS Vds=0.5V

E 0.4
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6
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0

20 40 60 80 1CiO 1i20 14011 160 180 Lmin, drawn [nm]

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Figure 7 Trend of the "square-law span" voltage at the minimum channel-length, vs. Lmin drawn of several technology nodes and device types (LSTP- low standby power -and LOP -low operating power-)
The selected properties are: * the "square-law span" voltage as defined in section 3 (Figure 7) * the usable current factor beta-square (Figure 8) * the normalized MOS capacitance (including junction and overlap capacitance, Figure 9) * the unity gain frequency gm/27CC (Figure 10). Notice that the "square-law span" voltage reduces less than linear proportional with the feature size scaling for successive technology nodes (0.18ptm to 32nm nodes shown). The feature size proportionality is often used to predict the circuit consequences of technology scaling trends but underestimates the device capability [3, 8].

Being able to maintain square-law behaviour over a wider range is beneficial for maintaining a good linearity and signal-to-noise ratio in many circuit architectures. This invariant square-law span is explained by the persistence of the 1.2V power-supply, i.e. the apparent "constant supply-voltage" technology scaling from the 0.13ptm to 65nm LSTP nodes, with only a marginal decrease to I.lV for 45nm, and IV for 32nm LSTP. Notice that the LOP nodes (typically operating at slightly lower power supply levels than LSTP technologies) exhibit a slightly lower square-law-span.
500 450 400 0) 350 300 250 cm 200 Cn 150
50 0
* X +

per-[tm2 roll-up due to its short minimum L. There appears to be no magic capacitance reduction factor associated with such an ultra-thin floating body device.
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0 cn

50 45 40 35 30 25 20 15 10 5 0

NMOS * .18um LSTP

-

90nm LOP 65nm LSTP + 65nm LOP

E>
-

9Onm LSTP 45nm LST P 32nm LOP

_~~~~~~~~~i~~~~~~~~~~~~~~~~~~~~~
0

100*
0

Figure 9 Total NMOS device capacitance per pim gatewidth, normalized per ptm channel length [fF/ tm2]

Ldrawn [10g(jPM)]

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o o

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co

lt

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Figure 8 NMOS usable Beta, (f3 normalized xLeff/Weff) as function of channel length for several technology nodes

For long channel lengths, the increase of capacitance values from 0.18ptm-45nm approximately doubles, due to the capacitance-equivalent-oxide thickness reduction from approx 3 to 1.5nm.
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N
0

140 -T

NMOS
-

120 +
100

The trends for the usable current factor are given in Figure 8. The "usable f3 " for the minimum channel length of a technology node (the actual current factor available for circuit design) is degrading with technology scaling. The expected improving trend in f3 =RCO, (favourable scaling with gate-oxide thickness) is still present for longer than minimum channel lengths. This also holds for the 32nm node where a TCAD calibrated finFET model is deployed [20], and especially when biased within the square-law regime the finFET stands out [9, 10]. The capacitance and unity-gain frequency results are monitored at a fixed Vgt gate-overdrive bias setting per technology node, independent of channel length. This operating point is chosen at the upper Vgt,corner value of the square-law span (the values of which are plotted in Figure 7) for the shortest channel length per technology (always at constant Vd=0.5V), and kept at that value for all channel lengths. This operating point yields a highlinearity bias condition for small-signal high-frequency circuit operation. At this square-law corner operating point, and for several technologies, the device capacitance (junction + MOS Cgate) per ptm gate width is plotted as a function of the length in Figure 9. These results are normalized through division by the drawn length. Obviously, such a normalized capacitance (fF/Lm2) increases for shorter channel length, as the relative contribution of the edge (overlap, fringe, and junction capacitance) increases. The 32nm node, despite of having a finFET architecture, shows the highest normalized capacitance-

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80 +
60 +

90nm LOP 65nm LSTP - $ - 65nm LOP 45nm LSTP -*- .18um LSTP 32nm LOP
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Figure 10 Small-signal unity gain frequency (at the corner Vgt operating point) vs. channel length

The load capacitance value for calculating the unity-gain frequency (Fug=g /27CC, see Figure 10. The small-signal unity gain frequency is chosen as the capacitance for the same device and operating point from which the g. is taken, including its associated drain junction capacitance. The maximum unity-gain frequency for the chosen operating point increases for the minimum channels from 26GHz at 0.18ptm to 128GHz for the 32nm LSTP node. Note that this analysis method yields 25-35% less maximum unity gain frequency than e.g. in Figure 4. For longer than minimum channel lengths the small signal bandwidth curves from different technology nodes fall on top of each other. This behaviour was confirmed in measurements [11]. A well known issue of scaled devices is the ever reducing intrinsic device gain gm/gds.

This is illustrated in Figure 11. The gain at minimum channel length is still approximately 20x for the 0. 18 pim node, and a mere 6x for the 65nm technology node. The superior channel control of the FinFET device promises a breakthrough, and brings the gain back to 20x for Lmin=32nm according to TCAD-based device simulations. This high small-signal gain gm/gd, out of a revolutionary device concept re-enables conventional design techniques allowing disturbance suppression by feedback techniques, and good common-mode and supply rejection.
80 T 70 + v
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the same unity gain settling bandwidth spending a mere 0.33mW. Especially digital and other large-signal circuits such as clock buffers and power amplifiers are impacted more by large-signal slew-rate bandwidth Idrain/2TCCV than by small-signal settling bandwidth gm/2TC. B
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Figure 11 Small-signal device gain vs. channel length (biased at half the peak gm value) This nanometer CMOS device analysis suggests that (with the exception of the small-signal device gain) no disruptive changes are foreseen with regard to the relevant analog device trends.
5.

Figure 12 Small-signal settling power efficiency (for 1 im' device area) vs. unity gain bandwidth at the Vgt,comer operating point In order to check whether power efficiency benefits appear also in this large-signal case, a set of ringoscillators with varying channel length and constant active area was analysed within the 65nm technology node. The maximum oscillation frequency and the dynamic power efficiency (normalized to 1 pLm2 device area) were determined. This analysis was done both in simulation and on silicon measurements. The results are shown in Figure 13.
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Circuit level investigation

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N

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40 q

The benefit of the higher usable beta (Figure 8) for channel lengths beyond minimum within a certain technology node, expresses itself as an improved power efficiency (provided the normalized capacitance per unit area is invariant at a fixed Ldrawn as shown in Figure 9). For example, in the 0.18 ptm technology node 1.6mW needs to be spent per lum2 device area to reach the highest achievable 26GHz small-signal unity gain bandwidth. A designer can now choose to exploit the higher bandwidth capability of a new technology node at approximately constant power efficiency. The dissipated power will increase proportional with the increased unity gain bandwidth to 6.3mW for 1 pLm2 at 128GHz in the 32nm node. Or the designer can choose to exploit the 32nm technology at a fixed 26GHz settling bandwidth and improve power efficiency by nearly a factor 5 to realize

In [12] this device level analysis was extended to an analog-to-digital converter building block. Here a similar analysis is performed for the "settling power efficiency". This is the small-signal unity-gain bandwidth per unit power, and the trend results are shown in Figure 12.

,- 30
0 .O a

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t
a.

20

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1

Figure 13 Large-signal power efficiency normalized on 1 prm2 total inverter area versus the maximum oscillation frequency: simulated (thick solid line), and measured (dotted lines, 33 samples) Similar to the small-signal case, power efficiency can be improved. At one tenth of the maximum achievable oscillation frequency within one and the same 65nm

10

100

technology node, large-signal power efficiency can be improved 3x by increasing the device length at constant device area. Bottom line conclusion is that scaled technologies still have healthy properties for analog circuit design (the type of design that is not bound to feature size channel length only). Higher operational speed can be obtained by using the shortest channel lengths, at the expense of proportionally more power. Using advanced processes at slightly relaxed channel lengths improves the performance/power ratio.
6. Variability impact

ducibility and thus a Cpk above 0.5), which means that the traditional freedom in dimension choice will be restricted (Figure 15). 130 175 200 INA=1 nA 1.6

0.d C.)

0.8 0.6 0.4 0.2

1.2 1-

1.4

0-0
100

150

Analog design has a long history in recognizing the deterministic background of fluctuation (temperature derating, metal density, well edge distance, and sub-halfwavelength exposure) and operational handling of random stochastic effects (mismatch, jitter). This knowledge can, and is being exploited to cope with the huge number of effects that are classified under variability (e.g. STI stress, well proximity, statistical timing, and layer density uniformity). Furthermore many effects playing a major role on the scale of billion-transistor digital circuit blocks are less relevant for analog building blocks, as these circuits have a complexity scale of 1% transistor count or less compared to state-of-art digital. This makes the discussed power efficiency advantage at longer channel lengths a feasible alternative for analog circuit use in scaled technologies. The impact of temperature de-rating is illustrated by Figure 14.

Pitch [nm]

200

250

300

Figure 15 Sub-half wavelength exposure: forbidden pitches

Printability at sub-half wavelength pitches simply requires good uniformity and poses extra conditions to account for during layout. Positive side of these uniformity restrictions is a homogenized layout environment removing unwanted sources of variability (see Figure
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Figure 16 single pitch layout: improved exposure

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/ /

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~~~ + - 65n18m LSTP _ 45~~~~9nm LSTP

Furthermore, these additional uniformity restrictions make the layout style of conventional bulk designs very similar to the placement of multiples of a unit cell for finFETs (see Figure 17). RIFEI ___ilk

32nm LSTP

-40.0 -20.0

0.0

20.0 40.0 60.0 80.0

Temperature [C]

Figure 14 Device leakage as function of temperature

For LSTP devices, the off current is dominated by the temperature dependant source-drain channel leakage. Only for LOP technologies beyond the 90nm node, gate leakage overrules source-drain channel leakage at elevated temperatures. For LOP this has the advantage that hardly any temperature de-rating remains, at the expense of this high leakage level (hundreds of mA for a billion transistor design). Notice the extreme promise of standby condition improvement with the 32nm finFET architecture. For conventional bulk device architectures beyond the 65nm node, this low standby level will be difficult to reach. Exploitation of the nanometer scale technologies requires good exposure control (with good repro-

Figure 17 Homogenized bulk layout similar to quantized finFET layout

For these small devices, it becomes interesting to judge the impact of the local device-to-device mismatch proportional to 1<(area) in comparison to the global process variation [13]. For many process generations proportionality existed of the mismatch factor AVT with the gate oxide thickness, which scaled with feature size. Figure 18 shows the trend of this matching constant from the 0.5 ptm node, through the 0.18 ptm node, to the

65nm node. Between those last two nodes the proportionality nearly disappears. The oxide thickness scaling is less aggressive and additional charge fluctuation contributions dominate. Figure 19 shows that local mismatch fluctuation for small devices has reached a similar magnitude as the global process spread.
6

straints of device mismatch [14, 15, 16, 5]. This leads to building block architectures as shown in Figure 21. Integration density and long-term storage functionality of digital design is exploited to create a solution with better power and area efficiency.
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1.8

2.0

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Figure 18 Standard deviation of mismatch fluctuation remains nearly constant after the 0. 18 pm node (65 nm data by courtesy H. Tuinhout and Crolles-2 Alliance).
Note that local variations between transistors can have a much more severe impact than a global process spread. A clear example is the design of Static RAM cells, where the mismatch problems have led to architectures that use more than the traditional 6 transistors to form a memory cell.
0.90

i op

Figure 20 Histogram of global fluctuation (timing bins around 2ns) and local differential fluctuation (timing bins around Ons) of clock edge arrival time across two 35-stage buffer branches in 65nm technology node.

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=
1 4 4

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Having the technique of calibration established means that, also for analog building block design, multi-path signal handling becomes feasible. When interleaved, these calibrated signal paths can run individually at lower speeds (which is good for power efficiency [17, 18]), or overall speed can be maximised [19].

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x fnfp

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10 pA
jVn

to Digital

0.60

Decoder

0.50 0.30

0.40

0.50

0.60

0.70

Vn

(simulation)
L 12 Bits

Figure 19 Mismatch fluctuation scatter plot for W/L=0.2/0. 1, P versus Nmos diode voltage (9Onm node).

Output

The impact of local variations can be illustrated on the time-skew consequence for clock distribution in a clock tree. Whereas a well-balanced clock tree aims at systematic reduction of the time skew between different branches of a clock tree, mismatch fluctuation puts a lower limit to the achievable results. The one sigma spread on the global arrival time is 180ps, and the one sigma spread for differential arrival time is 30ps. Therefore buffer insertion to balance the arrival time doesn't help anymore once a time alignment of several tens of picoseconds is reached. Countermeasures-by-design to bring variability under control are pursued. For local (mismatch) variability in analog design the route to follow is auto-calibration. This "digitally enhanced analog" is becoming more and more established to break away from the area con-

Figure 21 Auto-calibration mixed-signal building block architecture [14]

Global variability of digital circuit blocks is kept under control by dividing a chip into multiple voltage domains. For those domains, dynamic power dissipation is handled by active supply control, and power switches are used to keep standby power at the desired level.
7.

Conclusions and outlook

A scaling trend analysis of analog circuit performance in CMOS technology has been presented. A device-centric view on the prospects for future circuit design is created

by analysing the MOS transistor in design-centric boundary conditions. Also at a modest operating bias, a higher analog circuit bandwidth is reached when scaling to more advanced technology nodes. For applications subject to constant bandwidth specifications, significant power efficiency improvements can be obtained when scaling to a next technology node. An invariant normalized capacitance, in combination with a higher current factor (usable 3 ,) at non-minimum channel lengths causes this advantage. Nevertheless, exploitation of the integration density and speed benefits of new technology nodes requires the analog functions to be mapped on more devices with a smaller device area. The increased mismatch fluctuation is dealt with by an expansion of digital control loops. More and more digital hardware is being spent for correction. This approach started with manual trimming and redundancy, subsequently auto-calibration, and nowadays by digital signal-correction processing to compensate for signal impairments created by poor analog device properties. In order to address the inevitably large device fluctuations in the nanometer CMOS era circuit architectures with increased tolerances will be needed to avoid manufacturing yield limitations.
8. Acknowledgement The author gratefully acknowledges the contributions and discussions with his colleagues at NXP Semiconduc9. References

tors.

[11] L.F.Tiemeijer, et.al., "Record RF performance of standard 90 nm CMOS technology" 2004 IEDM Technical Digest page(s):441 - 444 [12] M.;Vertregt, P.C.S.Scholtens, "Assessment of the Merits of CMOS Technology Scaling for Analog Circuit Design", Proceedings ESSCIRC2004 pp: 57-64 [13] M.J.M. Pelgrom et.al.; "Matching properties of MOS transistors", IEEE Journal of Solid-State Circuits, Vol. SC-24, pp. 1433-1440, 1989 [14] H van der Ploeg, et.al., "A 2.5-V 12-b 54-Msample/s 0.25-ptm CMOS ADC in 1-mm2 with mixed-signal chopping and calibration", IEEE Journal of Solid-State Circuits, Dec. 2001, pp: 1859-1867 [15] B Murmann, B.E Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification", IEEE Journal of Solid-State Circuits, Dec 2003 pp:2040-2050 [16] R.C. Taft, et.al., "A 1.8-V 1.6-GSample/s 8-b selfcalibrating folding ADC with 7.26 ENOB at Nyquist frequency", IEEE Journal of Solid-State Circuits. 2004 Page(s):2107 - 2115 [17] D. Draxelmayr: "A 6b 600MHz 10mW ADC array in digital 90nm CMOS"; ISSCC 2004, p. 264-265. [18] S.M Louwsma,.et.al., "A 1.6GS/s, 16 times interleaved track&hold with 7.6ENOB in 0. 12pm CMOS", Proceedings ESSCIRC2004 pp: 343-346 [19] K. Poulton, et.al., "A 20 GS/s 8 b ADC with a 1 MB memory in 0.18um CMOS", ISSCC 2003, p. 318-319. [20] Smit, G.J. et al. "PSP-based compact FinFET model describing DC and RF measurements" Tech.Digest IEDM 2006.

[1] Pelgrom, M.J.M.et.al., "Transistor matching in analog CMOS applications" IEDM '98 Technical Digest, Page(s):915 - 918 [2] A.P.Chandrakasan, et.al., "Low-power CMOS digital design" IEEE Journal of Solid-State Circuits, April 1992 Page(s):473 - 484 [3] R. Brederlow et.al, "A mixed-signal Design Roadmap" IEEE-Design-Test-of-Computers (USA), vol.18, no.6, p.34-46, Nov.-Dec. 2001 [4] G. Geelen et.al.: "A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipelined ADC with 0.5pJ/Conversion-Step"; ISSCC 2006, p. 214-215. [5] G. van der Plas, et.al.: "A 0.l6pJ/Conversion-Step 2.5mW 1.25Gs/s 4b ADC in a 90nm Digital CMOS process"; ISSCC 2006, p. 566-567. [6] K.Bult,: "Analog design in deep sub-micron CMOS", Proceedings ESSCIRC,2000 Page(s): 126 - 132 [7] PSP model website http://pspmodel.asu.edu/ [8] Y. Chiu, B. Nikolic, and P. R. Gray, "Scaling of Analog-to-Digital Converters into Ultra-DeepSubmicron CMOS", in Proceedings of IEEE Custom Integrated Circuits Conference, CICC'05, San Jose, CA, Sept. 18-21, 2005, pp. 375-382 [9] V.Subramaniana, et.al., "Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs", 2005 IEDM Technical Digest.Page(s):898 - 901 [10] G.Knoblinger,: "Multi-Gate MOSFET Design", Proceedings ESSCIRC2006 pp. 66-69