8088 Memory Interface: EPROM: Figure 10-20, Page 356 8088 starts executing instructions after a hardware reset

t from FFFF0h location. We often call location FFFF0h the cold start location. The software stored in this section of memory would contain a JMP instruction at location FFFF0h that jumps to location F8000h so that the remainder of the program can execute. 2732 EPROMs (4K*8) memory devices are in very common use with 8088. F8000h to FFFFFh is the address range for eight 2732 EPROMs. Because of higher access time of EPROM we have to generate wait state when this portion of memory is accessed. For this purpose we attach the output of NAND gate to READY pin of microprocessor. This we insert one WAIT state in bus cycle when this memory portion is accessed. RAM: Figure 10-21, Page 358 It does not require wait states for interfacing. An ideal section for the RAM is the very bottom, which contains vectors of interrupts. Interrupt vectors are often modified by software packages, so it is rather important to encode this section of the memory with RAM. Sixteen 62256 (32K*8) SRAMs are interfaced to the 8088, beginning at memory location 00000h. Ending address is 7FFFFh. 512 Kbytes is the total RAM here. 8086 Memory Interface: 8086 has the data bus twice as wide as the bus for 8088. 8086, 80186, 80286 and 80386SX must be able to write data to any 16-bit location or any 8-bit location. This means that the 16-bit data bus must be divided into two separate sections (banks) that are 8-bit wide so the microprocessor can write to either half (8-bit) or both halves (16-bit). One bank (low bank) holds all the even-numbered memory locations, and the other bank (high bank) holds the odd-numbered memory locations. 8086 use the BHE and A0 address bit to select one or both banks of memory used for the data transfer. (BHE) (BLE) FFFFF FFFFE FFFFD FFFFC FFFFB FFFFA

00003 00001 (High Bank) (Odd Bank)

00002 00000 (Low Bank) (Even Bank)

BHE 0 0 1 1

BLE 0 1 0 1

Function Both banks enabled for a 16-bit transfer. High bank enabled for an 8-bit transfer. Low bank enabled for an 8-bit transfer. No banks enabled.

Bank selection is accomplished in two ways: A separate write signal is developed to select a write to each bank of the memory. OR Separate decoders are used for each bank.

Separate Bank Decoders: The use of separate bank decoders is often the least effective way to decode memory addresses for the 8086. In this method low bank and high bank of memory is selected by separate decoders. Low bank decoder is enabled by using A0/BLE pin of microprocessors address bus and high bank decoder is enabled by using BHE pin of microprocessor. The only advantage of this method is to converse energy because only the bank or banks are enabled. Separate Bank Write Strobes: The most effective way to handle bank selection is to develop a separate write strobe for each memory bank. This technique requires only one decoder to select a 16-bit wide memory. This often saves money and reduces the number of components in a system. To generate separate read strobes for each memory bank is unnecessary, because the 8086 microprocessors read only the byte of data that they used at any given time from half of the data bus during a read, the microprocessor ignores the 8-bit section it doesnt need without any conflicts or special problems. For generating separate bank write strobes for memory banks the A0 is combined with WR for the low bank selection signal (LWR) and BHE is combined with WR for the high bank selection signal (HWR). A memory system that uses separate write strobes is constructed differently from either the 8-bit system (8088) or the system using separate memory banks. Memory in a system that uses separate write strobes is decoded as 16-bit wide memory. D0 D7 will be connected to low bank and D8 D15 to high bank.