Circuits and Electronics

CIRCUITS AND
6.002 ELECTRONICS
Introduction and Lumped Circuit Abstraction
6.002 Fall 2000 Lecture 1 1
ADMINISTRIVIA
Lecturer: Prof. Anant Agarwal

Textbook: Agarwal and Lang (A&L)
Readings are important!

Handout no. 3
Assignments —
Homework exercises
Labs
Quizzes
Final exam
Two homework assignments can

be missed (except HW11).
Collaboration policy
Homework
You may collaborate with
others, but do your own
write-up.
Lab
You may work in a team of
two, but do you own write-up.
Info handout
Reading for today —
Chapter 1 of the book
What is engineering?
Purposeful use of science
What is 6.002 about?

Gainful employment of
Maxwell’s equations
From electrons to digital gates

and op-amps
Nature as observed in experiments

V 3 6 9 12 …
I 0.1 0.2 0.3 0.4 …
Physics laws or “abstractions”

Maxwell’s abstraction for
Ohm’s tables of data
V=RI
Lumped circuit abstraction
+–
R V C L M S
6.002
Simple amplifier abstraction
Operational Digital abstraction

amplifier abstraction
abstraction
+ Combinational logic
- f
Filters
Clocked digital abstraction
Analog system Instruction set abstraction

components: Pentium, MIPS 6.004
Modulators, Programming languages
oscillators, Java, C++, Matlab 6.001
RF amps, Software systems 6.033
power supplies 6.061 Operating systems, Browsers
Mice, toasters, sonar, stereos, doom, space shuttle
6.455 6.170
Lumped Circuit Abstraction
The Big Jump

from physics
to EECS
Consider
I
+
V
?
Suppose we wish to answer this question:
What is the current through the bulb?
We could do it the Hard Way…
Apply Maxwell’s
Differential form Integral form
∂B ∂φ B
Faraday’s ∇× E = − ∫ E ⋅ dl = − ∂t
∂t
∂ρ ∂q
Continuity ∇ ⋅ J = − ∫ J ⋅ dS = − ∂t
∂t
ρ q
Others ∇⋅E = ∫ E ⋅ dS =
ε0 ε0
Instead, there is an Easy Way…
First, let us build some insight:
Analogy
F
a?
I ask you: What is the acceleration?

You quickly ask me: What is the mass?
I tell you: m
F
You respond: a =
m
Done !! !
Instead, there is an Easy Way…
First, let us build some insight:
Analogy
F
a?
In doing so, you ignored

the object’s shape
its temperature
its color
point of force application
Point-mass discretization
The Easy Way…
Consider the filament of the light bulb.
We do not care about
how current flows inside the filament
its temperature, shape, orientation, etc.
Then, we can replace the bulb with a

discrete resistor
for the purpose of calculating the current.
6.002 Fall 2000 Lecture 1 10
The Easy Way…
Replace the bulb with a

discrete resistor
for the purpose of calculating the current.
A
I
+ V
R and I=
V R
–
B
In EE, we do things
the easy way…
R represents the only property of interest!

Like with point-mass: replace objects
F
with their mass m to find a =
m
6.002 Fall 2000 Lecture 1 11
The Easy Way…
A
I
+ V
R and I=
V R
–
B
In EE, we do things
the easy way…
R represents the only property of interest!
R relates element v and i
I= called element v-i relationship
6.002 Fall 2000 Lecture 1 12
R is a lumped element abstraction

for the bulb.
6.002 Fall 2000 Lecture 1 13
R is a lumped element abstraction

for the bulb.
Not so fast, though …

I
A + S
A
V
SB
B –
black box
Although we will take the easy way
using lumped abstractions for the rest
of this course, we must make sure (at
least the first time) that our
abstraction is reasonable. In this case,
ensuring that V I
are defined
for the element
6.002 Fall 2000 Lecture 1 14
I
A
+ SA
V I
V
SB must be defined
B – for the element
black box
6.002 Fall 2000 Lecture 1 15
I must be defined. True when

I into S A = I out of S B
∂q
True only when = 0 in the filament!
∂t
∫ J ⋅ dS
SA
∫ J ⋅ dS
SB
∂q
∫ J ⋅ dS − ∫ J ⋅ dS = ∂t
SA SB
IA IB
from ell
ax w ∂q
M I A = I B only if =0
∂t
So let’s assume this
6.002 Fall 2000 Lecture 1 16

V Must also be defined.
see
A&L
So let’s assume this too
∂φ B
VAB defined when =0
∂t
So VAB = ∫AB E ⋅ dl outside elements
6.002 Fall 2000 Lecture 1 17
Lumped Matter Discipline (LMD)

Or self imposed constraints:
∂φ B
= 0 outside
∂t
∂q
More in = 0 inside elements
Chapter 1 ∂t bulb, wire, battery
of A & L
Lumped circuit abstraction applies when

elements adhere to the lumped matter
discipline.
6.002 Fall 2000 Lecture 1 18
Demo Lumped element examples

only for the
whose behavior is completely
sorts of captured by their V–I
questions we relationship.
as EEs would
like to ask!
Demo
Exploding resistor demo
can’t predict that!
Pickle demo
can’t predict light, smell
6.002 Fall 2000 Lecture 1 19
So, what does this buy us?
Replace the differential equations

with simple algebra using lumped
circuit abstraction (LCA).
For example —
a
R1 R4
R3
V
+ b d
–
R2 R5
What can we say about voltages in a loop

under the lumped matter discipline?
6.002 Fall 2000 Lecture 1 20
What can we say about voltages in a loop

under LMD?
R1 R4
R3
V
+ b d
–
R2 R5
∂φ B
∫ E ⋅ dl = − ∂t under DMD
0
∫ E ⋅ dl + ∫ E ⋅ dl + ∫ E ⋅ dl = 0
ca ab bc
+ Vca + Vab + Vbc = 0
Kirchhoff’s Voltage Law (KVL):
The sum of the voltages in a loop is 0.
6.002 Fall 2000 Lecture 1 21
What can we say about currents?
Consider
S
I ca I da
a
I ba
6.002 Fall 2000 Lecture 1 22
What can we say about currents?
S
I ca I
da
a
I ba
∂q
∫S J ⋅ dS = − ∂t under LMD
0
I ca + I da + I ba = 0
Kirchhoff’s Current Law (KCL):

The sum of the currents into a node is 0.
simply conservation of charge
6.002 Fall 2000 Lecture 1 23
KVL and KCL Summary
KVL:
∑ jν j = 0
loop
KCL:
∑jij = 0
node
6.002 Fall 2000 Lecture 1 24
CIRCUITS AND
6.002 ELECTRONICS
Amplifiers --
Small Signal Model
6.002 Fall 2000 Lecture 10 1
Review
MOSFET amp
VS
RL
vO
vI
iDS
Saturation discipline — operate

MOSFET only in saturation region
Large signal analysis
1. Find vO vs vI under saturation discipline.
2. Valid vI , vO ranges under saturation discipline.
Reading: Small signal model -- Chapter 8
6.002 Fall 2000 Lecture 10 2
Large Signal Review
1 vO vs vI
K
vO = VS − (vI −1)2 RL
valid for vI ≥ VT
and
vO ≥ vI – VT
K 2
(same as iDS ≤ vO )
2
6.002 Fall 2000 Lecture 10 3
Large Signal Review
2 Valid operating ranges
v
O
V
S
5V
corresponding vO > vI −VT
interesting vO = vI −VT
region for vO vO < vI −VT
1V
vI
VT
1V 2V
“interesting” region
for vI . Saturation
discipline satisfied.
6.002 Fall 2000 Lecture 10 4
But…
vO
VS
5V
vO = vI −VT
vO
1V
vI
vI
VT
1V 2V
Demo
Amplifies alright,
vI
but distorts
vO
Amp is nonlinear … /
6.002 Fall 2000 Lecture 10 5
Small Signal Model

vO
~ 5V VS Focus on this line segment
(VI , VO )
~ 1V
vI
VT
1V ~ 2V
K (vI − VT )
2
vO = VS − RL
2
Amp all right, but nonlinear!
Hmmm … So what about our linear amplifier ???
Insight:
But, observe vI vs vO about some
point (VI , VO) … looks quite linear !
6.002 Fall 2000 Lecture 10 6
Trick vo looks
linear
∆vO VO vi
(VI ,VO )
VI
∆vI
Operate amp at VI , VO
Æ DC “bias” (good choice: midpoint
of input operating range)
Superimpose small signal on top of VI
Response to small signal seems to be

approximately linear
6.002 Fall 2000 Lecture 10 7
Trick vo looks
linear
∆vO VO vi
(VI ,VO )
VI
∆vI
Operate amp at VI , VO
Æ DC “bias” (good choice: midpoint
of input operating range)
Superimpose small signal on top of VI
Response to small signal seems to be
approximately linear
Let’s look at this in more detail —
I graphically next
II mathematically week
III from a circuit viewpoint
6.002 Fall 2000 Lecture 10 8
I Graphically
We use a DC bias VI to “boost” interesting input

signal above VT, and in fact, well above VT .
VS
interesting RL
input signal
vO
∆vI +
–
VI
+
–
Offset voltage or bias
6.002 Fall 2000 Lecture 10 9
Graphically
VS
interesting
RL
input signal vO
∆vI +
–
VI
+
–
vO
VS operating
point
VO VI , VO
vO = vI −VT
vI
0 VT
VI
Good choice for operating point:
midpoint of input operating range
6.002 Fall 2000 Lecture 10 10
Small Signal Model
aka incremental model

aka linearized model
Notation —
Input: vI = VI + vi
total DC small
variable bias signal (like ∆vI)
bias voltage aka operating point voltage
Output: vO = VO + vo
Graphically,
vI vO
vi vo
VI
VO
0 t 0 t
6.002 Fall 2000 Lecture 10 11
II Mathematically
(… watch my fingers)
RL K
vO = VS − (vI −VT ) VO = VS − RL K (VI −VT )2
2 2
substituting vI = VI + vi vi << VI
RL K
vO = VS − ( [VI + vi ] − vT )2
RL K
= VS − ( [VI −VT ] + vi )2
= VS −
RL K
2
(
[VI −VT ]2 + 2 [VI − vT ]vi + vi 2 )
RL K
VO + vo = VS − (VI − VT )2 − RL K (VI −VT ) vi
2
From ,
vo = −RL K (VI −VT ) vi
gm related to VI
6.002 Fall 2000 Lecture 10 12
Mathematically
vo = −RL K (VI −VT ) vi
gm related to VI
vo = −g m RL vi
For a given DC operating point voltage VI,
VI – VT is constant. So,
vo = − A vi
constant w.r.t. vi
In other words, our circuit behaves like a linear amplifier

for small signals
6.002 Fall 2000 Lecture 10 13
Another way
RL K
vO = VS − (vI −VT )2
VS −
R K
L
2
v −V
I
(
T
2 
 )
d  
vo = ⋅ vi
dv
I
v = V
I I
slope at VI
vo = −RL K (VI −VT ) ⋅ vi
g m = K (VI −VT )
A = −g m RL amp gain
Also, see Figure 8.9 in the course notes

for a graphical interpretation of this result
6.002 Fall 2000 Lecture 10 14
More next lecture …

iDS
Demo
load line
input signal response
operating point
VI
vO
VO
How to choose the bias point:

1. Gain component g m ∝ VI
2. vi gets big Æ distortion.
So bias carefully
3. Input valid operating range.
Bias at midpoint of input operating
range for maximum swing.
6.002 Fall 2000 Lecture 10 15
CIRCUITS AND
6.002 ELECTRONICS
Small Signal Circuits
6.002 Fall 2000 Lecture 11 1

Review:
Small signal notation
vA = VA + va
total operating small

point signal
vOUT = f (vI )
d
vout = f (vI ) ⋅ vi
dv I v I =VI
VS

vI = VI + vi RL
vO = VO + vo
vi +
–
VI +
–
6.002 Fall 2000 Lecture 11 2

Review:
I Graphical view
(using transfer function)
vO
behaves linear
for small
perturbations
vI
6.002 Fall 2000 Lecture 11 3

Review:
II Mathematical view
K (vI − VT )
2
vO = VS − RL
2
V − K (v − V )2 R 
d  S 2 I T L

vo = ⋅ vi
dv I
v I =VI
vo = − K (VI − VT ) RL ⋅ vi
gm related to VI
constant for fixed
DC bias
6.002 Fall 2000 Lecture 11 4

How to choose the bias point,
using yet another graphical view
based on the load line Demo
i DS
K 2
i DS < vO
2
V S vO
load line DS R − R
i =
L L
input signal
response
VI
vO
VO
v I = VT
− 1 + 1 + 2 KR LV S
v I = VT +
KR L
Choosing a bias point:
1. Gain g m RL ∝ VI
2. Input valid operating range for amp.
3. Bias to select gain and input swing.
6.002 Fall 2000 Lecture 11 5

III The Small Signal Circuit View
We can derive small circuit equivalent
models for our devices, and thereby conduct
small signal analysis directly on circuits
e.g. large signal
circuit model
for amp R +
VS
vOUT –
K
iD = (vI − VT )
2
vI +
– 1
2
We can replace large signal models with

small signal circuit models.
Foundations: Section 8.2.1 and also in the
last slide in this lecture.
6.002 Fall 2000 Lecture 11 6

Small Signal Circuit Analysis
1 Find operating point using DC bias

inputs using large signal model.
2 Develop small signal (linearized)

models for elements.
3 Replace original elements with small

signal models.
Analyze resulting linearized circuit…

Key: Can use superposition and other
linear circuit tools with linearized
circuit!
6.002 Fall 2000 Lecture 11 7

Small Signal Models
A MOSFET
D
large vGS K
signal iDS = (vGS − VT )2
2
S
Small signal?
6.002 Fall 2000 Lecture 11 8

Small Signal Models
A MOSFET
D
large vGS K
signal iDS = (vGS − VT )2
2
S
Small signal:
K
iDS = (vGS − VT )
2
2
∂  K (v − V )2 
ids =  2 GS T  ⋅ v gs
∂vGS vGS =VGS
ids = K (VGS − VT ) ⋅ v gs ids is linear in vgs !

gm
D
small v gs
signal ids = K (VGS − VT ) v gs
ids = g m v gs
S
6.002 Fall 2000 Lecture 11 9
B DC Supply VS
vS = VS
large iS
signal + vS = VS
–
Small signal ∂VS

vs = ⋅ is
∂iS iS = I S
is +
vs vs = 0
–
DC source behaves
as short to small
signals.
6.002 Fall 2000 Lecture 11 10

C Similarly, R
large iR + v R = R iR
vR
signal R – ∂ ( RiR )
vr = ⋅ ir
∂iR iR = I R
vr = R ⋅ ir
ir +
small vr
signal R –
6.002 Fall 2000 Lecture 11 11

Amplifier example:
Large signal Small signal
RL + V RL
vO – S vo
+ v iDS + vi ids
– I –
K
= (vI − VT ) ids = K (VI − VT ) ⋅ vi
2
iDS
2
ids RL + vo = 0
K
vO = VS − (vI − VT )2 RL
2 vo = −ids RL
vo = − K (VI − VT )RL ⋅ vi
= − g m RL ⋅ vi
Notice, first we need to find operating

point voltages/currents.
Get these from a large signal analysis.
6.002 Fall 2000 Lecture 11 12

III The Small Signal Circuit View
To find the relationship between the small signal parameters of
a circuit, we can replace large signal device models with
corresponding small signal device models, and then analyze the
resulting small signal circuit.
Foundations: (Also see section 8.2.1 of A&L)

KVL, KCL applied to some circuit C yields:
" + v A + " + vOUT + " + vB + " 1
Replace total variables with

operating point variables plus small signal variables
" + VA + v a " + VOUT + vout + VB + vb + "
Operating point variables themselves satisfy the
same KVL, KCL equations
" + VA " + VOUT + VB +"
so, we can cancel them out
Leaving
" + va " + vout + vb + " 2
But 2 is the same equation as 1 with small signal

variables replacing total variables, so 2 must reflect same
topology as in C, except that small signal models are used.
Since small signal models are linear, our linear tools will now
apply…
6.002 Fall 2000 Lecture 11 13

CIRCUITS AND
6.002 ELECTRONICS
Capacitors
and First-Order Systems
6.002 Fall 2000 Lecture 12 1

Motivation
5V
Demo 5V
B C
A
5V
0V
5
A
0
5
Expect this, right?
B But observe this!
0
5 Expected
C Observed
0
Reading:
Delay! Chapters 9 & 10
6.002 Fall 2000 Lecture 12 2
The Capacitor
D
G n-channel MOSFET
symbol
S
drain
n s
m+ o i
gate e+ x l n-channel
t + i p
i MOSFET
a+ d
l + e n-channel c
+ o
n n
source
D
G
S
CGS
6.002 Fall 2000 Lecture 12 3
Ideal Linear Capacitor
+ + A d
++++
EA
- - C=
E ----- d
obeys DMD!
total charge on
capacitor
= +q − q = 0
i
q +
C v
–
q = C v
coulombs farads volts
6.002 Fall 2000 Lecture 12 4

Ideal Linear Capacitor
i
q +
C v
–
q = C v
dq
i=
dt
d (Cv )
=
dt
dv
=C
dt
 E = 1 Cv 2 
 2 
A capacitor is an energy storage device

Æ memory device Æ history matters!
6.002 Fall 2000 Lecture 12 5

Analyzing an RC circuit
Thévenin Equivalent:
+
R C vC (t )
vI (t ) +
– –
Apply node method:
vC − vI dvC
+C =0
R dt
dvC t ≥ t0
RC + vC = vI
dt vC (t0 ) given
units
of time
6.002 Fall 2000 Lecture 12 6

Let’s do an example:
+
R C vC (t )
v I (t ) +
–
–
vI (t ) = VI
vC (0 ) = V0 given
dvC
RC + vC = VI X
dt
6.002 Fall 2000 Lecture 12 7

Example…
vI (t ) = VI
vC (0 ) = V0 given
dvC
RC + vC = VI X
dt
vC (t ) = vCH (t ) + vCP (t )
total homogeneous particular
Method of homogeneous and particular

solutions:
1 Find the particular solution.
2 Find the homogeneous solution.
3 The total solution is the sum of
the particular and homogeneous
solutions.
Use the initial conditions to solve
for the remaining constants.
6.002 Fall 2000 Lecture 12 8
1 Particular solution
dvCP
RC + vCP = VI
dt
vCP = VI works
dVI
RC + VI = VI
dt
0
In general, use trial and error.
vCP : any solution that satisfies the

original equation X
6.002 Fall 2000 Lecture 12 9

2 Homogeneous solution
dvCH
RC + vCH = 0 Y
dt
vCH : solution to the homogeneous
equation Y
(set drive to zero)
vCH = A e st assume solution
of this form. A, s?
dA e st
RC + A e st = 0
dt
R CA s e st + A e st = 0
Discard trivial A = 0 solution,

R C s +1 = 0 Characteristic equation
1
s= −
RC
−t RC
or vCH = Ae RC
called time
constant τ
6.002 Fall 2000 Lecture 12 10
3 Total solution
vC = vCP + vCH
−t
vC = VI + A e RC
Find remaining unknown from initial

conditions:
Given, vC = V0 at t = 0
so, V0 = VI + A
or A = V0 − VI
−t
thus vC = VI + (V0 − VI ) e RC
also
dvC (V − VI ) −t
iC = C =− 0 e RC
dt R
6.002 Fall 2000 Lecture 12 11

−t
vC = VI + (V0 − VI ) e RC
vC
VI
V0
t
0
RC
6.002 Fall 2000 Lecture 12 12

Examples
vC vC
5V 5V
−t −t
5 + 5e RC 5e RC
0V t 0V t
VO = 0V 5 VO = 5V 5
VI = 5V 0 VI = 0V 0
τ = RC
Remember
B
demo
6.002 Fall 2000 Lecture 12 13

CIRCUITS AND
6.002 ELECTRONICS
Digital Circuit
6.002 Fall 2000 Lecture 13 1

Review
vI R +
VI vI +
– C vC
–
t
0
vC (0 ) = VO
−t
vC = VI + (VO − VI ) e RC 1
vC
VI
time constant RC
VO
t
RC
6.002 Fall 2000 Lecture 13 2

Let’s apply the result to
an inverter.
A B
X
First, rising delay tr at B
VS VS
A
B
vA
5V CGS
X
t
0
1 Æ 0 at A
6.002 Fall 2000 Lecture 13 3

VS VS
A
B
CGS
vA X
5V
t vB
0 5V ideal
1 Æ 0 at A observed
t
0
6.002 Fall 2000 Lecture 13 4

VS VS
A
B
vA
5V CGS
X
t
0 vB
1 Æ 0 at A 5V
VOH
t
0 tr
rising delay of X
6.002 Fall 2000 Lecture 13 5

Equivalent circuit for 0Æ1 at B
RL +
vI = VS + CGS vB
– –
vI = VS
for t ≥ 0
vB (0 ) = 0
From 1
−t
vB = VS + (0 − VS ) e RL CGS
Now, we need to find t for which

vB = VOH .
6.002 Fall 2000 Lecture 13 6

Or −t
vOH = VS − VS e RL CGS
Find tr :
−t r
VS e RL CGS
= VS − VOH
− tr VS − VOH
= ln
RL CGS VS
VS − VOH
t r = − RL CGS ln
VS
6.002 Fall 2000 Lecture 13 7

Or −t
vOH = VS − VS e RL CGS
Find tr :
−t r
VS e RL CGS
= VS − VOH
− tr VS − VOH
= ln
RLCGS VS
VS − VOH
t r = − RL CGS ln
VS
e.g. RL = 1K VS = 5V
CGS = 0.1 pF VOH = 4V
−12 5−4
t r = −1 × 10 × 0.1 × 10
3
ln
5
= 0.16 ns
RC = 0.1 ns !
6.002 Fall 2000 Lecture 13 8
Falling Delay tf
Falling delay tf is
the t for which vB falls to VOL
Equivalent circuit for 1 Æ 0 at B
RL vB (0 ) = VS
(5V )
VS +
– +
CGS vB
RON –
6.002 Fall 2000 Lecture 13 9

Falling Delay tf
Equivalent circuit for 1 Æ 0 at B
RL vB (0 ) = VS
(5V )
VS +
– +
CGS vB
RON –
X
Thévenin replacement …
RTH +
VTH +
– CGS vB
–
RTH = RL || RON
RON
VTH = VS
RON + RL
6.002 Fall 2000 Lecture 13 10
From 1
−t
vB = VTH + (VS − VTH ) e RTH CGS
Falling decay tf is
the t for which vB falls to VOL
−t f
VOL = VTH + (VS − VTH ) e RTH CGS
VOL − VTH
or t f = − RTH CGS ln
VS − VTH
6.002 Fall 2000 Lecture 13 11

VOL − VTH
t f = − RTH CGS ln
VS − VTH
e.g. RL = 1K VS = 5V RON = 10Ω

CGS = 0.1 pF VOL = 1V
RTH ≈ 10Ω, VTH ≈ 0V
−12 1
t f = −10 ⋅ 0.1 ⋅10 ln
5
= 1.6 ps
RC = 1 ps !
6.002 Fall 2000 Lecture 13 12

For recitation: Slow may be better
Problem
chip
pin 2
pin 1 v
CL
v:
ideal observed slow!
So the engineers decided to speed it up…
RL made RL small
RON made RON small
6.002 Fall 2000 Lecture 13 13

For recitation: Slow may be better
Problem
chip
pin 2
pin 1 v
CL
v:
ideal observed slow!
… but, disaster!
v: observed
expected
VIL
6.002 Fall 2000 Lecture 13 14

Why? Consider … Demo
Case 1 R1
pin1
R0
ok
6.002 Fall 2000 Lecture 13 15

Why? Consider … Demo
Case 2 CP
R1
pin1 pin2
R0
R2
crosstalk!
CP
R +
v +
model for crosstalk: –
–
6.002 Fall 2000 Lecture 13 16

Case 3
… 6.002 expert saw the solution

CP
R1
+
R0 –
R2
slower transitions!
Detailed analysis in recitation.
6.002 Fall 2000 Lecture 13 17

CIRCUITS AND
6.002 ELECTRONICS
State and Memory
6.002 Fall 2000 Lecture 14 1

Review
Recall
R +
vI +
– C vC
–
v I = VI for t ≥0 vC (0 )
−t
vC = VI + (vC (0)− VI ) e RC 1
Reading: Sections 10.3, 10.5, and 10.7
6.002 Fall 2000 Lecture 14 2

This lecture will dwell on the
memory property of capacitors.
For the RC circuit in the previous slide
vI
vI VI
t
t ≥0 0
vC
VI
−t
vC = VI + (vC (0)− VI ) e RC
vC (0 )
t
0
Notice that the capacitor voltage for t ≥ 0 is
independent of the form of the input voltage
before t = 0 . Instead, it depends only on the
capacitor voltage at t = 0 , and the input voltage
for t ≥ 0 .
6.002 Fall 2000 Lecture 14 3
State
State : summary of past inputs relevant

to predicting the future
q=CV
for linear capacitors,

capacitor voltage V
is also state variable
state variable, actually
6.002 Fall 2000 Lecture 14 4

State
Back to our simple RC circuit 1

vC = f (vC (0 ), vI (t ))
−t
vC = VI + (vC (0 ) − VI ) e RC
Summarizes the past input relevant

to predicting future behavior
6.002 Fall 2000 Lecture 14 5

State
We are often interested in circuit

response for
zero state vC (0) = 0
zero input vI (t) = 0
Correspondingly,
zero state response or ZSR
−t
vC = VI − VI e RC 2
zero input response or ZIR

−t
vC = vC (0 ) e RC 3
6.002 Fall 2000 Lecture 14 6

One application of STATE
DIGITAL MEMORY
Why memory?
Or, why is combinational logic insufficient?
Examples
Consider adding 6 numbers on your
calculator
2+9+6+5+3+8
M+
“Remembering” transient inputs
6.002 Fall 2000 Lecture 14 7

Memory Abstraction
A 1-bit memory element
The
6.004
d IN view $
store M The
NEC
d OUT View ¥
☺
Remembers input when store goes high.

Like a camera that records input (dIN) when the
user presses the shutter release button.
The recorded value is visible at dOUT .
d IN
store
d OUT remembers the 1

6.002 Fall 2000 Lecture 14 8
Building a memory element …
A First attempt
dIN dOUT
* storage
C node
store
6.002 Fall 2000 Lecture 14 9

A
dIN vC d
* OUT
store = 1
C
dIN vC d
* OUT
store = 0
C
vC RL
5V
Stored value leaks away VOH
t
−t
T
from 2
RL C
vC = 5 ⋅ e
VOH
T = − RLC ln
5
store pulse width >> RON C
6.002 Fall 2000 Lecture 14 10

B Second attempt buffer
dIN dOUT
*
RIN
C buffer
store
Input resistance RIN
VOH
T = − RIN C ln
5
RIN >> RL
Better, but still not perfect.
Demo
6.002 Fall 2000 Lecture 14 11

C Third attempt buffer + refresh
store
dIN dOUT
*
C
store
Does this work?
No. External value can

influence storage node.
6.002 Fall 2000 Lecture 14 12

D Fourth attempt buffer + decoupled

refresh
store
dIN dOUT
*
C
store
Works!
6.002 Fall 2000 Lecture 14 13

A Memory Array
store IN
4-bit memory
Address
OUT
Decoder
A d IN
00 S M
d OUT
B d IN A
01 S M
d OUT
a0 a1
2
Address d IN
C B
10 S M
d OUT
D d IN C
11 S M
d OUT
IN store
OUT
D
6.002 Fall 2000 Lecture 14 14

Truth table for decoder
a0 a1 A B C D
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
6.002 Fall 2000 Lecture 14 15

Agarwal’s top 10 list on memory
10 I have no recollection, Senator.

9 I forgot the homework was due today.
8 Adlibbing ≡ ZSR
7 I think, therefore I am.
6 I think that was right.
5 I forgot the rest …
6.002 Fall 2000 Lecture 14 16

CIRCUITS AND
6.002 ELECTRONICS
Second-Order Systems
6.002 Fall 2000 Lecture 15 1

5V 5V
Demo
50Ω
2KΩ 2KΩ
S
A C
B
+ large
– loop CGS
Our old friend, the inverter, driving another.

The parasitic inductance of the wire and
the gate-to-source capacitance of the
MOSFET are shown
[Review complex algebra appendix for next class]
6.002 Fall 2000 Lecture 15 2

5V 5V
Demo
50Ω
2KΩ 2KΩ
S
C
A
B
+ large
– loop CGS
Relevant circuit:
2KΩ L
B
5V +
– CGS
6.002 Fall 2000 Lecture 15 3

Observed Output 2kΩ
5
vA
0 t
vB
2kΩ
0 t
vC
0 t
Now, let’s try to speed up our inverter by

closing the switch S to lower the effective
resistance
6.002 Fall 2000 Lecture 15 4

Observed Output ~50Ω
5
vA
0 t
vB
50Ω
0 t
vC
0 t
Huh!
6.002 Fall 2000 Lecture 15 5

First, let’s analyze the LC network
L i (t )
+
+ C v(t )
vI (t ) – –
Node method:
dv
i (t ) = C Recall
dt
di
1 t
dv vI − v = L
∫ (vI − v) dt = C dt
L −∞ dt 1 t
∫ (vI − v) dt = i
L −∞
1 d 2v
(v I − v ) =C 2
L dt
d 2v
LC 2 + v = vI
dt
time2 v, i state variables
6.002 Fall 2000 Lecture 15 6

Solving
Recall, the method of homogeneous and
particular solutions:
1 Find the particular solution.
2 Find the homogeneous solution.
L
4 steps
3 The total solution is the sum of the
particular and homogeneous.
Use initial conditions to solve for the
remaining constants.
v = vP (t ) + vH (t )
6.002 Fall 2000 Lecture 15 7

Let’s solve
d 2v
LC 2 + v = vI
dt
For input
vI
V0
t
0
And for initial conditions

v(0) = 0 i(0) = 0 [ZSR]
6.002 Fall 2000 Lecture 15 8

1 Particular solution
d 2 vP
LC 2 + vP = V0
dt
vP = V0 is a solution.
6.002 Fall 2000 Lecture 15 9

2 Homogeneous solution
Solution to
d 2 vH
LC 2 + vH = 0
dt
Recall, vH : solution to homogeneous
equation (drive set to zero)
Four-step method:
A Assume solution of the form*

vH = Ae st , A, s = ?
so, LCAs 2 e st + Ae st = 0
1 characteristic
B s =−
2
equation
LC
1
s=±j j = −1
LC
1
C Roots s = ± jω o ωo =
LC
General solution,
D vH = A1e jωot + A2 e − jωot

Differential equations are commonly
*
solved by guessing solutions
6.002 Fall 2000 Lecture 15 10

3 Total solution
v(t ) = vP (t ) + vH (t )
v( t ) = V0 + A1e jωot + A2 e − jωot
Find unknowns from initial conditions.

v(0) = 0
0 = V0 + A1 + A2
i ( 0) = 0
dv
i (t ) = C
dt
i( t ) = CA1 jωo e jωot − CA2 jωo e − jωot
so, 0 = CA1 jωo − CA2 jωo

or, A1 = A2
− V0 = 2 A
V0
A1 = −
2
v( t ) = V0 − (e + e − jωot )
V0 jωot
so,
2
6.002 Fall 2000 Lecture 15 11
3 Total solution
Remember Euler relation
e jx = cos x + j sin x
(verify using Taylor’s
expansion)
e jx + e − jx
= cos x
2
so, v( t ) = V0 − V0 cos ωot where

1
ωo =
i( t ) = CV0ωo sin ωot LC
The output looks sinusoidal
6.002 Fall 2000 Lecture 15 12

Plotting the Total Solution
v(t )
2V0
V0
0 π π ωo t
3π 2π
2 2
i (t )
CV0ωo
0 π π ωo t
3π 2π
2 2
− CV0ωo
6.002 Fall 2000 Lecture 15 13

Summary of Method
1 Write DE for circuit by applying

node method.
2 Find particular solution vP by guessing
and trial & error.
3 Find homogeneous solution vH
A Assume solution of the form Aest .

B Obtain characteristic equation.
C Solve characteristic equation
for roots si .
D Form vH by summing Ai esit
terms.
4 Total solution is vP + vH ,
solve for remaining constants using
initial conditions.
6.002 Fall 2000 Lecture 15 14

Example
What if we have:
iC + vC (0) = V
L C vC
– iC (0) = 0
We can obtain the answer directly from

the homogeneous solution (V0 = 0).
6.002 Fall 2000 Lecture 15 15

Example
iC + vC (0) = V
L C vC
– iC (0) = 0
We can obtain the answer directly from

the homogeneous solution (V0 = 0).
vC ( t ) = A1e jωot + A2 e − jωot
vC (0) = V
V = A1 + A2
iC (0) = 0
0 = CA1 jωo − CA2 jωo
V
or A1 = A2 =
2
or vC =
2
(e + e − jω o t )
V jω o t
vC = V cos ωot
iC = −CV ωo sin ωot
6.002 Fall 2000 Lecture 15 16
Example
vC
V
ωo t
2π
CVωo iC
ωo t
2π
− CVωo
6.002 Fall 2000 Lecture 15 17

Energy
EC
1
1 CV 2
C: CvC
2 2
2
ωo t
2π
EL
1 1
L : LiC
2 CV 2
2 2
ωo t
2π
1 1 1
Notice
2 2
CvC + LiC = CV 2
2 2 2
Total energy in the system is a constant,

but it sloshes back and forth between the
Capacitor and the inductor
6.002 Fall 2000 Lecture 15 18

RLC Circuits
R L i (t )
+
vI (t ) +
– C v(t )
–
v(t )
no R
add R
t
Damped sinusoids with R – remember demo!
See A&L Section 12.2
6.002 Fall 2000 Lecture 15 19

CIRCUITS AND
6.002 ELECTRONICS
Sinusoidal Steady State
6.002 Fall 2000 Lecture 16 1
Review
We now understand the why of:
5V v
R
L
Today, look at response of networks

to sinusoidal drive.
Sinusoids important because signals can be
represented as a sum of sinusoids. Response to
sinusoids of various frequencies -- aka frequency
response -- tells us a lot about the system
6.002 Fall 2000 Lecture 16 2
Motivation
For motivation, consider our old friend,

the amplifier: V S
Demo
vO
R vC
vi +
–
CGS
VBIAS +
–
Observe vo amplitude as the frequency of the

input vi changes. Notice it decreases with
frequency.
Also observe vo shift as frequency changes
(phase).
Need to study behavior of networks for

sinusoidal drive.
6.002 Fall 2000 Lecture 16 3
Sinusoidal Response of RC Network
Example:
iC
R +
vI +
– vC
–
vI (t ) = Vi cos ω t for t ≥ 0 (Vi real)

=0 for t < 0
vC (0) = 0 for t = 0
vI
0 t
6.002 Fall 2000 Lecture 16 4
Our Approach
Example:
iC
R +
vI
+
– vC
Determine vC(t)
e m e!
Effort
Ind ulg
Usual
approach
agony
sneaky approach
very
sneaky
easy
re
e

0
:0
ur
:
2
:
0
tu
1
2
11
11
ct

lec
le
is
t
Th
ex
N
6.002 Fall 2000 Lecture 16 5
Let’s use the usual approach…
1 Set up DE.
2 Find vp.
3 Find vH.
4 vC = vP + vH, solve for unknowns
using initial conditions
6.002 Fall 2000 Lecture 16 6
Usual approach…
1 Set up DE
dvC
RC + vC = vI
dt
= Vi cos ω t
That was easy!
6.002 Fall 2000 Lecture 16 7
2 Find vp
dvP
RC + vP = Vi cos ωt
dt
First try: vP = A Æ nope

Second try: vP = A cos ωt Æ nope
Third try: vP = A cos(ωt + φ ) frequency

amplitude phase
− RCAω sin(ωt + φ ) + A cos(ωt + φ ) = Vi cos ωt
− RCAω sin ωt cos φ − RCAω cos ωt sin φ +

A cos ωt cos φ − A sin ωt sin φ = Vi cos ωt
..
. gasp !
works, but trig nightmare!
6.002 Fall 2000 Lecture 16 8

Let’s get sneaky!
Find particular solution to another input…
dvPS
RC + vPS = vIS (S: sneaky :-))
dt
= Vi e st
Try solution PS = st
v V p e Nice
dV p e st property
RC + V p e st = Vi e st of
dt exponentials
sRCV p e st + V p e st = Vi e st
( sRC + 1 )V p = Vi
Vi
Vp =
1 + sRC
Vi
Thus, vPS = ⋅ e st
1 + sRC easy!
is particular solution to Vi e st
Vi
ly ⋅ e jω t solution for i V e jω t
1 + jωRC
where we replace s = jω
Vp complex amplitude
6.002 Fall 2000 Lecture 16 9

2 Fourth try to find vP…
using the sneaky approach
Fact 1: Finding the response to

Vi e jω t
was easy.
Fact 2: vI = Vi cos ωt
= real[Vi e jω t ] = real[vIS ]
from Euler relation,

e jω t = cos ωt + j sin ωt
real vI response vP real

part vIS response vPS part
an inverse superposition argument,

assuming system is real, linear.
6.002 Fall 2000 Lecture 16 10

2 Fourth try to find vP…
so, complex
vP = Re[vPS ] = Re[V p e jωt ]
 Vi 
= Re  ⋅ e jω t 
1+ jωRC 
Vi (1 − jωRC ) jω t 
= Re ⋅e
 1 + ω 2 R 2C 2 
 Vi j φ jω t 
= Re  ⋅ e e  , tan φ = −ωRC
 1+ω R C
2 2 2

 Vi j( ωt +φ ) 
= Re  ⋅ e 
 1 + ω 2 R 2C 2
Vi
vP = ⋅ cos( ωt + φ )
1+ω R C2 2 2
Recall, vP is particular response to Vi cos ωt .
6.002 Fall 2000 Lecture 16 11

3 Find vH
−t
Recall, vH = Ae RC
6.002 Fall 2000 Lecture 16 12
4 Find total solution

vC = vP + vH
t
Vi −
vC = cos( ωt + φ ) + Ae RC
1+ω R C
2 2 2
where φ = tan −1 ( −ωRC )
Given vC(0) = 0 for t = 0

so,
Vi
A=− cos(φ )
1+ ω R C
2 2 2
Done! Phew !
6.002 Fall 2000 Lecture 16 13
We are usually interested only in the

particular solution for sinusoids,
i.e. after transients have died.
t
−
Notice when t → ∞, vC → vP as e RC
→0
0
t
Vi −
vC = cos( ωt + φ ) + Ae RC
1+ω R C
2 2 2
where φ = tan −1 ( −ωRC )

Vi
A=− cos(φ )
1+ ω R C
2 2 2
Vp
∠Vp
Described as
SSS: Sinusoidal Steady State
6.002 Fall 2000 Lecture 16 14
All information about SSS is contained

in Vp , the complex amplitude!
Recall Vi Steps 3 , 4
Vp = were a waste of
1 + jωRC
time!
Vp 1
=
Vi 1+ jωRC
Vp 1
= e jφ where
Vi 1 + ω 2 R 2C 2
φ = tan −1 − ωRC
Vp 1
magnitude =
Vi 1 + ω 2 R 2C 2
Vp
phase φ : ∠ = − tan −1 ωRC
Vi
6.002 Fall 2000 Lecture 16 15
Visualizing the process of finding the

particular solution vP
Vi cos ωt D.E.
drive V p cos[ωt + ∠V p ]
+
nightmare
particular
trig.
solution
algebraic
sneak
equation take
in
+ real
Vi e jωt
complex part
drive
algebra V p e jω t
the sneaky path!
6.002 Fall 2000 Lecture 16 16
Magnitude Plot
transfer function
Vp Vp 1
H ( jω ) = =
Vi Vi 1 + ω 2 R 2C 2
Vp
1
Vi
log
scale
ω
log 1
ω=
scale RC
From demo: explains vo fall off

for high frequencies!
6.002 Fall 2000 Lecture 16 17
Phase Plot
φ = tan −1 − ωRC
Vp
φ =∠
Vi
1
ω=
RC ω
0
log scale
π
−
4
π
−
2
6.002 Fall 2000 Lecture 16 18
CIRCUITS AND
6.002 ELECTRONICS
The Impedance Model
6.002 Fall 2000 Lecture 17 1

Review
Sinusoidal Steady State (SSS)

Reading 13.1, 13.2
R +
vI = Vi cos ωt +
– C vO
–
Focus on steady state, only care

SSS about vP as vH dies away.
Focus on sinusoids.
Sinusoidal Steady State (SSS)

Reading 13.1, 13.2
Reading: Section 13.3 from course notes.
6.002 Fall 2000 Lecture 17 2

Review vP
Vi cos ωt 1 V p cos[ωt + ∠V p ]
usual set
nightmare
circuit up
trig.
model DE
Vp 3
vH
sneak 2
take 4
in complex
real total
Vi e jωt algebra
part
drive
The Sneaky Path
V p e jω t
Vi
1 + jωRC
Vp contains all the information we need:

Vp Amplitude of output cosine
∠V p phase
6.002 Fall 2000 Lecture 17 3
Review vO = V p cos(ωt + ∠V p )
Vp
= H ( jω ) transfer
1
=
Vi 1 + jωRC function
Vp
remember
Vi 1 demo
1
2
1 1
1 + ω 2 R 2C 2 ωRC
1
ω
ω=
RC
Bode plot break frequency
Vp 1
∠ ω=
Vi RC
0 ω
⎛ − ωRC ⎞ π
tan −1 ⎜ ⎟ −
⎝ 1 ⎠ 4
π
−
2
The Frequency View

6.002 Fall 2000 Lecture 17 4
Is there an even simpler way
to get Vp ?
Vi
Vp =
1 + jωRC
Divide numerator and denominator by jωC.

1
jω C
V p = Vi
1
+R
jω C
Hmmm… looks like a voltage divider

relationship.
ZC
V p = Vi
ZC + R
Let’s explore further…
6.002 Fall 2000 Lecture 17 5

The Impedance Model
Is there an even simpler way to get Vp ?
Consider:
iR i R = I r e jω t vR = RiR
+
vR R vR = Vr e jω t Vr e jω t = RI r e jω t
–
Resistor Vr = RI r
jω t dvC
iC iC = I C e iC = C
+ dt
vC C vC = VC e jω t I C e jω t = CVC jωe jω t
–
1
Capacitor VC = IC
j ωC
ZC
jω t diL
iL iL = I l e vL = L
+ dt
vL L vL = Vl e jω t Vl e jω t = LI l jωe jω t
–
Inductor Vl = jωL I l
6.002 Fall 2000 Lecture 17
ZL 6
The Impedance Model
In other words,
Ic Vc = Z C I c
capacitor
+ 1
Vc ZC ZC =
– j ωC
impedance
Il
inductor
+ Vl = Z l I l
Vl ZL
– Z l = j ωL
resistor Ir
+ Vr = Z r I r
Vr ZR
– Zr = R
For a drive of the form Vc e jωt ,

complex amplitude Vc is related to the
complex amplitude Ic algebraically,
by a generalization of Ohm’s Law.
6.002 Fall 2000 Lecture 17 7

Back to RC example…
R
+
vI +
– C vC
–
Impedance model:
ZR = R
Ic
+ 1
Vi +
– Vc ZC =
– jωC
1
jωC ZC
Vc = Vi = Vi
1 ZC + Z R
+R
jωC
1
Vc = Vi Done!
1 + jωRC
All our old friends apply!

KVL, KCL, superposition…
6.002 Fall 2000 Lecture 17 8
Another example, recall series RLC:
Remember, we want only the steady-state
response to sinusoid
Ir
L C +
Vi +
– R Vr
–
Vi e jω t Vr e jω t
Vi cos ωt Vr cos(ωt + ∠Vr )

Vi Z R
Vr =
Z L + ZC + Z R
Vi R
Vr =
1
j ωL + +R
jωC
Vi jωCR
Vr =
− ω 2 LC + 1 + jωCR
We will study this and other functions

in more detail in the next lecture.
6.002 Fall 2000 Lecture 17 9

The Big Picture…
Vi cos ωt V p cos[ωt + ∠V p ]
usual set
nightmare
circuit up
trig.
model DE
6.002 Fall 2000 Lecture 17 10

The Big Picture…
usual set
nightmare
circuit up
trig.
model DE
take
Vi e jωt complex
real
drive algebra
part
6.002 Fall 2000 Lecture 17 11

The Big Picture…
usual set
nightmare
circuit up
trig.
model DE
take
Vi e jωt complex
real
drive algebra
part
impedance-based complex
circuit model algebra
No D.E.s, no trig!
6.002 Fall 2000 Lecture 17 12

Back to Ir
Vr jωRC Vi L C +
= + R Vr
Vi 1 + jωRC − ω 2 LC –
–
Let’s study this transfer function

Vr jωRC
=
Vi 1 + jωRC − ω 2 LC
=
jωRC
⋅
(1 − ω 2 LC ) − jωRC
(1 − ω LC ) + jωRC (1 − ω 2 LC ) − jωRC
2
Vr ωRC
=
Vi (1 − ω 2
LC ) + (ωRC )
2 2
Observe
Low ω : ≈ ωRC
R
High ω : ≈
ωL
ω LC = 1 : ≈ 1
6.002 Fall 2000 Lecture 17 13

Graphically
Vr ωRC
=
Vi (1 − ω 2
LC ) + (ωRC )
2 2
Low ω : ≈ ωRC
R
High ω : ≈
ωL
ω LC = 1 : ≈ 1
Vr
Vi
1 “Band Pass”
ωRC R
ωL
ω
1
LC
Remember this trick to sketch the form of
transfer functions quickly.
More next week…
6.002 Fall 2000 Lecture 17 14
CIRCUITS AND
6.002 ELECTRONICS
Filters
6.002 Fall 2000 Lecture 18 1

Review
R
+
vI + C vC
–
–
ZR
+
Vi +
– ZC Vc
–
ZC
Vc = ⋅ Vi
ZC + Z R
1
Vc j ωC 1
= =
+ R 1 + jωRC
Vi 1
j ωC
Reading: Section 14.5, 14.6, 15.3 from A & L.
6.002 Fall 2000 Lecture 18 2

A Filter
ZR
+
Vi +
– ZC Vc
–
ZC 1
Vc = ⋅ Vi =
ZC + Z R 1 + jωRC
Vc
H (ω ) =
Vi
1 “Low Pass Filter”
ω
Demo
with audio
6.002 Fall 2000 Lecture 18 3

Quick Review of Impedances-
Just as
A
I ab +
R1 Vab
Vab RAB = = R1 + R2
I ab
R2
–
B
A
I ab +
R1 Vab
Vab Z AB = = R1 + jωL
I ab
j ωL
–
B
6.002 Fall 2000 Lecture 18 4

Quick Review of Impedances
Similarly
A
Z AB = R1 + Z C || R2 + Z L
R1
Z C R2
= R1 + + ZL
C R2 Z C + R2
R2
L = R1 + + jωL
1 + jωCR2
B
6.002 Fall 2000 Lecture 18 5

We can build other filters by
combining impedances
Z (ω )
L
Z R
C
ω
6.002 Fall 2000 Lecture 18 6

We can build other filters by
combining impedances
Z (ω)
L
Z R
C ω
H (ω )
+ HPF
– High Pass Filter
ω
H (ω )
+ LPF
– Low Pass Filter
ω
H (ω )
+ HPF
–
ω
6.002 Fall 2000 Lecture 18 7

Check out:
L C
+
Vi +
– R Vr
–
Intuitively:
Vr
1
Vi
q
w fre L bloc
ks hig
k s lo h freq
bloc
C ω
1
ωo =
LC
Vr R
Vi
=
1 At resonance,
jω L + +R ω = ωo
jω C
j ω RC and
= ZL + ZC = 0,
1 − ω 2 LC + j ω RC
so Vi sees
Vr ω RC
= only R!
Vi (1 − ω 2
LC ) + (ω RC )
2 2
More later…
6.002 Fall 2000 Lecture 18 8
What about:
+ Vlc –
L C
Vi +
– R
Vlc
Vi Band Stop Filter
1 C open L open
Check out Vl and Vc in the lab.
6.002 Fall 2000 Lecture 18 9

Another example:
R
+
Vi +
– L C Vo
Vo
Vi BPF
Cs
s hort ho
rt
L
ωo ω
Application: see AM radio coming up shortly
6.002 Fall 2000 Lecture 18 10

AM Radio Receiver
antenna
demodulator
Vi +
– L C
amplifier
Thévenin
antenna
model
crystal radio demo
6.002 Fall 2000 Lecture 18 11

AM Receiver
R
demodulator
Vi +
– L C
amplifier
signal filter
strength WBZ
10 KHz News
Radio
f
540 …1000 1010 1020 1030 … 1600 KHz
“Selectivity” important —
relates to a parameter “Q” for the filter. Next…
6.002 Fall 2000 Lecture 18 12

Selectivity:
Look at series RLC in more detail
L C
+
Vi +
– R Vr
–
Vr R
Recall, =
Vi R + jω L + 1
jω C
Vr
Vi
1
higher Q
1
2 Δω
bandwidth
ωo ω
ωo
Define Q = quality factor
Δω
high Q ⇒ more selective
6.002 Fall 2000 Lecture 18 13

Quality Factor Q
ωo
Q=
Δω
ωο:
Vr R 1
= =
Vi R + jω L + 1 ⎛ L 1 ⎞
1 + j⎜ ω − ⎟
jω C ⎝ R ω CR ⎠
at ωο =0
1
ωo =
LC
Δω ?
6.002 Fall 2000 Lecture 18 14

Quality Factor Q
ωo
Q=
Δω
Δω :
1
Note that abs magnitude is
2
Vr 1 1
when = =
Vi ⎛ L 1 ⎞ 1 ± j1
1 + j⎜ ω − ⎟
⎝ R ω CR ⎠
ωL 1
i.e. when − = ±1
R ω CR
ωR 1
ω2 m − =0
L LC
Looking at the roots of both equations,
R 1 R2 4 R 1 R2 4
ω1 = + + ω2 = − + +
2 L 2 L2 LC 2L 2 L2 LC
R
Δω = ω1 − ω2 =
L
6.002 Fall 2000 Lecture 18 15

Quality Factor Q
ωo
Q=
Δω
ωo ωo L ωo =
1
Q= =
R R LC
L
The lower the R (for series R),

the sharper the peak
6.002 Fall 2000 Lecture 18 16

Quality Factor Q
Another way of looking at Q :
energy stored
Q = 2π
energy lost per cycle
1 2
L Ir
= 2π 2
1 2 2π
Ir R
2 ω0
ωo L
Q=
R
6.002 Fall 2000 Lecture 18 17

CIRCUITS AND
6.002 ELECTRONICS
The Operational Amplifier

Abstraction
6.002 Fall 2000 Lecture 19 1

Review
MOSFET amplifier — 3 ports
power
VS
+ port
+ vO output
input port
vI –
port –
–
Amplifier abstraction
VS
+
vI vO
+ +
vI v
– – – O
Function of vI
6.002 Fall 2000 Lecture 19 2

Review
vI vO
Function of vI
Can use as an abstract building block for

more complex circuits (of course, need
to be careful about input and output).
Today
Introduce a more powerful amplifier
abstraction and use it to build more
complex circuits.
Reading: Chapter 15 from A & L.
6.002 Fall 2000 Lecture 19 3

Operational Amplifier
Op Amp
VS
power +
+ port –
input
port – output
port
+
–
−VS
More abstract representation:
+ +
vIN vOUT
– –
6.002 Fall 2000 Lecture 19 4

Circuit model (ideal):
+ vO
i=0
v+
+
v +
Av
–
– v– A→∞
–
i=0
i.e. ∞ input resistance

0 output resistance
“A” virtually ∞
No saturation
6.002 Fall 2000 Lecture 19 5

Using it…
12V + VS = 12V
–
+ vO
vIN
–
− VS = −12V RL
–
12V +
Demo
vO active region
12V
saturation
vIN
− 10 μV 10μV
A ~ 106
− 12V but unreliable,
temp. dependent
(Note: possible confusion with MOSFET saturation!)
6.002 Fall 2000 Lecture 19 6

Let us build a circuit…
Circuit: noninverting amplifier
v+
+
v− vO
vIN +
–
–
R1
R2
Equivalent circuit model
+ op amp
i=0
v+ vO
+ A(v + − v − )
vIN +
– – R1
−
v
–
i=0
R2
6.002 Fall 2000 Lecture 19 7

Let us analyze the circuit:
Find vO in terms of vIN, etc.
vO = A(v + − v − )
⎛ R2 ⎞
= A⎜ vIN − vO ⎟
⎝ R1 + R2 ⎠
⎛ AR2 ⎞
vO ⎜ 1 + ⎟ = AvIN
⎝ R1 + R2 ⎠
AvIN
vO =
AR2
1+
R1 + R2
What happens when “A” is very large?
6.002 Fall 2000 Lecture 19 8

Let’s see… When A is large
AvIN AvIN
vO = ≈
AR2 AR2
1+
R1 + R2 R1 + R2
(R1 + R2 )
≈ vIN
R2
Suppose A = 10 6
R1 = 9 R gain
R2 = R
10 6 ⋅ vIN
vO =
10 6 R
1+
9R + R
10 6 ⋅ vIN
= Demo
1
1 + 10 ⋅6
10
vO ≈ vIN ⋅ 10
Gain:
determined by resistor ratio
insensitive to A, temperature, fab variations
6.002 Fall 2000 Lecture 19 9

Why did this happen?
Insight:
5V
v+ 12V
+ 10V
v− A vO = 2vIN
vIN + 5V –
– R
6V 6V
vO
–
negative i =0 2
feedback R
e.g. vIN = 5V
Suppose I perturb the circuit…
(e.g., force vO momentarily to 12V somehow).
Stable point is when v+ ≈ v- .
Key: negative feedback Æ portion of
output fed to –ve input.
e.g. Car antilock brakes
Æ small corrections.
6.002 Fall 2000 Lecture 19 10

Question: How to control a
high-strung device?
Antilock brakes
is it
turning?
yes/no c k
db a it’s
fee all about
Michelin control
no yes
release apply
cs
di
v. v. powerful brakes
6.002 Fall 2000 Lecture 19 11

More op amp insights:
Observe, under negative feedback,
⎛ R1 + R2 ⎞
⎜ ⎟vIN
v R1 ⎠
v+ − v− = O = ⎝ →0
A A
v+ ≈ v−
We also know
i+ ≈ 0
i -≈ 0
Æyields an easier analysis method

(under negative feedback).
6.002 Fall 2000 Lecture 19 12

Insightful analysis method
under negative feedback
v+ ≈ v−
i+ ≈ 0
i− ≈ 0
R1 + R2
a vIN g vO = vIN
R2
+
vO
b vIN –
vIN +
– R1 f vIN
c vIN R2
e i=0
vIN
d R2
R2
6.002 Fall 2000 Lecture 19 13

Question:
a vIN v +
+ c vIN
v − vO ?
vIN +
– b vIN –
vO ≈ vIN
R1 + R2
or vO = vIN
R2
with R1 = 0
R2 = ∞
6.002 Fall 2000 Lecture 19 14

Why is this circuit useful?
+
vO
vIN +
–
–
vO ≈ vIN
Buffer
voltage gain = 1
input impedance = ∞
output impedance = 0
current gain = ∞
power gain = ∞
6.002 Fall 2000 Lecture 19 15

CIRCUITS AND
6.002 ELECTRONICS
Basic Circuit Analysis Method

(KVL and KCL method)

Review
Lumped Matter Discipline LMD:
Constraints we impose on ourselves to simplify
our analysis
∂φ B Outside elements
=0
∂t
∂q Inside elements
=0
∂t
wires resistors sources
Allows us to create the lumped circuit
abstraction

Review
LMD allows us to create the

lumped circuit abstraction
i
+
v Lumped circuit element
-
power consumed by element = vi

Review
Review
Maxwell’s equations simplify to

algebraic KVL and KCL under LMD!
KVL:
∑ jν j = 0
loop
KCL:
∑jij = 0
node

Review
R1 R4
R3
+ b d
–
R2 R5
vca + vab + vbc = 0 KVL

DEMO
ica + ida + iba = 0 KCL

Method 1: Basic KVL, KCL method of
Circuit analysis
Goal: Find all element v’s and i’s

1. write element v-i relationships
(from lumped circuit abstraction)
2. write KCL for all nodes
3. write KVL for all loops
lots of unknowns
lots of equations
lots of fun
solve

Method 1: Basic KVL, KCL method of
Circuit analysis
Element Relationships
R
For R, V = IR
For voltage source, V = V0 +–
V0
For current source, I = I 0 J
Io
3 lumped circuit elements

KVL, KCL Example
a
+ +
ν1 R1 ν4 R4
– R3 –
+ + b d
ν 0 = V0 –
– +ν 3 –
+ +
ν2 R2 ν5 R5
– –
c
The Demo Circuit

Associated variables discipline
i
+
ν Element e
-
Current is taken to be positive going

into the positive voltage terminal
Then power consumed = νi is positive

by element e

KVL, KCL Example
a
i1 L 2 i4
+ +
ν1 R1 ν 4 R4
i0 – R3 –
+ + L1 b i3
ν 0 = V0 – d
– i2 +ν 3 – i5
+ +
ν2 R2 ν 5 R5
– L3 –
c
L4
The Demo Circuit
6.002 Fall 2000 Lecture 2 10

Analyze
ν 0 …ν 5 ,ι0 …ι5 12 unknowns
1. Element relationships (v, i )
v0 = V0 given v3 = i3 R3 6 equations
v1 = i1 R1 v4 = i4 R4
v2 = i2 R2 v5 = i5 R5
2. KCL at the nodes
a: i0 + i1 + i4 = 0 3 independent
b: i2 + i3 − i1 = 0 equations
d: i5 − i3 − i4 = 0
e: − i0 − i2 − i5 = 0 redundant
3. KVL for loops
L1: − v0 + v1 + v2 = 0 3 independent
L2: v1 + v3 − v4 = 0 equations
L3: v3 + v5 − v2 = 0
L4: − v0 + v4 + v5 = 0 redundant n s
ti o
ua owns
eq nk n
u
1 2 12
/
ugh @#!
6.002 Fall 2000 Lecture 2 11

Other Analysis Methods
Method 2— Apply element combination rules
R1 R2 R3 RN R1 + R2 + + RN
A … ⇔
B G1 G2 GN ⇔ G1 + G2 + GN
1
Gi =
Ri
V1 V2 V1 + V2
C +– +– ⇔ +–
D
I1 I2 ⇔ I1 + I 2
J
J
Surprisingly, these rules (along with superposition, which

you will learn about later) can solve the circuit on page 8
6.002 Fall 2000 Lecture 2 12

Other Analysis Methods
Method 2— Apply element combination rules
Example I =?
V + R1
–
R2 R3
I I
R1
V +
– V +
– R
R2 R3
R2 + R3
R2 R3
R = R1 +
R2 + R3
V
I=
R
6.002 Fall 2000 Lecture 2 13

Method 3—Node analysis
Particular application of KVL, KCL method
1. Select reference node ( ground)

from which voltages are measured.
2. Label voltages of remaining nodes

with respect to ground.
These are the primary unknowns.
3. Write KCL for all but the ground

node, substituting device laws and
KVL.
4. Solve for node voltages.
5. Back solve for branch voltages and

currents (i.e., the secondary unknowns)
6.002 Fall 2000 Lecture 2 14

Example: Old Faithful
plus current source
V0
R1 R R4
3 e2
+ V e1
– 0
R2 R5 I1
Step 1
Step 2
6.002 Fall 2000 Lecture 2 15

plus current source
V0
R1 R R4
3 e2
+ V e1
– 0
for
R2 R5 I1 convenience,
J
write
1
Gi =
Ri
KCL at e1
(e1 − V0 )G1 + (e1 − e2 )G3 + (e1 )G2 = 0
KCL at e2
(e2 − e1 )G3 + (e2 − V0 )G4 + (e2 )G5 − I1 = 0
Step 3
6.002 Fall 2000 Lecture 2 16

plus current source
V0
R1 R R4
3 e2
+ V e1
– 0
R2 R5 I1
J
1
Gi =
Ri
KCL at e1
(e1 − V0 )G1 + (e1 − e2 )G3 + (e1 )G2 = 0
KCL at l2
(e2 − e1 )G3 + (e2 − V0 )G4 + (e2 )G5 − I1 = 0
move constant terms to RHS & collect unknowns

e1 (G1 + G2 + G3 ) + e2 (−G3 ) = V0 (G1 )
e1 (−G3 ) + e2 (G3 + G4 + G5 ) = V0 (G4 ) + I1
2 equations, 2 unknowns Solve for e’s
(compare units) Step 4
6.002 Fall 2000 Lecture 2 17

In matrix form:
G1 + G2 + G3 − G3   e1   G1V0 
 =
 − G3 G3 + G4 + G5  e2  G V + I 
 4 0 1
conductivity unknown sources

matrix node
voltages
Solve
G3 + G4 + G5 G3   G1V0 
 e1   G3 G1 + G2 + G3  G4V0 + I1 
e  = (G1 + G2 + G3 )(G3 + G4 + G5 ) − G3 2
 2
e = 3 4
(
G +G +G G V + G G V + I
5 1 0 3 4 0 1
)( ) ( )( )
1 G G +G G +G G +G G +G G +G G +G 2 +G G +G G
1 3 1 4 1 5 2 3 2 4 2 5 3 3 4 3 5
(G3 )(G1V0 ) + (G1 + G2 + G3 )(G4V0 + I 1 )

e2 = 2
G1G3 + G1G4 + G1G5 + G2G3 + G2G4 + G2 G5 + G3 + G3G4 + G3G5
(same denominator)
Notice: linear in V0 , I1 , no negatives

in denominator
6.002 Fall 2000 Lecture 2 18

Solve, given
G1  1 G2  1 1
 = = G3 =
G5  8.2 K G4  3.9 K 1.5 K
I1 = 0
(
G G V + G +G +G G V + I
e = 3 10 1 2 3 40 1
)( )
( )(
2 G + G + G + G + G + G −G 2
1 2 3 3 4 5 3
)
1 1 1
G +G +G = + + =1
1 2 3 8.2 3.9 1.5
1 1 1
G3 + G4 + G5 = + + =1
1.5 3.9 8.2
1 1 1
× + 1×
e2 = 8.2 1.5 3.9 V
0
1
1− 2
1.5
Check out the
e2 = 0.6V0 DEMO
If V0 = 3V , then e2 = 1.8V0
6.002 Fall 2000 Lecture 2 19

CIRCUITS AND
6.002 ELECTRONICS
Operational Amplifier Circuits
6.002 Fall 2000 Lecture 20 1

Review
Operational amplifier abstraction
+ ∞ input resistance
0 output resistance
– Gain “A” very large
Building block for analog systems

We will see these examples:
Digital-to-analog converters
Filters
Clock generators
Amplifiers
Adders
Integrators & Differentiators
Reading: Chapter 15.5 & 15.6 of A & L.
6.002 Fall 2000 Lecture 20 2

Consider this circuit:
i R2
i R1
v− –
v2 +
– v+ + +
v1 + R1 vOUT
– R2 –
+ R2 vOUT = v − − iR2
v = v1
R1 + R2 −
v − v
≈ v− = v− − 2 ⋅ R2
R1
v2 − v −
i= ⎡ R ⎤ R
R1 = v − ⎢1 + 2 ⎥ − v2 2
⎣ R1 ⎦ R1
R2 R + R2 R
= v1 ⋅ 1 − v2 2
R1 + R2 R1 R1
R2
= (v1 − v2 )
R1
subtracts!
6.002 Fall 2000 Lecture 20 3
Another way of solving —
use superposition
v1 → 0 v2 → 0
R2 R1
v+ + vOUT1
R1 v1 + R2
– – –
R2
v2 + vOUT2
– +
R1
R1 || R2
+ R1 + R2
R2 vOUT1 =v ⋅
vOUT2 = − v2 R1
R1
v1 ⋅ R2 R1 + R2
= ⋅
R1 + R2 R1
R2
= v1
R1
vOUT = vOUT1 + vOUT2
R2
= (v1 − v2 )
R1
Still subtracts!
6.002 Fall 2000 Lecture 20 4
Let’s build an intergrator…
+
vI +
–
∫ dt vO
–
Let’s start with the following insight:

i
+
i +
– C vO
–
t
1
vO = ∫ i dt
C −∞
vO is related to ∫ i dt
But we need to somehow convert

voltage vI to current.
6.002 Fall 2000 Lecture 20 5

First try… use resistor
+ vR – i
+
R
vI + vO vI
– C →i
R
–
But, vO must be very small compared
to vR, or else
v
i≠ I
R
When is vO small compared to vR ?
dv
RC O + vO = vI larger the RC,
dt smaller the vO
vR
dvO
when RC >> vO for good
dt
dvO integrator
RC ≈ vI ωRC >> 1
dt t
1
or vO ≈ ∫
RC −∞
vI dt
Demo
6.002 Fall 2000 Lecture 20 6
There’s a better way…
Notice i
i
–
v − ≈ 0V under negative feedback

vI
so, i =
R
–
vI + R
– +
vC
vI + –
R
–
R vO = −vC
vI + +
– + vO t
1 vI
– vO = − ∫ dt
C −∞ R
We have our integrator.
6.002 Fall 2000 Lecture 20 7
Now, let’s build a differentiator…
d +
vI +
– vO
dt
–
Let’s start with the following insights:

i
+ dvI
vI – C i=C
dt
dvI
i is related to
dt
But we need to somehow convert current
to voltage.
6.002 Fall 2000 Lecture 20 8

Differentiator…
Recall i
i
–
+
R
i
–
+ + vO = −iR
vO
– current
0V
to
i R voltage
C –
vI + + vC – vO
– +
vI = vC
dvI
i=C
dt
Demo vO = − RC
dvI
dt
6.002 Fall 2000 Lecture 20 9
CIRCUITS AND
6.002 ELECTRONICS
Op Amps Positive Feedback
6.002 Fall 2000 Lecture 21 1

Negative vs Positive Feedback
Consider this circuit — negative feedback
vIN
R1 R2
–
vIN + R1
– + + R
vOUT = − 2 vIN
– R1
and this — positive feedback s is

ly g e
a a
an t p
R2 ee ex
s n
+ on
vIN + R1
– – + R2
“
–
vOUT = − vIN ”
R1
What’s the difference?
Consider what happens when there is a pertubation…

Positive feedback drives op amp into saturation:
vOUT → ±VS
6.002 Fall 2000 Lecture 21 2

Static Analysis of Positive Feedback Ckt
R2
R1
+ vOUT
v IN +
– –
v + R2 vOUT
R1
v IN +
– v − +
– A(v + − v − )
vOUT = A(v + − v − )
= Av +
 v − vIN 
= A OUT ⋅ R1 + vIN 
 R1 + R2 
AR1 AR1vIN
= vOUT − + AvIN
R1 + R2 R1 + R2
 AR1   R1 
vOUT 1 − = v A 1 −
 IN  R + R 
 R1 + R2   1 2
1 − R1 
 R +R  R2
vOUT = 1 2
 ⋅ Av IN = − vIN
− AR 1  R1
 R1 + R2 
6.002 Fall 2000 Lecture 21 3
Representing dynamics of op amp…
v+ +
vo
+ R v* +
– C – Av*
(v + − v − )
v− –
6.002 Fall 2000 Lecture 21 4

Representing dynamics of op amp…
Consider this circuit and let’s analyze its
dynamics to build insight.
R1 R2
+
vo
–
R3 R4
vo
Circuit model R2 A
R1 +
v+ +
+ R v* +
– C – vo
v− (v + − v − ) –
–
R3 R4
Let’s develop equation representing time

behavior of vo .
6.002 Fall 2000 Lecture 21 5

Dynamics of op amp…
vo
vo = Av *
or v =
*
A
dv* *
RC + v = v+ − v_
dt vo R1 +
v+ = = γ vo
RC dvo vo R1 + R2
+ = v+ − v_
vo R3
=−
A dt A −
v = γ vo
+ R3 + R4
= ( γ − −γ ) vo
neglect
dvo  1 A − + 
or +

+ ( γ − γ ) vo = 0

dt  RC RC
dvo A − +
+ ( γ − γ ) vo = 0
dt RC
time −1
dvo vo RC
or + = 0 where T = − +
dt T A( γ − γ )
vo ( 0 ) = 0
6.002 Fall 2000 Lecture 21 6

Consider a small disturbance to vo
(noise).
− + T is positive
if γ > γ
t
−
vo = K e T
stable
+
if γ > γ− T is negative
t
T
vo = K e unstable
+ −
if γ = γ T is very large
vo = K neutral
vo
unstable
K neutral
stable
t
disturbance
Now, let’s build some useful circuits with

positive feedback.
6.002 Fall 2000 Lecture 21 7
One use for instability: Build on the
basic op amp as a comparator
+ VS
v+ + vo
v− –
− VS
vo
+ VS
v+ − v−
0
− VS
vo
+
−
v →0 v
t
6.002 Fall 2000 Lecture 21 8

Now, use positive feedback
vi –
vo
+ R2
+ vo R1
v = R1
R1 + R2
e.g. R1 = R2
+
v = 7.5 vo = 15
vi VS = 15
( vi = v − ) > 7.5 v− < v+

v − > 7.5 v − < −7.5
vo = −15 v − = −7.5
6.002 Fall 2000 Lecture 21 9

Now, use positive feedback
vi –
vo
+ R2
+ vo R1
v = R1
R1 + R2
+ VS R1 e.g. R1 = R2
v = vo = +VS 15
R1 + R2 vi VS = 15
( vi = v − ) > v + v− < v+
v − > 7.5 v − < −7.5
− VS R1
vo = −VS − 15 v − =
R1 + R2
6.002 Fall 2000 Lecture 21 10

vo
15
VS
hysteresis
vi
− 7 .5 0 7 .5
Demo − VS
− 15
Why is hysteresis useful?

vi e.g., analog
v o to digital
7.5
t
− 7.5
Demo
6.002 Fall 2000 Lecture 21 11
Without hysteresis
vi analog
vo to digital
vi
7.5
t
− 7.5
6.002 Fall 2000 Lecture 21 12

Oscillator — can create a clock
R
vC
–
vo
C + R1
vo
R1
2
vo
VS
VS v+
2 v−
vC
−
t
v
VS
−
2 v+
− VS
Assume vo = VS at t = 0
Demo vC = 0
6.002 Fall 2000 Lecture 21 13
Clocks in Digital Systems
We built an oscillator using an op amp.
t
can use as a clock
Why do we use a clock in a digital system?

(See page 735 of A & L)
1 1 0
sender receiver
clock
a 1,1,0?
b When is the signal valid?
common timebase -- when to “look” at a signal
(e.g. whenever the clock is high)
Æ Discretization of time
one bit of information associated with
an interval of time (cycle)
6.002 Fall 2000 Lecture 21 14
CIRCUITS AND
6.002 ELECTRONICS
Energy and Power
6.002 Fall 2000 Lecture 22 1

Why worry about energy?
small batteries
Æ good
Today:
How long will the battery last?
in standby mode
in active use
Will the chip overheat and self-destruct?
6.002 Fall 2000 Lecture 22 2

Look at energy dissipation in
MOSFET gates
VS
+
+ C vO
vI
– –
C: wiring capacitance and

CGS of following gate
Let us determine
standby power
active use power
Let’s work out a few related examples first.
6.002 Fall 2000 Lecture 22 3

Example 1: I
+
V +
– R V
–
V2
Power P = VI =
R
Energy dissipated in time T
E = VIT
6.002 Fall 2000 Lecture 22 4

Example 1:
for our gate
VS VS
RL
RL
vO
vI high vO vI low
RON RON
2
VS
P= P=0
RL + RON
6.002 Fall 2000 Lecture 22 5

Example 2:
Consider
R1
S1 S2
VS +
– C R2
T
T1 T2
S1 closed S1 open
S 2 open S 2 closed
t
Find energy dissipated in each cycle.

Find average power P.
6.002 Fall 2000 Lecture 22 6

T1 : S1 closed, S2 open
i
assume
R1 vC = 0 at t = 0
VS +
– +
C vC
–
vC i
VS VS −t
VS R1C
R1 e
R1
t t
6.002 Fall 2000 Lecture 22 7

Total energy provided by source during T1
T1
E = ∫ VS i dt
0
T1 2 −t
VS
=∫ e R1C
dt
0
R1
2 −t T1
VS
=− R1C e R1C
R1 0
−T1
 
= C VS  1 − e 
2 R1C
 
 
2
≈ C VS if T1 >> R1C
I.e., if we wait long enough
1 2
C VS stored on C ,
2 Independent
1 of R!
2
E1 = C VS dissipated in R1
2
6.002 Fall 2000 Lecture 22 8

T2 : S2 closed, S1 open
+
vC C R2
–
Initially, vC = VS (recall T1 >> R1C)
So, initially,
1
energy stored in capacitor = CVS
2
Assume T2 >> R2C

So, capacitor discharges ~fully in T2
So, energy dissipated in R2 during T2
1 2
E2 = CVS
2
E1, E2 independent of R2 !
6.002 Fall 2000 Lecture 22 9

Putting the two together:
Energy dissipated in each cycle
E = E1 + E2
1 2 1 2
= CVS + CVS
2 2
2
E = CVS energy dissipated in
charging & discharging C
Assumes C charges and discharges fully.
Average power
E
P=
T
2
CVS
=
T
2
= CVS f
1
frequency f =
T
6.002 Fall 2000 Lecture 22 10
Back to our inverter —
VS
RL
vO
vIN RON C
What is P for the following input?
vIN
T T
2 2
t
T 1
T=
f
6.002 Fall 2000 Lecture 22 11

Equivalent Circuit
RL
VS +
– C
RON
What is P for the following input?

vIN
T T
2 2
t
T 1
T=
f
6.002 Fall 2000 Lecture 22 12

What is P for gate?
We can show (see section 12.2 of A & L)
2 2
VS 2 RL
P= + CVS f
2( RL + RON ) (RL + RON )2
when RL >> RON
2
VS
P=
2
+ CVS f e r
2 RL mb
e
rem
e r
mb
me
re
P STATIC P DYNAMIC
independent of f. related to switching
MOSFET ON half capacitor
the time.
6.002 Fall 2000 Lecture 22 13

What is P for gate?
when RL >> RON
2
VS 2
P= + CVS f
2 RL
In standby mode,
In standby mode,
fÆ0,
half the gates in a
so dynamic power
chip can be
is 0
assumed to be on.
So P STATIC per
gate is still VS2 .
2RL
Relates to standby
power.
6.002 Fall 2000 Lecture 22 14

Some numbers…
a chip with 106 gates clocking
at 100 MHZ C =1f F
RL = 10 kΩ
f = 100 × 10 6
VS = 5 V
25
P = 10 6  + 10 −15
× 25 × 100 × 10 6

 2 × 10
4
= 10 6 [1.25 milliwatts + 2.5 microwatts ]
1.25KW! 2.5W
problem ! not bad
must get rid of this α VS 2
α f
reduce VS
next
lecture 5 V → 1V
2.5 W → 150 mW
6.002 Fall 2000 Lecture 22 15
CIRCUITS AND
6.002 ELECTRONICS
Energy, CMOS
6.002 Fall 2000 Lecture 23 1

Review
VS
RL
2
vO VS
vI P=
RL + RON
RON
T1: closed open

T2: open R closed
1
S1 S2
VS +
– C R2
1
T = T1 + T2 =
f
2
P = CVS f
Reading: Section 11.5 of A & L.
6.002 Fall 2000 Lecture 23 2

Review VS
RL
Inverter —
vO
vI RON C
1
Square wave input T= RL >> RON
2 f
VS 2 T
P= + CVS f >>" RC"
2 RL 2
Demo time constant
P STATIC P DYNAMIC
independent of f. related to switching
MOSFET ON half capacitor.
the time.
In standby mode,
In standby mode, half fÆ0,
the gates in a chip can so dynamic power is 0
be assumed to be on.
So P STATIC per gate is
still VS2 .
2RL
6.002 Fall 2000 Lecture 23 3

Review
2
VS 2
P= + CVS f
2 RL
Chip with 106 gates clocking at 100 MHz
C = 1 f F, RL = 10 KΩ , f = 100 × 10 6 , VS = 5 V
⎡ 5 2
−15 6⎤
P = 10 ⎢
6
+ 10 × 5 × 100 × 10 ⎥
2
gates ⎣ 2 × 10 × 10
3
⎦
= 10 6 [1.25 milliwatts + 2.5 μ watts ]
1.25KWatts + 2.5Watts
problem ! not bad
• independent of f • αf
• also standby power • αVS2
(assume ½ MOSFETs reduce VS
ON if f Æ 0) 5VÆ1V
• must get rid of this! 2.5VÆ150mW
6.002 Fall 2000 Lecture 23 4

How to get rid of static power
Intuition:
VS VS
RL
i RL
vO high
vI high vO low vI low
MOSFET
RON off
idea !
VS
vI high vO low
6.002 Fall 2000 Lecture 23 5

New Device PFET
• N-channel MOSFET (NFET)
D
on when vGS ≥ VTN
G off when vGS < VTN
e.g. VTN = 1V
S
• P-channel MOSFET (PFET)

S
on when vGS ≤ VTP
G off when vGS > VTP
e.g. VTP = -1V
D 5V
ON when
less than 4V
6.002 Fall 2000 Lecture 23 6

VS
S
PU = pull up
G D
vI vO
+ D
– G PD = pull down
S
works like an inverter!

IN OUT
6.002 Fall 2000 Lecture 23 7

works like an inverter!
IN OUT
vI = 5V (input high) vI = 0V (input low)
VS = 5V VS = 5V
RON p
vO vO
+ +
vI = 5V = 0V vI = 0V = 5V
– RON n –
Complementary
Called “CMOS logic”
MOS
(our previous logic was called “NMOS”)
6.002 Fall 2000 Lecture 23 8

Key: no path from VS to GND!
no static power!
Let’s compute P DYNAMIC
VS
vI
T
vI vO
t
C f =
1
T
closed for closed for

vI low vI high
RON p
VS +
– C RON n
From
2
P = CVS f
6.002 Fall 2000 Lecture 23 9

For our previous example —
C = 1 f F, VS = 5 V , f = 100 MHz , 1
2
P = CV S f
− 15
= 10 × 5 2 × 100 × 10 6
= 2 . 5 μwatts per gate
P = 2 . 5 μwatts for 10 6 gate chip
Gates f P “keep
100 ~2.5 all
106 MHz watts Pentium? else
same”
300 ~15
2x106 MHz watts PII?
600 ~30
2x106 MHz watts PII?
~240
s p !
8x106 1.2 GHz watts
~1875
PIII?
ga
25x106 3 GHz watts PIV?
6.002 Fall 2000 Lecture 23 10

How to reduce power
A VS 5V Æ 3V Æ 1.8V Æ 1.5V
~PIV Æ 170 watts Æ better, but high
and use big heatsink
B Turn off clock when not in use.

C Change VS depending on need.
Æ Æ next time:
power supply
6.002 Fall 2000 Lecture 23 11

CMOS Logic
NAND:
VS
A B Z
0 0 1
A B 0 1 1
1 0 1
1 1 0
Z
A
5V 5V
0V S 5V S
on off
G D G D
6.002 Fall 2000 Lecture 23 12

In general, if we want to implement F
VS e.g. F = A ⋅ B = A + B
short short when
when F A = 0 or B = 0,
is true,
else open open otherwise
A
Z
B short
when F short when
is true, A · B is true,
else open else open
m b er
reme gan’s law
eM o r
D
6.002 Fall 2000 Lecture 23 13

CIRCUITS AND
6.002 ELECTRONICS
Power Conversion Circuits

and Diodes
6.002 Fall 2000 Lecture 24 1

Power Conversion Circuits (PCC)
+
PCC – 5V DC
110V
60Hz
solar cells, 3V +
battery DC
PCC – 5V DC
DC-to-DC UP converter
Power efficiency of converter important,

so use lots of devices:
MOSFET switches, clock circuits,
inductors, capacitors, op amps, diodes
R
Reading: Chapter 16 and 4.4 of A & L.
6.002 Fall 2000 Lecture 24 2
First, let’s look at the diode
iD ⎛ VvD ⎞
iD = I S e − 1 ⎟
⎜ T
+ ⎜ ⎟
⎝ ⎠
vD
I S = 10 −12 A
–
VT = 0.025V
Boltzmann’s constant
kT
VT = temperature in Kelvins
q charge of an electron
iD iD
vD vD
− IS mV V
Can use this exponential model with

analysis methods learned earlier
analytical graphical incremental
(Our fake expodweeb was modeled after this device!)
6.002 Fall 2000 Lecture 24 3

Another analysis method:
piecewise–linear analysis
P–L diode models:
iD
iD ≥ 0 Æ vD = 0
“short”
or
on
vD
vD < 0 Æ iD = 0 0
“open”
or
off
Ideal diode model
6.002 Fall 2000 Lecture 24 4

“Practical” diode model +–

ideal with offset
0.6V
iD
Short segment
Open segment vD = 0
vD
iD = 0 0.6V
6.002 Fall 2000 Lecture 24 5

Piecewise–linear analysis method

Replace nonlinear characteristic with
linear segments.
Perform linear analysis within each
segment.
6.002 Fall 2000 Lecture 24 6

Example
(We will build up towards an AC-to-DC converter)
Consider 0.6V
+–
+
vI +
– R vO
–
vI is a sine wave
6.002 Fall 2000 Lecture 24 7

Example
0 .6 V
+– Equivalent
+ circuit
vI +
– R vO
–
“Short segment”:
iD = (vI − 0.6 ) / R
+–
+
0.6V
vI ≥ 0.6 + vI R vO = vI − 0.6
–
–
“Open segment”:
iD = 0
+–
+
0.6V
vI < 0.6
+ vI R vO = 0
–
–
6.002 Fall 2000 Lecture 24 8

Example
vI
vO
0.6
t
6.002 Fall 2000 Lecture 24 9

Now consider — a half-wave rectifier
0.6V
+–
+
vI + C R vO
–
–
6.002 Fall 2000 Lecture 24 10

A half-wave rectifier
vI diode on diode off
vO
t
C
current
pulses
charging
Demo capacitor
MIT’s supply shows

“snipping” at the peaks
(because current drawn
at the peaks)
6.002 Fall 2000 Lecture 24 11

se
DC-to-DC UP Converter Do not u
resistive
s!
i el em en t
+
VI +
vS C vO load
DC –
switch
S –
vS
S S
closed open
t
T
Tp
The circuit has 3 states:
I. S is on, diode is off
i increases linearly
II. S turns off, diode turns on
C charges up, vO increases
III. S is off, diode turns off
C holds vO (discharges into load)
6.002 Fall 2000 Lecture 24 12

More detailed analysis
I. Assume i(0) = 0, vO(0) > 0

S on at t = 0, diode off
L
vO
i
VI +
– C
i
VI T
i (T ) = VI di
L slope = VI = L
L dt
i is a ramp
t
T
1
ΔE = energy stored at t = T : Li( T )2
2
2
VI T 2
ΔE =
2L
6.002 Fall 2000 Lecture 24 13

II. S turns off at t = T
diode turns on (ignore diode voltage drop)
L vO
i
VI +
– S C
i State III starts here

VI T
L
0 t
T T′ TP
1
ωO =
LC
Diode turns off at T′ when i tries to go negative.
6.002 Fall 2000 Lecture 24 14

II. S turns off at t = T, diode turns on
Let’s look at the voltage profile
i
VI T
L
0 t
T T′ TP
1
ωO =
LC
Capacitor voltage III.

vO
ignore
diode
vO (T ) ΔvO
drop
1
ωO =
LC
0 t
T T′ TP
Diode turns off at T′ when I tries to go negative.
6.002 Fall 2000 Lecture 24 15

II. S turns off at t = T, diode turns on
Let’s look at the voltage profile
i
VI T
L
0 t
T T′ TP
1
ωO =
LC
Capacitor voltage III.

vO
ignore
diode
vO (T ) ΔvO
drop
1
ωO =
LC
0 t
T T′ TP
Diode turns off at T′ when I tries to go negative.
6.002 Fall 2000 Lecture 24 16

Eg, no load
+
VI +
– S C vO
–
C holds vO after T′
i is zero
Capacitor voltage
vO
0 t
T′ TP
6.002 Fall 2000 Lecture 24 17

Eg, no load
+
VI +
– S C vO
–
C holds vO after T′
i is zero
until S turns ON at TP, and cycle repeats
I II III I II III …
Thus, vO increases each cycle, if there is no load.
vO
vO (n)
t
TP 2TP 3TP
6.002 Fall 2000 Lecture 24 18
What is vO after n cycles Æ vO(n) ?
Use energy argument … (KVL tedious!)
Each cycle deposits ∆E in capacitor.
1
2
ΔE = L i( t = T ) 2
1 VI T 2 2
ΔE = 2
2 L 1 ⎛ VI T ⎞
= L⎜ ⎟
2 ⎝ L ⎠
After n cycles, energy on capacitor
2
nVI T 2
nΔE =
2L
1
This energy must equal CvO ( n )2
2
2 2
1 nV T
so,
2
CvO ( n ) = I
2 2L
2
nVI T 2 1
or vO ( n ) = ωO =
LC LC
vO ( n ) = VI T ωO n
6.002 Fall 2000 Lecture 24 19
How to maintain vO at a given value?
+
VI + vO load
–
–
vO
pwm
control
compare
T change T
Tp + vref
–
2
VI T 2
recall ΔE =
2L
Another example of negative feedback:

if (v
O − vref ) ↑ then T ↓
if (v
O − vref ) ↓ then T ↑
6.002 Fall 2000 Lecture 24 20

CIRCUITS AND
6.002 ELECTRONICS
Violating the Abstraction Barrier
6.002 Fall 2000 Lecture 25 1

Case 1: The Double Take
Problem R VO
“0” Æ “1” Vi
expected observed
VO “1” VO “1”
huh?
“0” t “0” t
in forbidden region!
6.002 Fall 2000 Lecture 25 2

(a) DC case
R VO V1
very high
Vi impedance,
like open
circuit
Vi = 5V DC VO = 5V DC V1 = 5V DC OK
6.002 Fall 2000 Lecture 25 3

(b) Step
R VO V1
very high
Vi impedance,
like open
circuit
5V Vi
b.1
0V t
t=0
VO
5V
b.3
VO = 2.5V not ok!
t
t=0 2T
b.2
5V V1
looks ok!
t
t=0 T
6.002 Fall 2000 Lecture 25 4
2.5
R
5
....
Vi R→
characteristic
impedance instantaneous R divider
finite propagation speed
of signals
5V 5V 5V
0 0 2T 0 T
6.002 Fall 2000 Lecture 25 5

Question: So why did our circuits work?
5V V1
o u rce
1. Look only at V1
“S
i n ation”
Term
O
0 t
DEM 0 T
5V VO
2. Keep wires short
EM O w ire 0 t
D mal l
e s 0
us
le l
Paral ation
in
5V VO term
3. Termination
2.5V t
O 0
DEM at the
R
add
end
More in 6.014
6.002 Fall 2000 Lecture 25 6

Case 2: The Double Dip
Problem Æ strange spikes on supply
0 1
V 1 0
OK
driving a 50 Ω
resistor!
0
V
input
driving a 50 Ω
resistor! Why?
6.002 Fall 2000 Lecture 25 7

Drop across inductor
VS Ldi
dt
Inverter current
v inductor
VS
solution 1. short wires

2. low inductance wires
3. avoid big current swings
6.002 Fall 2000 Lecture 25 8

Case 3: The Double Team, or,
Slower may be faster!
Problem
a given chip
worked,
but was slow.
ideal
C
actual
Let’s try speeding it up by using stronger

drivers
ideal
ω
L actual
Disaster!
6.002 Fall 2000 Lecture 25 9
Why? DEMO
Consider
ok
C
R1 DEMO
R0
R2
dV
α
dt
dV
C
dt
crosstalk!
6.002 Fall 2000 Lecture 25 10

How does this relate to chip?
Solution
DEMO
small dV
dt
Load output! — put cap on outputs of chip

— jitter edges
— slew edges
6.002 Fall 2000 Lecture 25 11

Case 4: The Double Jump
Careful abstraction violation for the
better…
Recall
Vo
Vi expect
Vo
Vi
but, observe
Vo
Vi
6.002 Fall 2000 Lecture 25 12

Case 4: The Double Jump
Careful abstraction violation for the
better…
5V
Vi
5V 5V + 3V
So, pullup has
0V 3V stronger drive
as output rises
6.002 Fall 2000 Lecture 25 13

CIRCUITS AND
6.002 ELECTRONICS
Superposition, Thévenin and Norton

Review
Circuit Analysis Methods
z KVL: KCL: VI
∑Vi = 0 ∑ Ii = 0
loop node
z Circuit composition rules

z Node method – the workhorse of 6.002
KCL at nodes using V ’s referenced
from ground
(KVL implicit in “ (ei − e j ) G ”)

Linearity
Consider R1
e
R2 I
J
V +
–
Write node equations –

e −V e
+ −I =0
R1 R2
Notice:
linear in e,V , I
No eV ,VI
terms

Linearity R1
Consider
R2 I
J
V +
–
Write node equations --

e −V e
+ −I =0 linear in e,V , I
R1 R2
Rearrange --
1 1 V
 R + R e =
R1
+ I
 1 2
conductance node linear sum

matrix voltages of sources
G e = S

Linearity
Write node equations --

e −V e
+ −I =0 linear in e,V , I
R1 R2
Rearrange --
1 1 V
 R + R e =
R1
+ I
 1 2
conductance node linear sum

matrix voltages of sources
G e = S
R2 RR
or e= V+ 1 2 I
R1 + R2 R1 + R2
e = a1V1 + a2V2 + … + b1 I1 + b2 I 2 + …
Linear!
Linearity ⇒ Homogeneity
Superposition

Superposition
Homogeneity
x1
x2 .
. y
.
⇓
αx1
αx2 .. αy
.

Superposition
Superposition
x1a x1b
x2 a .
.. ya x2 b .
.. yb
⇓
x1a + x1b
x2 a + x2 b .
.. y a + yb

Superposition
Specific superposition example:
V1 0
0 y1 V2 y2
⇓
V1 + 0
0 + V2 y1 + y2

Method 4: Superposition method
The output of a circuit is
determined by summing the
responses to each source
acting alone.
u r ce s
e nt so
e p e nd
ind only
6.002 Fall 2000 Lecture 3 10

i i
+ +
V =0 +
– v v
- -
short
i i
+ +
I =0 v
J
v
- -
open
6.002 Fall 2000 Lecture 3 11

Back to the example
Use superposition method
R1
e
R2 I
V +
– J
6.002 Fall 2000 Lecture 3 12

Back to the example
Use superposition method
V acting alone
e
R1
R2
R2 I = 0 eV = V
V + R1 + R2
–
I acting alone
e
R1
R1 R2
R2 I eI = I
J
V =0 R1 + R2
sum superposition
R2 R1 R2
e = eV + eI = V+ I
R1 + R2 R1 + R2
Voilà !
6.002 Fall 2000 Lecture 3 13
Demo
salt
water
constant
+
–
?
+
–
output shows
sinusoid superposition
6.002 Fall 2000 Lecture 3 14

Yet another method…
Consider
itr a r y network
Arb N
resistors i
Vm +
+ In v i
J
–
J -
also
By superposition independent
of external
v = ∑ α mVm + ∑ β n I n + Ri excitement &
m n
behaves like
no resistance a resistor
units units
By setting All
∀n I n = 0, ∀mVm = 0, ∀n I n = 0,
i = 0 i = 0 ∀mVm = 0
independent of external
excitation and behaves like a
voltage “ vTH ”
6.002 Fall 2000 Lecture 3 15

Or
v = vTH + RTH i
As far as the external world is concerned

(for the purpose of I-V relation),
“Arbitrary network N” is indistinguishable
from:
RTH
N
Thévenin +
equivalent + vTH v i
J
–
network -
vTH open circuit voltage

at terminal pair (a.k.a. port)
RTH resistance of network seen
from port
( Vm ’s, I n ’s set to 0)
6.002 Fall 2000 Lecture 3 16

Method 4:
The Thévenin Method
i
N
J +
+
+ – v E
– -
Thévenin equivalent
RTH i
+
+ vTH
– v E
-
Replace network N with its Thévenin

equivalent, then solve external network E.
6.002 Fall 2000 Lecture 3 17

Example:
i1 R1
+
V R2 I
J
–
i1 R1
RTH
+ VTH + I
V
– –
V − VTH
i1 =
R1 + RTH
6.002 Fall 2000 Lecture 3 18

Example:
VTH : +
VTH R2 I
J
VTH = IR2 -
RTH : +
RTH R2
RTH = R2 -
6.002 Fall 2000 Lecture 3 19

Graphically, v = vTH + RTH i
1
RTH
v
vTH
“V ”
OC
− I SC
Open circuit v = vTH VOC

(i ≡ 0)
− vTH − I SC
Short circuit i =
(v ≡ 0) RTH
6.002 Fall 2000 Lecture 3 20

in recitation,
Method 5: see text
The Norton Method
i
J +
+ IN RTH = RN
–
J
+ v
– -
Norton
equivalent
VTH
IN =
RTH
6.002 Fall 2000 Lecture 3 21

Summary
Discretize matter
LMD LCA
Physics EE
R, I, V Linear networks
Analysis methods (linear)
KVL, KCL, I — V
Combination rules
Node method
Superposition
Thévenin
Norton
Next
Nonlinear analysis
Discretize voltage
… 101100 …
6.002 Fall 2000 Lecture 3 22

CIRCUITS AND
6.002 ELECTRONICS
The Digital Abstraction

Review
z Discretize matter by agreeing to
observe the lumped matter discipline
Lumped Circuit Abstraction
zAnalysis tool kit: KVL/KCL, node method,

superposition, Thévenin, Norton
(remember superposition, Thévenin,
Norton apply only for linear circuits)

Today
Discretize value Digital abstraction
Interestingly, we will see shortly that the

tools learned in the previous three
lectures are sufficient to analyze simple
digital circuits
Reading: Chapter 5 of Agarwal & Lang

But first, why digital?
In the past …
Analog signal processing
R1
R2 V0
V1 +
–
+ V1 and V2
V2 – might represent the
outputs of two
sensors, for example.
By superposition,
R2 R1
V0 = V1 + V2
R1 + R2 R1 + R2
If R1 = R 2 ,
V1 + V2
V0 =
2
The above is an “adder” circuit.

Noise Problem
add noise on
this wire
Receiver:
huh?
… noise hampers our ability to distinguish

between small differences in value —
e.g. between 3.1V and 3.2V.

Value Discretization
Restrict values to be one of two
HIGH LOW
5V 0V
TRUE FALSE
1 0
…like two digits 0 and 1
Why is this discretization useful?
(Remember, numbers larger than 1 can be

represented using multiple binary digits and
coding, much like using multiple decimal digits to
represent numbers greater than 9. E.g., the
binary number 101 has decimal value 5.)

Digital System
noise
VN
VS
VR
sender receiver
VN = 0V
VS VR
5V “0” “1” “0” HIGH “0” “1” “0”
5V
2.5V t 2.5V t
0V LOW 0V
With noise
VN = 0.2V VS
VS
“0” “1” “0”
“0” “1” “0” 0.2V
5V t
2.5V t 2.5V t
0V

Digital System
Better noise immunity

Lots of “noise margin”
For “1”: noise margin 5V to 2.5V = 2.5V

For “0”: noise margin 0V to 2.5V = 2.5V

Voltage Thresholds
and Logic Values
5V
1
1
1
sender 2.5V receiver
0 0 0
0V

But, but, but …
What about 2.5V?
Hmmm… create “no man’s land”
or forbidden region
For example,
5V
1 1
VH
3V
sender forbidden receiver
region
2V
VL
0 0
0V
“1” V 5V
H
“0” 0V V
L
6.002 Fall 2000 Lecture 4 10

But, but, but …
Where’s the noise margin?
What if the sender sent 1: VH ?
Hold the sender to tougher standards!
5V
V
1 0H
1
V
IH
sender receiver
V
IL
0
0
V
0L
0V
6.002 Fall 2000 Lecture 4 11

But, but, but …
Where’s the noise margin?
What if the sender sent 1: VH ?
Hold the sender to tougher standards!
5V
V
1 0H
1
V
IH
sender Noise margins receiver
V
IL
0
0
V
0L
0V
“1” noise margin: V - V

IH 0H
“0” noise margin: V - V
IL 0L
6.002 Fall 2000 Lecture 4 12

0 1 0 1 sender
5V
V
0H
V
IH
V
IL
V
0L
0V t
0 1 0 1 receiver
5V
V
0H
V
IH
V
IL
V
0L
0V t
Digital systems follow static discipline: if

inputs to the digital system meet valid input
thresholds, then the system guarantees its
outputs will meet valid output thresholds.
6.002 Fall 2000 Lecture 4 13

Processing digital signals
Recall, we have only two values —
1,0 Map naturally to logic: T, F

Can also represent numbers
6.002 Fall 2000 Lecture 4 14

Processing digital signals
Boolean Logic
If X is true and Y is true
Then Z is true else Z is false.
Z = X AND Y
X, Y, Z
Z = X • Y are digital signals
Boolean equation “0” , “1”
X AND gate
Y Z
Truth table representation:

X Y Z
0 0 0
0 1 0
1 0 0
1 1 1
Enumerate all input combinations
6.002 Fall 2000 Lecture 4 15

Combinational gate
abstraction
Adheres to static discipline
Outputs are a function of
inputs alone.
Digital logic designers do not

have to care about what is
inside a gate.
6.002 Fall 2000 Lecture 4 16

Demo
Noise
X
Y Z
Z = X • Y
6.002 Fall 2000 Lecture 4 17

Examples for recitation
Z = X • Y
6.002 Fall 2000 Lecture 4 18

In recitation…
Another example of a gate
If (A is true) OR (B is true)
then C is true
else C is false
C = A + B Boolean equation
OR
A
B C
OR gate
More gates
B B X
Y Z
Inverter NAND
Z = X • Y
6.002 Fall 2000 Lecture 4 19

Boolean Identities
X • 1 = X
X • 0 = X
X + 1 = 1
X +0 = X
1 = 0
0 = 1
AB + AC = A • (B + C)
Digital Circuits
Implement: output = A + B • C
B
C B•C
A output
6.002 Fall 2000 Lecture 4 20

CIRCUITS AND
6.002 ELECTRONICS
Inside the Digital Gate

Review
The Digital Abstraction
z Discretize value 0, 1
z Static discipline
meet voltage thresholds
sender receiver
VOH VIH forbidden
VIL region
VOL
Specifies how gates must be designed

Review
Combinational gate abstraction

outputs function of input alone
satisfies static discipline
A B C
A
B C 0 0 1
NAND 0 1 1
1 0 1
1 1 0

For example: Demo
a digital circuit
A A⋅ B
B
D
C
D = (C ⋅ (A ⋅ B ))
3 gates here
A Pentium III class microprocessor

is a circuit with over 4 million gates !!
The RAW chip

being built at the
Lab for Computer Science at MIT
has about 3 million gates.

How to build a digital gate
Analogy
i tc hes)
l ik e (li ke sw
power taps
supply A B
C
if A=ON AND B=ON
C has H20
else C has no H20
Use this insight to build an AND gate.

How to build a digital gate
OR gate
A

Electrical Analogy
C
A B
V +
–
Bulb C is ON if A AND B are ON,

else C is off
Key: “switch” device

Electrical Analogy
equivalent ckt
Key: “switch” device
in
C =0
in
control out
C
in
out
C=1
3-Terminal device out

if C = 0
short circuit between in and out
else
open circuit between in and out
For mechanical switch,

control mechanical pressure
Consider
VS
RL RL
VOUT + VS VOUT
–
IN
C C
VS = “1”
OUT
VS
VOUT
Truth table for
C =0
C VOUT
VS 0 1
1 0
VOUT
C =1

What about?
Truth table for
VS
VOUT c1 c2 VO
c1 0 0 1
0 1 1
c2
1 0 1
1 1 0
VS Truth table for
VOUT
c1 c2 VO
c1 c2 0 0 1
0 1 0
1 0 0
1 1 0
6.002 Fall 2000 Lecture 5 10

What about?
can also build compound gates
VS
D
A C D = (A ⋅ B) + C
B
6.002 Fall 2000 Lecture 5 11

The MOSFET Device
Metal-Oxide
Semiconductor
Field-Effect
Transistor
drain
D
G
gate
≡
S
source
3 terminal lumped element

behaves like a switch
G : control terminal
D, S : behave in a symmetric
manner (for our needs)
6.002 Fall 2000 Lecture 5 12

The MOSFET Device
Understand its operation by viewing it
as a two-port element —
e c k out k
Ch extboo l
the t s interna
for it ture. D iDS +
r u c iG
s t G vDS
+
vGS S
– –
D D
iDS
G off G on
vGS < VT S vGS ≥ VT S
VT ≈ 1V typically
“Switch” model (S model) of the MOSFET
6.002 Fall 2000 Lecture 5 13

Demo
Check the MOS device

on a scope. i DS
+
vDS
+
vGS
– –
iDS
vGS ≥ VT
vGS < VT
vDS
iDS vs vDS
6.002 Fall 2000 Lecture 5 14

A MOSFET Inverter
VS = 5V
RL
vOUT
B
A IN
A B
Note the power of abstraction.

The abstract inverter gate representation
hides the internal details such as power
supply connections, RL, GND, etc.
(When we build digital circuits, the
and are common across all gates!)
6.002 Fall 2000 Lecture 5 15

Example
vOUT
5V vIN vOUT
0V V v IN
T =1V 5V
The T1000 model laptop desires gates that satisfy
the static discipline with voltage thresholds. Does
out inverter qualify?
VOL = 0.5V VIL = 0.9V
VOH = 4.5V VIH = 4.1V
sender receiver
1: 5 5 1
4.5 V 4.1
OH VIH
0.9 VIL
0.5 VOL
0: 0 0 0
Our inverter satisfies this.
6.002 Fall 2000 Lecture 5 16
E.g.:
Does our inverter satisfy the static
discipline for these thresholds:
VOL = 0.2V VIL = 0.5V

yes
VOH = 4.8V VIH = 4.5V
x
VOL = 0.5V VIL = 1.5V
no
VOH = 4.5V VIH = 3.5V
6.002 Fall 2000 Lecture 5 17

Switch resistor (SR) model
of MOSFET
…more accurate MOS model
D D D
G G RON
G
S vGS < VT S vGS ≥ VT S
e.g. RON = 5 KΩ
6.002 Fall 2000 Lecture 5 18

SR Model of MOSFET
D D D
G G RON
G
S vGS < VT S vGS ≥ VT S
MOSFET MOSFET
S model SR model
vGS ≥ VT
vGS ≥ VT
iDS iDS 1
RON
vGS < VT vGS < VT

vDS vDS
6.002 Fall 2000 Lecture 5 19

Using the SR model
VS
RL RL
vOUT + VS vOUT
–
IN
C C
VS = “1”
OUT
VS Truth table for

RL
vOUT
C VOUT
RON
C =0
0 1
1 0
VS
RL Choose RL, RON, VS such that:
vOUT V R
C =1 RON v = S ON ≤ V
OUT R +R OL
vGS ≥ VT ON L
6.002 Fall 2000 Lecture 5 20

CIRCUITS AND
6.002 ELECTRONICS
Nonlinear Analysis

Review
Discretize matter t LCA

m1 X KVL, KCL, i-v
any
m2 X Composition rules
circuit
m3 X Node method
m4 X Superposition linear
m5 X Thévenin, Norton circuits

Review
Discretize value t Digital abstraction

X Subcircuits for given “switch”
setting are linear! So, all 5
methods (m1 – m5) can be
applied
VS VS
A =1
RL B =1 RL
C C
A B RON RON
SR MOSFET Model

Today
Nonlinear Analysis
X Analytical method
based on m1, m2, m3
X Graphical method
X Introduction to incremental analysis

How do we analyze nonlinear
circuits, for example:
iD Hypothetical
+ nonlinear
V + vD D
–
- device
(Expo Dweeb ☺)
+ vD -
D
iD
iD = aebvD
iD
a
vD
0,0
(Curiously, the device supplies power when vD is negative)
Method 1: Analytical Method
Using the node method,
(remember the node method applies for linear or
nonlinear circuits)
vD − V
+ iD = 0 1
R
iD = aebvD 2
2 unknowns 2 equations
Solve the equation by

trial and error
numerical methods

Method 2: Graphical Method
Notice: the solution satisfies equations
1 and 2
iD
2 iD = aebvD
a
vD
V vD
iD 1 iD = −
R R
V 1
R slope = −
R
vD
V

Combine the two constraints
iD
V called “loadline”
1
R for reasons you
~ 0 .4 will see later
a
¼ vD
~ 0.5 V
1
e.g. V =1 vD = 0.5V
R =1 iD = 0.4 A
1
a=
4
b =1

Method 3: Incremental Analysis
Motivation: music over a light beam
Can we pull this off?
iD iR
+
vI (t ) +
– vD LED AMP
-
light
intensity iR ∝ I R
I D ∝ iD
light intensity IR
vI music signal in photoreceiver
t LED: Light
Emitting
expoDweep ☺
vI (t ) iD (t ) light iR (t ) sound
nonlinear
linear
problem! will result in distortion
Problem:
The LED is nonlinear distortion
iD
iD
vD
t vD = vI
vD
t
iD
vD
t
6.002 Fall 2000 Lecture 6 10

If only it were linear …
iD
iD
vD
vD
t
it would’ve been ok.
What do we do?
Zen is the answer
… next lecture!
6.002 Fall 2000 Lecture 6 11
CIRCUITS AND
6.002 ELECTRONICS
Incremental Analysis

Review
Nonlinear Analysis
X Analytical method
X Graphical method
Today
X Incremental analysis
Reading: Section 4.5

Method 3: Incremental Analysis
Motivation: music over a light beam
Can we pull this off?
iD iR
+
vI (t ) +
– vD LED AMP
-
light
intensity iR ∝ I R
I D ∝ iD
light intensity IR
vI music signal in photoreceiver
t LED: Light
Emitting
expoDweep ☺
vI (t ) iD (t ) light iR (t ) sound
nonlinear
linear
problem! will result in distortion
Problem:
The LED is nonlinear distortion
iD
iD
vD
t vD = vI
vD
t
iD
vD
t

Insight:
iD
ID small region
looks linear
(about VD , ID)
vD
VD
DC offset
or DC bias
Trick:
iD = I D + id
vi (t ) +
– +
vI vD LED
+ -
VI – vD = VD + vd
VI vi

Result
iD
id
ID
vD
VD
very small
vd

Result
vD = vI vd
VD vD
t
iD id
iD
ID ~linear!
t
Demo

The incremental method:
(or small signal method)
1. Operate at some DC offset

or bias point VD, ID .
2. Superimpose small signal vd
(music) on top of VD .
3. Response id to small signal vd
is approximately linear.
Notation:
iD = I D + id
total DC small
variable offset superimposed
signal

What does this mean
mathematically?
Or, why is the small signal response
linear? nonlinear
iD = f (vD )
large DC
We replaced vd
vD = VD + ∆vD increment
about VD
using Taylor’s Expansion to expand

f(vD) near vD=VD :
df (vD )
iD = f (VD ) + ⋅ ∆vD
dvD vD =VD
1 d 2 f (v D ) 2
+ ⋅ ∆vD + "
2! dvD 2 v
D =VD
neglect higher order terms

because ∆vD is small

d f (v D )
iD ≈ f (VD ) + ⋅ ∆vD
d vD vD =VD
constant constant w.r.t. ∆vD

w.r.t. ∆vD slope at VD, ID
We can write
d f (v D )
X : I D + ∆iD ≈ f (VD ) + ⋅ ∆ vD
d vD vD =VD
equating DC and time-varying parts,

I D = f (VD ) operating point
d f (v D )
∆iD = ⋅ ∆vD
d vD vD =VD
constant w.r.t. ∆vD

so, ∆ iD ∝ ∆vD By notation,
∆ iD = id
∆ v D = vd
6.002 Fall 2000 Lecture 7 10
In our example,
bv D
iD = a e
From X : I D + id ≈ a e bVD + a e bVD ⋅ b ⋅ vd
Equate DC and incremental terms,
I D = a ebVD operating point

aka bias pt.
aka DC offset
id = a ebVD ⋅ b ⋅ vd
id = I D ⋅ b ⋅ vd small signal
behavior
constant linear!
6.002 Fall 2000 Lecture 7 11

Graphical interpretation
I D = a ebVD operating point
id = I D ⋅ b ⋅ vd
A
slope at
iD
VD, ID
id
ID B
operating
point
vd
vD
VD
we are
approximating
A with B
6.002 Fall 2000 Lecture 7 12

graphically
We saw the small signal mathematically
now, circuit
Large signal circuit:
ID
+ +
VI – LED VD I D = a ebVD
-
Small signal response: id = I D b vd
+ vd -
behaves like:
id 1
R=
ID b
small signal circuit:
id
+ 1
vi + vd
– - I Db
Linear!
6.002 Fall 2000 Lecture 7 13

CIRCUITS AND
6.002 ELECTRONICS
Dependent Sources
and Amplifiers
6.002 – Fall 2002: Lecture 8 1

Review
Nonlinear circuits — can use the

node method
Small signal trick resulted in linear
response
Today
Dependent sources
Amplifiers
Reading: Chapter 7.1, 7.2
6.002 – Fall 2002: Lecture 8 2

Dependent sources
Seen previously
+ v – v
Resistor i=
i R R
+ v –
Independent
i=I
Current source i I
2-terminal 1-port devices
New type of device: Dependent source

iI i O
+ f ( vI ) +
control output
vI vO port
port
– –
2-port device
E.g., Voltage Controlled Current Source

Current at output port is a function of voltage
at the input port
6.002 – Fall 2002: Lecture 8 3
Dependent Sources: Examples
Example 1: Find V
+
R V
–
independent
current
I = I0
source
V = I0R
6.002 – Fall 2002: Lecture 8 4

Example 2: Find V
voltage +
R V
controled –
current
source K
I = f (V ) =
V
iI iO
K
f (vI ) =
+ vI +
+
R V vI vO
–
– –
6.002 – Fall 2002: Lecture 8 5

Example 2: Find V
voltage
controled
+
current R V
source –
K
I = f (V ) =
V
e.g. K = 10-3 Amp·Volt
R = 1kΩ
K
V = IR = R
V
or V 2 = KR
or V = KR
= 10 −3 ⋅ 10 3
= 1 Volt
6.002 – Fall 2002: Lecture 8 6

Another dependent source example
RL VS +
–
iIN iD
+ +
vI +
–
vIN vO
– –
iD = f (vIN )
e.g.
iD = f (vIN )
K
= (vIN − 1) for vIN ≥ 1
2
2
iD = 0 otherwise
Find vO as a function of vI .
6.002 – Fall 2002: Lecture 8 7

VS
RL
iIN iD
+ +
vI +
–
vIN vO
– –
iD = f (vIN )
e.g. iD = f (vIN )
K
= (vIN − 1) for vIN ≥ 1
2
2
iD = 0 otherwise
6.002 – Fall 2002: Lecture 8 8

VS
RL
vI vO
K
iD = (vIN − 1) for vIN ≥ 1
2
vI +
– 2
iD = 0 otherwise
6.002 – Fall 2002: Lecture 8 9

VS
RL
vI vO
K
2
vI +
– 2
iD = 0 otherwise
KVL
− VS + iD RL + vO = 0
vO = VS − iD RL
K
vO = VS − (vI − 1) RL for vI ≥ 1
2
2
vO = VS for vI < 1
Hold that thought
6.002 – Fall 2002: Lecture 8 10

Next, Amplifiers
6.002 – Fall 2002: Lecture 8 11

Why amplify?
Signal amplification key to both analog
and digital processing.
Analog:
AMP
IN OUT
Input Output
Port Port
Besides the obvious advantages of being
heard farther away, amplification is key
to noise tolerance during communication
6.002 – Fall 2002: Lecture 8 12

Why amplify?
Amplification is key to noise tolerance

during communication
No amplification
10 mV
e
nois
1 mV
useful
signal
huh?
6.002 – Fall 2002: Lecture 8 13

Try amplification
e
nois
AMP
not bad!
6.002 – Fall 2002: Lecture 8 14

Why amplify?
Digital:
Valid region
5V 5V
VIH IN VOH
OUT
VIL
VOL
0V 0V
Digital System
IN OUT
5V 5V
VIH V OH
VIL
V OL
0V t 0V t
6.002 – Fall 2002: Lecture 8 15

Why amplify?
Digital:
Static discipline requires amplification!

Minimum amplification needed:
VIH VOH VOH − VOL

VIL VIH − VIL
VOL
6.002 – Fall 2002: Lecture 8 16

An amplifier is a 3-ported device, actually
Power port
iI iO
Input +v Amplifier + v Output
port – I – O port
We often don’t show the power port.

Also, for convenience we commonly observe
“the common ground discipline.”
In other words, all ports often share a
common reference point called “ground.”
POWER
IN OUT
How do we build one?
6.002 – Fall 2002: Lecture 8 17

Remember?
VS
RL
vI vO
K
2
vI +
– 2
iD = 0 otherwise
KVL
− VS + iD RL + vO = 0
vO = VS − iD RL
K
vO = VS − (vI − 1) RL for vI ≥ 1
2
2
vO = VS for vI < 1
Claim: This is an amplifier
6.002 – Fall 2002: Lecture 8 18

So, where’s the amplification?
Let’s look at the vO versus vI curve.
mA
e.g. VS = 10V , K = 2 2 , RL = 5 kΩ
V
K
vO = VS − RL (vI − 1)
2
2
2
= 10 − ⋅10 −3 ⋅ 5 ⋅ 103 (vI − 1)
2
2
vO = 10 − 5 (vI − 1)
2
vO
VS
∆vO
vI
1 ∆vI
∆vO
>1 amplification
∆v I
6.002 – Fall 2002: Lecture 8 19
Plot vO versus vI
vO = 10 − 5 (vI − 1)
2
vI vO
0.0 10.00
1.0 10.00
1.5 8.75
0.1 change 2.0 5.00 1V change
in vI 2.1 4.00 in vO
2.2 2.80
2.3 1.50
2.4 ~ 0.00 Gain!
Demo Measure vO .
6.002 – Fall 2002: Lecture 8 20

One nit …
vO
What
happens
here?
vI
1
Mathematically,
K
vO = VS − RL (vI − 1)
2
So is mathematically predicted behavior
6.002 – Fall 2002: Lecture 8 21

One nit …
vO K
vO = VS − RL (vI − 1)
2
2
What
happens
here?
vI
1
However, from
K
iD = (vI − 1)2 for vI ≥ 1
2
VS
RL
vO
VCCS iD
For vO>0, VCCS consumes power: vO iD

For vO<0, VCCS must supply power!
6.002 – Fall 2002: Lecture 8 22

If VCCS is a device that can source
power, then the mathematically
predicted behavior will be observed —
vO K
i.e. vO = VS − RL (vI − 1)
2
2
where vO goes -ve
vI
6.002 – Fall 2002: Lecture 8 23

If VCCS is a passive device,
then it cannot source power,
so vO cannot go -ve.
So, something must give!
Turns out, our model breaks down.
Commonly K
iD = (vI − 1)
2
2
will no longer be valid when vO ≤ 0 .
e.g. iD saturates (stops increasing)
and we observe:
vO
vI
1
6.002 – Fall 2002: Lecture 8 24

CIRCUITS AND
6.002 ELECTRONICS
MOSFET Amplifier
Large Signal Analysis

Review
Amp constructed using dependent source
control a DS b output
port a′ b ′ port
Dependent source in a circuit
a + b
+
–
v i = f (v )
a′ – b′
Superposition with dependent sources:

one way tleave all dependent sources in;
solve for one independent source at a
time [section 3.5.1 of the text]
Next, quick review of amp …
Reading: Chapter 7.3–7.7

Amp review
VS
RL
vO
VCCS
K
iD = (vI − 1)
2
vI 2
+
– for vI ≥ 1V
= 0 otherwise
vO = VS − iD RL
K
(vI − 1)2
2

Key device Needed:
v B
A
i = f (v )
voltage controlled
current source
C
Let’s look at our old friend, the MOSFET …

Key device Needed:
Our old friend, the MOSFET …
First, we sort of lied. The on-state behavior of the

MOSFET is quite a bit more complex than either the
ideal switch or the resistor model would have you believe.
D
G
vGS < VT
D S
G
S
vGS ≥ VT
?

Graphically
Demo
iDS v+DS
+
vGS –
–
vDS = vGS − VT
iDS iDS iDS vGS 1
n
vGS ≥ VT egio Saturation
region
de r
vGS ≥ VT vGS 2
T ri o
vGS3
vGS < VT vGS < VT ...

vDS vDS vDS
vGS < VT Cutoff
S MODEL SR MODEL region

Graphically
iDS v+DS
+
vGS –
–
vDS = vGS − VT
iDS iDS iDS vGS 1
n
vGS ≥ VT egio Saturation
region
de r
vGS ≥ VT vGS 2
T ri o
vGS3
vGS < VT vGS < VT ...

vDS vDS vDS
vGS < VT
S MODEL SR MODEL when
vDS ≥ vGS − VT
Notice that
MOSFET
behaves like a
current source
MOSFET SCS Model
When vDS ≥ vGS − VT
the MOSFET is in its saturation region, and the
switch current source (SCS) model of the MOSFET is
more accurate than the S or SR model
D
G
vGS < VT
D S
G D
iDS = f (vGS )
S G K
= (vGS − VT )
2
vGS ≥ VT 2
when
S vDS ≥ vGS − VT

Reconciling the models…
vDS = vGS − VT
iDS iDS iDS vGS 1
n
egio
vGS ≥ VT Saturation
region
de r
vGS ≥ VT vGS 2
T ri o
vGS3
...
vGS < VT vGS < VT
vDS vDS vDS
vGS < VT
S MODEL SR MODEL SCS MODEL
for digital for analog
for fun!
designs designs
When to use each model in 6.002?

Note: alternatively (in more advanced courses)
vDS ≥ vGS − VT use SCS model
vDS < vGS − VT use SR model
or, use SU Model (Section 7.8 of A&L)
Back to Amplifier
VS
vI vO
AMP
VS
RL
vO
G D K
vI iDS = (vI − VT )
2
S 2
in saturation
region
To ensure the MOSFET operates as a VCCS,

we must operate it in its saturation region
only. To do so, we promise to adhere to the
“saturation discipline”
6.002 Fall 2000 Lecture 9 10

MOSFET Amplifier
VS
RL
vO
G D K
vI iDS = (vI − VT )
2
S 2
in saturation
region
To ensure the MOSFET operates as a VCCS,

we must operate it in its saturation region
only. We promise to adhere to the
“saturation discipline.”
In other words, we will operate the amp

circuit such that
vGS ≥ VT and vDS ≥ vGS – VT at all times.

vO ≥ vI – vT
6.002 Fall 2000 Lecture 9 11

Let’s analyze the circuit
First, replace the MOSFET with its
SCS model.
VS
RL
vO
D K
G iDS = (vI − VT )
2
A
+ 2
vGS = vI + vI for vO ≥ vI − VT
–
S
–
6.002 Fall 2000 Lecture 9 12

Let’s analyze the circuit
VS
RL
vO
D K
G iDS = (vI − VT )2 A
+ 2
vGS = vI + vI for vO ≥ vI − VT
– – S
(vO = vDS in our example)

1 Analytical method: vO vs vI
vO = VS − iDS RL B
K
or vO = VS − (vI − VT ) RL for vI ≥ VT
2
2 vO ≥ vI − VT
vO = VS vI < VT
for
(MOSFET turns off)
6.002 Fall 2000 Lecture 9 13

2 Graphical method vO vs vI
K
From A : iDS = (vI − VT ) ,
2
2
vO ≥ vI − VT
for
⇓
2iDS
vO ≥
K
⇓
K 2
iDS ≤ vO
2
VS v0
B : iDS = −
RL RL
6.002 Fall 2000 Lecture 9 14

K K 2
A : iDS = (vI − VT ) , for iDS ≤ vO
2
2 2
VS vO
B : DS
i = −
RL RL
iDS
VS K 2
iDS ≤ vO
RL 2
B Lo A
ad
li n vI
e
= vGS
vO
VS
Constraints A and B must be met
6.002 Fall 2000 Lecture 9 15

iDS
VS K 2
iDS ≤ vO
RL 2
B A
vI
I DS VI
vO
VO VS
Constraints A and B must be met.

Then, given VI, we can find VO, IDS .
6.002 Fall 2000 Lecture 9 16

of Amplifier
(under “saturation discipline”)
1 vO versus vI
2 Valid input operating range and

valid output operating range
6.002 Fall 2000 Lecture 9 17

1 vO versus vI
vO
K
VS − (vI − VT ) RL
2
VS 2
vO = vI − VT
gets into
triode region
vI
VT
6.002 Fall 2000 Lecture 9 18

2 What are valid operating ranges
under the saturation discipline?
Our
vI ≥ VT
K 2
Constraints vO ≥ vI − VT iDS ≤ vO
2
iDS K 2
iDS ≤ vO
2
VS
K
iDS = (vI − VT )
2
RL
2 vI
V v
iDS = S − O
RL RL
vO
VS
? vI = VT
vO = VS and iDS = 0
6.002 Fall 2000 Lecture 9 19
2 What are valid operating ranges
under the saturation discipline?
iDS K 2
iDS ≤ vO
2
K
iDS = (vI − VT )
2
2 vI
VS vO
iDS = −
RL RL
vO
− 1 + 1 + 2 KRLVS
vI = VT +
KRL vI = VT
− 1 + 1 + 2 KRLVS vO = VS and iDS = 0
vO =
KRL
VS vO
iDS = −
RL RL
6.002 Fall 2000 Lecture 9 20
Summary
1 vO versus vI
K
vO = VS − (vI − VT )2 RL
2
2 Valid operating ranges under the

saturation discipline?
Valid input range:
− 1 + 1 + 2 KRLVS
vI : VT to VT +
KRL
corresponding output range:

− 1 + 1 + 2 KRLVS
vO : VS to
KRL
6.002 Fall 2000 Lecture 9 21

Circuits and Electronics

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CIRCUITS AND

Introduction and Lumped Circuit Abstraction

6.002 Fall 2000 Lecture 1 1

Lecturer: Prof. Anant Agarwal

Readings are important!

6.002 Fall 2000 Lecture 1 2

Two homework assignments can

6.002 Fall 2000 Lecture 1 3

What is 6.002 about?

From electrons to digital gates

6.002 Fall 2000 Lecture 1 4

Nature as observed in experiments

I 0.1 0.2 0.3 0.4 …

Physics laws or “abstractions”

Simple amplifier abstraction

Operational Digital abstraction

Analog system Instruction set abstraction

Lumped Circuit Abstraction

The Big Jump

6.002 Fall 2000 Lecture 1 6

We could do it the Hard Way…

Differential form Integral form

6.002 Fall 2000 Lecture 1 7

Instead, there is an Easy Way…

First, let us build some insight:

I ask you: What is the acceleration?

6.002 Fall 2000 Lecture 1 8

Instead, there is an Easy Way…

First, let us build some insight:

In doing so, you ignored

6.002 Fall 2000 Lecture 1 9

The Easy Way…

Consider the filament of the light bulb.

We do not care about

how current flows inside the filament

its temperature, shape, orientation, etc.

Then, we can replace the bulb with a

6.002 Fall 2000 Lecture 1 10

The Easy Way…

Replace the bulb with a

R represents the only property of interest!

6.002 Fall 2000 Lecture 1 11

The Easy Way…

R represents the only property of interest!

R relates element v and i

I= called element v-i relationship

6.002 Fall 2000 Lecture 1 12

R is a lumped element abstraction

6.002 Fall 2000 Lecture 1 13

R is a lumped element abstraction

Not so fast, though …

6.002 Fall 2000 Lecture 1 14

6.002 Fall 2000 Lecture 1 15

I must be defined. True when

6.002 Fall 2000 Lecture 1 16

So let’s assume this too

6.002 Fall 2000 Lecture 1 17

Lumped Matter Discipline (LMD)

Lumped circuit abstraction applies when

6.002 Fall 2000 Lecture 1 18

Demo Lumped element examples

6.002 Fall 2000 Lecture 1 19

Saturation discipline — operate

Response to small signal seems to be