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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 2, FEBRUARY 2014

An Efcient Partial Power Processing DC/DC Converter for Distributed PV Architectures


Mohammed S. Agamy, Senior Member, IEEE, Maja Harfman-Todorovic, Member, IEEE, Ahmed Elasser, Senior Member, IEEE, Song Chi, Member, IEEE, Robert L. Steigerwald, Fellow, IEEE, Juan A. Sabate, Member, IEEE, Adam J. McCann, Li Zhang, and Frank J. Mueller

AbstractIn this paper, a dc/dc power converter for distributed photovoltaic (PV) plant architectures is presented. The proposed converter has the advantages of simplicity, high efciency, and low cost. High efciency is achieved by having a portion of the input PV power directly fed forward to the output without being processed by the converter. The operation of this converter allows for a simplied maximum power point tracker design using fewer measurements. The stability analysis of the distributed PV system comprised of the proposed dc/dc converters conrms the stable operation even with a large number of deployed converters. The experimental results show a composite weighted efciency of 98.22% with very high maximum power point tracking efciency. Index TermsBuckboost converter, distributed photovoltaic (PV) architectures, maximum power point tracking (MPPT), partial power processing.
Fig. 1. PV plant architectures: (a) centralized, (b) multistring distribution, (c) string distribution, and (d) module distribution.

I. INTRODUCTION

HOTOVOLTAIC (PV) power plants with distributed power electronic converters provide several advantages over the standard central inverter systems, including higher energy yield, more exibility in plant design, and improved monitoring and diagnostics capabilities [1][18]. Studies show that the distribution of dc/dc converters along with the maximum power point tracking (MPPT) controllers associated with them, as shown in Fig. 1, provides a signicant increase in the annual energy yield of the system. A tradeoff study including detailed energy yield, reliability, and cost analysis showed that a selection of a stringlevel MPPT architecture [see Fig. 1(c)] is the best approach for large commercial installations and utility scale PV systems (200 kW up to 2 MW) as it provides an annual energy yield gain of 68% [4], which is more than enough to compensate for the cost of the additional power electronics.

Manuscript received September 28, 2012; revised December 13, 2012 and February 11, 2013; accepted March 11, 2013. Date of current version August 20, 2013. This work was supported in part by the U.S. Depart-ment of Energy under Grant DE-EE0000572. Recommended for publication by Associate Editor M. Ponce-Silva. M. S. Agamy is with the School of Engineering, University of British Columbia, Kelowna, BC V1Y 9W9 Canada (e-mail: mohammed. agamy@ubc.ca). M. Harfman-Todorovic, A. Elasser, S. Chi, R. L. Steigerwald, J. A. Sabate, A. J. McCann, L. Zhang, and F. J. Mueller are with the GE Global Research Center, Niskayuna, NY 12309 USA (e-mail: harfmanm@ge.com; ahmed.elasser@ge.com; Chis@ge.com; r.steigerwald@ieee.org; sabate@ge. com; mccanna@ge.com; zhangl@ge.com; mueller@ge.com). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2013.2255315

One of the key factors affecting the distributed PV system design is the proper selection and design of the dc/dc converters used in these architectures. Using converters of smaller power ratings leads to a decrease in conversion efciency as well as an increase in cost per unit power as compared to large centralized converters. This has to be taken into account to ensure that the benets of distributing the dc/dc converters in a PV plant are not offset by the drop in conversion efciency. DC/DC converter efciencies on the order of 98% or higher are needed such that the gains in energy yield obtained by distributing the dc/dc power conversion stage do not get canceled out by the drop in the power converter efciency. These converters replace the input dc/dc stage in two-stage central inverters, whereas in the case of single-stage inverters, their design is signicantly simplied as they can now be designed to operate with a constant input dc voltage rather than a wide input voltage range and the MPPT function is shifted to the dc/dc converters. Even though the added stage adds to the losses, if this added conversion stage is designed with high enough efciency (98% or higher) and with the added energy yield due to the distribution of MPPT, the impact of power converter distribution on efciency is reduced [4], [26]. This slight reduction in efciency is offset by the increase in energy yield in distributed systems, and thus, the overall energy harvested from the solar array is improved compared to central inverter systems. Furthermore, the simplication of the inverter design improves the reliability of the inverter stage. In this paper, a high-efciency partial power buckboost dc/dc converter is presented for use in distributed PV systems based on its performance, reliability, and estimated cost. Based on the comparative system study in [4], power converters at the string or multistring level (1.56 kW rated power)

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Fig. 2.

(a) Full power versus (b) partial power processing structures. Fig. 3. Fraction of total power processed versus voltage gain for a partial power converter.

show the best performance/cost tradeoff point. Therefore, a 3.5-kW partial power processing dc/dc converter design is proposed in this paper. The input to the converter can be either one multicrystalline silicon (mc-Si) string, multiple cadmium telluride (CdTe) or copper indium gallium selenide (CIGS) strings. The converter is composed of two interleaved 1.75 kW channels to reduce input current ripple. Efciency is maximized by using a partial power-processing scheme as well as operating only one of the two interleaved channels at light loads. Furthermore, in very light load conditions the converter is operated in discontinuous conduction mode to reduce device turn on losses. This paper is organized as follows. Section II presents a comparative study of some key candidate topologies for distributed PV architectures. In Section III, the design and operation of the proposed partial power converter are given. Experimental results are presented in Section IV for the proposed converter tested in a laboratory setup as well as an actual eld test of a set of parallel converters connected in a distributed architecture. Further, measurements are also presented to show the stability of the parallel-operated converters feeding a common grid-tied inverter stage. Finally, Section V contains concluding remarks. II. COMPARISON OF CANDIDATE DC/DC CONVERTER TOPOLOGIES One way to improve efciency of the dc/dc converters is by means of using partial power processing, as shown in Fig. 2 [19][26]. In these converters, part of the input power is directly fed forward to the output, thus achieving close to 100% efciency, and the remaining part of the power processed by the dc/dc converter is determined by the voltage regulation requirements, i.e., the percentage of power processed by the converter depends on the voltage difference between the PV side and the dc-link voltage. Fig. 3 shows the relation between the required voltage gain and the percentage of input power being processed by the converter. With a proper design, the power converter can be designed to handle around 3040% of the input power under nominal operating conditions, thus improving its cost, size, and efciency. Therefore, the dc/dc converter block does not need to have excessively high efciency over its operating range to achieve overall high conversion efciency. An example of this is shown in Fig. 4, where a dc/dc converter with an assumed efciency of 95% leads to an overall efciency above 98% for input voltages that are equal to 60% or higher of the output dc-link voltage when used in a partial power conversion mode.

Fig. 4. Example of overall efciency of a partial power conversion topology assuming a 95% dc/dc converter efciency.

Energy yield and cost analysis of utility and large commercial PV power plants led to the conclusion that a string-level dc/dc power converters provide the optimum cost/benet point for plants constructed using high-power low-voltage modules (e.g., mc-Si), whereas for plants made of higher voltage, lower power thin lm modules a string combiner dc/dc converter distribution represents the optimal design point. Therefore, the target is to identify the best converter: its design, operation, and control for the string/multistring inputs mentioned in the previous section. Converter size, cost, and ease of system integration are also key factors in the selection process. For string converters rated at (1.56 kW), the estimated gain in energy yield is in the range of 39% over the standard central inverter system [4]; therefore, a target weighted efciency of 98% is needed in order not to have a signicant negative impact on the annual yield. This weighted efciency is based on the California Energy Commission (CEC) weighted efciency formula for solar inverters CEC = 0.0410% + 0.0520% + 0.1230% + 0.2150% + 0.5375% + 0.05100% . (1)

Key ratings targeted for the converter design are as follows: 1) rated power: 1.56 kW; 2) input dc-voltage range: 200600 V; 3) output dc-voltage: 600 V; 4) efciency: 98% or above; 5) suitable for parallel operation with several other converters to feed a grid tied inverter stage.

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Fig. 5. Three-level boost converter. (a) Circuit topology. (b) Efciency for different input power and input voltages. Fig. 6. Partial power boost converter. (a) Circuit topology. (b) Efciency for different input power and input voltages.

The dc/dc converter topology to be used for such application should provide the voltage step-up capabilities, MPPT, high efciency, high reliability, and design simplicity. Input output isolation is not a necessary feature; however, it facilitates the parallel connection of multiple dcac inverter stages to the same transformer, since nonisolated topologies require the inverters to be isolated in order for them to be operated in parallel, which requires the use of large power line medium voltage transformers. Providing the isolation in the dc/dc converter allows the inverters to be tied to a multiwinding power transformer, which leads to size reduction and cost savings. On the other hand, the addition of the high-frequency isolation transformer complicates the design and adds to the converter cost. In the following sections, some basic converter topologies are assessed for their suitability for application in a distributed PV architecture. A. Transformerless Topologies The boost converter is the simplest solution for this application since it has a low part count and a simple design. However, the boost converter in this operational range has the following disadvantages: a switching voltage in the (8001200 V) range is required, which leads to using a relatively low switching frequency and consequently a large input inductor. Furthermore, the boost converter cannot meet the efciency requirement without adding auxiliary circuits for soft switching. To solve the problem of low-frequency operation, a threelevel boost topology can be used, as shown in Fig. 5(a) [27]. Since the voltage stress on the switches is half the output voltage, high-frequency operation and compact size can be achieved by using MOSFETs of lower voltage rating (400600 V). Efciency can also be improved by operating the inductor in a

critical conduction mode. The efciency curves of such a converter are shown in Fig. 5(b). Another solution is to use a modied boost converter with partial power processing [23], [24] as shown in Fig. 6(a). In this proposed topology, the output voltage is the sum of the PV string voltage and the voltage of the output capacitor. Since this converter does not need to process all the input power, the overall conversion efciency is very high for a very wide range of the converter input power as shown in Fig. 6(b). The converter has a very simple topology but it still needs to use devices of high-voltage rating. B. Topologies With High-Frequency Transformers The full-bridge converter is one of the most used isolated topologies in this power range whether it is a current-fed or voltage-fed converter, as shown in Fig. 7. However, the converter is built of four switches, an isolation transformer, and an output rectier; the added components lead to reduced reliability, lower power density, and higher cost. Furthermore, achieving efciencies higher than 98% at low cost becomes much more challenging for these converters. To improve the efciency, a partial power processing full bridge can be used [28], where only a fraction of the generated power in the PV string ows through the full-bridge converter and the remaining power is directly fed forward to the output of the converter. However, this mode of operation leads to the loss of the benet of the converter being an isolated topology. Resonant converters can also be used for building high-power-density converters since they can operate at high switching frequencies with natural zero-voltage switching. On the other hand, they suffer from low partial load efciency and complex design and

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TABLE I MTBF COMPARISONS FOR TWO CONVERTERS WITH ELECTROLYTIC AND FILM CAPACITORS

C. Reliability Evaluation With the higher number of converters and components in distributed PV plants, the general perception is that the system reliability will be reduced, leading to the requirement of a very high reliability for the distributed dc/dc converters. However, a more practical evaluation metric is system availability. Since in a distributed system there are multiple converters operating in parallel, the failure of one or a few converters will have a low impact on the plant power delivery capability. Therefore, dc/dc converters with similar reliability to a central converter provide high plant availability. The converter reliability is dependent on the number and types of components and their respective stresses, which gives an advantage to single-switch topologies and to partial power converters, where components are exposed to lower overall stress. The use of lm capacitors to replace electrolytics is also a key reliability factor [31][33]. As an example, since the three-level boost converter, in Fig. 5, and the partial power boost converter, in Fig. 6, appeared to best meet the performance/cost requirements for distributed solar applications, these two converters were analyzed in more detail for reliability assessment. Voltage and/or current stresses of the different converter components were evaluated under different power and system voltage conditions in order to estimate the converter reliability using the Telcordia reliability prediction procedure for electronic equipment [34]. Table I shows the mean time between failures (MTBF) for the two converter options with lm and electrolytic capacitors. Two channel-interleaved variants of both converters were analyzed at the rated converter power of 3.5 kW and an input dc voltage of 480 V. For both cases, each 800 V rated lm capacitor was replaced with two electrolytic capacitors rated at 450 V. The voltage stresses were halved for each electrolytic capacitor. The results indicate that reliabilities are signicantly impacted for both topologies. The impact is more severe on the three-level boost topology due to a larger number of capacitors being used. According to the values shown in Table I, high-frequency converter designs provide a signicant benet in terms of enabling the use of more reliable lm capacitors to replace electrolytic capacitors for this case. The reliability assessment of semiconductor devices was made based on the maximum voltage stresses they are required to withstand and the power loss per device. The overall converter reliability for both the partial power converter and the three-level boost converter was found to be in excess of 290 000 h, which exceeds the renewable energy market reliability requirements.

Fig. 7. Full-bridge converter-based topologies: (a) current-fed, (b) voltagefed, and (c) with partial power.

Fig. 8. Resonant converter with partial power. (a) Topology. (b) Efciency curves at different input power and input voltage.

control [29], [30]. The efciency can be improved with connections similar to the full bridge with partial power processing as shown in Fig. 8; however, the resulting converter still remains complex and expensive in terms of topology design and control implementation.

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TABLE II COMPARISON BETWEEN KEY TOPOLOGIES UNDER STUDY

D. Comparison of Topologies The major considerations when designing a solar power converter are efciency, design complexity, reliability, power density, and cost. The number of switching devices is a key factor affecting efciency, reliability, and cost; therefore, it is essential to minimize the number of switches, which gives an advantage to single-switch topologies. Replacing electrolytic capacitors with lm or ceramic capacitors provides clear reliability gains, but for this to be practical, the switching frequency has to be increased, which impacts efciency. Since efciency has a direct impact on energy yield, there is a tradeoff between achieving soft switching in fast switching converters and the complexity of the converter and/or controller design. This leads to the preference of methods such as discontinuous conduction mode or critical conduction mode operation, or using new emerging wide band gap devices with better switching characteristics, to reduce switching losses and improve efciency compared to adding auxiliary circuits or using complex resonant converter control methods. The challenges with new devices are their cost and unproven reliability, but initial designs and tests show them as promising solutions [35]. Table II shows a comparison of the different converter topologies with respect to the key factors inuencing the dc/dc converter selection for distributed PV architectures. Based on this comparison, it follows that simple single-switch topologies with partial power processing, such as the proposed partial power boost topology, to improve efciency are the strongest candidates for this type of application. Threelevel boost converters also present a good solution; however, the need for twice the number of semiconductor devices and passive components leads to higher cost and lower reliability. The use of interleaved congurations of partial power boost converters and three-level boost converters helps improve system performance; however, the implementation of the interleaved topologies is much simpler from both control and topology aspects in the case of the proposed, new, partial power boost converter. III. PROPOSED CONVERTER OPERATION AND DESIGN Based on the comparison in Section II, the dc/dc converter chosen for the distributed PV system is the partial power processing boost converter as shown in Fig. 9(a), or a multichannel

Fig. 9. Partial power boost dc/dc converter with a Si IGBT and a SiC Schottky diode. One channel is rated at 1.75 kW. Input Voltage: 200 to 600 V, Output Voltage: 600 V regulated. (a) one channel; (b) two channels.

interleaved converter structure as shown in Fig. 9(b). In this topology, the output voltage is the sum of the PV string voltage and the voltage of the output capacitor. Since this converter does not need to process all the input power, the overall conversion efciency is very high. The converter has a very simple topology composed of only one switching device and one diode per channel. The switches and diodes have to withstand the total output voltage. Classical partial power processing converters include a high-frequency transformer in their design. The proposed topology does not require a high-frequency transformer, which simplies the design and reduces the required converter cost. The voltage gain of the regulated voltage Vs under medium to heavy loading conditions [in a continuous inductor current conduction mode (CCM)] is given in (2), which is the conversion ratio of a noninverting buckboost converter Vs = d Vin . 1d (2)

In a discontinuous inductor current conduction mode (DCM), the capacitor voltage is given by Vs = 1 2 1+ 2dRload 1 Vin Lin fsw (3)

where d is the duty ratio, fsw is the switching frequency, Lin is the input inductance, and Rload is the equivalent load resistance. And the fraction of input power processed by the converter is

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Fig. 10. Percentage of input power processed by the converter versus input voltage with a 600-V output voltage. Fig. 12. Critical inductor value versus duty ratio and fraction of rated power at 30-kHz switching frequency.

Stage 2 (dTs < t < T2 ): The IGBT is turned OFF and the inductor current is diverted to the diode (D) where the energy is discharged into the capacitor Cs . For a continuous conduction mode T2 = Ts , and the cycle ends at this stage Lin diL in = Vs dt dVs Vs + Vin = iL in Cs . dt Rload (7) (8)

Stage 3 (T2 < t < Ts ): This stage occurs in the case of DCM. In this mode, power is transferred from the input and output capacitors to the output Lin
Fig. 11. (a) Stages of operation of the partial power processing dc/dc converter and (b) the corresponding timing diagram.

diL in =0 dt Vs + Vin dVs Cs = . dt Rload

(9) (10)

given by Fraction of Power Processed =


Vs Vin Vs Vin

(4)

+1

The target converter design for this application is an input voltage range of (200600 V) with an output dc-link voltage of 600 V. For this range of operation, Fig. 10 shows the percentage of input power to be processed by the converter over the entire input voltage range, with a 600 V output. The operation of the converter is similar to that of a simple boost circuit. The stages of operation over a switching period Ts are shown in Fig. 11 and can be summarized as follows. Stage 1 (0 < t < dTs ): In this stage, insulated gate bipolar transistor (IGBT) (S) is turned ON and the inductor current builds up Lin diL in = Vin dt Vs + Vin dVs = Cs . dt Rload (5) (6)

It is also worth noting that during this mode of operation, resonances can occur between the input inductor and device capacitance. The DCM operation leads to zero-current turn-on of the IGBT, thus reducing the turn-on losses at light load. Under light-load conditions, the converter is designed to transition to a critical conduction mode and then DCM to reduce power losses at turn-on. The input inductor value can be chosen as a function of converter power and operational duty ratio as shown in Fig. 12. Fig. 13 shows the loss breakdown of the dc/dc converter under rated design conditions (3.5 kW, 400 V input), indicating the dominance of the IGBT switching losses over all the other loss components. Therefore, a switching frequency of 30 kHz was chosen in order to meet the required efciency target. Based on this chosen switching frequency, and in order to reduce turn-on losses at light load, the input inductor is designed to transition to a critical conduction mode when the input power drops below 40% of the rated power of any converter channel. Diode losses are primarily conduction losses since SiC Schottky diodes are used to eliminate reverse recovery losses. IGBTs with voltage rating of 1200 V were chosen for this application in order to build converters suitable for operation with a dc-link voltage up to 750 V. In lower voltage applications,

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Fig. 14. Simplied block diagram of the controller including the MPPT control block.

Fig. 13. Converter loss breakdown as a percentage of the total losses at nominal operating conditions.

the IGBTs can be replaced by MOSFETs, while in this voltage range only SiC MOSFETs can be used and since they represent an emerging technology, they still do not meet cost targets for PV applications. However, preliminary studies of these devices show that they can signicantly improve the power density of the propose converters while maintaining the same superior performance [35]. Since the dc-link voltage is held constant by the dc-link capacitors of the inverter, the converter capacitors Cin and Cs are designed to lter out the high-frequency ripple generated at the switching frequency or twice the switching frequency depending on the number of operational channels. This eliminates the need for electrolytic capacitors, which can now be replaced by small-size, high-reliability thin-lm capacitors. A 3.5-kW two-channel interleaved converter is shown in Fig. 9(b). When the input PV power is less than 50% of the rating, the switching is stopped in one of the channels, thus eliminating all the associated switching losses and improving light-load efciency. Operation can be alternated between the two channels in order to improve the reliability of the converter. Converter control is based on having an output constant dc voltage. The dc-link voltage is controlled by the dcac inverter modulation. The duty cycle (d) is calculated to adjust the PV string voltage Vin such that the maximum power of the PV string/array can be tracked. In this case, Vs is determined in order to compensate the difference between the PV voltage Vin and the output dc-link voltage. The input voltage command Vin Cm d is calculated by the MPPT controller. A perturb and observe MPPT algorithm is used for locating local maximum power points. This algorithm is associated with a global PV voltage sweep in order to locate the global maximum power point [34][38]. The voltage sweep is performed periodically whenever a substantial change in the PV array output power is observed. A owchart showing the implemented MPPT algorithm is shown in the Appendix. With a constant output dc-link voltage Vout , the MPPT control can be simplied to maximize the output current Iout through perturbing the input PV voltage Vin . There is no power calculation required in this algorithm, thus reducing computation complexity and time. Fig. 14 shows a simplied block diagram of the converter controller. Since the system under study involved a large number of inverters running in parallel feeding a common dc link, the overall system

Fig. 15. Frequency response of the closed loop system with multiple parallel operating converters with (a) input voltage V in = 500 V and (b) input voltage V in = 200 V.

stability should be evaluated. Based on (5)(10) and with the representation of the inverter side by its input capacitance, the output to control transfer function is derived to be G= where z = Vin (1 + s/z ) (1 d)(1 + Q n s o n + , on =
s2 2 o n

(11)

dV i 2 n L i n (1 d ) 2 R l o a d

(1 d ) Lin Cn

d ) R l o a d , Qn = (1 , C n /L i n

Cn = Cdc + nCs , Cdc represents the inverter input capacitance, and n is the number of parallel-operating converters. The system closed-loop frequency response at different input voltage levels and different number of parallel converters is shown in Fig. 15, indicating the overall system stability. The system stability is veried experimentally including the frequency response of the inverter in the following section. In addition to the MPPT control, the converter can also be used for monitoring and diagnostics of the PV strings and the dc-network in the plant, fault detection, as well as clamping the PV string voltage. IV. EXPERIMENTAL RESULTS A 3.5-kW, 30-kHz, two-channel dc/dc converter prototype as shown in Fig. 16 was built and tested. Converter component values are listed in Table III. The converter power density is 19.5 W/in3 . SiC Schottky diodes are used for D1 and D2 in order to avoid reverse recovery losses at high frequency. The input PV voltage ranges from 200 to 600 V, while the output

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Fig. 16.

Prototype of the 3.5 kW (two channels).

Fig. 18. Efciency improvement due to coordinated switching of the two channels. (Solid lines two channels switching, Dotted lines: one channel switched OFF at light load.)

TABLE III CONVERTER COMPONENTS

Fig. 19.

Block diagram of converter test setup.

Fig. 17. Measured efciency for different input power, input voltages, and converter congurations.

voltage is xed at 600 V, which is regulated by the grid-tied dcac inverter stage. Converter efciency evaluation was performed using a variable-input dc voltage (200480 V) and an electronic load operating in a xed voltage mode with a set point of 600 V. Efciency measurements were performed across the full-load range (10100%) in order to generate the weighted efciency number for solar converters as given in (1). As seen in Fig. 17,

the weighted efciency of each individual channel exceeds 98% with a peak efciency reaching 98.9%. The number of channels operated is decided by the input power; therefore, for power levels less than 50% of the converter rating only one channel is switched. This improves the efciency prole, giving a weighted efciency of 98.22%, as shown in Fig. 18. The converter was then tested with a PV emulator input and its output connected to the DC link of a grid tied inverter as shown in Fig. 19. Interleaved inductor currents and the resulting low ripple input current are shown in Fig. 20(a). CCM operation at high input power and DCM operation at low input power are shown in Fig. 20(b) and Fig. 20(c), respectively. Global MPPT sweep is performed, as shown in Fig. 21 to locate the absolute maximum output power by sweeping the PV voltage from its open-circuit value, to a set minimum value (200 V in this test). Since the output voltage is constant, the output current prole during the sweep matches the PV (power voltage prole). Finally, the MPPT performance was studied by using the PV emulator to apply a transient irradiance prole, as shown in Fig. 22(a) to the PV string characteristic. Fig. 22(b) shows the power extracted from the PV string and the tracking efciency of the MPPT controller. At low power levels, only one channel is switched and as the input PV power increases both channels are operated. With a constant output voltage, a low-power condition is indicated by the drop of the output current below a predened threshold (ideally 50% of the rated output current). The MPPT efciency achieved is above 99.78% under the static condition and during fast transients it remains above 96%, which guarantees high PV energy extraction.

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Fig. 20. Converter waveforms for different conditions: (a) interleaved inductor currents (yellow & green, LEM output 1 V/div1.6 A/div), total input current (magenta, 2 A/div), and gate of S1 (blue, 5 V/div), at input of 2 kW; (b) IGBT voltage (yellow, 200 V/div), diode voltage (magenta, 200 V/div), and inductor current (green, 3 A/div) of one channel, at total input of 1.75 kW and gate of S1 (blue, 10 V/div); and (c) IGBT voltage (yellow, 200 V/div), diode voltage (magenta, 200 V/div), and inductor current (green, 2A/div) and gate of S1 (blue, 10V/div) of one channel, at total input of 700 W.

Fig. 22. (a) Irradiance prole (200 W/m2 /div) and (b) Extracted PV power (blue, 200 W/div) and MPPT efciency (red, %).

Fig. 21. Converter waveforms during a global MPPT sweep: Ch1 (yellow): PV input voltage (100 V/div), Ch2 (blue): Output voltage (100 V/div), Ch3 (magenta): Converter output current (1 A/div), Ch4 (green): Input PV current (1 A/div).

Distributed PV power plants consist of a large number of dc/dc converters connected in parallel to the central dc/ac inverter as shown in Fig. 23. Usually, dc/dc converters are designed for predened stand-alone input and load conditions, e.g., for an ideal input voltage source and a resistive load. However, the predened conditions are hardly met in this system. Therefore, the dynamic performance of the dc/dc converter within the system can be very different from that in the stand-alone operation. Specically, each individual converter may have well designed control loops in a stand-alone operation, but exhibit deteriorated performance within a system. Generally, converter input and output impedances are used for the verication of the power system stability and dynamic performance [39][42]. Fig. 24 shows the schematic of the experimental setup used to verify the system stability. The dc/dc converters under test were connected to a single-phase dc/ac inverter. In order to ensure the small signal stability of the interconnected system, formed by integrating subsystems that are individually stable, the minor loop gain TM = Zo /Zin must be checked for stability [43], [44].

Fig. 23.

Parallel boards connected to a three-phase inverter in a large PV plant.

To determine the system stability, the construction of TM from measured impedances Zo and Zin at the interface between the dc/dc converter and the dc/ac inverter is shown in Fig. 25. The blue trace in Fig. 25(a) represents the measured loop gain of the simple system shown in Fig. 24(a) with one dc/dc converter connected to the inverter and the red trace represents the measured loop gain with three dc/dc converters, the outputs of which are connected in parallel to the dc link of the inverter

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Fig. 24. Interconnection system under test formed by integrating two subsystems: (a) one converter connected to one single-phase inverter and (b) three parallel converters connected to one single-phase inverter.

Fig. 25. Measured loop gain magnitude and phase in case of one dc/dc converter connected to one dc/ac inverter (blue) and three parallel converters connected to the same inverter (red).

for the 10.5 kW system under test. To determine if the system is stable, the phase margin test is used [45]. From Fig. 25, it can be seen that the phase margin for the case of one dc/dc converter (blue trace) is measured to be 61 at 25.1 kHz and 84 at 42.1 kHz, while for the case of three parallel dc/dc converters (red) trace the phase margin is 62 at 18 kHz and 100 at 50 kHz. This method can be expanded to systems with a much larger number of parallel-connected converters feeding a high-power dc/ac inverter stage to determine the overall system stability. Stability of the power system was also tested in the time domain by applying global MPPT sweeps, as shown in Figs. 26 and 27. In this case, three dc/dc converters were connected in parallel to the dc/ac inverter. The input of each converter is connected to three parallel PV strings, each consisting of four series modules. The measured transient waveforms of the dclink voltage, input currents of the three dc/dc converters are shown in Fig. 26. In Fig. 27, the dc-link voltage and the three output currents from each converter are shown during a similar global MPPT sweep. The measurements in Figs. 26 and 27 conrm the stability of the parallel-connected set of converters even under dynamically varying conditions. Further, the two gures show another benet of distributed dc converter architectures for solar applications since each of the converters can be properly timed to locate the maximum power point of the string or array it is connected to without causing a signicant dip in the overall system power as would be the

Fig. 26. Input current of three parallel converters connected to a PV array and feeding an inverter during shifted global MPPT sweeps. Ch 1 (yellow): dc-link voltage (100 V/div), Ch 2 (blue): input current of dcdc converter 1 (1 A/div), Ch 3 (magenta): input current of dcdc converter 2 (1 A/div), Ch 4 (green): input current of dcdc converter 3 (1 A/div).

Fig. 27. Output current of three parallel converters connected to a PV array and feeding an inverter during shifted global MPPT sweeps. Ch1 (yellow): dc-link voltage (100 V/div), Ch2 (blue): input current of dcdc converter 1 (1 A/div), Ch 3 (magenta): input current of dcdc converter 2 (1 A/div), Ch 4 (green): input current of dcdc converter 3 (1 A/div).

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case if a central inverter were to perform a global maximum power point sweep. The output current waveform during the voltage sweep, in Fig. 27, takes the typical form of a PV power curve verifying the simplied MPPT control described earlier that uses only the output current, rather than calculating power in each computation cycle. V. CONCLUSION A simple high-efciency dc/dc converter suitable for medium- to large-scale distributed PV applications is proposed. High efciency is achieved by means of partial power processing as well as by coordinating the operation of the interleaved channels of the converter. The output of the converter being a xed dc bus also simplies the MPPT implementation. Furthermore, feedback signals can be used as monitoring and diagnostics tools for assessing the condition of the PV plant. The proposed converter was fully tested for performance parameters including the efciency, switching operation, MPPT performance, and parallel operation under static and dynamic conditions. Experimental results show excellent performance and fulllment of the design objectives. A set of three parallel converters was also tested in a solar eld and showed uninterrupted performance over a long period of time under varying environmental and weather conditions. APPENDIX Flowchart of the MPPT algorithm.

any legal liability or responsibility for the accuracy, completeness, or usefulness of any information, apparatus, product, or process disclosed, or represents that its use would not infringe privately owned rights. References herein to any specic commercial product, process, or service by trade name, trademark, manufacturer or otherwise does not necessarily constitute or imply its endorsement, recommendation, or favoring by the U.S. Government or any agency thereof. The views and opinions of authors expressed herein do not necessarily state or reect those of the U.S. government or any agency thereof. REFERENCES
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ACKNOWLEDGMENT Disclaimer: This report was prepared as an account of work sponsored by an agency of the U.S. Government. Neither the U.S. Government nor any agency thereof, nor any of their employees, makes any warranty, express or implied, or assumes

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Mohammed S. Agamy (S01M08SM11) received the B.Sc. (Hons.) and M.Sc. degrees from Alexandria University, Alexandria, Egypt, in 2000 and 2003, respectively, and the Ph.D. degree from Queens University, Kingston, ON, Canada, in 2008, all in electrical engineering. He is currently an Assistant Professor at the School of Engineering, University of British Columbia, Kelowna, BC, Canada. From 2008 to July 2012, he was a Lead Power Electronics Engineer at the General Electric Global Research Center, Niskayuna, NY, USA, where his research was focused on power supply technologies for renewable energy sources and medical equipment. From May 2003 to October 2008, he was with the Energy and Power Electronics Applied Research Laboratory, Queens University as a Research Assistant and then a Postdoctoral Fellow. From September 2000 to April 2003, he was an Assistant Lecturer at Alexandria University. He holds two U.S. patents with six others pending and has more than 35 published technical papers in refereed journals and conferences. His research interests include resonant converters, power factor correction, softswitching techniques, and modeling and control of power converters and electric machines. Dr. Agamy serves as a Reviewer for the IEEE TRANSACTIONS ON POWER ELECTRONICS, the IEEE TRANSACTIONS ON EDUCATION, the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, IEEE JOURNAL OF PHOTOVOLTAICS, International Journal of Electronics, and several IEEE conferences.

Maja Harfman-Todorovic (S02M08) received the Dipl.Ing. degree from the Faculty of Electrical Engineering, University of Belgrade, Belgrade, Serbia, in 2001, and the M.S. and Ph.D. degrees from Texas A&M University, College Station, TX, USA, in 2004 and 2008, respectively. Since March 2008, she has been a Lead Engineer in the Utility Power Electronics Laboratory, General Electric Research Center, Niskayuna, NY, USA. She holds one U.S. patent with eight others pending and has more than 30 published technical papers in refereed journals and conferences. Her research interests include converters for PV applications, subsea oil and gas applications, switching-mode power supply design, uninterruptible power systems, energy storage devices, and digital control of power converters. Dr. Harfman-Todorovic serves as a Reviewer for the IEEE TRANSACTIONS ON POWER ELECTRONICS, the IEEE TRANSACTIONS ON EDUCATION, the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, and several IEEE conferences.

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Ahmed Elasser (S92M96SM12) was born in Demnate, Morocco, in 1963. He received the Ingenieur DEtat diploma in electric power engineering from the Mohammadia School of Engineering, Rabat, Morocco, in 1985, and the M.S. and Ph.D. degrees in electric power engineering and power electronics from Rensselaer Polytechnic Institute, Troy, NY, USA, in 1993 and 1996, respectively. He worked as an Electrical Maintenance Engineer and then as a Laboratory Engineer from 1986 to 1992, in Morocco. In 1996, he joined the General Electric (GE) Global Research Center (GRC), Niskayuna, NY, as a Senior Professional. His previous research interests include the study, modeling, and application of power semiconductor devices, systems modeling and simulation, silicon carbide devices, six-sigma quality, and e-engineering. From 2002 to 2007, he led the new ideas and innovation within the GRC Micro and Nano Structures Technology (MNST) organization and he was heading the MNST Disruptive Technology Council. He worked across GRC with various technology councils to create a culture of innovation and growth. His current research interests include silicon carbide power devices fabrication, design, modeling, testing, characterization, and applications; he has also been working on photovoltaic systems, focusing on plant architectures, distributed MPPT, and balance of systems work. He has presented at many IEEE conferences on power electronics, power semiconductor devices, and PV systems. He has authored or coauthored more than 25 papers, holds 13 patents, and has several patents pending. Dr. Elasser is a Regular Reviewer for various IEEE publications and conferences and has recently served as a Topic Chair for the ECCE 2011 sustainable energy track as well as a Session Chair. He received the GE Dushman Team Award, in 1996 and a GE Whitney team award, in 2012, he also earned numerous awards from the GE Research Center for his technical and organizational contributions. GE Industrial Systems also recognized him for his numerous contributions to circuit breaker modeling and design.

Juan A. Sabate (M94) received the M.S. and Ph.D. degrees in electrical engineering from Virginia Tech, Blacksburg, VA, USA, in 1988 and 1994, respectively. Since 2000, he has been a Power Electronic Researcher in GE Global Research Center, Niskayuna, NY, USA. He has led multidisciplinary teams of scientists and engineers to develop power supplies and high-power switching ampliers for GE energy and medical applications. From 1997 to 2000, he was with Philips Electronics Research in Briarcliff Manor, New York, where he conducted research and advanced development of high power density power supplies for commercial applications, and ballasts for uorescent and HID lamps. From 1994 to 1997, he was with Hewlett-Packard in their R&D center in Barcelona, Spain, where he designed high power density dcdc converters and special purpose sensors. In addition, from 1994 to 1997, he was a Lecturer and Adjunct Professor in the Ramon Llull University, Barcelona, where he was responsible for the Power Electronics Curriculum. His research interests include high-performance power conversion, distributed power generation, lighting electronics, and modeling and control of PWM converters. He has published more than 50 journal and conference papers, and holds 14 U.S. patents.

Song Chi (S04M07) received the B.S. degree from Northeastern University, Shenyang, China, in 1993, the M.S. degree from Tsinghua University, Beijing, China, in 2000, and the Ph.D. degree from The Ohio State University, Columbus, OH, USA, in 2007, all in electrical engineering. He is currently with the GE Global Research Center, Niskayuna, NY, USA. Prior to joining GE, he was a Senior Engineer with the Research and Engineering Center of Whirlpool. He has authored or coauthored 15 technical papers in IEEE conferences and journals. He has two patents pending. His research interests include sensorless control of ac drives, ux-weakening control of Surface mounted permanent magnet/interior permanent magnet machines, controls of power conversion systems such as distributed solar systems and high-delity gradient ampliers of magnetic resonance imager.

Adam J. McCann was born in Salt Lake City, UT, USA, in 1987. He received the B.S. and M.Eng. degrees from Cornell University, Ithaca, NY, USA, in applied engineering physics and electrical and computer engineering, in 2010 and 2011, respectively. He joined General Electric Global Research Center (GRC) in Niskayuna, NY, USA, as part of the Edison Engineering Development program, in 2011. While at GRC, he has coauthored papers in signal processing and remote monitoring applications along with patents pending in the area of OCR and pattern recognition. His current research interests include embedded device architectures and communication platforms in the Internet of Things.

Robert L. Steigerwald (S66M79SM85F94) received the B.S.E.E. degree from Clarkson College, Omaha, NE, USA, in 1967, and the M.E.E. and Ph.D. degrees from Rensselaer Polytechnic Institute, Troy, NY, USA, in 1968 and 1978, respectively. He joined GE Global Research, in 1968, where he did research and development in many areas of Power Electronics until his retirement in 2005. He formed his consulting company (Adirondack Power Processing, LLC), in 2006. His inventions and designs have been applied to variable speed DC and AC motor drives, induction heating, high-frequency lamp ballasts, uninterruptable power supplies, utility interactive photovoltaics, satellite power supplies, radar and sonar power supplies, CT X-ray generators, and MRI gradient ampliers. These applications employ both low- and high-voltage power supplies including high power factor converters and resonant, soft-switched converters. He has received 120 patents and published more than 50 technical papers. Dr. Steigerwald received the William E. Newell Outstanding Achievement Award by the Power Electronics Society in 1993, and the IEEE 3rd Millennium medal in 2000 for outstanding achievements. He is currently on the Scientic Advisory Board of the Center for Power Electronic Systems at Virginia Tech, Blacksburg, USA.

Li Zhang received the Ph.D. degree from the University of Massachusetts Amherst, Amherst, MA, USA, in 2004, and the M.S. degree from the University of Electronic Science and Technology of China, Chengdu, China, in 2000. He is currently a Lead Scientist in the Distributed Intelligent Systems Lab at GE Global Research Center, Niskayuna, NY, USA. He has over 15 years experience in the elds of Internet of Things, electromechanical systems design, smart sensing systems, automatic identication, wireless networking, remote monitoring, and diagnostics. He is an industrys expert in the design of Cyber Physical Systems and is actively leading GEs research efforts in designing hardware, software, algorithms, networks and web-based interaction systems for digitizing millions of assets and objects found in aviation systems, power systems, healthcare, pharmaceutics, etc.

Frank J. Mueller attended Rensselaer Polytechnic Institute (RPI), Troy, NY, in 1977, pursuing a major in physics. In 1979, he enlisted in the U.S. Air Force where he completed a Navy ET-A school at Great Lakes Naval Base and then specialized in Meteorological Equipment training at Chanute Air Force Base (AFB), IL, USA (he graduated at the top of his class). Afterward, he went to Blytheville Air Force Base, Blytheville, AR, USA, where he maintained the weather radar and other meteorological equipment for the base. In 1983, he joined the microprocessor laboratory at RPI assisting in lab preparations and later also supported a Power Electronics Lab which included laying out gate drive circuits. In 1996, he joined General Electric, Niskayuna, NY, USA, and has been active in Power Electronics testing and layout. He has experience in optics, ultrahigh vacuum systems, and high-voltage work up to 160 kV and has been leading his organizations safety program since 1999. He holds two U.S. patents and has two pending.

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