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N.P.R. POLYTECHNIC COLLEGE NATHAM 624 401.


ISO 9001:2008

Reach the Stars

E LEARNING MATERIAL

SUB CODE: 14062 EMBEDDED SYSTEM

ELECTRONICS & COMMUNICATION ENGINEEIRNG (VI - SEMESTER)


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SYLLABUS EMBEDDED SYSTEM SUB CODE : 14062

UNIT

TOPIC

Introduction to embedded System and LPC 2148 ARM I Controller

II

Embedded C Basic, GPIO (Slow), Timer and Interrupt

III

PWM, ADC, DAC and RTC

IV

I2C, I2C Feature, UART

RTOS and C/OS II

Unit 1: Introduction to Embedded System and LPC 2148 ARM Controller: Definition of Embedded System - Features of Embedded System Types

of Embedded System - List of Embedded System Devices - LPC 2148 ARM Controller - Block Diagram - Memory and on chip peripheral

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devices - ARM 7TDMI-S - Debug and Emulation Trace Facility - Memory Map - Memory remap and Boot Block - CPU Registers - Modes of

Operation - PSW Instruction Set - Assembly Language Program for Addition, Subtraction, Multiplication and Division. Unit 2: Embedded C Basics, GPIO(Slow) Timer Interrupt: Embedded C Basics - GPIO (Slow) Register Map - Pin Connect Block - 8 bit LEDs - 8 bit Switches - Buzzer - Relay -Stepper Motor Interfaces Embedded C Programs for the above - Timer/Counter - Block Diagram Register Map -Program for Time Delay and Counter Operation - Vector Interrupt Controller (VIC) Register Map -External Interrupts -

Timer/Counter based Interrupt - Programs for the above. Unit 3: PWM, ADC, DAC and RTC: PWM Features - Block Diagram - Register Map - Program for Generating single ended PWM - ADC Feature - Block Diagram - Register Map Program for ADC and Temperature sensor LM 35 interface -

DAC Feature Block Diagram - Register Map - Program for Generating analog output - RTC Feature - Block Diagram - Register Map Program For Display the time in LCD display. Unit 4: I2C, I2C Feature, UART: Introduction to I2C Start, Stop, ACK, Restart, NACK signals Data transfer from Master to Slave and Slave to Master - I2C feature in LPC 2148 Block diagram Register map I2C Master mode operation Interfacing I2C based I/O expander PCF8574 Interfacing LED 7 segment display Interfacing I2C based EEPROM

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Program for the above - UART feature UART0 Block diagram Register map Transmission and reception of messages for PC Unit 5: RTOS and C/OS II: Foreground/Background systems

Function of OS Introduction to RTOS - Resources Shared resources Critical Section Multitasking Tasks Kernal Scheduler Round robbin Non Pre-emptive and Pre-emptive scheduling - Context switch EventFlag Mutual exclusion Semophore Message Mail Boxes Clock ticks TaskStates Task Stacks Task Control Blocks (TCB) Introduction to C OS II Porting ofCOS II to Micro controller RTOS functions OS_STK OS_EVENT OSInit() OSStart() OSTaskCreate() OSTaskDel() OSSemCreate() OSSemPend() OSSemPost() TaskStk[] [] OSTimeDly() - Application programs using the above functions Reference Books: 1.LPC 2148 User Manual 2. MicroC/OS - II The Real Time Kernel - Jean J.Labrosse

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UNIT I (ITRODUCTION CONTROLLER) Definition of embedded system: An embedded system is a computer system designed to perform one or a few dedicated functions in real time and control a complete device . It is a system dedicated for an application(s) or is a specific part of an application or product or a part of a larger system. Typically an embedded system consists of a TO EMBEDDED SYSTEM & LPC2148 ARM

microcomputer with software in ROM / FLASH memory, which starts running a dedicated application as soon as power is turned on and does not stop until power is turned off. The program run by the processor is not generally reprogrammable by the end user. A general-purpose definition of embedded systems is that they are devices used to control, monitor or assist the operation of equipment, machinery or plant. "Embedded" reflects the fact that they are an integral part of the system that includes hardware and mechanical parts. Characteristics of Embedded system: An Embedded system is characterized by the following: 1. Dedicated functions or tasks or application. 2. Real time response. 3. generally not reprogrammable by the end user. 4. part of the system that includes hardware and mechanical parts. Features of Embedded Systems

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Embedded systems example the versatility of the embedded computer system lends itself to utility in all kinds of enterprises, from the simplification of deliverable products to a reduction in costs in their development and manufacture. Embedded Systems are the crucial components of the modern

compacted devices with multifunction capabilities. Embedded systems are specific computer programs that combine the functions of specially designed softwares and hardwares and are completely encapsulated by the devices that they control. An embedded system has specific requirements and performs predefined tasks, unlike a general-purpose personal computer. An embedded system is a programmed hardware device. A programmable hardware chip is the platform and it is programmed with particular applications. Embedded systems are a combination of hardware and software which facilitates mass production and a host of applications. Features of Embedded Operating System 1-Embedded systems are designed to do some specific task, rather than be a general-purpose computer for multiple tasks. Some also have realtime performance constraints that must be met, for reasons such as safety and usability; others may have low or no performance

requirements, allowing the system hardware to be simplified to reduce costs. 2-Embedded systems are not always standalone devices. Many embedded systems consist of small, computerized parts within a larger device that serves a more general purpose. For example, the Gibson Robot Guitar features an embedded system for tuning the strings, but the overall purpose of the Robot Guitar is, of course, to play music similarly, an

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embedded system in an automobile provides a specific function as a subsystem of the car itself. 3-The program instructions written for embedded systems are referred to as firmware, and are stored in read-only memory or Flash memory chips. They run with limited computer hardware resources: little memory, small or non-existent keyboard and/or screen. * Size & Weight : Microcontrollers are designed to deliver maximum

performance for minimum size and weight. A centralised on-board computer system would greatly outweigh a collection of microcontrollers. * Efficiency : Microcontrollers are designed to perform repeated

functions for long periods of time without failing or requiring service. Other computer systems are prone to software and hardware failure as well as a whole host of other problems recognisable to the users of any home computer. Above all other considerations, computer systems must be 100% reliable when trusted to control such functions as braking in an automobile. Types of Embedded System:

Small Scale Embedded system Medium Scale Embedded system. Large Scale Embedded System.

List of embedded system devices: 1.Mobile phone 4.Avionovcs 7.Ipod 10.DVD player 2.Mobile computer 5.Washing machine 8.MP 3 Player 11.Tv remote 3.Automatic car 6.Microwave oven 9.Xerox machine 12.TV set top box

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13.Sewing Machine 14.Millatry application 15.Internet real Time application.

LPC 2148 Features: 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. 8 to 40 kB of on-chip static RAM and 32 to 512 kB of on-chip flash program memory. 128 bit wide interface/accelerator enables high speed 60 MHz operation. In-System/In-Application Programming (ISP/IAP) via on-chip bootloader software. Single flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 ms. EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the on-chip RealMonitor software and high speed tracing of instruction execution. USB 2.0 Full Speed compliant Device Controller with 2 kB of endpoint RAM. In addition, the LPC2146/8 provide 8 kB of on-chip RAM accessible to USB by DMA. One or two (LPC2141/2 vs. LPC2144/6/8) 10-bit A/D converters provide a total of 6/14 analog inputs, with conversion times as low as 2.44 s per channel. Single 10-bit D/A converter provides variable analog output.

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Two 32-bit timers/external event counters (with four capture and four compare channels each), PWM unit (six outputs) and watchdog. Low power real-time clock with independent power and dedicated 32 kHz clock input. Multiple serial interfaces including two UARTs (16C550), two Fast I2Cbus (400 kbit/s), SPI and SSP with buffering and variable data length capabilities. Vectored interrupt controller with configurable priorities and vector addresses. Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package. Up to nine edge or level sensitive external interrupt pins available. 60 MHz maximum CPU clock available from programmable on-chip PLL with settling time of 100 s. On-chip integrated oscillator operates with an external crystal in range from 1 MHz to 30 MHz and with an external oscillator up to 50 MHz. Power saving modes include Idle and Power-down. Individual enable/disable of peripheral functions as well as peripheral clock scaling for additional power optimization. Processor wake-up from Power-down mode via external interrupt, USB, Brown-Out Detect (BOD) or Real-Time Clock (RTC). Single power supply chip with Power-On Reset (POR) and BOD circuits:

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CPU operating voltage range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/O pads.

Applications Industrial control Medical systems Access control Point-of-sale Communication gateway Embedded soft modem General purpose applications .

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LPC 2148 Architectural overview:

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The LPC2148 consists of an ARM7TDMI-S CPU with emulation support, the ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced High-performance Bus (AHB) for interface to the interrupt controller, and the VLSI pheral functions. The LPC2141/24/6/8 configures the ARM7TDMI-S processor in little-endian byte order. AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the 4 gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the AHB address space. LPC2141/2/4/6/8 peripheral functions (other than the interrupt controller) are connected to the VPB bus. The AHB to VPB bridge interfaces the VPB bus to the AHB bus. VPB peripherals are also allocated a 2 megabyte range of addresses, beginning at the 3.5 gigabyte address point. Each VPB peripheral is allocated a 16 kB address space within the VPB address space.The connection of on-chip peripherals to device pins is controlled by a Pin Connect Block ARM7TDMI-S processor: The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive realtime interrupt response from a small and cost-effective processor core.

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Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one

instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue.The key idea behind THUMB is that of a super-reduced instruction set.

Essentially, the ARM7TDMI-S processor has two instruction sets: The standard 32-bit ARM instruction set. A 16-bit THUMB instruction set. The THUMB sets 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARMs performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32bit register set as ARM code. THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.

On-chip Flash memory system: The LPC2141/2/4/6/8 incorporate a 32 kB, 64 kB, 128 kB, 256 kB, and 512 kB Flash memory system respectively. This memory may be used for

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both code and data storage. Programming of the Flash memory may be accomplished in several ways: over the serial built-in JTAG interface, using In System Programming (ISP) and UART0, or by means of In Application Programming (IAP) capabilities. The application program, using the IAP functions, may also erase and/or program the Flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. When the LPC2141/2/4/6/8 on-chip bootloader is used, 32 kB, 64 kB,

128 kB, 256 kB, and 500 kB of Flash memory is available for user code. The LPC2141/2/4/6/8 Flash memory provides minimum of 100,000 erase/write cycles and 20 years of data-retention.

On-chip Static RAM (SRAM): On-chip Static RAM (SRAM) may be used for code and/or data storage. The on-chip SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2141/2/4/6/8 provide 8/16/32 kB of static RAM respectively. The LPC2141/2/4/6/8 SRAM is designed to be accessed as a byteaddressed memory. Word and halfword accesses to the memory ignore the alignment of the address and access the naturally-aligned value that is addressed (so a memory access ignores address bits 0 and 1 for word accesses, and ignores bit 0 for halfword accesses).Therefore valid reads and writes require data accessed as halfwords to originate from addresses with address line 0 being 0 (addresses ending with 0, 2, 4, 6, 8, A, C, and E in hexadecimal notation) and data accessed as words to originate from addresses with address lines 0 and 1 being 0 (addresses ending with 0, 4, 8, and C in hexadecimal notation). This rule applies to both off and onchip memory usage.

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The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during back-to-back writes. The write-back buffer always holds the last data sent by software to the SRAM. This data is only written to the SRAM when another write is requested by software (the data is only written to the SRAM when software does another write). If a chip reset occurs, actual SRAM contents will not reflect the most recent write request (i.e. after a "warm" chip reset, the SRAM does not reflect the last write operation). Any software that checks SRAM contents after reset must take this into account. Two identical writes to a location guarantee that the data will be present after a Reset. Alternatively, a dummy write operation before entering idle or power-down mode will similarly

guarantee that the last data written will be present in SRAM after a subsequent Reset.

LPC 2148 memory re-mapping and boot block Memory map concepts and operating modes: The basic concept on the LPC2141/2/4/6/8 is that each memory area has a "natural" location in the memory map. This is the address range for which code residing in that area is written. The bulk of each memory space remains permanently fixed in the same location, eliminating the need to have portions of the code designed to run in different address ranges. Because of the location of the interrupt vectors on the ARM7 processor (at addresses 0x0000 0000 through 0x0000 001C,), a small portion of the Boot Block and SRAM spaces need to be re-mapped in order to allow alternative uses of interrupts in the different operating modes . Remapping of the interrupts is accomplished via the Memory Mapping Control feature .

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Memory re-mapping In order to allow for compatibility with future derivatives, the entire Boot Block is mapped to the top of the on-chip memory space. In this manner, the use of larger or smaller flash modules will not require changing the location of the Boot Block (which would require changing the Boot Loader code itself) or changing the mapping of the Boot Block interrupt vectors. Memory spaces other than the interrupt vectors remain in fixed locations. The portion of memory that is re-mapped to allow interrupt processing in different modes includes the interrupt vector area (32 bytes) and an additional 32 bytes, for a total of 64 bytes. The re-mapped code locations overlay addresses 0x0000 0000 through 0x0000 003F. A typical user

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program in the Flash memory can place the entire FIQ handler at address 0x0000 001C without any need to consider memory boundaries. The vector contained in the SRAM, external memory, and Boot Block must contain branches to the actual interrupt handlers, or to other instructions that accomplish the branch to the interrupt handlers. There are three reasons this configuration was chosen: 1. To give the FIQ handler in the Flash memory the advantage of not having to take a memory boundary caused by the remapping into account. 2. Minimize the need to for the SRAM and Boot Block vectors to deal with arbitrary boundaries in the middle of code space. 3. To provide space to store constants for jumping beyond the range of single word branch instructions. Re-mapped memory areas, including the Boot Block and interrupt vectors, continue to appear in their original location in addition to the re-mapped address. Embedded Trace Macrocell Features Closely track the instructions that the ARM core is executing. 1 External trigger input 10 pin interface All registers are programmed through JTAG interface. Does not consume power when trace is not being used. THUMB instruction set support

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Applications As the microcontroller has significant amounts of on-chip memories, it is not possible to determine how the processor core is operating simply by observing the external pins. The ETM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to a trace port. A software debugger allows configuration of the ETM using a JTAG interface and displays the trace information that has been captured, in a format that a user can easily understand.

Description The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external Trace Port Analyzer captures the trace information under software debugger control. Trace port can broadcast the Instruction trace information. Instruction trace (or PC trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly

compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image ofthe code being executed. Self-modifying code can not be traced because of this restriction.

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Arm Processor Fundamentals Arm Core Introduction:

The ARM Processor, like all RISC processors, uses a load store architecture. This means that it has two instruction types for transferring data in and out of the processor. Load instructions copy data from

memory to registers in the core and the store instructions copy data from registers to memory. There are n o data processing instructions that

directly manipulate data in memory. The data processing is carried out only in registers. Data
Instruction Decoder Sign extend

Write

Register file r -r

Barrel shifter

Rd result
MAC

r15 pc
ALU

Address Registers

Rm

B
Incrementer

Rn N

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Address ARM Core data flow model

Data items are placed in the register file.

The register file is a

storage bank made up of 32 bit registers. The registers hold 32 bit signed or unsigned numbers. The sign extend converts 8 bit or 16 bit numbers to 32 bit values as they are read from memory and placed in register.

ARM instructions typically have two source registers Rn and Rm, and result register Rd. Source operands are read from the register file via internal buses A & B. The ALU or MAC takes the register values Rn and Rm from the A and B buses and compute result. Data processing instructions write the result in Rd. address. Rm can be preprocessed in the barrel shifter before it enters ALU. The Rd is written back to the register file using result bus. For load, store instructions the incrementer updates the address register before the core reads or writes next register or memory. The processor continues executing instructions until an exception or interrupt changes the normal flow. Load and store instructions use the ALU to generate an

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ARM Registers

General purpose registers hold either data or an address.

The

active registers available in user mode are r0-r15 and cpsr. spsr is alos available in other than user mode. r0-r12 are 32 bit general purpose registers. purpose 32 bit registers. r13 stack pointer which holds top of stack address. r14 Link register where the core puts return address during call. r15 program counter contains the address of next instruction to be fetched. cpsr Current program status register which is used by the ARM core for monitoring and control internal operations. status, extension and control. Flags 31 28 Status Extension control 7 6 5 4 0 Mode Processor mode The fields of cpsr are flag, r13-r15 are special

Condition flags

Interrupt flags

Thumb state cpsr 27 26 25 24 23 Q Res J Res 20 19 GE(3:0) 16 15 Res 10 9 E 8 A

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Q saturation flag (saturated signed & unsigned arithmetic) J = 1 Java execution Res = reserved GE(3:0) Greater or equal flags (parallel modulo add & subtract) E Controls the data endiness

A = 1 disables imprecise data aborts I = 1 disables IRQ interrupts F = 1 disables FIQ interrupts T = 1 Thumb state ; = 0 ARM state. Mode 10000 10001 10010 10011 10111 11011 11111 user mode FIQ mode IRQ mode supervisor mode abort mode undefined mode system mode

Except user mode all others are privileged modes. Processor exerts abort mdoe when there is a failed attempt to access memory.

Fast interrupt request and Interrupt request modes correspond to two interrupt levels of ARM processor.

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Supervisor mode is the mode that the processor is in after reset and OS Kernel operates in.

System mode is special version of user mode that allows full readwrite access to the cpsr.

undefined mode is used when processor encounters an instruction that is undefined.

Actually there are 37 registers in register file. hidden from a program at different times.

20 registers are

These registers are called

banked registers, are identified by shading in the diagram.

r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10

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r11 r12 r13 sp r14 lr r15 pc r8_fiq r9_fiq r10_fiq Fast r11_fiq r12_fiq r13_fiq r14_fiq Interrupt Request r13_irq r13_svc r14_irq r14_svc r14_undef r14_abt r13_undef r13_abt supervisory undefined abort Interrupt request

cpsr spsr_fiq spsr_irq spsr_svc spsr_undef spsr_abt

A banked register maps one to one onto a user mode register. If we change processor mode, a banked register from the new mode will replace an existing register.

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The saved program status register (spsr) stores the previous modes cpsr. cpsr is not copied into spsr when a mode change is forced due to a program writing directly to cpsr.

The state of the core determines which instruction set is being executed. 1. ARM 2. Thumb 3. Jazelle

We

cannot

intermingle

sequential

ARM,

Thumb

and

Jazelle

instructions.

ARM Thumb Jazelle

32 bit 16 bit 8 bit and is hybrid mix of software and hardware

designed to speed up the execution of Java byte codes.

Pipe line :

Using a pipe line speeds up execution by fetching the next instruction while other instructions are being decoded and executed. ARM7 has 3 stages pipe line.

Example : Instruction 1

ADD

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Instruction 2 Instruction 3 SUB CMP

Fetch
Cycle 1

decode

execute

Cycle 2

time
Cycle 3

In the first cycle, the core fetches ADD instruction from memory. In the second cycle the core fetches SUB instruction and decode ADD instruction. In the third cycle the ARM core fetches CMP instruction,

decode SUB instruction and execute ADD instruction.

ARM9 has five stage pipe line including memory write and ARM10 has 6 stage pipe line.

The ARM pipe line has not processed an instruction until passes completely through the execute stage. For example, ARM7 has executed an instruction only when the fourth instruction is fetched.

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The program counter always points to the address of the instruction being executed plus two instructions ahead. This is important when the pc is used for calculating a relative offset. When the processor is in

thumb state the pc is the instruction address plus 4.

Characteristics of pipe line :

1. The execution of a branch instruction or branching by direct modification of pc causes the ARM core to flush its pipe line. 2. An instruction in execute stage will complete even though an interrupt has been raised. Other instructions in the pipe line will be abandoned, the processor start filling the pipe line from the appropriate entry in the vector table. 3. ARM10 uses branch prediction which reduces the effect of pipe line flush.

Exceptions, Interrupts and Vector Table

When an exception (unplanned changes occur in flow of control) or interrupt (immediate program needed apart from regular program sequence) occurs, the processor sets the pc to a specified memory address. The address in with in special address range called Vector table. The entries in the Vector table are instructions that branches to specific routines designed to handle a particular exception or interrupt.

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When an exception or interrupt occurs the processor suspends normal execution and starts loading instructions from the exception vector table. The memory map address 0 x 00000000is reserved for vector table. On some processors the vector table can be optionally located at higher address 0 x FFFF 0000. Operating systems such as Linux and MS

embedded products can take advantage of this feature. 1. reset vector : is the location of first instruction executed by processor when power is supplied to processor. This instruction branches to the initialization code. 2. undefined instruction vector : used when the processor can not decode a instruction. 3. Software interrupt vector : called when SWI instruction is executed. 4. Prefetch abort vector :occurs when the processor attempts to fetch an instruction from address without access permissions. 5. Data abort vector : occurs when the processor attempts to access an data (from data memory) without access permission. 6. Interrupt request vector : used by external hardware to interrupt normal execution. (IRQ are not masked) 7. Fast Interrupt request vector : FIQ are not masked. Core Extensions There are three hardware extensions ARM wraps around the core, cache and tightly coupled Memory, Memory Management and the Coprocessor interface. 1. Cache and Tightly couple Memory Cache is the fast memory placed in between main memory and

core which speed up fetching. Von Neumann architecture has unified cache for both data and instruction.

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ARM Core

Unified cache

Logic & Control

AMBA Bus Interface unit

Main Memory

On-chip AMBA bus Harvard style core provides separate cache for data and instruction. A cache provides an overall increase in performance but at the expense of predictable execution. but for real time systems it is

paramount that code execution is deterministic-time taken for load, store data or instruction must be predictable. This is fast SRAM located close to the core and guarantees the clock required to fetch instruction or data.
ARM Core Logic & Control

Data TCM D

Inst. TCM

I
Main Memory

AMBA Bus Interface Unit

D+I On-chip AMBA bus

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Memory Management :

Embedded

systems

use

multiple

memory

devices.

Memory

management hardware helps to organize these devices and protection.

ARM cores have three different types of memory management hardware 1) non protected memory, Memory protection unit (MPU) and Memory Management unit (MMU) full protection.

Non protected memory is fixed and provides little flexibility used for small embedded systems.

MPU employs a simple system that uses limited number of memory regions. These regions are controlled with a set of special

coprocessor registers and each region is defined with specific access permissions.

MMU uses a set of translation tables to provide fine grained control over memory. These tables are stored in main memory and provide a Virtual to physical address map as well as access permissions.

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Coprocessors :

Coprocessor extends the processing features of a core by extending the instruction set or by provid8ing configuration registers. More than one coprocessor can be added to the ARM core via the coprocessor interface.

The

coprocessor

can

be

accessed

through

dedicated

ARM

instructions.

The

coprocessor

can

extend

ARM

instructions

by

providing

instructions for special operations. Ex: Vector Floating Point.

Architecture Revisions :

Every ARM implementation executes a specific Instruction Set Architecture (ISA). The code written to earlier architecture revision will also execute on as latter version of architecture.

The ARM nomenclature indicates the feature of the processor and not include architecture revision information. Nomenclature

ARM[x] [y] [z] [T] [D] [M] [I] [E] [J] [F] [S]

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x family ; y memory management / protection unit ; z cache T thumb 16 bit decoder D JTAG debug M Fast Multiplier I - Embedded JCE Macro cell E enhanced instructions (assume TDMI) J Jazelle F Vector floating point unit S Synthesizible version

All

ARM

cores

after

ARM7TDMI

include

the

TDMI

features

eventhough not include in letters.

family

group

of

processor

that

shares

the

same

hardware

characteristics. JTAG IEE1149.1 Standard Test Access Port and boundary scan architecture (developed by Joint Test Action Group) Embedded processor ICE that macro cell allows debut hardware built into the

breakpoints and watch points to be set.

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Synthesizable processor core is supplied as source code that can be compiled into a form easily used by EDA tools.

Architecture Revision

Revision ARMv1 ARMv2

Example core ARM 1 ARM 2

ISA Enhancement first arm ; 26 bit addressing 32 bit multiplier ; coprocessor support 32 bit

ARMv2a

ARM 3

on chip Instruction coprocessor Management

cache

SWAP

15

for

cache

ARMv3

ARM 6 & ARM 7DI

32 bit addressing ; cpsr & spsr undefined instruction and abort MMU support Virtual memory

ARMv3M

ARM 7M

signed & unsigned multiple instructions

long

ARMv4

Strong ARM

Load / store instructions for signed / unsigned half words / bytes new mode system reserve SWI space for

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architecturally operations defined

26 bit addressing mode longer supported

no

ARMv4T

ARM 7 TDMI & ARM Thumb 97 ARM 9E and ARM 10E superset of ARMv4T Extra instructions change added to

ARMv5TE

state between thumb & ARM Enhanced multiple instruction Extra DSP type instructions Faster Multiply accumulate

ARMv5 TEJ ARMv6

ARM 7 EJ, ARM 926EJ ARM 11

Java acceleration improved instructions multiprocess

unaligned and mixed endian data handling new multimedia instructions

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ARM processor families :

ARM has designed a number of processors that are grouped into different families according to the core they use. The families are based on ARM 7, ARM 9, ARM 10 and ARM 11 cores. ARM 8 was developed but was soon superseded.

ARM family attribute comparison

ARM 7

ARM 9

ARM 10

ARM 11

Pipe depth

line 3

Typical MHz mW / MHz MIPS / MHz

80 0.06 0.97

150 0.19 1.1 Harvard

260 0.5 1.3 Harvard

335 0.4 1.2 Harvard

Architecture Von Neumann Multiplier 8 x 32

8 x 32

16 x 32

16 x 32

ARM Processor Variants

CPU Core

MMU MPU none none

/ Cache

Jazelle Thumb E

ARM 7 TDMI ARM 7 EJ-S

none none

no yes

yes yes

no yes

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ARM 7 20T MMU undefined 8K 16K / 16K 8K / 8K Cache TCM 4K / 4K Cache TCM TCM ARM 1020E ARM 1022 E ARMM EJ-S MMU MMU 32K / 32K 16K / 16K Cache TCM Cache TCM Cache TCM no no & yes yes yes yes yes yes Yes & no yes No

ARM 9207 ARM 992T ARM 926EJ-S ARM 940T ARM 946 E-S ARM 966 E-S

MMU MMU MMU MPU MPU none

no no & yes no no no

yes yes yes yes yes yes

no no yes no yes Yes

1026 MMU & MPU

ARM 1136 J-S ARM 1136 JFS

MMU MMU

& yes yes &

yes yes

yes yes

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ARM Instruction Set

ARM instructions are classified as : 1) Data processing instructions 2) Branch instructions (control flow instructions) 3) Load store instructions (data transfer instructions) in addition software interrupt instructions and program status register instructions.

Data Processing instructions :

Enable the programmer to perform

arithmetic and logical operations on data in registers. Generally, these instructions require two operands and produce a single result. * Rules apply to data processing instructions : - All operands are 32 bit wide and come from registers or are specified as literals in the instruction itself. - Each of the operand registers and the result register are independently specified in the instruction.

Arithmetic Operations :

ADD r0, r1, r2 ADC r0, r1, r2 SUB r0, r1, r2 SBC r0, r1, r2

; ; ; ;

r0 = r1 + r2 r0 = r1 + r2 + c r0 = r1 r2 r0 = r1 r2 + c 1

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RSB r0, r1, r2 RSC r0, r1, r2 ; ; r0 = r2 r1 r0 = r2 r1 + c 1

Bit Wise Logical Operations

AND r0, r1, r2 ORR r0, r1, r2 EOR r0, r1, r2 BIC r0, r1, r2

; ; ; ;

r0 = r1 AND r2 r0 = r1 OR r2 r0 = r1 XOR r2 r0 = r1 AND NOT r2

Register movement operations

MOV r0, r2 MVN r0, r2

; ;

r0 = r2 r0 = NOT r2

Comparison Operations

CMP r1, r2 ; CMN r1, r2 ; TST r1, r2 ;

set cc on r1 r2 set cc on r1 + r2 set cc on r1 AND r2 set cc on r1 XOR r2

TEQ r1, r2 ;

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These instructions do not produce a result. Just set6 the condition code bits operation. (N, Z, C and V) in the cpsr according to the selected

The mnemonics stand for compare (CMP) compare negated (CMN), bit test (TST) and test equal (TEQ).

Immediate Operands: If, instead of adding two registers second operand can be replaced by immediate value.

ADD r3, r3, # 1 ;

r3 = r3 + 1

Shifted register operands : By using barrel shifter, the second operand may be shifted before it is combined with the first operand. ADD r3, r2, r1, LSL # 3 ; r3 = r2 + 8 x r1

Shift Operations :

LSL : Logical shift left by 0 to 31 places ; fill the vacated bits at LS and of the word with zero. LSR : Logical shift right by 0 to 32 places ; fill the vacated bits at MS end of the word with zero.

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ASL : ASR : Arithmetic shift left ; Synonym for LSL Arithmetic shift right by o to 32 places ; fill the vacated bits at

MS end of the word with zeros if the source operand was positive, or with ones if negative. ROR : rotate right by 0 to 32 places ; RRX : rotate right extended by 1 place (with carry)

Setting the condition codes :

Any data processing instruction can set condition codes (N, Z, C and V) if the programmer wishes it to. At the assembly language level this request is indicated by adding S. S stands for set condition codes.

Example : 64 bit addition ADDS r2, r2, r0 ; ADC r3, r3, r2

Data Transfer Instructions :

There are three basic forms of data transfer instructions. transfer instructions move data between ARM registers and memory.

Data

Single register load & store : data may be byte, 16 bit or 32 bit .

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Multiple register load & store : large data transfer in efficient manner. Single register swap : Exchange register with memory content.

LDR r0, [r1]

r0

mem32[r1]

STR r0,[r1]

mem32[r1]

r0

LDR r0, [r1, # 4] ;

r0

mem32[r1+4] pre indexing

(base + offset)

LDR r0, [r1, # 4]! write back ;

r0

mem32[r1+4] with pre index +

r1

r1 + 4

The exclamation mark indicates that the instruction should update the base register.

LDR r0, [r1], #4 ; ; LDR B r0, [r1]

r0

mem32[r1] post index mem8 [r1]

r1 = r1 + 4 ; r0

8 bit data in memory STR B

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LDR H STR H LDR SB LDR SH load signed byte load signed half word half word

The offset may be immediate, register, scaled register.

Multiple Load store Instructions :

These instructions allow any subset (or all) of the 16 registers to be transferred with a single instruction.

LDM

Load registers

Multiple Instructions

STM

Save registers

Multiple LDM 1A

LDM DA

1A 1B DA DB

increment after increment before decrement after decrement before

LDM 1B STM 1A STM 1B

LDM DB STM DA STM DB

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Co-processor Instructions

There are two types of undefined instruction. The first set are totally illegal, and cause the undefined instruction vector to be called whenever they are encountered. The second set are only classed as illegal if there is no co-processor in the system which can execute them. Unsurprisingly, these are called the co-processor instructions. Note that the ARM itself treats all undefined instructions as possible co-processor ones. The only thing which distinguishes the first class from the second is that no coprocessor will ever indicate that it can execute the first type.

CPI Co-processor instruction

The ARM asserts this when it encounters any undefined instruction. All co-processors in the system monitor it, ready to leap into action when they see it become active.

CPA Co-processor absent

When a co-processor sees that an undefined instruction has been fetched (by reading the CPI signal), it uses CPA to tell the ARM if it can execute it. There are two parts to the instruction which determine whether it is 'co-processable'. The first is a single bit which indicates whether a particular undefined instruction is a proper co-processor one (the bit is set) or an undefined one (the bit is clear).

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The second part is the co-processor id. This is a four-bit field which determines which of 16 possible co-processors the instruction is aimed at. If this field matches the co-processor's id, and the instruction is a true coprocessor one, the co-processor lets the ARM know by setting the CPA signal low. If none of the co-processors recognises the id, or there aren't any, the CPA line will remain in its normal high state, and the ARM will initiate an undefined instruction trap.

CPB Co-processor busy

Once a co-processor claims an instruction, the ARM must wait for it to become available to actually execute it. This is necessary because the co-processor might still be in the middle of executing a previous undefined instruction. The ARM waits for the co-processor to become ready by monitoring CPB. This is high while the co-processor is tied up performing some internal operation, and is taken low when it is ready to accept the new instruction.

Software interrupt instruction

The final group is the most simple, and the most complex. It is very simple because it contains just one instruction, SWI, whose assembler format has absolutely no variants or options.

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The general form of SWI is:

SWI{cond} <expression>

SWI is the user's access to the operating system of the computer. When a SWI is executed, the CPU enters supervisor mode, saves the return address in R14_SVC, and jumps to location 8. From here, the operating system takes over. The way in which the SWI is used depends on <expression>. This is encoded as a 24-bit field in the instruction.

Program for Addition ,Subtraction,Multiplication and Division Addition: UART: LDR R0,=VPBDIV

MOV R1,#0X01 STR R1,[R0] LDR R0,=U0LCR MOV R1,#0X83 STR R1,[R0] LDR R0,=U0DLL

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MOV R1,#0X4E STR R1,[R0] LDR R0,=U0DLM MOV R1,#0X00 STR R1,[R0] LDR R0,=U0LCR MOV R1,#0X03 STR R1,[R0] LDR R0,=U0FCR MOV R1,#0X05 STR R1,[R0] LDR R0,=PINSEL0 MOV R1,#0X00000005//PINSEL0 FOR RX & TX STR R1,[R0] MOV R7,R8 LDR R10,=0Xff000000 and r9,r7,r10 ror r8,r9,#0x18// LDR R0,=U0THR STR R8,[R0] //added value move to UOTHR GCD1: LDR R0,=U0LSR

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LDR R2,[R0] MOV R1,#0X20 AND R3,R1,R2 //IF R3 IS 0X20 THEN 4BIT IS TRANSMITTED CMP R3,R1 BNE GCD1 ror r10,r10,#0x08 and r9,r7,r10 ror r8,r9,#0x10// LDR R0,=U0THR STR R8,[R0] //added value move to UOTHR GCD2: LDR R0,=U0LSR LDR R2,[R0] MOV R1,#0X20 AND R3,R1,R2 //IF R3 IS 0X20 THEN 4BIT IS TRANSMITTED CMP R3,R1 BNE GCD ror r10,r10,#0x08 and r9,r7,r10 ror r8,r9,#0x08 LDR R0,=U0THR STR R8,[R0] //added value move to UOTHR //ELSE WAIT IN SAME LOOP //ELSE WAIT IN SAME LOOP

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GCD3: LDR R0,=U0LSR LDR R2,[R0] MOV R1,#0X20 AND R3,R1,R2 //IF R3 IS 0X20 THEN 4BIT IS TRANSMITTED CMP R3,R1 BNE GCD ror r10,r10,#0x08 and r9,r7,r10 mov r8,r7 LDR R0,=U0THR STR R8,[R0] //added value move to UOTHR //ELSE WAIT IN SAME LOOP

GCD4:

LDR R0,=U0LSR LDR R2,[R0] MOV R1,#0X20 AND R3,R1,R2 //IF R3 IS 0X20 THEN 4BIT IS TRANSMITTED CMP R3,R1 BNE GCD4 MOV PC,LR //ELSE WAIT IN SAME LOOP

Subtraction:

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UART: LDR R0,=VPBDIV MOV R1,#0X01 STR R1,[R0] LDR R0,=U0LCR MOV R1,#0X83 STR R1,[R0] LDR R0,=U0DLL MOV R1,#0X4E STR R1,[R0] LDR R0,=U0DLM MOV R1,#0X00 STR R1,[R0] LDR R0,=U0LCR MOV R1,#0X03 STR R1,[R0] LDR R0,=U0FCR MOV R1,#0X05 STR R1,[R0] LDR R0,=PINSEL0 MOV R1,#0X00000005//PINSEL0 FOR RX & TX STR R1,[R0]

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MOV R7,R8 LDR R10,=0Xff000000 and r9,r7,r10 ror r8,r9,#0x18// LDR R0,=U0THR STR R8,[R0] //subtract value move to UOTHR GCD1: LDR R0,=U0LSR LDR R2,[R0] MOV R1,#0X20 AND R3,R1,R2 //IF R3 IS 0X20 THEN 4BIT IS TRANSMITTED CMP R3,R1 BNE GCD1 ror r10,r10,#0x08 and r9,r7,r10 ror r8,r9,#0x10// LDR R0,=U0THR STR R8,[R0] //subtract value move to UOTHR GCD2: LDR R0,=U0LSR LDR R2,[R0] MOV R1,#0X20 AND R3,R1,R2 //IF R3 IS 0X20 THEN 4BIT IS TRANSMITTED //ELSE WAIT IN SAME LOOP

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CMP R3,R1 BNE GCD ror r10,r10,#0x08 and r9,r7,r10 ror r8,r9,#0x08/ LDR R0,=U0THR STR R8,[R0] //subtract value move to UOTHR //ELSE WAIT IN SAME LOOP

GCD3:

LDR R0,=U0LSR LDR R2,[R0] MOV R1,#0X20 AND R3,R1,R2 //IF R3 IS 0X20 THEN 4BIT IS TRANSMITTED CMP R3,R1 //ELSE WAIT IN SAME LOOP

BNE GCD ror r10,r10,#0x08 and r9,r7,r10 mov r8,r7 LDR R0,=U0THR STR R8,[R0] //subtract value move to UOTHR GCD4: LDR R0,=U0LSR LDR R2,[R0]

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MOV R1,#0X20 AND R3,R1,R2 //IF R3 IS 0X20 THEN 4BIT IS TRANSMITTED CMP R3,R1 BNE GCD4 MOV PC,LR //ELSE WAIT IN SAME LOOP

Multiplication: UART: LDR R0,=VPBDIV

MOV R1,#0X01 STR R1,[R0] LDR R0,=U0LCR MOV R1,#0X83 STR R1,[R0] LDR R0,=U0DLL MOV R1,#0X4E STR R1,[R0] LDR R0,=U0DLM MOV R1,#0X00 STR R1,[R0] LDR R0,=U0LCR MOV R1,#0X03

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STR R1,[R0] LDR R0,=U0FCR MOV R1,#0X05 STR R1,[R0] LDR R0,=PINSEL0 MOV R1,#0X00000005//PINSEL0 FOR RX & TX STR R1,[R0] MOV R7,R8 LDR R10,=0Xff000000 and r9,r7,r10 ror r8,r9,#0x18// LDR R0,=U0THR STR R8,[R0] //multiplication value move to UOTHR GCD1: LDR R0,=U0LSR LDR R2,[R0] MOV R1,#0X20 AND R3,R1,R2 //IF R3 IS 0X20 THEN 4BIT IS TRANSMITTED CMP R3,R1 BNE GCD1 ror r10,r10,#0x08 and r9,r7,r10 //ELSE WAIT IN SAME LOOP

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ror r8,r9,#0x10// LDR R0,=U0THR STR R8,[R0] //multiplication value move to UOTHR GCD2: LDR R0,=U0LSR LDR R2,[R0] MOV R1,#0X20 AND R3,R1,R2 //IF R3 IS 0X20 THEN 4BIT IS TRANSMITTED CMP R3,R1 BNE GCD ror r10,r10,#0x08 and r9,r7,r10 ror r8,r9,#0x08/ LDR R0,=U0THR STR R8,[R0] //multiplication value move to UOTHR GCD3: LDR R0,=U0LSR LDR R2,[R0] MOV R1,#0X20 AND R3,R1,R2 //IF R3 IS 0X20 THEN 4BIT IS TRANSMITTED CMP R3,R1 BNE GCD ror r10,r10,#0x08 //ELSE WAIT IN SAME LOOP //ELSE WAIT IN SAME LOOP

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and r9,r7,r10 mov r8,r7 LDR R0,=U0THR STR R8,[R0] //multiplication value move to UOTHR GCD4: LDR R0,=U0LSR LDR R2,[R0] MOV R1,#0X20 AND R3,R1,R2 //IF R3 IS 0X20 THEN 4BIT IS TRANSMITTED CMP R3,R1 BNE GCD4 MOV PC,LR //ELSE WAIT IN SAME LOOP

Division: UART: LDR R0,=VPBDIV

MOV R1,#0X01 STR R1,[R0] LDR R0,=U0LCR MOV R1,#0X83 STR R1,[R0] LDR R0,=U0DLL

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MOV R1,#0X4E STR R1,[R0] LDR R0,=U0DLM MOV R1,#0X00 STR R1,[R0] LDR R0,=U0LCR MOV R1,#0X03 STR R1,[R0] LDR R0,=U0FCR MOV R1,#0X05 STR R1,[R0] LDR R0,=PINSEL0 MOV R1,#0X00000005//PINSEL0 FOR RX & TX STR R1,[R0] MOV R7,R8 LDR R10,=0Xff000000 and r9,r7,r10 ror r8,r9,#0x18// LDR R0,=U0THR STR R8,[R0] //added value move to UOTHR GCD1: LDR R0,=U0LSR

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LDR R2,[R0] MOV R1,#0X20 AND R3,R1,R2 //IF R3 IS 0X20 THEN 4BIT IS TRANSMITTED CMP R3,R1 BNE GCD1 ror r10,r10,#0x08 and r9,r7,r10 ror r8,r9,#0x10// LDR R0,=U0THR STR R8,[R0] //added value move to UOTHR GCD2: LDR R0,=U0LSR LDR R2,[R0] MOV R1,#0X20 AND R3,R1,R2 //IF R3 IS 0X20 THEN 4BIT IS TRANSMITTED CMP R3,R1 BNE GCD ror r10,r10,#0x08 and r9,r7,r10 ror r8,r9,#0x08/ LDR R0,=U0THR STR R8,[R0] //added value move to UOTHR //ELSE WAIT IN SAME LOOP //ELSE WAIT IN SAME LOOP

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GCD3: LDR R0,=U0LSR LDR R2,[R0] MOV R1,#0X20 AND R3,R1,R2 //IF R3 IS 0X20 THEN 4BIT IS TRANSMITTED CMP R3,R1 BNE GCD ror r10,r10,#0x08 and r9,r7,r10 mov r8,r7 LDR R0,=U0THR STR R8,[R0] //added value move to UOTHR GCD4: LDR R0,=U0LSR LDR R2,[R0] MOV R1,#0X20 AND R3,R1,R2 //IF R3 IS 0X20 THEN 4BIT IS TRANSMITTED CMP R3,R1 BNE GCD4 MOV PC,LR //ELSE WAIT IN SAME LOOP //ELSE WAIT IN SAME LOOP

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UNIT II (EMBEDDED C BASIC,GPIO,TIMER &EXTERNEL INTERRUPTS)

PIN CONNECT BLOCK Features: Allows individual pin configuration.

Applications The purpose of the Pin Connect Block is to configure the microcontroller pins to the desired functions.

Description The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. Selection of a single function on a port pin completely excludes all other functions otherwise available on the same pin.The only partial exception from the above rule of exclusion is the case of inputs to the A/D converter. Regardless of the function that is selected for the port pin that also hosts the A/D input, this A/D input can be read at any time and variations of

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the voltage level on this pin will be reflected in the A/D readings. However, valid analog reading(s) can be obtained if and only if the function of an analog input is selected. Only in this case proper interface circuit is active in between the physical pin and the A/D module. In all other cases, a part of digital logic necessary for the digital function to be performed will be active, and will disrupt proper behavior of the A/D

Register description Pin Function Select Register 0 (PINSEL0 - 0xE002 C000) The PINSEL0 register controls the functions of the pins as per the settings l. The direction control bit in the IO0DIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically.

Pin function Select register 1 (PINSEL1 - 0xE002 C004) The PINSEL1 register controls the functions of the pins as per the settings . The direction control bit in the IO0DIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically.

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Pin function Select register 2 (PINSEL2 - 0xE002 C014) The PINSEL2 register controls the functions of the pins as per the settings . The direction control bit in the IO1DIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically.

GPIO

Features Every physical GPIO port is accessible via either the group of registers providing an enhanced features and accelerated port access or the

legacy group of registers. GPIO registers are relocated to the ARM local bus so that the fastest possible I/O timing can be achieved Mask registers allow treating sets of port bits as a group, leaving other bits Unchanged . All registers are byte and half-word addressable Entire port value can be written in one instruction.Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port Direction control of individual bits. All I/O default to inputs after reset.

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Backward compatibility with other earlier devices is maintained with legacy

Register description: IOPIN GPIO Port Pin value register. The current state of the GPIO

configured port pins can always be read from this register, regardless of pin direction.

IOSET GPIO Port Output Set register.

This register controls the

state of output pins in conjunction with the IOCLR register. Writing ones produces highs at the corresponding port pins. Writing zeroes has no effect.

IODIR GPIO Port Direction control register. This register individually controls the direction of each port pin.

IOCLR GPIO Port Output Clear register. This register controls the state of output pins. Writing ones produces lows at the corresponding port pins and clears the corresponding bits in the IOSET register. Writing zeroes has no effect.

Applications General purpose I/O Driving LEDs, or other indicators

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Controlling off-chip devices Sensing digital inputs

TIMER Timer /Counter TIMER0 and TIMER1 Features A 32-bit Timer/Counter with a programmable 32-bit Prescaler. Counter or Timer operation Up to four 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. Four 32-bit match registers that allow: Continuous operation with optional interrupt generation on match. Stop timer on match with optional interrupt generation. Reset timer on match with optional interrupt generation. Up to four external outputs corresponding to match registers, with the following capabilities: Set low on match. Set high on match. Toggle on match. Do nothing on match.

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Applications Interval Timer for counting internal events. Pulse Width Demodulator via Capture inputs. Free running timer.

Description The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally-supplied clock, and can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt.

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BLOCK DIAGRAM FOR TIMER:

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Register description Interrupt Register (IR, TIMER0: T0IR - 0xE000 4000 and TIMER1: T1IR - 0xE000 8000) The Interrupt Register consists of four bits for the match interrupts and four bits for the capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be high. Otherwise, the bit will be low. Writing a logic one to the corresponding IR bit will reset the interrupt. Writing a zero has no effect

. Timer Control Register (TCR, TIMER0: T0TCR - 0xE000 4004 and TIMER1: T1TCR - 0xE000 8004) The Timer Control Register (TCR) is used to control the operation of the Timer/Counter.

Count Control Register (CTCR, TIMER0: T0CTCR - 0xE000 4070 and TIMER1: T1TCR - 0xE000 8070) The Count Control Register (CTCR) is used to select between Timer and Counter mode and in Counter mode to select the pin and edge(s) for counting. When Counter Mode is chosen as a mode of operation, the CAP input (selected by the CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two consecutive samples of this CAP input, one of the following four events is recognized: rising edge, falling edge, either of edges or no changes in the level of the selected CAP input. Only

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if the identified event corresponds to the one selected by bits 1:0 in the CTCR register, the Timer Counter register will be incremented. Effective processing of the externally supplied clock to the counter has some limitations. Since two successive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input, the frequency of the CAP input can not exceed one half of the PCLK clock. Consequently, duration of the high/low levels on the same CAP input in this case can not be shorter than 1/PCLK.

Timer Counter (TC, TIMER0: T0TC - 0xE000 4008 and TIMER1: T1TC - 0xE000 8008) The 32-bit Timer Counter is incremented when the Prescale Counter reaches its terminal count. Unless it is reset before reaching its upper limit, the TC will count up through the value 0xFFFF FFFF and then wrap back to the value 0x0000 0000. This event does not cause an interrupt, but a Match register can be used to detect an overflow if needed.

Prescale Register (PR, TIMER0: T0PR - 0xE000 400C and TIMER1: T1PR - 0xE000 800C) The 32-bit Prescale Register specifies the maximum value for the Prescale Counter.

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Prescale Counter Register (PC, TIMER0: T0PC - 0xE000 4010 and TIMER1: T1PC - 0xE000 8010) The 32-bit Prescale Counter controls division of PCLK by some constant value before it is applied to the Timer Counter. This allows control of the relationship of the resolution of the timer versus the maximum time before the timer overflows. The Prescale Counter is incremented on every PCLK. When it reaches the value stored in the Prescale Register,the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK. This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when PR = 1, etc.

Match Registers (MR0 - MR3) The Match register values are continuously compared to the Timer Counter value. When the two values are equal, actions can be triggered automatically. The action possibilities are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are controlled by the settings in the MCR register.

Match Control Register (MCR, TIMER0: T0MCR - 0xE000 4014 and TIMER1: T1MCR - 0xE000 8014) The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter.

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Capture Registers (CR0 - CR3) Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin. The settings in the Capture Control Register determine whether the capture function is enabled, and whether a capture event happens on the rising edge of the associated pin, the falling edge, or on both edges.

Capture Control Register (CCR, TIMER0: T0CCR - 0xE000 4028 and TIMER1: T1CCR - 0xE000 8028) The Capture Control Register is used to control whether one of the four Capture Registers is loaded with the value in the Timer Counter when the capture event occurs, and whether an interrupt is generated by the capture event. Setting both the rising and falling bits at the same time is a valid configuration, resulting in a capture event for both edges. In the description below, "n" represents the Timer number, 0 or 1.

External Match Register (EMR, TIMER0: T0EMR - 0xE000 403C; and TIMER1: T1EMR - 0xE000 803C) The External Match Register provides both control and status of the external match pins MAT(0-3).

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VECTOR INTERRUPT CONTROLL(VIC) Features ARM PrimeCell Vectored Interrupt Controller 32 interrupt request inputs 16 vectored IRQ interrupts 16 priority levels dynamically assigned to interrupt requests Software interrupt generation Description The Vectored Interrupt Controller (VIC) takes 32 interrupt request inputs and programmably assigns them into 3 categories, FIQ, vectored IRQ, and non-vectored IRQ. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. Fast Interrupt reQuest (FIQ) requests have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting aninterrupt. Vectored IRQs have the middle priority, but only 16 of the 32 requests can be assigned to this category. Any of the 32 requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

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Non-vectored IRQs have the lowest priority. The VIC ORs the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are requesting, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active. All registers in the VIC are word registers. Byte and halfword reads and write are not supported. . Register description Software Interrupt register (VICSoftInt - 0xFFFF F018) The contents of this register are ORed with the 32 interrupt requests from the various peripherals, before any other logic is applied.

Software Interrupt Clear register (VICSoftIntClear - 0xFFFF F01C) This register allows software to clear one or more bits in the Software Interrupt register, without having to first read it.

Raw Interrupt status register (VICRawIntr - 0xFFFF F008) This is a read only register. This register reads out the state of the 32 interrupt requests and software interrupts, regardless of enabling or classification.

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Interrupt Enable register (VICIntEnable - 0xFFFF F010) This is a read/write accessible register. This register controls which of the 32 interrupt requests and software interrupts contribute to FIQ or IRQ.

Interrupt Enable Clear register (VICIntEnClear - 0xFFFF F014) This is a write only register. This register allows software to clear one or more bits in the Interrupt Enable register

Interrupt Select register (VICIntSelect - 0xFFFF F00C) This is a read/write accessible register. This register classifies each of the 32 interrupt requests as contributing to FIQ or IRQ

IRQ Status register (VICIRQStatus - 0xFFFF F000) This is a read only register. This register reads out the state of those interrupt requests that are enabled and classified as IRQ. It does not differentiate between vectored and non-vectored IRQs

FIQ Status register (VICFIQStatus - 0xFFFF F004) This is a read only register. This register reads out the state of those interrupt requests that are enabled and classified as FIQ. If more than one request is classified as FIQ, the FIQ service routine can read this register to see which request(s) is (are) active.

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Vector Address registers 0-15 (VICVectAddr0-15 - 0xFFFF F10013C) These are a read/write accessible registers. These registers hold the addresses of the Interrupt Service routines (ISRs) for the 16 vectored IRQ slots.

Default Vector Address register (VICDefVectAddr - 0xFFFF F034) This is a read/write accessible register. This register holds the address of the Interrupt Service routine (ISR) for non-vectored IRQs.

Vector Address register (VICVectAddr - 0xFFFF F030) This is a read/write accessible register. When an IRQ interrupt occurs, the IRQ service routine can read this register and jump to the value read. Protection Enable register (VICProtection - 0xFFFF F020) This is a read/write accessible register. It controls access to the VIC registers by software running in User mode.

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EXTERNAL INTERRUPTS FEATURE: The LPC2141/2/4/6/8 includes four External Interrupt Inputs as selectable pin functions. The External Interrupt Inputs can optionally be used to wake up the processor from Power-down mode.

Register description The external interrupt function has four registers associated with it. The EXTINT register contains the interrupt flags, and the EXTWAKEUP register contains bits that enable individual external interrupts to wake up the microcontroller from Power-down mode. The EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters.

External Interrupt Flag register (EXTINT - 0xE01F C140) When a pin is selected for its external interrupt function, the level or edge on that pin (selected by its bits in the EXTPOLAR and EXTMODE registers) will set its interrupt flag in this register. This asserts the corresponding interrupt request to the VIC, which will cause an interrupt if interrupts from the pin are enabled. Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corresponding bits. In level-sensitive mode this action is efficacious only when the pin is in its inactive state. Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling wakeup and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise

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the event that was just triggered by activity on the EINT pin will not be recognized in the future.

Interrupt Wakeup register (INTWAKE - 0xE01F C144) Enable bits in the INTWAKE register allow the external interrupts and other sources to wake up the processor if it is in Power-down mode. The related EINTn function must be mapped to the pin in order for the wakeup process to take place. It is not necessary for the interrupt to be enabled in the Vectored Interrupt Controller for a wakeup to take place. This arrangement allows additional capabilities, such as having an external interrupt input wake up the processor from Power-down mode without causing an interrupt (simply resuming operation), or allowing an interrupt to be enabled during Powerdown without waking the processor up if it is asserted (eliminating the need to disable the interrupt if the wakeup feature is not desirable in the application) Program: Switch Interface: #include <iolpc2148.h> #include <stdio.h> #define BAUD 19200 static void delay(void ) { volatile int i,j; for (i=0;i<0x3F;i++)

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for (j=0;j<500;j++); } void main() { PINSEL0 = 0x00000000; PINSEL1 = 0x00000000; PINSEL2 = 0x00000000;

IO0DIR = 0X00000000; IO1DIR = 0Xff000000; // IO0DIR = 0XFFFFFFFF; // IO0PIN = 0XFFFFFFFF; // // while(1);

while(1) { IO1CLR = 0XFF000000; IO1SET = (~(IO0PIN & 0x00FF0000)<<0x08); delay(); } }

Led Interface:

#include<ioLPC2148.H>

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void delay() { for(int i=0x00;i<=0xff;i++) for(int j=0x00;j<=0xFf;j++); } void main() { PINSEL0=0X00000000; PINSEL1=0X00000000; IO1DIR=0XFF000000; while(1) { IO1SET=0XF0000000; delay(); IO1CLR=0XF0000000; delay(); IO1SET=0X0f000000; delay(); IO1CLR=0X0f000000; delay(); } }

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Relay Interface:

#include <iolpc2148.h> void delay() { unsigned int i,j; for(i=0;i<0xff;i++) for(j=0;j<0xff;j++); } int main (void) { IO0DIR = 0XFFFFFFFF; while(1) { IO0PIN = 0xA0000000; delay(); IO0PIN = 0x00000000; delay(); } }

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Buzzer bInterface:

#include<iolpc2148.h> #include<stdio.h> void delay() { for(int i=0;i<=0xffF;i++) for(int j=0;j<=0xff;j++); } int putchar(int a) { while (!(U0LSR&0x20)); return(U0THR=a); } void main() { IO0DIR = 0X00008000; TOP: IO0PIN=0X00008000; delay(); IO0PIN=0X00000000; delay(); goto TOP; }

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Stepper Motor Interface:

#include<iolpc2148.h> void delay_ms(); void main() { IO0DIR=0x000000F0; while(1) { IO0PIN = 0X00000090; delay_ms(); IO0PIN = 0X00000050; delay_ms(); IO0PIN = 0X00000060; delay_ms(); IO0PIN = 0X000000A0; delay_ms(); } } void delay_ms() { int i,j; for(i=0;i<0x0f;i++) for(j=0;j<1500;j++);

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UNIT III (PWM , ADC , DAC & RTC)

PWM 16.1 Features Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types. The match registers also allow: Continuous operation with optional interrupt generation on match. Stop timer on match with optional interrupt generation. Reset timer on match with optional interrupt generation. An external output for each match register with the following capabilities: Set low on match. Set high on match. Toggle on match. Do nothing on match. Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses.

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Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must "release" new match values before they can become effective. May be used as a standard timer if the PWM mode is not enabled. A 32-bit Timer/Counter with a programmable 32-bit Prescaler. Four 32-bit capture channels take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt.

Description The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2141/2/4/6/8. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. It also includes four capture inputs to save the timer value when an input signal transitions, and optionally generate an interrupt when those events occur. The PWM function is in addition to these features, and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-

overlapping PWM outputs with individual control of all three pulse widths

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and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge).

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BLOCK DIAGRAM FOR PWM

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Register description PWM Interrupt Register (PWMIR - 0xE001 4000) The PWM Interrupt Register consists of eleven bits seven for the match interrupts and four reserved for the future use. If an interrupt is generated then thecorresponding bit in the PWMIR will be high. Otherwise, the bit will be low. Writing a logic one to the corresponding IR bit will reset the interrupt. Writing a zero has no effect.

PWM Timer Control Register (PWMTCR - 0xE001 4004) The PWM Timer Control Register (PWMTCR) is used to control the operation of the PWM Timer Counter.

PWM Timer Counter (PWMTC - 0xE001 4008) The 32-bit PWM Timer Counter is incremented when the Prescale Counter reaches its terminal count. Unless it is reset before reaching its upper limit, the PWMTC will count up through the value 0xFFFF FFFF and then wrap back to the value 0x0000 0000. This event does not cause an interrupt, but a Match register can be used to detect an overflow if needed.

PWM Prescale Register (PWMPR - 0xE001 400C) The 32-bit PWM Prescale Register specifies the maximum value for the PWM Prescale Counter.

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PWM Prescale Counter register (PWMPC - 0xE001 4010) The 32-bit PWM Prescale Counter controls division of PCLK by some constant value before it is applied to the PWM Timer Counter. This allows control of the relationship of the resolution of the timer versus the maximum time before the timer overflows. The PWM Prescale Counter is incremented on every PCLK. When it reaches the value stored in the PWM Prescale Register, the PWM Timer Counter is incremented and the PWM Prescale Counter is reset on the next PCLK. This causes the PWM TC to increment on every PCLK when PWMPR = 0, every 2 PCLKs when PWMPR = 1, etc.

PWM Match Registers (PWMMR0 - PWMMR6) The 32-bit PWM Match register values are continuously compared to the PWM Timer Counter value. When the two values are equal, actions can be triggered automatically. The action possibilities are to generate an interrupt, reset the PWM Timer Counter, or stop the timer. Actions are controlled by the settings in the PWMMCR register.

PWM Match Control Register (PWMMCR - 0xE001 4014) The PWM Match Control Register is used to control what operations are performed when one of the PWM Match Registers matches the PWM Timer Counter

PWM Control Register (PWMPCR - 0xE001 404C) The PWM Control Register is used to enable and select the type of each PWM channel.

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PWM Latch Enable Register (PWMLER - 0xE001 4050) The PWM Latch Enable Register is used to control the update of the PWM Match registers when they are used for PWM generation. When software writes to the location of a PWM Match register while the Timer is in PWM mode, the value is held in a shadow register. When a PWM Match 0 event occurs (normally also resetting the timer in PWMmode), the contents of shadow registers will be transferred to the actual Match registers if the corresponding bit in the Latch Enable Register has been set. At that point, the new values will take effect and determine the course of the next PWM cycle. Once the transfer of new values has taken place, all bits of the LER are automatically cleared. Until the corresponding bit in the PWMLER is set and a PWM Match 0 event occurs, any value written to the PWM Match registers has no effect on PWM operation. ADC CONVERTER Features 10 bit successive approximation analog to digital converter (one in LPC2141/2 and two in LPC2144/6/8). Input multiplexing among 6 or 8 pins (ADC0 and ADC1). Power-down mode. Measurement range 0 V to VREF (typically 3 V; not to exceed VDDA voltage level). 10 bit conversion time 2.44 s.

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Burst conversion mode for single or multiple inputs. Optional conversion on transition on input pin or Timer Match signal. Global Start command for both converters (LPC2144/6/8 only).

Description Basic clocking for the A/D converters is provided by the VPB clock. A programmable divider is included in each converter, to scale this clock to the 4.5 MHz (max) clock needed by the successive approximation process. A fully accurate conversion requires 11 of these clocks.

Register description ADCR A/D Control Register. The ADCR register must be written to

select the operating mode before A/D conversion can occur.

ADGDR A/D Global Data Register. This register contains the ADCs DONE bit and the result of the most recent A/D Conversion

ADSTAT A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. ADGSR A/D Global Start Register. This address can be written (in the AD0 address range) to start conversions in both A/D converters simultaneously.

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ADINTEN A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.

ADDR0 A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0.

Operation Hardware-triggered conversion If the BURST bit in the ADCR is 0 and the START field contains 010-111, the ADC will start a conversion when a transition occurs on a selected pin or Timer Match signal. The choices include conversion on a specified edge of any of 4 Match signals, or conversion on a specified edge of either of 2 Capture/Match pins. The pin state from the selected pad or the selected Match signal, XORed with ADCR bit 27, is used in the edge detection logic. Interrupts An interrupt request is asserted to the Vectored Interrupt Controller (VIC) when the DONE bit is 1. Software can use the Interrupt Enable bit for the A/D Converter in the VIC to whether this assertion results in an interrupt. DONE is negated when the ADDR is read. Digital-to-Analog Converter (DAC) Features 10 bit digital to analog converter

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Resistor string architecture Buffered output Power-down mode Selectable speed vs. power DAC Register (DACR - 0xE006 C000) This read/write register includes the digital value to be converted to analog, and a bit that trades off performance vs. power. Bits 5:0 are reserved for future, higher-resolution D/A converters.

Operation Bits 19:18 of the PINSEL1 register control whether the DAC is enabled and controlling the state of pin P0.25/AD0.4/AOUT. When these bits are 10, the DAC is powered on and active. The settling times noted in the description of the BIAS bit are valid for a capacitance load on the AOUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time.

REAL TIME CLOCK (RTC) Features Measures the passage of time to maintain a calendar and clock. Ultra Low Power design to support battery powered systems. Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year.

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Dedicated 32 kHz oscillator or programmable prescaler from VPB clock. Dedicated power supply pin can be connected to a battery or to the main 3.3 V.

Description The Real Time Clock (RTC) is a set of counters for measuring time when system power is on, and optionally when it is off. It uses little power in Power-down mode. On the LPC2148, the RTC can be clocked by a separate 32.768 KHz oscillator, or by a programmable prescale divider based on the VPB clock. Also, the RTC is powered by its own power supply pin, VBAT, which can be connected to a battery or to the same 3.3 V supply used by the rest of the device.

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BLOCK DIAGRAM FOR RTC:

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Register description The RTC includes a number of registers. The address space is split into four sections by functionality. The first eight addresses are the

Miscellaneous Register Group The second set of eight locations are the Time Counter Group. The third set of eight locations contain the Alarm Register Group ILR CTC CCR CIIR AMR CTIME0 CTIME1 CTIME2 SEC MIN HOUR DOM DOW DOY MONTH YEAR Interrupt Location Register Clock Tick Counter RO Clock Control Register Counter Increment Interrupt Register Alarm Mask Register Consolidated Time Register 0 Consolidated Time Register 1 Consolidated Time Register 2 Seconds Counter Minutes Register Hours Register Day of Month Register Day of Week Register Day of Year Register Months Register R/W Years Register R/W

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ALSEC ALMIN Alarm value for Seconds Alarm value for Minutes

ALHOUR Alarm value for Seconds ALDOM ALDOW ALDOY ALMON ALYEAR PREINT Alarm value for Day of Month Alarm value for Day of Week Alarm value for Day of Year Alarm value for Months Alarm value for Year Prescaler value, integer portion

PREFRAC Prescaler value, integer portion

RTC usage notes If the RTC is used, VBAT must be connected to either pin V3 or an independent power supply (external battery). Otherwise, VBAT should be tied to the ground (VSS). No provision is made in the LPC2141/2/4/6/8 to retain RTC status upon the VBAT power loss, or to maintain time incrementation if the clock source is lost, interrupted, or altered. Since the RTC operates using one of two available clocks (the VPB clock (PCLK) or the 32 kHz signal coming from the RTCX1-2pins), any interruption of the selected clock willcause the time to drift away from the time value it would have provided otherwise. The variance could be to actual clock time if the RTC was initialized to that, or simply an error in elapsed time since the RTC was activated. While the signal from RTCX1-2 pins can be used to

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supply the RTC clock at anytime, selecting the PCLK as the RTC clock and entering the Power-down mode will cause a lapse in the time update. Also, feeding the RTC with the PCLK and altering this timebase during system operation (by reconfiguring the PLL, the VPB divider, or the RTC prescaler) will result in some form of accumulated time error. Accumulated time errors may occur in case RTC clock source is switched between the PCLK to the RTCX pins, too. Once the 32 kHz signal from RTCX1-2 pins is selected as a clock source, the RTC can operate completely without the presence of the VPB clock (PCLK). Therefore, power sensitive applications (i.e. battery powered application) utilizing the RTC will reduce the power consumption by using the signal from RTCX1-2 pins, and writing a 0 into the PCRTC bit in the PCONP power control register Program: ADC Converstion: //HEADER FILE DECLARATION #include<iolpc2148.h> #include<stdio.h> #define DESIRED_BAUDRATE 19200 #define CRYSTAL_FREQUENCY_IN_HZ 12000000 #define PCLK VPBDIV=0x01 CRYSTAL_FREQUENCY_IN_HZ // since

#define DIVISOR (PCLK/(16*DESIRED_BAUDRATE)) unsigned char arr[10]={"ADC ---->"}; unsigned int ADCresult; #define LCD_EN 0X00000800

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#define RS 0X00000100 0X02000200 #define DIOW void delay_ms() { unsigned int i,j; for(j=0;j<0xff;j++) for(i=0;i<0xff;i++); }

void busy_check() { delay_ms(); IO0CLR = RS; IO0CLR = DIOW; }

void command_write(int comm) { busy_check(); IO1PIN = comm<<16; IO0SET = LCD_EN; IO0CLR = LCD_EN; // IO1CLR = comm<<16;

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void lcd_out(unsigned char z) {

busy_check(); IO0SET = RS ; IO0CLR = DIOW; IO1PIN = (z<<16) ; //data with Rs=1 //RS =1

IO0SET = LCD_EN; IO0CLR = LCD_EN; // } void lcd_init() { command_write(0x38); command_write(0x0f); command_write(0x01); command_write(0xc0); command_write(0x80); IO1CLR = (z<<16) ; //data with Rs=1

for(int i=0;i<=9;i++)//latitude lcd_out(arr[i]);

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void ADC_init() { AD0CR_bit.SEL = 2; //enable AD0.3 only

AD0CR_bit.CLKDIV = 12000000 / 4500000; AD0CR_bit.BURST = 1; AD0CR_bit.CLKS = 0; AD0CR_bit.PDN = 1; // put A/D into continuous convert mode //11 clocks/10 bit accuracy //power up the unit //start 1st cnvrsn

AD0CR_bit.START = 0x0001; immediately

void READ_ADC() { while(AD0DR_bit.DONE == 0); ADCresult = (AD0DR>>6)& 0x3ff ; AD0DR0[6] to AD0DR0[15] printf("ADC VALUE ---->%x",ADCresult); putchar(0x0d); //END OF THE LINE putchar(0x0A); //NEW LINE COMMAND //wait until conversion done // convesion data holds

void ADC_display() {

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command_write(0x8a); lcd_out((ADCresult/1000)+0x30); lcd_out(((ADCresult%1000)/100)+0x30); lcd_out((((ADCresult%1000)%100)/10)+0x30); lcd_out((((ADCresult%1000)%100)%10)+0x30);

void Arm_Uart0_Init() {

//UART Config.

U0LCR=0x83; Register. // word length. // transmission. 1

//

U0LCR:

UART0

Line

Control

0x83: enable Divisor Latch access, set 8-bit

stop

bit,

no

parity,

disable

break

VPBDIV=0x01; PCLK = processor clock .

// VPBDIV: VPB bus clock divider 0x01:

U0DLL=DIVISOR&0xFF; (LSB). U0DLM=DIVISOR>>8; (MSB). U0LCR=0x03 ; Register //

// U0DLL:

UART0

Divisor

Latch

// U0DLM:

UART0

Divisor

Latch

U0LCR:

UART0

Line

Control

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// 0x03: same as above, but disable Divisor Latch access. // And same time U0THR (Transmitting register writing)holding the data. U0FCR=0x05 ; // U0FCR: UART0 FIFO Control Register

// 0x05: Clear Tx FIFO and enable Rx and Tx FIFOs }

int putchar(int a) { while (!(U0LSR&0x20)); return(U0THR=a);

void main() {

PINSEL0=0x00000005; PINSEL1=0x01000000; PINSEL2=0x00000000;

IO0DIR =0x5FFF7FFF; IO1DIR =0xFFFFFFFF;

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IO0CLR = 0X00000800 ; IO1PIN =0X00000000; IO0PIN =0X00000000;

Arm_Uart0_Init(); lcd_init(); ADC_init(); while(1) { READ_ADC(); delay_ms(); ADC_display(); } }

//UAET INIT FUNCTION //LCD INIT FUNCTION //ADC INIT FUNCTION

//READ THE ADC OUTPUT

//ADC VALUE DISPLAY TO THE LCD

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UNIT IV (I2C & UART) I2C interfaces I2C0 and I2C1 Features Standard I2C compliant bus interfaces that may be configured as Master, Slave, or Master/Slave. Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. Programmable clock to allow adjustment of I2C transfer rates. Bidirectional data transfer between masters and slaves. Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. The I2C-bus may be used for test and diagnostic purposes.

11.2 Applications Interfaces to external I2C standard parts, such as serial RAMs, LCDs, tone generators,etc.

11.3 Description

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A typical I2C-bus configuration is shown in Figure 24. Depending on the state of the direction bit (R/W), two types of data transfers are possible on the I2C-bus: Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows the data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the I2C-bus will not be released. The LPC2148 I2C interfaces are byte oriented, and have four operating modes: master transmitter mode, master receiver mode, slave transmitter mode and slave receiver mode.

I2C operating modes In a given application, the I2C block may operate as a master, a slave, or both. In the slave mode, the I2C hardware looks for its own slave address and the general call address. If one of these addresses is detected, an interrupt is requested. If the processor wishes to become the bus master,

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the hardware waits until the bus is free before the master mode is entered so that a possible slave operation is not interrupted. If bus arbitration is lost in the master mode, the I2C block switches to the slave mode immediately and can detect its own slave address in the same serial transfer. 1 Master Transmitter mode In this mode data is transmitted from master to slave. Before the master transmitter mode can be entered, the I2CONSET register must be initialized . I2CEN must be set to 1 to enable the I2C function. If the AA bit is 0, the I2C interface will not acknowledge any address when another device is master of the bus, so it can not enter slave mode. The STA, STO and SI bits must be 0. The SI Bit is cleared by writing 1 to the SIC bit in the I2CONCLR register. The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this mode the data direction bit (R/W) should be 0 which means Write. The first byte transmitted contains the slave address and Write bit. Data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is

received..START and STOP conditions are output to indicate the beginning and the end of a serial transfer. The I2C interface will enter master transmitter mode when software sets the STA bit. The logic will send the START condition as soon as the bus is free. After the START condition is transmitted, the SI bit is set, and the status code in the I2STAT register is 0x08. This status code is used to vector to a state service routine which will load the slave address and Write bit to the I2DAT register, and then clear the SI bit. SI is cleared by writing a 1 to the SIC bit in the I2CONCLR register. When the slave address and R/W bit have been transmitted and an

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acknowledgment bit has been received, the SI bit is set again, and the possible status codes now are 0x18, 0x20, or 0x38 for the master mode, or 0x68, 0x78, or 0xB0 if the slave mode was enabled (by setting AA to 1).

Master Receiver mode In the master receiver mode, data is received from a slave transmitter. The transfer is initiated in the same way as in the master transmitter mode. When the START condition has been transmitted, the interrupt service routine must load the slave address and the data direction bit to the I2C Data register (I2DAT), and then clear the SI bit. In this case, the data direction bit (R/W) should be 1 to indicate a read.

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Slave Receiver mode In the slave receiver mode, data bytes are received from a master transmitter. To initialize the slave receiver mode, user write the Slave Address register (I2ADR) and write the I2C Control Set register (I2CONSET) as shown in Table 134. I2EN must be set to 1 to enable the I2C function. AA bit must be set to 1 to acknowledge its own slave address or the general call address. The STA, STO and SI bits are set to 0.

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Slave Transmitter mode The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit will be 1, indicating a read operation. Serial data is transmitted via SDA while the serial clock is input through SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. In a given application, I2C may operate as a master and as a slave. In the slave mode, the I2C hardware looks for its own slave address and the general call address. If one of these addresses is detected, an interrupt is requested. When the microcontrollers wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. If bus arbitration is lost in the master mode, the I2C interface switches to the slave mode immediately and can detect its own slave address in the same serial transfer.

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I2C Implementation and operation Figure shows how the on-chip I2C-bus interface is implemented, and the following text describes the individual blocks.

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I2C BLOCK DIAGRAM

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1 Input filters and output stages Input signals are synchronized with the internal clock, and spikes shorter than three clocks are filtered out. 2 Address Register, I2ADDR This register may be loaded with the 7-bit slave address (7 most significant bits) to which the I2C block will respond when programmed as a slave transmitter or receiver. The LSB (GC) is used to enable general call address (0x00) recognition. 3. Comparator The comparator compares the received 7-bit slave address with its own slave address (7 most significant bits in I2ADR). It also compares the first received 8-bit byte with the general call address (0x00). If an equality is found, the appropriate status bits are set and an interrupt is requested. 4 Shift register, I2DAT This 8-bit register contains a byte of serial data to be transmitted or a byte which has just been received. Data in I2DAT is always shifted from right to left; the first bit to be transmitted is the MSB (bit 7) and, after a byte has been received, the first bit of received data is located at the MSB of I2DAT. While data is being shifted out, data on the bus is simultaneously being shifted in; I2DAT always contains the last byte present on the bus. Thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in I2DAT. 5 Arbitration and synchronization logic In the master transmitter mode, the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the I2C-bus. If

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another device on the bus overrules a logic1 and pulls the SDA line low, arbitration is lost, and the I2C block immediately changes from master transmitter to slave receiver. The I2C block will continue to output clock pulses (on SCL) until transmission of the current serial byte is complete. Arbitration may also be lost in the master receiver mode. Loss of arbitration in this mode can only occur while the I2C block is returning a not acknowledge: (logic 1) to the bus. Arbitration is lost when another device on the bus pulls this signal LOW. Since this can occur only at the end of a serial byte, the I2C block generates no further clock pulses. A slave may stretch the space duration to slow down the bus master. The space duration may also be stretched for handshaking purposes. This can be done after each bit or after a complete byte transfer. the I2C block will stretch the SCL space duration after a byte has been transmitted or received and the acknowledge bit has been transferred. The serial interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is cleared. 6 Serial clock generator This programmable clock pulse generator provides the SCL clock pulses when the I2C block is in the master transmitter or master receiver mode. It is switched off when the I2C block is in a slave mode. The I2C output clock frequency and duty cycle is programmable via the I2C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH registers for details. The output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other SCL clock sources as described above. 7 Timing and control The timing and control logic generates the timing and control signals for serial byte handling. This logic block provides the shift pulses for I2DAT, enables the comparator,generates and detects start and stop conditions,

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receives and transmits acknowledge bits, controls the master and slave modes, contains interrupt request logic, and monitors the I2C-bus status. 8 Control register, I2CONSET and I2CONCLR The I2C control register contains bits used to control the following I2C block functions: start and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition, and acknowledgment. The contents of the I2C control register may be read as I2CONSET. Writing to I2CONSET will set bits in the I2C control register that correspond to ones in the value written. Conversely, writing to I2CONCLR will clear bits in the I2C control register that correspond to ones in the value written.

9 Status decoder and Status register The status decoder takes all of the internal status bits and compresses them into a 5-bit code. This code is unique for each I2C-bus status. The 5-bit code may be used to generate vector addresses for fast processing of the various service routines. Each service routine processes a particular bus status. There are 26 possible bus states if all four modes of the I2C block are used. The 5-bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set (by hardware) and remains stable until the interrupt flag is cleared by software. The three least significant bits of the status register are always zero. If the status code is used as a vector to service routines, then the routines are displaced by eight address locations. Eight bytes of code is

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sufficient for most of the service routines

Universal Asynchronous Receiver/Transmitter 0 (UART0) 9.1 Features 16 byte Receive and Transmit FIFOs Register locations conform to 550 industry standard. Receiver FIFO trigger points at 1, 4, 8, and 14 bytes. Built-in fractional baud rate generator with autobauding capabilities. Mechanism that enables software and hardware flow control

implementation.

Register description 1.UART0 Receiver Buffer Register (U0RBR - 0xE000 C000, when DLAB = 0, Read Only) The U0RBR is the top byte of the UART0 Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the oldest received data bit. If the character received is less than 8 bits, the unused MSBs are padded with zeroes. The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the U0RBR. The U0RBR is always Read Only. Since PE, FE and BI

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bits correspond to the byte sitting on the top of the RBR FIFO (i.e.the one that will be read in the next read from the RBR), the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the U0LSR register, and then to read a byte from the U0RBR.

2 UART0 Transmit Holding Register (U0THR - 0xE000 C000, when DLAB = 0, Write Only) The U0THR is the top byte of the UART0 TX FIFO. The top byte is the newest character in the TX FIFO and can be written via the bus interface. The LSB represents the first bit to transmit. The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the U0THR. The U0THR is always Write Only.

3 UART0 Divisor Latch Registers (U0DLL - 0xE000 C000 and U0DLM 0xE000 C004, when DLAB = 1) The UART0 Divisor Latch is part of the UART0 Fractional Baud Rate Generator and holds the value used to divide the clock supplied by the fractional prescaler in order to produce the baud rate clock, which must be 16x the desired baud rate (Equation 1). The U0DLL and U0DLM registers together form a 16 bit divisor where U0DLL contains the lower 8 bits of the divisor and U0DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in U0LCR must be one in order to access the UART0 Divisor Latches.

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4.UART0 Fractional Divider Register (U0FDR - 0xE000 C028) The UART0 Fractional Divider Register (U0FDR) controls the clock prescaler for the baud rate generation and can be read and written at users discretion. This pre-scaler takes the VPB clock and generates an output clock per specified fractional requirements. This register controls the clock pre-scaler for the baud rate generation. The reset value of the register keeps the fractional capabilities of UART0 disabled making sure that UART0 is fully software and hardware compatible with UARTs not equipped with this feature. UART0 baudrate can be calculated as: Where PCLK is the peripheral clock, U0DLM and U0DLL are the standard UART0 baud rate divider registers, and DIVADDVAL and MULVAL are UART0 fractional baudrate generator specific parameters. The value of MULVAL and DIVADDVAL should comply to the following conditions: 1. 0 < MULVAL 15 2. 0 DIVADDVAL 15

UART0 baudrate calculation Example 1: Using UART0baudrate formula from above, it can be determined that system with PCLK = 20 MHz, U0DL = 130 (U0DLM = 0x00 and U0DLL = 0x82), DIVADDVAL = 0 and MULVAL = 1 will enable UART0 with UART0baudrate = 9615 bauds.

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Example 2: Using UART0baudrate formula from above, it can be determined that system with PCLK = 20 MHz, U0DL = 93 (U0DLM = 0x00 and U0DLL = 0x5D), DIVADDVAL = 2 and MULVAL = 5 will enable UART0 with UART0baudrate = 9600 bauds.

5.UART0 Interrupt Enable Register (U0IER - 0xE000 C004, when DLAB = 0) The U0IER is used to enable UART0 interrupt sources.

6.UART0 Interrupt Identification Register (U0IIR - 0xE000 C008, Read Only) The U0IIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an U0IIR access. If an interrupt occurs during an U0IIR access, the interrupt is recorded for the next U0IIR access. Given the status of U0IIR[3:0], an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt. The U0IIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine.

7.UART0 FIFO Control Register (U0FCR - 0xE000 C008) The U0FCR controls the operation of the UART0 Rx and TX FIFOs.

8.UART0 Line Control Register (U0LCR - 0xE000 C00C)

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The U0LCR determines the format of the data character that is to be transmitted or received.

9.UART0 Line Status Register (U0LSR - 0xE000 C014, Read Only) The U0LSR is a read-only register that provides status information on the UART0 TX and RX blocks.

10.UART0 Scratch pad register (U0SCR - 0xE000 C01C) The U0SCR has no effect on the UART0 operation. This register can be written and/or read at users discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the U0SCR has occurred.

11.UART0 Auto-baud Control Register (U0ACR - 0xE000 C020) The UART0 Auto-baud Control Register (U0ACR) controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at users discretion.

12.UART0 Transmit Enable Register (U0TER - 0xE000 C030) LPC2141/2/4/6/8s U0TER enables implementation of software flow control. When TXEn=1, UART0 transmitter will keep sending data as long as they are available. As soon as TXEn becomes 0, UART0 transmission will stop

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Architecture The architecture of the UART0 is shown below in the block diagram.

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The VPB interface provides a communications link between the CPU or host and the UART0. The UART0 receiver block, U0RX, monitors the serial input line, RXD0, for valid input. The UART0 RX Shift Register (U0RSR) accepts valid characters via RXD0. After a valid character is assembled in the U0RSR, it is passed to the UART0 RX Buffer Register FIFO to await access by the CPU or host via the generic host interface The UART0 transmitter block, U0TX, accepts data written by the CPU or host and buffers the data in the UART0 TX Holding Register FIFO (U0THR). The UART0 TX Shift Register (U0TSR) reads the data stored in the U0THR and assembles the data to transmit via the serial output pin, TXD0. The UART0 Baud Rate Generator block, U0BRG, generates the timing enables used by the UART0 TX block. The U0BRG clock input source is the VPB clock (PCLK). The main clock is divided down per the divisor specified in the U0DLL and U0DLM registers. This divided down clock is a 16x oversample clock, NBAUDOUT. The interrupt interface contains registers U0IER and U0IIR. The interrupt interface receives several one clock wide enables from the U0TX and U0RX blocks. Status information from the U0TX and U0RX is stored in the U0LSR. Control information for the U0TX and U0RX is stored in the U0LCR.

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UNIT V (RTOS and C/OS II) Foreground/Background: Systems which do not use a RTOS are generally designed as shown in figure 1. These systems are called foreground/background. An

application consist of an infinite loop which calls application modules to perform the desired operations. The modules are executed sequentially (background) with interrupt service routines (ISRs) handling

asynchronous events (foreground). Critical operations must be performed by the ISRs to ensure that they are dealt with in a timely fashion. Because of this, ISRs have a tendency to take longer than they should. Information for a background module made available by an ISR is not processed until the background routine gets its turn to execute. The latency in this case depends on how long the background loop takes to execute. The main functions of an OS include: In a multitasking operating system where multiple programs can be running at the same time, the operating system determines which applications should run in what order and how much time should be allowed for each application before giving another application a turn. It manages the sharing of internal memory among multiple applications.It handles and monitors input and output to and from attached hardware devices, such as hard disks, printers, and dial-up ports. It sends messages to each application or interactive user (or to asystem operator) about the status of operation and any errors that may have occurred.

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It can offload the management of what are called /batch/ jobs (forexample, printing) so that the initiating application is freed from this work. On computers that can provide parallel processing, an operating system can manage how to divide the program so that it runs on more than one processor at a time.Scheduling the activities of the CPU and resources to achieve efficiency and prevention of deadlock. DEFINITION OF KERNAL:

The kernel is the essential center of a computer operating system, the core that provides basic services for all other parts of the operating system. A synonym is nucleus. A kernel can be contrasted with a shell, the outermost part of an operating system that interacts with user commands. Kernel and shell are terms used more frequently in Unix operating systems than in IBM mainframe or Microsoft Windows systems.

Typically, a kernel (or any comparable center of an operating system) includes an interrupt handler that handles all requests or completed I/O operations that compete for the kernel's services, a scheduler that determines which programs share the kernel's processing time in what order, and a supervisor that actually gives use of the computer to each process when it is scheduled. A kernel may also include a manager of the operating system's address spaces in memory or storage, sharing these among all components and other users of the kernel's services. A kernel's services are requested by other parts of the operating system or by application programs through a specified set of program interfaces sometimes known as system calls.

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Because the code that makes up the kernel is needed continuously, it is usually loaded into computer storage in an area that is protected so that it will not be overlaid with other less frequently used parts of the operating system.

Context switch: A context switch is the computing process of saving and restoring the state (context) of a CPU such that multiple processes can share a single CPU resource. The context switch is an essential feature of a multitasking operating system. Context switches are usually time consuming and much of the design of operating systems is to minimize the time of context switches.

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A context switch can mean a register context switch, a task context switch, a thread context switch, or a process context switch. What will be switched is determined by the processor and the operating system. The scheduler is the part of the operating systems that manage context switching, it perform context switching in one of the following conditions:

1. Multitasking: One process needs to be switched out of (termed "yield" which means "give up") the CPU so another process can run. Within a preemptive multitasking operating system, the scheduler allows every task (according to its priority level) to run for some certain amount of time, called its time slice where a timer interrupt triggers the operating system to schedule another process for execution instead.

If a process will wait for one of the computer resources or will perform an I/O operation, the operating system schedules another process for execution instead.

2. Interrupt handling: Some CPU architectures (like the Intel x86 architecture) are interrupt driven. When an interrupt occurs, the scheduler calls its interrupt handler in order to serve the interrupt after switching contexts; the scheduler suspended the currently running process till executing the interrupt handler.

3. User and kernel mode switching: When a transition between user mode and kernel mode is required in an operating system, a context switch is not necessary; a mode transition is not by itself a context switch. However, depending on the operating system, a context switch may also take place at this time.

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Context switching can be performed primarily by software or hardware. Some CPUs have hardware support for context switches, else if not, it is performed totally by the operating system software. In a context switch, the state of a process must be saved somehow before running another process, so that, the scheduler resume the execution of the process from the point it was suspended; after restoring its complete state before running it again. In a context switch, the state of the first process must be saved somehow, so that, when the scheduler gets back to the execution of the first process, it can restore this state and continue.

The state of the process includes all the registers that the process may be using, especially the program counter, plus any other operating system specific data that may be necessary. This data is usually stored in a data structure called a process control block (PCB), or switchframe.

Now, in order to switch processes, the PCB for the first process must be created and saved. The PCBs are sometimes stored upon a per-process stack in kernel memory (as opposed to the user-mode stack), or there may be some specific operating system defined data structure for this information.

Since the operating system has effectively suspended the execution of the first process, it can now load the PCB and context of the second process. In doing so, the program counter from the PCB is loaded, and thus execution can continue in the new process. New processes are chosen from a queue or queues. Process and thread priority can influence which process continues execution, with processes of the highest priority checked first for ready threads to execute.

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Context Switch Definition: A context switch (also sometimes referred to as a process switch or a task switch) is the switching of the CPU (central processing unit) from one process or thread to another. A process (also sometimes referred to as a task) is an executing (i.e., running) instance of a program. In Linux, threads are lightweight processes that can run in parallel and share an address space (i.e., a range of memory locations) and other resources with their parent processes (i.e., the processes that created them).

A context is the contents of a CPU's registers and program counter at any point in time. A register is a small amount of very fast memory inside of a CPU (as opposed to the slower RAM main memory outside of the CPU) that is used to speed the execution of computer programs by providing quick access to commonly used values, generally those in the midst of a calculation. A program counter is a specialized register that indicates the position of the CPU in its instruction sequence and which holds either the address of the instruction being executed or the address of the next instruction to be executed, depending on the specific system.

Context switching can be described in slightly more detail as the kernel (i.e., the core of the operating system) performing the following activities with regard to processes (including threads) on the CPU: (1) suspending the progression of one process and storing the CPU's state (i.e., the context) for that process somewhere in memory, (2) retrieving the context of the next process from memory and restoring it in the CPU's registers and

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(3) returning to the location indicated by the program counter (i.e., returning to the line of code at which the process was interrupted) in order to resume the process.

A context switch is sometimes described as the kernel suspending execution of one process on the CPU and resuming execution of some other process that had previously been suspended. Although this wording can help clarify the concept, it can be confusing in itself because a process is, by definition, an executing instance of a program. Thus the wording suspending progression of a process might be preferable. Basic Critical Sections Critical section We need some way of arranging things so that a writer's modification appears "atomic" -- a reader always sees only the (consistent) old version, or the (consistent) new version, never some partially-modified inconsistent state. There are a variety of ways to avoid this problem, including:

Design the data structure so that the writer can update it in such a way that it is always in a consistent state. This requires hardware that supports atomic primitives powerful enough to update the data structure from one consistent state to the next consistent state in one atomic operation. Wikipedia:lock-free and wait-free algorithms.

Have the writer turn off the task scheduler while it is updating the data structure. Then the only time the reader could possibly see the data structure, the data structure is in a consistent state.

Have the writer turn off all interrupts (including the timer interrupt that kicks off the task scheduler) while it is updating the data

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structure. Then the only time the reader could possibly see the data structure, the data structure is in a consistent state. But this makes interrupt latency much worse.

Use a "lock" associated with each data structure. When the reader sees that the writer is updating the data structure, have the reader tell the task scheduler to run some other process until the writer is finished. (There are many kinds of locks).

Use a "monitor" associated with every routine that uses a data structure.

Whenever a lock or CS mechanism is called, it is important that the RTOS disable the scheduler, to prevent the atomic operations from being preempted and executed incorrectly. Remember that embedded systems need to be stable and robust, so we cannot risk having the operating system itself being preempted while it is trying to create a lock or critical section. If we have a function called DisableScheduler( ), we can call that function to disable the scheduler before any atomic operation is attempted, and we can then have a function called EnableScheduler( ) to restore the scheduler, and continue with normal operation. Event flag: An event flag is a process synchronization primitive in the OpenVMS operating system. It has two possible states, set or cleared. The following basic primitive operations are provided: * * Set Clear event event flag flag ($SETEF) ($CLREF)

* Wait for event flag ($WAITFR)--if the flag was clear, this would make the process wait until it was set.

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If the flag was already set, this would immediately return, leaving the flag set. Intertask Communication Information transfer is sometimes needed among tasks or between the task and the ISR. Information transfer can be also called intertask communication. There are two ways to implement it: through the global variable or by sending messages. When using the global variable, it is important to ensure that each task or ISR possesses the variable alone. The only way to ensure it is enabling the interrupt. When two tasks share one variable, each task possesses the variable alone through firstly enabling then disabling the interrupt or by the semaphore. Please note that a task can communicate with the ISR only through the global variable and the task wont know when the global variable has been modified by the ISR (unless the ISR sends signals to the task in manner of semaphore or the task keeps searching the variables value). In this case, CooCox CoOS supplies the mailboxes and the message queues to avoid the problems above. * Mailboxes System or the user code can send a message by the core services. A typical mail message, also known as the exchange of information, refers to a task or an ISR using a pointer variable, through the core services to put a message (that is, a pointer) into the mailbox. Similarly, one or more tasks can receive this message by the core services. The tasks sending and receiving the message promise that the content that the pointer points to is just that piece of message.

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The mailbox of CooCox CoOS is a typical message mailbox which is composed of two parts: one is the information which expressed by a pointer of void; the other is the waiting list which composed of the tasks waiting for this mailbox. The waiting list supports two kinds of sorting: FIFO and preemptive priority. The sorting mode is determined by the user when creating the mailbox. You can create a mailbox by calling CoCreateMbox ( ) in CooCox CoOS. After being created successfully, there wont be any message inside. You can send a message to the mailbox by calling CoPostMail ( ) or isr_PostMail ( ) respectively in a task or the ISR. You can also get a message from the mailbox by calling CoPendMail ( ) or CoAcceptMail ( ). * Message Queues Message queue is just an array of mailboxes used to send messages to the task in fact. The task or the ISR can put multiple messages (that is, the pointers of the message) to the message queue through the core services. Similarly, one or more tasks can receive this message by the core services. The tasks sending and receiving the message promise that the content that the pointer points to is just that piece of message. The difference between the mailbox and the message queue is that the former can store only one piece of message while the latter can store multiple of it. The maximum pieces of message stored in a queue are determined by the user when creating the queue in CooCox CoOS. In CooCox CoOS, message queue is composed of two parts: one is the struct which pointed to the message queue; the other is the waiting list which composed of the tasks waiting for this message queue. The waiting list supports two kinds of sorting: FIFO and preemptive

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priority. The sorting mode is determined by the user when creating the message queue. Mutual exclusion? Mutual exclusion (often abbreviated to mutex) algorithms are used in concurrent programming to avoid the simultaneous use of a common resource, such as a global variable, by pieces of computer code called critical sections. A critical section is a piece of code where a process or thread accesses a common resource. The critical section by itself is not a mechanism or algorithm for mutual exclusion. A program, process, or thread can have the critical section in it without any mechanism or algorithm, which implements mutual exclusion. Examples of such resources are fine-grained flags, counters or queues, used to communicate between code that runs concurrently, such as an application and its interrupt handlers. The synchronization of access to those resources is an acute problem because a thread can be stopped or started at any time. Non pre-Emptive Scheduling

A scheduling discipline is non preemptive if, once a process has been given the CPU it cannot be taken away from that process. Following are some characteristics of non preemptive scheduling:

In non preemptive system, short jobs are made to wait by longer jobs but the overall treatment of all processes is fair.

In non preemptive system, response times are more predictable because incoming high priority jobs can not displace waiting jobs.

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In non preemptive scheduling, a scheduler executes jobs in the following two situations:

When a process switches from running state to the waiting state. When a process terminates.

Nonpreemptive Scheduling:

Tasks remain active till completion Scheduling decisions only made after task completion.

Benefits: Reasonable when task execution times ~= task switching times.

Less computational resources needed for scheduling Disadvantages: Can leads to starvation (not met the deadline) especially for those real time tasks ( or high priority tasks).

Non pre-Emptive Vs Preemptive Scheduling:

Non-Preemptive: Non-preemptive algorithms are designed so that once a process enters the running state(is allowed a process), it is not removed from the processor until it has completed its service time ( or it explicitly yields the processor).

context_switch() is called only when the process terminates or blocks.

Preemptive: Preemptive algorithms are driven by the notion of prioritized computation. The process with the highest priority should

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always be the one currently using the processor. If a process is currently using the processor and a new process with a higher priority enters, the ready list, the process on the processor should be removed and returned to the ready list until it is once again the highest-priority process in the system.

context_switch() is called even when the process is running usually done via a timer interrupt.

Round-robin scheduling? Round-robin (RR) is one of the simplest scheduling algorithms for processes in an operating system, which assigns time slices to each process in equal portions and in circular order, handling all processes without priority. Round-robin scheduling is both simple and easy to implement, and starvation-free. Round-robin scheduling can also be applied to other scheduling problems, such as data packet scheduling in computer networks. The name of the algorithm comes from the round-robin principle known from other fields, where each person takes an equal share of something in turn.

What is the Scheduler? The "task scheduler" (or often "scheduler") is the part of the software that schedules which task to run next. The scheduler is the part of the software that chooses which task to run next.

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The scheduler is arguably the most difficult component of an RTOS to implement. Schedulers maintain a table of the current state of each task on the system, as well as the current priority of each task. The scheduler needs to manage the timer too. In general, there are 3 states that a task can be in: 1. Active. There can be only 1 active thread on a given processor at a time. 2. Ready. This task is ready to execute, but is not currently executing. 3. Blocked. This task is currently waiting on a lock or a critical section to become free. Some systems even allow for other states: 1. Sleeping. The task has voluntarily given up control for a certain period of time.

2. Low-Priority. This task only runs when all other tasks are blocked or sleeping. There are 2 ways the scheduler is called: * the current task voluntarily yield()s to the scheduler, calling the scheduler directly, or * the current task has run "long enough", the timer hardware interrupts it, and the timer interrupt routine calls the scheduler. Semaphore? In computer science, a semaphore is a protected variable or abstract data type which constitutes the classic method for restricting access to shared resources such as shared memory in a parallel programming

environment. A counting semaphore is a counter for a set of available

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resources, rather than are a the locked/unlocked classic solution flag to of a single race resource.Semaphores preventing

conditions in the dining philosophers problem, although they do not prevent resource deadlocks what is the difference between critical section, mutex and semophore? A semaphore is an object that can have a state of ON or OFF. It is used to communicate between two or more tasks.If you have two tasks, A and B, A can set a semaphore to ON, kick off task B, when task B has finished it can set the semaphore to OFF then task A knows that B is finished. A Mutex (mutual exclusion) is like semaphore in that it has two states, but in reality they are more like LOCKED and UNLOCKED. Typically, with a Mutex, you have a Lock and and Unlock function. When a task calls the Lock function, it either immediately locks the mutex if it was unlocked or it causes the task to wait until the mutex is unlocks by another task. A critical section is a mutex that is tied to a block of code. It's purpose is to only allow one task at a time be in a block of code.

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Shared resource: In computing, a shared resource or network share is a device or piece of information on a computer that can be remotely accessed from another computer, typically via a local area network or an enterprise Intranet, as if it were a resource in the local machine.

Examples are shared file access (also known as disk sharing and folder sharing), shared printer access (printer sharing), shared scanner access, etc. The shared resource is called a shared disk (also known as mounted disk), shared drive volume, shared folder, shared file, shared document, shared printer or shared scanner.

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The term file sharing traditionally means shared file access, especially in the context of operational systems and LAN services, for example in Microsoft Windows documentation. Though, as BitTorrent and similar protocols became available in the early 2000's, the term file sharing increasingly has become associated with peer-to-peer file sharing over the Internet. Shared file and printer access within a local area network may either be based on a centralized file server or print server, sometimes denoted client-server paradigm, or on a decentralized model, sometimes denoted peer-to-peer network topology or Workgroup (computer networking). In client-server communications, a client process on the local user computer takes the initiative to start the communication, while a server process on the file server or print server remote computer passively waits for requests to start a communication session. In a peer-to-peer network, any computer can be server as well as client. Task: Task is "an execution path through address space". In other words, a set of program instruction s is loaded in memory . The address registers have been loaded with the initial address of the program. At the next clock cycle , the CPU will start execution, in accord with the program. The sense is that some part of 'a plan is being accomplished'. As long as the program remains in this part of the address space, the task can continue, in principle, indefinitely, unless the program instructions contain a halt , exit, or return. In the computer field, "task" has the sense of a real-time application, as distinguished from process, which takes up space (memory), and execution time. See operating system . Both "task" and " process " should

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be distinguished from event, which takes place at a specifictime and place, and which can be planned for in a computer program. In a computer graphic user interface (GUI), an event can be as simple as a mouse click which is displayed on a certain part of the canvas . In older text-based computer interfaces, an event might be a keystroke.

For a real-time system, a computer may be too slow, so dedicated hardware solutions for performing a task may be employed, rather than a pure software solution. This hardware might be a digital, or an analog circuit, or a hybrid of many technologies.

For many commercial businesses, a person may be an integral part of the solution. In this case, the entire "person(s) + (hardware/software) system" serve as the agentof the task which is being performed.

Task scheduling algorithm: The assignment of start and end times to a set of tasks, subject to certain constraints. Constraints are typically either time constraints (the payload must be installed before the payload bay doors are closed) or resource constraints (this task requires a small crane and a crane operator). In the case where the tasks are programs to run concurrently on a computer, this is also known as multitasking.

Task interfaces to each other : The only multitasking problem that multitasked systems have to solve is that they cannot use the same data or hardware at the same time. There are two notably successful designs for coping with this problem:

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Semaphore Message passing

A semaphore is either locked, or unlocked. When locked a queue of tasks wait for the semaphore. Problems with semaphore designs are well known: priority inversion and deadlocks . In priority inversion, a high priority task waits because a low priority task has a semaphore. A typical solution is to have the task that has a semaphore run at the priority of the highest waiting task. In a deadlock, two tasks lock two semaphores, but in the opposite order. This is usually solved by careful design, implementing queues, or by having floored semaphores (which pass control of a semaphore to the higher priority task on defined conditions).

The other solution is to have tasks send messages to each other. These have exactly the same problems: Priority inversion occurs when a task is working on a low-priority message, and ignores a higher-priority message in its in-box. Deadlocks happen when two tasks wait for the other to respond.

Although their real-time behavior is less crisp than semaphore systems, message-based systems usually unstick themselves, and are generally better-behaved than semaphore systems. Task State: The operating system manages the Task Control Blocks by keeping track of the status or state of each task. A task can typically be in any one of the following states:

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* Executing * Ready * Suspended Executing state Ready state Suspended (of blocked) state - the task that is actually running - tasks that are ready to execute - tasks that are waiting on a

particular resource, and thus are not ready

Task state is "an execution path through address space". In other words, a set of program instruction s is loaded in memory . The address registers have been loaded with the initial address of the program. At the next clock cycle , the CPU will start execution, in accord with the program. The sense is that some part of 'a plan is being accomplished'. As long as the program remains in this part of the address space, the task can continue, in principle, indefinitely, unless the program instructions contain a halt , exit, or return.

In the computer field, "task" has the sense of a real-time application, as distinguished from process, which takes up space (memory), and execution time. See operating system . Both "task" and " process " should be distinguished from event, which takes place at a specifictime and place, and which can be planned for in a computer program. In a computer graphic user interface (GUI), an event can be as simple as a mouse click which is displayed on a certain part of the canvas .In older text-based computer interfaces, an event might be a keystroke.

For a real-time system, a computer may be too slow, so dedicated hardware solutions for performing a task may be employed, rather than a

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pure software solution. This hardware might be a digital, or an analog circuit, or a hybrid of many technologies. For many commercial businesses, a person may be an integral part of the solution. In this case, the entire "person(s) + (hardware/software) system" serve as the agentof the task which is being performed. Task control block: A Process Control Block (PCB, also called Task Control Block or Task Struct) is a data structure in the operating system kernel containing the information needed to manage a particular process. The PCB is "the manifestation of a process in an operating system". Implementations differ, but in general a PCB will include, directly or indirectly: * The identifier of the process (a process identifier, or PID) * Register values for the process including, notably, the Program Counter value for the process. Also Stack Pointer. * The address space for the process * Priority (in which higher priority process gets first preference. eg., nice value on Unix operating systems) * Process accounting information, such as when the process was last run, how much CPU time it has accumulated, etc. * Pointer to the next PCB i.e. pointer to the PCB of the next process to run * I/O Information (i.e. I/O devices allocated to this process, list of opened files, etc) During a context switch, the running process is stopped and another process is given a chance to run. The kernel must stop the execution of

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the running process, copy out the values in hardware registers to its PCB, and update the hardware registers with the values from the PCB of the new process. INTRODUCTION: C/OS-II

MicroC/OS-II (commonly termed C/OS-II or uC/OS-II), is a low-cost priority-based pre-emptive real time multitasking operating system kernel for microprocessors, written mainly in the C programming language. It is mainly intended for use in embedded systems.

Designation II is used because it is a second generation of a kernel originally published (with source code) in a two-part 1992 article in Embedded Systems Programming magazine and the book C/OS The Real-Time Kernel by Jean J. Labrosse (ISBN 0-87930-444-8). The author intended at first simply to describe the internals of a portable operating system he had developed for his own use, but the story later took a commercial turn for him.

uC/OS-II is currently maintained by Micrium Inc. and can be licensed on a per product or product line basis. Use of the operating system is free for educational non-commercial use. Additionally, Micrium provides other middleware software products such as uC/OS-View, uC/CAN, uC/TCP-IP, uC/FS, uC/GUI, uC/MOD-BUS, uC/LCD, uC/USB (Mass Storage Device and Bulk) and a large assortment of uC/TCP-IP applications such as client software for DHCP, POP3, SNTP, FTP, TFTP, DNS, SMTP, and TTCP. Server software includes HTTP, FTP, and TFTP. PPP is also available.

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Micro C/OS using ARM:

C/OS-II, The Real-Time Kernel is a highly portable, ROMable, very scalable, preemptive real-time, multitasking kernel (RTOS) for

microprocessors and microcontrollers. C/OS-II can manage up to 250 application tasks. A validation suite has been developed for C/OS-II and provides all the documentation necessary to prove that C/OS-II is suitable for Safety Critical Systems common to Aviation and Medical products. Although this feature may not be applicable to your needs, it does prove that C/OS-II is a very robust RTOS.

C/OS-II runs on a large number of processor architectures and ports. The vast number of ports should convince you that C/OS-II is truly very portable and thus will most likely be ported to new processors as they become available.

C/OS-II can be scaled to only contain the features you need for your application and thus provide a small footprint. Depending on the processor, on an ARM (Thumb mode) C/OS-II can be reduced to as little as 6K bytes of code space and 500 bytes of data space (excluding stacks).

The execution time for most of the services provided by C/OS-II is both constant and deterministic. This means that the execution times do not depend on the number of tasks running in your application. C/OS-II has

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been used in hundreds of products from companies all around the world are also using C/OS-II in curriculum teaching the subject of real-time systems.This ensures that engineers in the workplace are trained and ready to use C/OS-II in your products.

C/TCP-IP is a compact, reliable, high performance TCP/IP protocol stack and enables the rapid configuration of required network options to minimize your time to market.

CLEANEST SOURCE CODE:

C/TCP-IP delivers the highest quality source code, C/TCP-IP is a cleanroom design not derived from publicly available Unix stacks, yet maintains compatibility with Berkeley 4.4 socket layer interface. C/TCP-IP is written in ANSI C so it can be used with an array of cross-development tools.

HIGH PERFORMANCE:

Critical sections of C/TCP-IP were kept to a minimum and selected runtime validations can be disabled to enhance performance. C/TCP-IP implements zero copy buffer management for highest efficiency.

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SCALABLE AND ROMABLE:

C/TCP-IP allows you to adjust the memory footprint based on your requirements. C/TCP-IP can be configured to include only those network modules absolutely required by your system. If a module is not used, its not included in the build. Features of C/OS-II : Source Code: As I mentioned previously, this book contains all the source code for C/OS-II . I went to a lot of effort to provide you with a high-quality product. You may not agree with some of the style constructs that I use, but you should agree that the code is both clean and very consistent. Many commercial real-time kernels are provided in source form. I challenge you to find any such code that is as neat, consistent, well commented, and well organized as that in C/OS-II . Also, I believe that simply giving you the source code is not enough. You need to know how the code works and how the different pieces fit together. You will find that type of information in this book. The organization of a real-time kernel is not always apparent when staring at many source files and thousands of lines of code. Portable: Most of C/OS-II is written in highly portable ANSI C, with target microprocessor-specific code written in assembly language. Assembly language is kept to a minimum to make C/OS-II easy to port to other processors. Like C/OS, C/OS-II can be ported to a large number of microprocessors as long as the microprocessor provides a stack pointer

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and the CPU registers can be pushed onto and popped from the stack. Also, the C compiler should provide either in-line assembly or language extensions that allow you to enable and disable interrupts from C. C/OSII can run on most 8-, 16-, 32-, or even 64-bit microprocessors or microcontrollers and DSPs.All the ports that currently exist for C/OS can be converted to C/OS-II in about an hour. Also, because C/OS-II is upward compatible with C/OS, your C/OS applications should run on C/OS-II with few or no changes. ROMable : C/OS-II was designed for embedded applications. This means that if you have the proper tool chain (i.e., C compiler, assembler, and

linker/locator), you can embed C/OS-II as part of a product.

Scalable: I designed C/OS-II so that you can use only the services you need in your application. This means that a product can use just a few C/OS-II services, while another product can have the full set of features. This allows you to reduce the amount of memory (both RAM and ROM) needed by C/OS-II on a per-product basis. Scalability is accomplished with the use of conditional compilation. Simply specify (through #define constants) which features you need for your application or product. I did everything I could to reduce both the code and data space required by C/OS-II . Preemptive: C/OS-II is a fully preemptive real-time kernel. This means that C/OS-II always runs the highest priority task that is ready. Most commercial kernels are preemptive, and C/OS-II is comparable in performance with many of them.

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Multitasking: C/OS-II can manage up to 64 tasks; however, the current version of the software reserves eight of these tasks for system use. This leaves your application up to 56 tasks. Each task has a unique priority assigned to it, which means that C/OS-II cannot do round-robin scheduling. There are thus 64 priority levels. Deterministic: Execution time of all C/OS-II functions and services are deterministic. This means that you can always know how much time C/OS-II will take to execute a function or a service. Furthermore, except for one service, execution time of all C/OS-II services do not depend on the number of tasks running in your application. Task Stacks: Each task requires its own stack; however, C/OS-II allows each task to have a different stack size. This allows you to reduce the amount of RAM needed in your application. With C/OS-II's stack-checking feature, you can determine exactly how much stack space each task actually requires. Services: C/OS-II provides a number of system services, such as mailboxes, queues, semaphores, fixed-sized memory partitions, time--related

functions, and so on. Interrupt Management: Interrupts can suspend the execution of a task. If a higher priority task is awakened as a result of the interrupt, the highest priority task will run as soon as all nested interrupts complete. Interrupts can be nested up to 255 levels deep.

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Robust and Reliable: C/OS-II is based on C/OS, which has been used in hundreds of commercial applications since 1992. C/OS-II uses the same core and most of the same functions as C/OS yet offers more features. Source Code Conventions: All C/OS-II objects (functions, variables, #define constants, and macros) start with OS, indicating that they are related to the Operating System. Functions are found in alphabetical order in all the source code files. This allows you to locate any function quickly.You will find that the coding style I use is very consistent. I have been using the K&R style for many years; however, I have added some of my own enhancements to make the code (I believe) easier to read and maintain. Indention is always four spaces, Tabs are never used, at least one space appears on each side of an operator, comments are always to the right of code, and comment blocks are used to describe functions.

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