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# CHNG 3 NGN NG M T PHN CNG

3.1. Gii thiu VHDL 3.2. Cu trc m lnh 3.3. Cc kiu d liu 3.4. Cc php ton v thuc tnh

## 3.5. Code song song/Code tun t

3.6. My trng thi hu hn FSM

## 3.6. My trng thi hu hn FSM

3.6.1. Thit k mch s tun t - FSM 3.6.2. M t FSM trong VHDL

## 3.6.1. Thit k mch s tun t - FSM

My trng thi hu hn Finite State Machine (FSM) FSM loi Moore (ph thuc vo trng thi) FSM loi Mealy (ph thuc vo trng thi + tn hiu vo) Cc bc thit k:
Bc 1: V s trng thi Bc 2: Ti thiu ho s lng cc trng thi Bc 3: M ho trng thi Bc 4: La chn flip-flop Bc 5: Thc hin mch logic t hp Bc 6: Phn tch tn hiu theo thi gian
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## 3.6.1. Thit k mch s tun t - FSM

V d: Thit k mt b m 4. B m s m khi c tn hiu CE=1 (Count Enable) v ngng m khi CE= 0. Bc 1: V s trng thi FSM
CE=0 Count=0 CE=1 Count=1 CE=1 CE=0

CE=1

CE=0

Count=3 CE=1

Count=2

CE=0

## 3.6.1. Thit k mch s tun t - FSM

Ch chuyn trng thi ti sn ln ca xung nhp Ti sn ln ca xung nhp, ch c php 1 iu kin chuyn trng thi xy ra CE=0 CE=0 Count=0 CE=1 Count=1 CE=1 CE=0

## CE=1 CE=0 Count=3 CE=1

Count=2

1. Ta ang trng thi Count=0 2. CE = 0: i chn ca sn ln ca xung nhp 3. CE=1: i chn ca 1 sn ln khc nhng cha m 4. Sn ln ca xung nhp: chuyn sang trng thi Count=1, CE vn =1 5. CE = 0: i chn ca 1 sn ln khc 6. Sn ln ca xung nhp: chyn sang Count=1, vi CE=0

## 3.6.1. Thit k mch s tun t - FSM

Bc 2: Ti thiu ho s trng thi Bc 3: M ho cc trng thi

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Q1Q0=10

## 3.6.1. Thit k mch s tun t - FSM

Bc 4: Chn loi flip-flop. y n gin ta chn loi D Bc 5: Thc hin mch

## 3.6.1. Thit k mch s tun t - FSM

Chuyn FSM sang bng trng thi k tip
CE=0 Q1Q0=00 CE=1 CE=0 Q1Q0=11 CE=1 Q1Q0=01 CE=0

CE=1
Q1Q0=10 CE=0

CE=1

## 3.6.1. Thit k mch s tun t - FSM

Xc nh cc hm u vo flip-flop D
Present state Q1Q0 00 01 10 11 Next state Q1nQ0n CE=0 CE=1 00 01 01 10 10 11 11 00

## Excitation table for D flip-flop

Q 0 0 1 1 Q(next) 0 1 0 1 D 0 1 0 1

Q0 Q1n=D1 Q1 0 0 1 CE 0 1 0 1 1 CE Q0n=D0

Q0 Q1 0 1 1 0 1 0 0 1

D to be applied is identical to Qn

## 3.6.1. Thit k mch s tun t - FSM

Thc hin:
Q0 Q1n=D1 0 0 CE CE Q1 Q0 Q1n 0 1 Q1 1 1 0 1 CE Q0n=D0 Q0 Q1 0 1 1 0 1 0 0 1

D1

Q1
Q Q0 Q

Q0n

D0

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## 3.6.1. Thit k mch s tun t - FSM

Bc 6: Phn tch tn hiu theo thi gian
CE Q1 Q0 Q1n D1 Q1

Q
Q0 Q

Q0n

D0

Clk

CE
Q1
11

Q0

## 3.6.1. Thit k mch s tun t

FSM loi Moore
V d: Thit k b m 4, m n 3 th bo Bc 1: V s trng thi FSM:

CE=0 Count=0 Y=0 CE=1 CE=0 Count=3 Y=1 CE=1 Count=1 Y=0 CE=1 Count=2 Y=0

CE=0

CE=0

CE=1

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## 3.6.1 Thit k mch s tun t FSM loi Moore

c im:
Tn hiu u ra c xc nh ti mi trng thi Tn hiu ra ch ph thuc vo trng thi hin ti m khng ph thuc vo tn hiu vo Do , gi tr tn hiu ra c ghi bn trong vng trn biu din trng thi

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## 2.3 Thit k mch s tun t FSM loi Moore

Bc 2: Ti thiu ho s lng trng thi Bc 3: M ho trng thi

CE=0 Q1Q0=00 Y=0 CE=1 CE=0 Q1Q0=11 Y=1 CE=1 Q1Q0=01 Y=0 CE=1 Q1Q0=10 Y=0

CE=0

CE=0

CE=1

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## 3.6.1. Thit k mch s tun t FSM loi Moore

Bc 4: Chn loi flip-flop. y n gin ta chn loi D Bc 5: Thc hin mch

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## 3.6.1.Thit k mch s tun t FSM loi Moore

Chuyn FSM sang bng trng thi k tip
CE=0
Q1Q0=00 Y=0

CE=0 CE=1
Q1Q0=01 Y=0

CE=1 CE=0
Q1Q0=11 Y=1

CE=1
Q1Q0=10 Y=0

CE=0

CE=1

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## Next state Q1nQ0n CE=0 CE=1 00 01 01 10 10 11 11 00

Outputs Y 0 0 0 1

## 3.6.1. Thit k mch s tun t FSM loi Moore

Xc nh cc hm u vo flip-flop D
Present state Q1Q0 00 01 10 11 Next state Q1nQ0n CE=0 CE=1 00 01 01 10 10 11 11 00 Outputs Y 0 0 0 1

## Excitation table for D flip-flop

Q 0 0 1 1 Q(next) 0 1 0 1 D 0 1 0 1

Q0 Q1n=D1 Q1 0 0 1 CE 0 1 0 Y Q1 1 1 Q0 0 0 0 1 CE Q0n=D0

Q0 Q1 0 1 1 0 1 0 0 1

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D to be applied is identical to Qn

## 3.6.1. Thit k mch s tun t FSM loi Moore

Thc hin mch:
Q0 Q1n=D1 Q1 0 0 1 1 CE 0 1 0 1 CE Q0n=D0 0 1 1 0 Q0 Q1 1 0 0 1 Y Q1 Q0 0 0 0 1

CE Q1 Q0 Q1n

D1

Q1
Q Q0 Q

Q0n

D0

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## 3.6.1. Thit k mch s tun t FSM loi Moore

Bc 6: Phn tch tn hiu theo thi gian
CE Q1 Q0 Q1n D1 Q1 Y

Q
Q0 Q

Q0n

D0

Clk CE Q1 Q0
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## 3.6.1.Thit k mch s tun t

FSM loi Mealy
V d: Thit k b m 4, nu tn hiu m CE=1 v gi tr m =3 th tn hiu ra Y=1 Bc 1: V s trng thi FSM:
CE=0/Y=0 Count=0 CE=1/Y=0 Count=1 CE=1/Y=0 Count=2 CE=0/Y=0 CE=1/Y=0
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CE=0/Y=0

## 3.6.1. Thit k mch s tun t FSM loi Mealy

c im:
Tn hiu ra c xc nh cho mi trng thi v cc tn hiu vo ti trng thi Tn hiu ra ph thuc vo trng thi u hin ti v cc gi tr u vo ti trng thi Do gi tr tn hiu ra c ghi ti mi tn chuyn trng thi

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## 3.6.1. Thit k mch s tun t FSM loi Mealy

Bc 2: Ti thiu ho s lng trng thi Bc 3: M ho trng thi

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## 3.6.1. Thit k mch s tun t FSM loi Mealy

Bc 4: Chn loi flip-flop. y n gin ta chn loi D Bc 5: Thc hin mch

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## 2.3 Thit k mch s tun t FSM loi Mealy

Chuyn FSM sang bng trng thi k tip
CE=0/Y=0
Q1Q0=00

CE=0/Y=0 CE=1/Y=0
Q1Q0=01

## CE=1/Y=1 CE=0/Y=0 Q1Q0=11

Present state Q1Q0 00 01 10 11

CE=1/Y=0
Q1Q0=10 CE=0/Y=0

CE=1/Y=0

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Next state/Outputs Q1nQ0n/Y CE=0 CE=1 00/0 01/0 01/0 10/0 10/0 11/0 11/0 00/1

## 2.3 Thit k mch s tun t FSM loi Mealy

Xc nh cc hm u vo flip-flop D
Present state Q1Q0 00 01 10 11
Excitation table for D flip-flop
Q 0 0 1 1 Q(next) 0 1 0 1 D 0 1 0 1

Next state/Outputs Q1nQ0n/Y CE=0 CE=1 00/0 01/0 01/0 10/0 10/0 11/0 11/0 00/1 Q0

Q0

Q1n=D1

Q1
0 0 1 1

Q0n=D0

Q1
0 1 1 0

CE Y

0 1 0 1 Q0
Q1 0 0 0 0 0 0 0 1

CE

1 0 0 1

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D to be applied is identical to Qn

CE

## 2.3 Thit k mch s tun t FSM loi Mealy

Thc hin mch:
Q0 Q1n=D1 Q1 0 0 1 1 CE 0 1 0 1 CE Q0n=D0 0 1 1 0 Q0 Q1 1 0 0 1 CE Y Q0 Q1 0 0 0 0 0 0 1 0

CE Q1 Q0 Q1n

D1

Q1
Q Q0 Q

Q0n

D0

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## 3.6.1. Thit k mch s tun t FSM loi Mealy

Bc 6: Phn tch tn hiu theo thi gian CE Q Q
1 0

Q1n

D1

Q1

Q
Q0 Q

Q0n

D0

Clk CE Q1 Q0
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## 3.6.1. Thit k mch s tun t

M hnh FSM loi Moore
Inputs I D Clk Outputs O D Clk Q O=H(S) Mch logic t hp cho tn hiu ra Q Clock Q Next State S* Current State S

S*=F(S,I)

Clk

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## 3.6.1. Thit k mch s tun t

M hnh FSM loi Mealy Next State S*
Clock Inputs I D Clk S*=F(S,I) Outputs O D Clk Q O=H(S,I) Mch logic t hp cho tn hiu ra Q Q Current State S

Clk

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## 3.6. My trng thi hu hn FSM

3.6.1. Thit k mch s tun t - FSM 3.6.2. M t FSM trong VHDL
Gii thiu Kiu thit k th nht Kiu thit k th hai

## 3.6. My trng thi hu hn FSM

3.6.1. Thit k mch s tun t - FSM 3.6.2. M t FSM trong VHDL 3.6.2.1. Gii thiu 3.6.2.2. Kiu thit k th nht 3.6.2.3. Kiu thit k th hai

## 3.6.2. M t FSM trong VHDL

3.6.2.1. Gii thiu FSM gm 2 phn
Phn mch t hp
C 2 u vo: Pr_state , Input V 2 u ra: Nx_state, Output
Pr_state Nx_state Input Output

Logic t hp

## Phn mch tun t

C 3 u vo: Nx_state, clock, reset
Logic tun t
clock

V 1 u ra: Pr_state
Cha cc trigger

reset

## 3.6.2. M t FSM trong VHDL

3.6.2.1. Gii thiu
Phn mch t hp: Thng khng
dng process
Input Output

## Phn mch tun t: C mt process vi

danh sch nhy cha clock v reset
Pr_state

Logic t hp

Nx_state

Hot ng ca mch
- Khi reset th Pr_state tr v trng thi khi to ca h thng. - Ngc li, khi c clock khi tun t s lu tr trng thi Nx_state v chuyn ti u ra trng thi Pr_state
Logic tun t

clock reset

## 3.6.2. M t FSM trong VHDL

3.6.2.2. Kiu thit k th nht c im
u ra ca mch khng ph thuc vo clk Thit k ca hai phn tch ri nhau Tt c cc trng thi c khai bo r rng s dng kiu d liu lit k

## Thit k phn mch dy: S dng mt process

PROCESS (reset, clock) BEGIN IF (reset = 1) THEN pre_state <= state0; ELSIF (clockevent AND clock =1) THEN pre_state <= nx_state; END IF;
Pr_state Nx_state

Logic tun t

clock

reset

END PROCESS

## 3.6.2. M t FSM trong VHDL

3.6.2.2. Kiu thit k th nht
Thit k phn mch t hp: C th dng cc cu lnh song song hoc cu lnh tun t theo mu sau
PROCESS(input, pr_state) BEGIN CASE pr_state IS WHEN state0 => IF (input = ) THEN output <= <value>; nx_state <=state1; ELSE END IF; WHEN state1 => IF (input = ) THEN output <= <value>; nx_state <=state1; ELSE END IF; .. END CASE END PROCESS;

Input

Output

Logic t hp

Pr_state

Nx_state

## 3.6.2. M t FSM trong VHDL

3.6.2.2. Kiu thit k th nht

## 3.6.2. M t FSM trong VHDL

3.6.2.2. Kiu thit k th nht

## 3.6.2. M t FSM trong VHDL

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY counter IS PORT ( clk,rst: IN STD_LOGIC; count: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END counter; ARCHITECTURE state_machine OF counter IS TYPE state IS (zero, one, two, three, four, five, six, seven, eight, nine); SIGNAL pr_state, nx_state: state; BEGIN -------------Phn mch tun t bn di-----------PROCESS (rst, clk) BEGIN IF (rst = 1) THEN pr_state <= zero; ELSIF (clkEVENT AND clk = 1) THEN pr_state <= nx_state; END IF; END PROCESS;

## 3.6.2. M t FSM trong VHDL

-------------Phn mch t hp bn trn-----------PROCESS (pr_state) BEGIN CASE pr_state IS WHEN zero => count <= 0000; next_state <= one; WHEN one => count <= 0001; next_state <= two; WHEN two => count <= 0010; next_state <= three; WHEN three => count <= 0011; next_state <= four; WHEN four => count <= 0100; next_state <= five;

WHEN five => count <= 0101; next_state <= six; WHEN six => count <= 0110; next_state <= seven; WHEN seven => count <= 0111; next_state <= eight; WHEN eight => count <= 1000; next_state <= nine; WHEN nine => count <= 1001; next_state <= zero; END state_machine;

## 3.6.2. M t FSM trong VHDL

a ` b d clk rst FSM x
x=a x=b

H c hai trng thi l STATE0 v STATE1 u ra x = a khi h trng thi STATE0 u ra x = b khi h trng thi STATE1 d = 0 h gi nguyn trng thi d = 1 h chuyn trng thi

## 3.6.2. M t FSM trong VHDL

ENTITY FSM2 IS PORT ( a,b,d : IN BIT; rst, clk : IN STD_LOGIC; x : OUT BIT ); END FSM2; ARCHITECHTURE FSM OF FSM2 IS TYPE STATE IS ( STATE0, STATE1); SIGNAL pr_state, nx_state : STATE; BEGIN PROCESS(rst, clk) BEGIN IF (rst = 1) THEN pr_state = STATE0; ELSIF (clkevent and clk =1) THEN pr_state <=nx_state; END IF; END PROCESS; PROCESS (a,b,d,pr_state) BEGIN CASE pr_state IS WHEN STATE0 => x <= a; IF (d=1) THEN nx_state <= STATE1; ELSE nx_state <= STATE0; END IF; WHEN STATE1 => x <= b; IF (d=1) THEN nx_state <= STATE0; ELSE nx_state <= STATE1; END IF; END CASE; END PROCESS; END FSM;

## 3.6.2. M t FSM trong VHDL

3.6.2.3. Kiu thit k th hai c im
u ra ca mch ph thuc vo clk Thit k ca hai phn tch ri nhau Tt c cc trng thi c khai bo r rng s dng kiu d liu lit k Cn s dng thm mt s tn hiu trung gian tnh ton gi tr u ra ca mch t hp, nhng ch gn gi tr ny cho u ra ca h khi c tn hiu ng h tch cc.

a ` b d clk

FSM

x
x=a x=b

rst