XC73108 108-Macrocell CMOS CPLD: CC HP LP

XC73108 108-Macrocell CMOS CPLD
Product Specification Macrocells can individually be specied for high performance or low power operation by adding attributes to the logic schematic, or declaration statements to the behavioral description. To minimize power dissipation, unused Function Blocks are turned off and unused macrocells in used Function Blocks are congured for low power operation. Operating current for each design can be approximated for specic operating conditions using the following equation: ICC (mA)=MCHP (2.4) + MCLP (2.1) + MC (0.015 mA/MHz) f Where: MCHP MCLP MC f = = = = Macrocells in high-performance mode Macrocells in low-power mode Total number of macrocells used Clock frequency (MHz)
June 1, 1996 (Version 1.0)
Features
High-performance Complex Programmable Logic Devices (CPLDs) - 7.5 ns pin-to-pin speeds on all fast inputs - Up to 125 MHz maximum clock frequency 100% PCI compliant 18 outputs with 24 mA drive I/O operation at 3.3 V or 5 V Meets JEDEC Standard (8-1A) for 3.3 V 0.3 V 100% interconnect matrix - Maximizes resource utilization - Wire-AND capability via SMARTswitch High-speed arithmetic carry network - 1 ns ripple-carry delay per bit - 56 MHz 18-bit accumulators Multiple independent clocks Up to 120 inputs programmable as direct, latched, or registered Power management options Multiple security bits for design protection 108 macrocells with programmable I/O architecture Advanced Dual-Block architecture - 2 Fast Function Blocks - 10 High-Density Function Blocks 0.8 CMOS EPROM technology Available in 84-pin and 84-pin PLCC/CLCC, 144-pin PGA, 100-pin and 160-pin PQFP, and 225-pin BGA packages
Figure 1 shows a typical power calculation for the XC73108 device, programmed as six 16-bit counters and operating at the indicated clock frequency.
400
Typical ICC (mA)
300
High Perfo rman ce
200
Low
General Description
The XC73108 is a high performance CPLD providing general purpose logic integration. It consists of two PAL-like 24V9 Fast Function Blocks and ten High Density Function Blocks interconnected by the 100%-populated Universal Interconnect Matrix (UIM).
Pow
er
100
Power Management
The XC73108 features a power-management scheme that permits non-speed-critical paths of a design to be operated at reduced power. Overall power dissipation is often reduced signicantly, since, in most systems only a few paths are speed critical.
50 Clock Frequency (MHz)
100
X5697
Figure 1: Typical ICC vs. Frequency for XC73108
3- 115
PC84 PQ100 84 83 82 81 80 79 14 13 12 11 10 8
BG225/ PG144 H1 H2 G1 G3 E1 F3
PQ160 19 18 17 15 13 11
I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI I/FI
PQ160 22 23 24 26 28 30
BG225/ PG144 PQ100 J1 K1 J2 K3 L2 N1 16 17 18 19 20 22
PC84 2 3 4 5 6 7
6 12 FFB1 12 12 FFB2
13 14 15 17 18 19 20 21
26 30 31 32 34 35 37 38 39
N3 P4 P5 N6 P7 R6 P8 R8 N8
36 44 47 49 54 56 58 59 60
FO FO FO FO FO FO FO FO FO
MC1-1 MC1-2 MC1-4 MC1-5 MC1-6 MC1-7 MC1-8 MC1-9 9 39 45 Arithmetic Serial FB12 Carry Shift FB3 AND ARRAY AND ARRAY MC1-3 12 3 12 3
MC2-9 MC2-8 MC2-7 MC2-6 MC2-5 MC2-4 MC2-3 MC2-2 MC2-1 9 39 45
FO FO FO FO FO FO FO FO FO
142 143 144 146 148 152 154 156 4
A7 A6 B7 C6 B5 A3 C5 A2 B1
91 92 93 95 96 97 98 99 4
65 66 67 68 69 70 71 72
9 10 12 11 23 24 25 34 35 26 28 29 30 31 32 33 36 37 39 40 41 43
75 81 82 94 24 25 29 21 27 41 42 43 55 56 44 47 49 50 51 52 54 57 58 60 62 63 65
F14 E15 D15 E13 B15 A14 C11 A12 C13 B10 A5 A4 B4 B3 C3 C10 A11 B6 K2 L1 N2 M3 P3 P1 L3 M1 P2 R9 R10 P9 M14 N15 N10 R12 P12 P13 N12 P14 N14 M15 K14 J13 J15 H14 G13
105 107 109 112 114 123 125 128 116 130 147 151 153 155 158 129 133 145 25 27 33 35 42 34 32 29 37 62 63 64 86 88 68 71 73 75 77 79 82 90 92 95 97 98 101
I/O I/O I/O I/O I/O I/O I/O/FI I/O/FI I/O/FI
MC12-1 MC12-2 AND ARRAY AND ARRAY MC12-3 MC12-4 MC12-5 MC12-6 MC12-7 MC12-8 MC12-9 FB11 FB4
MC3-9 MC3-8 MC3-7 MC3-6 MC3-5 MC3-4 MC3-3 MC3-2 MC3-1
I/O/FI I/O/FI I/O/FI I/O I/O I/O I/O I/O I/O
21
21
96 93 91 89 87 84 78 76 74 72 69 57 67 55 50 48 45 43 16 14 12 8 6 2 159 9 7 140 139 138 135 113 115 136 134 126 124 122 117 111 108 106 104 103 102
K15 L15 K13 L14 L13 P15 N13 R14 N11 R13 R11 R7 P10 N7 P6 R4 N5 R2 F1 G2 F2 C1 D2 C2 B2 E2 E3 C8 A8 B8 C9 C14 D13 A10 B9 A13 B12 B13 B14 D14 E14 F13 G14 F15 G15
61 48 45 36 9 6 5 3 1 89 88 87 84 73 74 85 83 80 79 78 76 72 70 69 68 67 66
77 76 75 74 63 62 61 58 51 52 59 57 56 55 54 53 50 48 47 46 45 44
X5454
MC11-1 MC11-2 AND ARRAY MC11-4 MC11-5 MC11-6 MC11-7 MC11-8 MC11-9 FB10 FB5 AND ARRAY MC11-3
21
21
UIM
O O O/FCLK0 O/FCLK1 O/FCLK2 O I/O/FI I/O/FI I/O/FI
MC10-1 MC10-2 AND ARRAY AND ARRAY MC10-3 MC10-4 MC10-5 MC10-6 MC10-7 MC10-8 MC10-9 FB9 FB6
I/O/FI I/O/FI I/O/FI O/FOE1 O/FOE0 O/CKEN1 O/CKEN0 O O
21
21
MC9-1 MC9-2 AND ARRAY MC9-4 MC9-5 MC9-6 MC9-7 MC9-8 MC9-9 FB8 FB7 AND ARRAY MC9-3
21
21
MC8-1 MC8-2 AND ARRAY AND ARRAY MC8-3 MC8-4 MC8-5 MC8-6 MC8-7 MC8-8 MC8-9 Serial Shift Arithmetic Carry
21
21
Figure 2: XC73108 Architecture
3- 116
Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage with respect to GND DC Input voltage with respect to GND Voltage applied to 3-state output with respect to GND Storage temperature Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 Units V V V C C
Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operating Conditions

Symbol VCCINT VCCIO VCCIO VIL VIH VO TIN Parameter Supply voltage relative to GND Commercial TA = 0C to 70C Supply voltage relative to GND Industrial TA = 40C to 85C Supply voltage relative to GND Military TA = 55C to TC + 125C I/O supply voltage relative to GND Low-level input voltage High-level input voltage Output voltage Input signal transition time Min 4.75 4.5 4.5 3.0 0 2.0 0 Max 5.25 5.5 5.5 3.6 0.8 VCC +0.5 VCCIO 50 Units V V V V V V V ns
DC Characteristics Over Recommended Operating Conditions

Symbol VOH 3.3 V High-level output voltage 5 V TTL Low-level output voltage VOL 3.3 V Low-level output voltage IIL IOZ CIN CIN COUT1 ICC2 Input leakage current Output high-Z leakage current Input capacitance for Input and I/O pins Input capacitance for global control pins (FCLK0, FCLK1, FCLK2, FOE0, FOE1) Output capacitance Supply current (low power mode) Parameter 5 V TTL High-level output voltage Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA (FO) IOL = 12 mA (I/O) VCC = Min IOL = 10 mA VCC = Min VCC = Max VIN = GND or VCCIO VCC = Max VIN = GND or VCCIO VIN = GND f = 1.0 MHz VIN = GND f = 1.0 MHz VIN = GND f = 1.0 MHz VIN = VCC or GND VCCINT = VCCIO = 5V f = 1.0 MHz @ 25C Min 2.4 2.4 0.5 0.4 10.0 10.0 8.0 12.0 20.0 227 Typ Max Units V V V V A A pF pF pF mA
Notes: 1. Sample tested.

2. Measured with device programmed as six 16-bit counters.
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Power-up/Reset Timing Parameters

Symbol tWMR tRESET Parameter Master Reset input Low pulse width Configuration completion time Min 100 Typ 80 Max 160 Units ns s
Fast Function Block (FFB) External AC Characteristics3

XC73108-7
(Com only)
XC73108-10
(Com only)
XC73108-12
(Com/Ind only)
Symbol fCF tSUF tHF tCOF tPDFO tPDFU tCWF
Parameter Max count frequency 1, 2, 4 Fast input setup time before FCLK Fast input hold time after FCLK FCLK to output valid Fast input to output valid 1, 2 I/O to output valid 1, 2 Fast clock pulse width (High or Low)
Min 125.0 4.0 0
Max
Min 100.0 5.0 0
Max
Min 80.0 6.0 0
Max
5.5 7.5 13.5 4.0 5.0
8.0 10.0 19.0 5.5
9.0 12.0 22.0
XC73108-15 Min Max 66.7 7.0 0 12.0 15.0 27.0 6.0
XC73108-20 Min Max 50.0 10.0 0 15.0 20.0 35.0 6.0
Units MHz ns ns ns ns ns ns
Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of tFLOGILP tFLOGI or t LOGILP tLOGI. 2. Specications account for logic paths that use the maximum number of available product terms for a given macrocell. 3. All appropriate AC specications tested using Figure 3 as the test load circuit. 4. Export Control Max. ip-op toggle rate.
High-Density Function Block (FB) External AC Characteristics

XC73108-7
(Com only)
XC73108-10
(Com only)
XC73108-12
(Com/Ind only)
Symbol fC tSU tH tCO tPSU tPH tPCO tPD tCW tPCW
Parameter Max count frequency 1, 2 I/O setup time before FCLK 1, 2 I/O hold time after FCLK FCLK to output valid I/O setup time before p-term clock 2 I/O hold time after p-term clock P-term clock to output valid I/O to output valid 1, 2 Fast clock pulse width P-term clock pulse width
Min 83.3 12.0 0 4.0 0
Max
Min 62.5 16.0 0 6.0 0
Max
Min 55.6 18.0 0 7.0 0
Max
7.0
10.0
12.0
15.0 18.0 4.0 5.0 5.0 6.0
20.0 25.0 5.5 7.5
23.0 30.0
XC73108-15 Min Max 45.5 22.0 0 15.0 9.0 0 28.0 36.0 6.0 8.5
XC73108-20 Min Max 35.7 28.0 0 20.0 12.0 0 36.0 45.0 6.0 12.0
Units MHz ns ns ns ns ns ns ns ns ns
Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of tFLOGILP tFLOGI or t LOGILP tLOGI. 2. Specications account for logic paths that use the maximum number of available product terms for a given macrocell.
3- 118
Fast Function Block (FFB) Internal AC Characteristics

XC73108-7
(Com only)
XC73108-10
(Com only)
XC73108-12
(Com/Ind only)
Symbol tFLOGI tFLOGILP tFSUI tFHI tFCOI tFPDI tFAOI tPTXI tFFD
Parameter FFB logic array delay 1 Low-power FFB logic array delay 1 FFB register setup time FFB register hold time FFB register clock-to-output delay FFB register pass through delay FFB register async. set delay FFB p-term assignment delay FFB feedback delay
Min
Max 1.5 3.5
Min
Max 1.5 5.5
Min
Max 2.0 7.0
1.5 2.5 1.0 0.5 2.0 0.8 4.0
2.5 2.5 1.0 0.5 2.5 1.0 5.0
3.0 3.0 1.0 1.0 3.0 1.2 6.5
XC73108-15 Min Max 2.0 8.0 4.0 3.0 1.0 1.0 4.0 1.5 8.0
XC73108-20 Min Max 3.0 11.0 6.0 4.0 1.0 2.0 6.0 2.0 10.0
Units ns ns ns ns ns ns ns ns ns
Note: 1. Specications account for logic paths that use the maximum number of available product terms for a given macrocell.
High-Density Function Block (FB) Internal AC Characteristics

XC73108-7
(Com only)
XC73108-10
(Com only)
XC73108-12
(Com/Ind only)
Symbol Parameter tLOGI FB logic array delay 1 tLOGILP Low power FB logic delay 1 tSUI FB register setup time tHI FB register hold time tCOI FB register clock-to-output delay tPDI FB register pass through delay tAOI FB register async. set/reset delay tRA Set/reset recovery time before FCLK tHA Set/reset hold time after FCLK tPRA Set/reset recovery time before p-term clock tPHA Set/reset hold time after p-term clock tPCI FB p-term clock delay tOEI FB p-term output enable delay tCARY8 ALU carry delay within 1 FB 2 tCARYFB Carry lookahead delay per additional Functional Block 2
Min
Max 3.5 7.0
Min
Max 3.5 7.5
Min
Max 4.0 9.0
XC73108-15 Min Max 5.0 11.0 4.0 5.0
XC73108-20 Min Max 6.0 14.0 6.0 6.0
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1.5 3.5 1.0 1.5 2.5 15.0 0 7.5 5.0 1.0 3.0 5.0 1.0
2.5 3.5 1.0 2.5 3.0 19.0 0 10.0 6.0 0 4.0 6.0 1.5
3.0 4.0 1.0 4.0 4.0 21.0 0 12.0 8.0 0 5.0 8.0 2.0
1.0 4.0 5.0 25.0 0 15.0 9.0 0 7.0 12.0 3.0 31.0 0 20.0 12.0
1.0 4.0 7.0
0 9.0 15.0 4.0
Notes: 1. Specications account for logic paths that use the maximum number of available product terms for a given macrocell.
2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent macrocell(s) for adder with registered outputs.
3- 119
I/O Block External AC Characteristics

XC73108-7
(Com only)
XC73108-10
(Com only)
XC73108-12
(Com/Ind only)
Symbol Parameter fIN Max pipeline frequency (input register to FFB or FB register) 1 tSUIN Input register/latch setup time before FCLK Input register/latch hold time after tHIN FCLK tCOIN FCLK to input register/latch output tCESUIN Clock enable setup time before FCLK tCEHIN Clock enable hold time after FCLK tCWHIN FCLK pulse width high time tCWLIN FCLK pulse width low time
Min 83.3 4.0 0
Max
Min 62.5 5.0 0
Max
Min 55.6 6.0 0
Max
XC73108-15 Min Max 45.5 7.0 0
XC73108-20 Min Max 35.7 10.0 0
Units MHz ns ns
2.5 5.0 0 4.0 4.0 7.0 0 5.0 5.0
3.5 8.0 0 5.5 5.5
4.0 10.0 0 6.0 6.0
5.0 12.0 0 6.0 6.0
6.0
ns ns ns ns ns
Note: 1. Specications account for logic paths that use the maximum number of available product terms for a given macrocell.
Internal AC Characteristics
XC73108-7
(Com only)
XC73108-10
(Com only)
XC73108-12
(Com/Ind only)
Symbol tIN tFOUT tOUT tUIM tFOE tFOD tFCLKI
Parameter Input pad and buffer delay FFB output buffer and pad delay FB output buffer and pad delay Universal Interconnect Matrix delay FOE input to output valid FOE input to output disable Fast clock buffer delay
Min
Max 2.5 3.0 4.5 6.0 7.5 7.5 1.5
Min
Max 3.5 4.5 6.5 9.0 10.0 10.0 2.5
Min
Max 4.0 5.0 8.0 10.0 12.0 12.0 3.0
XC73108-15 Min Max 5.0 7.0 10.0 12.0 15.0 15.0 4.0
XC73108-20 Min Max 6.0 9.0 14.0 15.0 20.0 20.0 5.0
Units ns ns ns ns ns ns ns
VTEST
R1
Device Output
Test Point
R2 Device Imput Rise and Fall Times < 3 ns
CL
Output Type FO
VCCIO 5.0 V 3.3 V
VTEST 5.0 V 3.3 V
R1 160 260
R2 120 360
CL 35 pF 35 pF
X3491
Figure 3: AC Load Circuit
3- 120
XC73108 Pinouts
PQ160 PG144 BG225 PQ100 PC84 Input XC73108 Output PQ160 PG144 BG225 PQ100 PC84 Input XC73108 Output
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
D3 C2 B1 D2 E3 C1 E2 D1 F3 F2 E1 G2 G3 F1 G1 H2 H1 H3 J3 J1 K1 J2 K2 K3 L1 L2 M1 N1 M2 L3 N2 P1 M3 N3 P2 R1
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
75 76 77 78 79 80 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11
VCCIO O/CKEN1 N/C FO N/C O/FOE0 O O/FOE1 O VCCINT/VPP I/FI I/O/FI I/FI I/O/FI I/FI I/O/FI I/FI I/FI I/FI GND MR I/FI I/FI I/FI O I/FI O I/FI I/O/FI I/FI GND I/O/FI O/FCLK0 O O/FCLK1 FO I/O/FI N/C N/C GND MC10-7 MC10-3 MC10-6 MC10-4 MC1-1 MC10-9 MC5-7 MC5-8 MC5-9 MC5-5 MC5-1 MC5-6 MC5-2 MC2-1 MC5-4
MC10-1 MC10-2 MC10-8
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
N4 P3 R2 P4 N5 R3 P5 R4 N6 P6 R5 P7 N7 R6 R7 P8 R8 N8 N9 R9 R10 P9 P10 N10 R11 P11 R12 R13 P12 N11 P13 R14 N12 N13 P14 R15
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VCCIO O/FCLK2 I/O FO I/O VCCINT FO I/O FO I/O GND N/C N/C FO I/O FO I/O/FI FO FO FO VCCIO I/O I/O I/O N/C N/C I/O I/O I/O/FI GND I/O/FI I/O/FI I/O/FI I/O I/O/FI I/O I/O I/O I/O GND MC9-7 MC4-9 MC9-8 MC3-1 MC9-9 MC3-2 MC8-1 MC3-3 MC8-2 MC4-6 MC9-6 MC4-8 MC9-1 MC9-2 MC9-3 MC1-5 MC4-5 MC1-6 MC4-7 MC1-7 MC1-8 MC1-9 MC1-3 MC4-3 MC1-4 MC4-4 MC10-5 MC4-1 MC1-2 MC4-2
Note: With the XC73108 in the 225-pin ball grid array package, only 144 of the solder balls are connected, the remaining solder balls should be left unconnected.
3- 121
XC73108 Pinouts (continued)

PQ160 PG144 BG225 PQ100 PC84 Input XC73108 Output PQ160 PG144 BG225 PQ100 PC84 Input XC73108 Output
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
M13 N14 P15 M14 L13 N15 L14 M15 K13 K14 L15 J14 J13 K15 J15 H14 H15 H13 G13 G15 F15 G14 F14 F13 E15 E14 D15 C15 D14 E13 C14 B15 D13 C13 B14 A15
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
VCCIO I/O N/C I/O N/C I/O I/O I/O I/O I/O I/O/FI I/O I/O/FI VCCINT I/O I/O/FI I/O/FI I/O/FI GND GND I/O/FI I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O/FI I/O/FI N/C N/C GND MC7-6 MC12-4 MC6-5 MC12-5 MC6-4 MC12-9 MC7-7 MC8-9 MC7-1 MC7-2 MC7-3 MC12-1 MC7-4 MC12-2 MC7-5 MC12-3 MC8-6 MC3-9 MC8-7 MC8-8 MC9-4 MC3-5 MC9-5 MC3-6 MC8-4 MC3-7 MC8-5 MC3-8 MC3-4 MC8-3
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
C12 B13 A14 B12 C11 A13 B11 A12 C10 B10 A11 B9 C9 A10 A9 B8 A8 C8 C7 A7 A6 B7 B6 C6 A5 B5 A4 A3 B4 C5 B3 A2 C4 C3 B2 A1
78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2
54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
VCCIO I/O/FI I/O I/O/FI I/O/FI I/O GND I/O/FI I/O/FI I/O N/C N/C I/O/FI I/O I/O I/O GND I/O/FI I/O/FI I/O/FI VCCIO FO FO FO I/O/FI FO I/O FO N/C N/C I/O FO I/O FO I/O FO VCCINT I/O O/CKEN0 GND MC11-6 MC5-3 MC11-3 MC2-4 MC11-4 MC2-3 MC11-5 MC2-2 MC2-9 MC2-8 MC2-7 MC11-9 MC2-6 MC11-2 MC2-5 MC6-7 MC6-8 MC6-9 MC11-8 MC6-2 MC6-6 MC6-3 MC12-8 MC11-7 MC11-1 MC7-8 MC12-6 MC7-9 MC12-7 MC6-1
3- 122
Ordering Information XC73108 - 7 PC 84 C

Device Type Speed Temperature Range Number of Pins Package Type
Speed Options -20 -15 -12 -10 -7 20 ns pin-to-pin delay 15 ns pin-to-pin delay 12 ns pin-to-pin delay 10 ns pin-to-pin delay (commercial and industrial only) 7.5 ns pin-to-pin delay (commercial only)
Packaging Options PC84 84-Pin Plastic Leaded Chip Carrier WC84 84-Pin Windowed Ceramic Leaded Chip Carrier PQ100 100-Pin Plastic Quad Flat Pack PG144 144-Pin Windowed Pin-Grid-Array PQ160 160-Pin Plastic Quad Flat Pack BG225 225-Pin Plastic Ball-Grid-Array Temperature Options C Commercial0C to 70C I Industrial -40C to 85C M Military -55C (Ambient) to 125C (Case)
Component Availability
Pins Type Code 20 15 12 10 7 Plastic PLCC PC84 CI CI CI C C 84 Ceramic CLCC WC84 CI CI CI C C 100 Plastic PQFP PQ100 CI CI CI C C 144 Ceramic PGA PG144 CIM CIM CI C C 160 Plastic PQFP PQ160 CI CI CI C C 225 Plastic BGA BG225 CI CI CI C C
XC73108
C = Commercial = 0 to +70C
I = Industrial = 40 to 85C
M = Military = 55C(A) to 125C (C)
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3- 124

XC73108 108-Macrocell CMOS CPLD: CC HP LP

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XC73108 108-Macrocell CMOS CPLD: CC HP LP

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XC73108 108-Macrocell CMOS CPLD

June 1, 1996 (Version 1.0)

Typical ICC (mA)

50 Clock Frequency (MHz)

Figure 1: Typical ICC vs. Frequency for XC73108

June 1, 1996 (Version 1.0)