A Survey on Real-time Multi-core Systems involving Scheduling Techniques of Soft Real-time Systems

By
Anam Zaheer Khan anum.zaheer.khan@live.com Heavy Industries Taxila Education City, University

Scope of Paper
Effective utilization of a processor can be done or enhanced on multiprocessors, for different real-time applications whose preemption and migration

overheads can have multiple ranges and whose tolerances to tardiness are different, by designing new scheduling algorithms, implementing optimal ones, and designing novel validation tests. Key terms: - Parallelism, Real-time systems, Priority, Scheduling, multithreading, Preemptive & nonPreemptive, multi-core

They suggested the idea of stored-program model of computing in which the instructions stored sequentially in memory were supposed to execute sequentially or one after another in a linear, single-threaded fashion. Now-a-days this model is known as the Von Neumann Architecture. The advent of this model became the fundamental for the development and progress in mainframe technology. The 1960s decade was the time of arrival of the time-sharing operating System (OS). For the very first time, the time sharing operating systems introduced the idea of concurrency in programming execution. Running on the large-scale mainframe computers, the TS-OS enabled the multiple users access on a single main-frame computer simultaneously. Early days of personal computing was based on the single-user operating systems. The PCs were operating as, one program at a time, a standalone device. Programs followed the very basic model of single and straight-line instruction execution. Over time, as the computing performance exponentially grew, the more sophisticated computing platforms were developed. User environment, graphical performance, Graphical User Interfaces, or more commonly GUIs, became more important to the vendors to introduce advance in CPUs. On the other hand, the users were more into preferring the quick and responsive computing platforms. The GUIs became standard as it enabled users to run concurrent programs in same user environment. The invention of transistor in 1947-48 hugely affected the history of modern computers. This invention led to the creation of the integrated circuitry. In 1958, Jack Kilby & Robert Noyce brought The Chip on the scene. 1971 was the year of fist ever microprocessor designed by Faggin, Hoff & Mazor under the name Intel 4004 Computer Microprocessor [2][3]. The whole study now revolves around the idea of microprocessors or the

Abstract
This survey reports the assortment of approaches designed & implemented till date for real time task scheduling in multiprocessors. The performance metrics involved, Hard & Soft Real-time approaches, Taxonomy of Scheduling Algorithms, Better utilization of a processor, Nomenclature and the system terminologies are also incorporated. The soft real-time tasks are classified under Preemption and nonpreemption approaches. In a nutshell, this survey entirely wraps up the historical aspects as well as the up-to-the-minute scheduling algorithms of real-time multi-core processors.

1.1 BACKGROUND
Looking back into the history of todays modern multicore machines, mathematician John Von Neumann along with Electrical Engineer & Computer pioneer J. Presper Eckert and physicist John Muchly, in 1945, proposed in a memo [1], the idea of creating EDVAC (Electronic Discrete Variable Automatic Computer).

-----------------------------------------------------------------------------------------------------------------------------------------------------------------

multi-core systems and how other features are affecting their performance.

1.3 A BRIEF HISTORY

The first microprocessor was manufactured by Intel which was the 4-bit 4004. In 1970s this design was just like a number-crunching machine [2]. After this advancement to this processor was made that were 8008 and 8080 processors. Both were 8-bit, and Motorola followed suit with their 6800 which was equivalent to Intels 8080 [1][2]. After these developments, the development curve started to shoot up drastically by the implementation of Intels 8086 and 8088, 16-bit microprocessors, Motorola had their 68000 equivalent. Then Intels 80386 32-bit microprocessors came up and later the popular Pentium series of Intel were the first consumer-based Personal computers or PCs. 1.3.1 PERFORMANCE METRIC IN MICROPROCESSORS Gordon Moore, in 1965, observed that the number of transistors available would double every 18 months approximately. This idea is known as Moores Law which has been a guideline for computer designers for the past 4 decades. Over the past 40 years, CPU clock speed has tended to follow Moores Law [1][2][3]. The depiction of this law is clearly shown in figure 1. People use to think it is a predictor of clock frequency of computer which is unfortunately not really true. This idea is not too hard to understand why; as the common measuring of computing performance is the CPUs clock frequency. .

1.2 INTRODUCTION
A processor, so it is the brain of a computer system which tells the system what to do and what not to do via programming instructions. Typically, a processor is a single die which is integrated of large number of transistors. In the term of computing, a processor is said to be the unit which reads and execute the programming instructions. The data (typically a command) tells the processor what to do. 1.2.1 SINGLE-CORE PROCESSORS

Single-core processors can execute or process only a single instruction per unit time. These types of processors were used in early computing. 1.2.2 MULTI-CORE PROCESSOR

A multi-core processor is designed with two or more independent cores. Manufacturers integrate the cores onto a single die or onto multiple dies in a single chip package. 1.2.3 MANY-CORE PROCESSOR

Many-core processor is quite similar to the latter one. As in this the number of cores is huge enough. But the multi-processor techniques become inefficient due to the issue with congestion of supplying adequate instructions and data to the many-core processors. Typically, the threshold level is several tens of cores and possibly requires NoC (Network on Chip). Dual-Core Processors: It contains two (dual) cores. An example of which is Intel Core Duo or AMD Phenom II X2 [1]. Quad-Core Processors: It contains four (quad) cores, An example of which is Intel 2010 core line or AMD Phenom II X4 [1]. Hexa-Core Processors: It contains six (hexa) cores. Example is Intel Core i& Extreme Ed. 980X or AMD Phenom II X6 [1].

Figure 1: Depiction of Moores Law. (Courtesy: Multi-core Architecture by Nabendu Karmakar, Ch2: A Brief History of Microprocessor)

-----------------------------------------------------------------------------------------------------------------------------------------------------------------

Actually, what is usually quoted as Moores Law is a modification by Dave House i.e. the performances will double every 18 months. This prediction, even after revision by Dave House, needs further more correction. In 1990s, the earlier part of this decade, microprocessors really followed this Law; higher the frequency, more capable the computer performance will be. But as the time and advancements have been made and processor frequency has accomplished a plateau, now the time is to consider the other aspects of systems performance: Temperature dissipation, no. of cores, power consumption and frequency etc. Taking these factors into account, the multi-core processors usually runs at lower relatively slower frequencies, but the performance metric excels than a single-core processor. Another most important factor in this perspective is the amount of performance gained by the use of multi-core processor highly depends on the software algorithms and their implementation. In particular, the possible gains are limited by the fraction of the software that can be parallelized to run on multiple cores simultaneously; this effect is described by Amdahls law [1] [3]. Efforts to increase efficiency An increase in the performance can be seen from the introduction of Intels 8086 to the Pentium 4, one generation to the next. This was an increase in processor frequency as in Pentium 4, it ranged in speed (frequency) from 1.3 to 3.8 GHz over its 8 years lifetime [1]. If we do a comparison so, obviously, the chip size physically decreased while the no. of transistor on chip increased. Another most important factor; the clock speed: increase in this metric has also boosted up the heat dissipation across the chip to a risky level. One of the most important aspects in computer architect is the branch instruction which highly depends on the idea of gathering all necessary information before making a decision. Speeding up this process depends on processor prediction. The processor predicts that which path has to be taken; if wrong one is chosen the data computed has to be thrown out and backtrack to the correct path. This factor is also minimized (by removing branches) by using sophisticated neural network based predictors to decrease the miss prediction rate. Other techniques

that are used to enhance the performance include Register renaming, reordering buffers, software scheduling, cache tracing etc. Power and temperature constraints are also minimized. Power- and temperature-aware architectures have been designed. Power-aware architects maximize performance metrics while satisfying power constraints. Temperature-aware architect determines where the hot spots on the chips lie, by using simulations, and decrease the effect and no. of hot spots. Need of Multi-core Systems Though the processors have increased in speed and decreased in cost at a very high rate for a very long time according to the Gordon Moores Law but lately this law has begun to show the signs of failing. The smaller transistors have made it possible to increase the number of transistors mounted on a processor, also reduced the distance signals must travel allowing the clock frequencies to ascend at a high rate. Though this has simultaneously increased the system performance and reduced the systems cost but on the other hand, as processor frequencies soar, the amount of heat dissipation produced by the processor will climbs with it. Cooling down the processor is a major factor in limiting the speed up process of a processor. Reducing the transistor size has reduced the distance but they are so small now that the quantum behavior of electron affects their operating function [1]. According to the quantum mechanics, involved in the transistor mechanism, tiny particles e.g. electrons, are able to spontaneously channel over short distances at random. The base and emitter of a transistor are so close enough that a calculable amount of electrons can cross the barrier causing a small amount of leakage current to pass between them. This can cause a small short in the transistor. Smaller the size of transistor, higher will be the leakage current. If the operating voltages are kept low, the logical one and zero difference becomes too close and processor will not operate. In the end the issue of keeping the processor cool or to increase the clock frequencies issue is in a dilemma. The approach of making advancement in the high performance has to be changed.

-----------------------------------------------------------------------------------------------------------------------------------------------------------------

Adding another processing core to the same chip would result in doubling the performance and dissipating less heat. This statement is according to the theory but, the actual speed of each core is lesser than the fastest single-core processor, in practice. Manufacturing technology has reached to the point of placing two processor cores on a single chip which we now commonly known as Dual-Core processor. Two Heads are Better than One- A Trade off As it is understood that each processor core is slower than a single-core processor so a trade off must be made in order to get greater throughput. Though each processor is slower but together they can work better. Now each upcoming generation will likely to follow the trend of increasing no. of cores and decreasing the clock frequency. Now the trade-off has been made and for the efficiency of dual-core workload must also be divided or we can say there must also have parallelism that can use both the cores. Usually when applications are not multithreaded or limitations are there by memory performance, dual-core might not offer much advantage, or it may deliver a lesser amount of performance. Since, dual-core use a slower clock than for single-core so memory latency of dual-core processor will be slower than the single-core and the commands will take longer to pass through the memory controller. Operating System In performance measurement, another factor affecting the system performance is its operating system or OS. Looking towards the memory architecture, it is quite complex. An OS must know or should be aware that the system is NUMA i.e. Non-Uniform Memory Access []. It should also be geared up to deal with the multifaceted memory arrangements.

architecture with certain aspects. Its pictorial representation is illustrated in the figure below:

Figure 2: basic architectural design of a multi-core processor, courtesy (Multi-core architecture design by Nabedu karmaker)

1.4 BASIC MULTICORE PROCESSOR

Every manufacturer designs its own configuration of a multi-core architecture and they differ from one another but each design follows same basic principle

The step-by-step configuration is that the main component is the processor, closest to which is L1 cache (L1 is the general notation for cache, few authors use $ sign to represent cache as well). The cache L1 is the fast and frequently used by the processor for data storage and retrieving. L2 is the second level cache and is slower & larger than that of L1. It is considered as the off-chip. This level of cache is though slower than L1 but still is faster than that of main memory. Usually the L1 cache is 32KB, L2 cache is 2MB in comparison to which main memory is a bulk of 1GB-4GB [2]. These complete components, joins to make a one whole. Usually, in fact as in principle, when the data is not located in cache memory or the main memory of the processor, system turns itself to the hard disk to locate data. This one process takes exponentially additional time than required for reading from main memory.

-----------------------------------------------------------------------------------------------------------------------------------------------------------------

The communication among the two caches and the main memory is accomplished by using the two most important models. Either it uses a bus-based communication or the interconnected network approach. A single communication bus or the bus approach is used with the shared memory model and the Inter-connected network approach is employed with the distributed memory model. The figure below, shows the Multi-core design of the actual configuration, with shared and the distributed memory.

1.4.1 BASIC TERMS Parallelism In literature, the term parallelism is defined as the ability to do concurrent tasks simultaneously also, it is known as parallel structure or parallel construction. In computer architect terminology, this term refers to the ability to have pending multiple memory operations simultaneously with the goal of solving a problem in less time or solving a larger problem in the same time. The term parallelism basically differs from concurrency. Concurrency is the property of a system in which multiple tasks stay logically active and make progress simultaneously by interleaving the execution order of the tasks and thus creating an illusion of simultaneously executing instructions [2][5]. Multi-threading In computer hardware architecture the term multithreading is associated with the CPU hardwares ability that support to proficiently execute multiple threads at a time. The goal of multi-threading is to increase utilization and exploitation of single-core processor using thread-level or instruction level parallelism. In term of computer software, multi-threading is the execution of small programming sequence threads simultaneously and independently. Scheduling Generally, Scheduling is the process directly related to the multitasking and multiprocessing in the system. Scheduling regulates the use of distributing resources among parties which concurrently and asynchronously request them. Reducing resource starvation and fair resource distribution and allocation is the main objective of any scheduling algorithm. Latency Time delay that a task takes to complete itself or the delay experienced in a system is called latency. The term latency is sometime also called transport delay.

Figure (3a): Distributed Memory Model

Figure (3b): Shared Memory Model

Figure (3): The memory design model of shared and distributed architecture, courtesy: Nabandu karmaker

-----------------------------------------------------------------------------------------------------------------------------------------------------------------

Brach-Predictor A strategy to improve the flow in instruction pipelining also the prediction that which way a branch will go is called branch-prediction and the digital circuit which performs this task is known as branch-predictor. Dynamic memory-allocation The job of satisfying an allocation request by any process that consists of finding a block of vacant memory of adequate size is the dynamic memory allocation. Memory requests are fulfilled by allocating portions from a huge pool of memory called the heap. Preemption In general, preemption is the replacement of something with another thing considered to be of greater value or priority. In term of computer architecture, preemption is a task of suspending a process temporarily, which is being carried out by the system, without its assistance, and with the intent of resuming it later. This is usually done by the preemptive scheduler who has the authority to preempt, interrupt and resume the other systems task. Non-Preemption Non-Preemption doesnt allow Preemption. In this when the process enters the state of running; it does not terminate from the scheduler unless or until it finishes its time.

1.5.1 CLASSIFICATION Real-time systems can be classified as either Hardreal-time or soft-real-time systems. These two are classified on the bases of cost of failure or delay related with not meeting the requirement. Hard Real-Time Systems Hard real-time strictly abides by the rule or each task deadline. Its violation can lead to the disastrous results. When any event occurs in such system, it must be serviced in time. The preemption period for hard realtime task in worse case should be less than a few s [7]. Example of which is; anti-lock brake systems, ejection seats, controller for automotives and industrial process control systems etc. Soft Real-Time Systems In contrast to the hard real-time systems, soft real-time systems are the one in which mostly deadlines are met and few deadlines misses are accepted. It is less critical as compared to hard real-time systems so there is a room for few violations. However, these violations are not self-made or desirable in fact sometimes the lead to the degradation of QoS, and it often set to the violation be bounded. Examples are Multimedia systems, touch-screens and virtual-reality systems. 1.5.2 FUNDAMENTALS Periodic Task Job which has a regular period and has infinite sequence of task instances is called a periodic task. In which each of it is associated with the initial arrival time, the execution CPU cycles and the period. Scheduling While discussing real-time systems, Scheduling of a real time task is the execution of tasks in unit time, maintaining processor speed for each one of the corresponding task execution, where the job arrivals of each task satisfies timing constraints. The goal of task scheduling is to maximize the processor utilization by minimizing the total completion time of concurrent tasks, provided the deadline constraints are satisfied.

1.5 REAL-TIME SYSTEMS

The distinctive feature of a real-time system, while comparing to a non real-time system, is the addition of Timings in its specification or requirement. Which highlights the fact that the exactness or the precision of a real-time system relies not only on logically accurate segments of code that logically correct results, but as well as on executing the code segments and producing correct results within definite time frames. Therefore, a real-time system is said to have dual notions of correctness, logical and temporal [1]. In real-time systems, Deadline is the common terminology for the timing constraints or specifications, within which, all the running activities must complete their execution.

-----------------------------------------------------------------------------------------------------------------------------------------------------------------

1.5.3 SCHEDULING CATEGORIES The real time systems scheduling can be divided into further categories on the bases of their characteristics i.e. the attributes of the tasks, the computing platform and the total time when the scheduling is completed. An important task in the scheduling algorithm is not only to state the execution order but also determining the processor to be used. This approach is quite advantageous as scheduling process can be treated as a uni-processor systems using Earlier Deadline First (EDF) or Rate Monotonic [4][10][12][18][23]. EDF uses the dynamic scheduling and in which there is a single queue and the task migrations or partitions among processors are permissible. Proportionate fair or merely P-fair Scheduling is known to be the finest dynamic scheduling.

1.6.3 PERIODIC & SPORADIC TASK MODELS In real-time scheduling we are generally concerned with the proficiency of multi-processors in terms of execution of the set of tasks such that the time constraints are always met. The two very important basic models in this regard are Periodic Task model and Sporadic Task Model. In Periodic task model, separated by a fixed specific time interval, jobs are arriving strictly on time in a periodic manner. In Sporadic task model, there is not such compulsion of following the periodicity. Tasks can arrive at any time instance once a minimum arrival time between the tasks has elapsed since the arrival of latter job of the same task. 1.6.4 TAXONOMY OF SCHEDULING ALGORITHMS Following are the classification of scheduling algorithm on the bases of priority and allocation: Allocation No migration: Tasks assigned to each of the processors, are not permitted to migrate. Task-level migration: Jobs of a single task are allowed to execute on different processors but single job will strictly execute on single processor. Job level migration: Migration is permitted for a single job to execute on multiple processors but parallel execution is not permissible.

1.6 SYSTEM NOMENCLATURE

TERMINOLOGIES

&

In scheduling process of multi-core processors a generally terminologies and notations are followed which help the researchers to classify a consistent nomenclature which is as followed under the heading of classification of multi-core systems with the perspective of scheduling. 1.6.1 CLASSIFICATION OF MULTI-CORE SYSTEMS Categorically, the multi-core processors are classified into three general categories on the basis on scheduling. Heterogeneous In this type, the processors are not identical; the rate of execution of a task is dependent on both the processor and the task. It is understood that not all the tasks may be able to do execution on all different processors [4]. Homogeneous In this type when processors are identical so surely the rate of execution of all the tasks are also symmetrical and same on all the processors [4]. Uniform The speed factor is directly related to the rate of execution in this type of multi-processor [4].

Priority Fixed task priority: Fixed priority of all the jobs in a single task. Fixed job priority: Jobs of a task can have different priorities but the single job has fixed priority. Dynamic priority: A job can have multiple priorities at multiple time-set.

-----------------------------------------------------------------------------------------------------------------------------------------------------------------

EDF scheduling follows fixed job priority whereas the least laxity first scheduling follows Dynamic priority.

tasks has priorities which are represented by the task indices. Explicitly, few of the algorithms are explained as follow: Semi-Partitioned Fixed Priority Scheduling (SPFPS) SPFPS works on the strategy assignment for the assignment proposing linear utilization bound Monitoring Scheduling Algorithm is the tasks [10][11][12]. Extended Boundary fair (E-Bfair) Extended Boundary fair scheduler is considered to be optimal among all for the periodic tasks [4][10][11]. In this the minimization of scheduling points is done by the determining of the next boundary time by considering the irregular intervals of the sporadic tasks. Ant Colony Optimization (ACO) meta-heuristic The system works on a random no. of heterogeneous multi-core processors with, say, X no. of pre-emptive multi-core processors. In which each processor is bound to operate or execute single instruction per clock cycle with variable speed as per requirement of the tasks that are performing [11][24]. By utilizing the execution time factor and number of clock cycles the energy consumption is analyzed and estimated. Zero-Laxity policy (ZL) This policy works on the principle of assigning highest priority to the zero or negative laxity job and then assigns priorities to the remaining jobs as per the actual algorithm policy [25]. The algorithm is based on priority driven policy. A task starts a set of jobs separated by the factor of period from its forerunning job. In this policy, the platform is consisted of, say, X identical unitcapacity processors. The system does not undergo any penalty when a job is anticipated, pre-empted or when a job is migrated from one processor to the other. Semi-Partitioned (SPHRTS) Hard Real-Time Scheduling of least workload of next task by [11]. RMS or Rate applied to schedule

1.7 REAL-TIME PERFORMANCE METRICS

The effectiveness of scheduling algorithms and schedulable analyses comparison can be done by the four performance metrics [4]. They are as follow: Utilization bounds Approximation ratios Resource extension or speedup process Empirical measurements

1.8 SCHEDULING ALGORITHM BASED ON NON-PRE-EMPTIVE AND PRE-EMPTIVE SYSTEMS

Real-time systems implementation can be distinguished on the basis of Preemption or Non-Preemption. As preemption and non-preemption is defined earlier that, Preemption is one in which a task is suspended temporarily, which is being carried out by the system, without its assistance, and with the intent of resuming it later whereas, the non-preemption doesnt allow preemption. Comparatively, it is convenient and easier to implement preemptive scheduling algorithms for realtime systems. On the other hand, non-preemptive scheduling is relatively efficient, particularly for soft realtime applications, than the preemptive approach. Non-preemptive scheduling can exhibit dramatically lower overhead at run time whereas, the overhead of preemptive algorithms is quite complex to characterize and predict than that of non-preemptive algorithms. Non-preemptive scheduling on a uni-processor fully provides exclusive access to shared resources and data, which finishes the need for synchronization as well as its related overhead whereas, in Preemption involves this whole process. 1.8.1 IMPLIED METHODOLOGIES PREEMPTIVE TASK SCHEDULING FOR

Multi-core processors platform has, say, X identical processors and, say, Y independent tasks. In real-time scenario these tasks are typified by the Worse Case Execution Time or WCET, deadline and completion time .Arranged or sorted in the increasing order, these

The technique or the algorithm based on the concept of semi-partitioned scheduling consisted of strict migrations, where two subsequent jobs, followed by periodicity strategy, can be assigned to the two different

-----------------------------------------------------------------------------------------------------------------------------------------------------------------

processors [26]. Based on pre-emptive scheduling, tasks are assigned by EDF with strict migration policy. Before defining next Scheduling policy, a brief go through to the preliminary concept. A scheduling policy is designed which employs the two scheduling properties called job urgency and inter-job concurrency to assign priorities to the jobs. Primarily, a scheduling policy called DDF (Dynamic Density First) is developed, in which allocate a higher priority to a job with a larger dynamic density [11][12]. Lagging And Dynamic Density (LADD) Lagging And Dynamic Density scheduler is acquired from DDF schedule. LADD categorize jobs into lagging and non-lagging groups [11][27]. Lagging group has higher priority jobs whereas, those in the non-lagging group has lower priorities. LADD prioritize in the order that the lagging jobs come first and then jobs with higher dynamic density. Allowance-fit Another real-time, partitioned, processor scheduling algorithm, Allowance-fit, works on the problem for sporadic tasks having strict deadlines constrain & works on a fixed priority scheduling [28]. This technique allocates tasks to the processors by the method of allowance criteria. Its core purpose is to divide the tasks as equivalently as possible among the processors. Partitioned Deadline Monotonic Scheduling (PDMS) Multiprocessor Hierarchical Synchronization Protocol (MHSP) works on the principle of scheduling synchronization protocol [11][22]. It is designed for hierarchically scheduled multiprocessor systems and is proposed to deal with both partitioned and global scheduling approaches used in Multiprocessor Synchronization Hierarchical Scheduling (MSHS) []. It assembles those tasks, which have dependency on each other and follows the mutual exclusion principle to share the resources, into a separate independent components. A global scheduler then schedules the components on the core.

Lifetime Reliability-Aware Task Allocation (LRATA) Lifetime Reliability-Aware Task Allocation (LRATA) scheduling works on the aging effects of the processors. The multi-core is consisted of, say, M heterogeneous un-identical processors. A task can utilize different time of execution and powers on different processors. So, each one of the task is differentiated or categorized by its execution time and the total power consumption on different processors. Energy Efficient Scheduling (EES) Energy Efficient Scheduling (EES) is power utilization aware scheduling scheme [11]. It has been designed to trim down the power consumed unnecessarily. It works on the Dynamic Voltage Scaling (DVS) technology. Pfair global task scheduling (Pfair) Pfair global task scheduling is the real-time scheduling algorithm [10][11]. In this all tasks are characterized by their release time, execution time, priority, period and deadline. By utilizing these factors, the weight of the task can be predicted. Pfair simply applies the method to utilize the deadline and weight of the tasks to characterize their priorities. Gang EDF The Gang Earlier Deadline First algorithm is a widespread scheduling algorithm for real-time systems whether Uni-or Multi-processors [10][11][17][18]. EDF scheduling is the dynamic priority driven scheduling algorithms. Gang EDF simply applies the Earlier Deadline First policy. Earlier the deadline, highest is the priority. Real-time TAsk Splitting (ReTAS) scheduling algorithm

Real-time TAsk Splitting (ReTAS) scheduling algorithm [11] allocates mostly un-split tasks to a single processor while split tasks are assigned to two or more processors. It divides the time into equivalent duration time-slots and in each timeslot processor consists of one or more time reserves.

-----------------------------------------------------------------------------------------------------------------------------------------------------------------

Synchronization Aware Task Allocation (SATA) SATA decreases scheduling penalties undergone by tasks due to remote blocking [11][29]. So a synchronization conscious partitioned fixed priority scheduler is designed which does not supports task migration. The fundamental thought is to group the tasks that require common shared resource and reorganize them by converting global resource sharing into local sharing. 1.8.2 SUMMARY FEATURES SCHEDULING ALGORITMHS Algorithms SPFPS E-Bfair ACO metaheuristic ZL Policy SPHRTS LADD Allowance-fit PDMS LRATA EES EPfair Gang EDF ReTAS SATA Features Effective System utilization Minimization of Scheduling points & overheads Resource & Energy objective Priority-driven & work-conservative First-fit-decreasing or periodic strategy Lagging: higher priority, Non-Lagging: lower priority Allowance criteria Uni-processor synchronization protocols called Stack-based Resource allocation Protocol Processor Aging Effect Reduce Power Consumption Dynamic priority allocation Earlier Deadline; Highest Priority Slot-based tasks splitting Synchronization penalties OF PREEMPTIVE

ACO metaheuristic

High

Medium

Medium

Low

No

Yes

ZL Policy

SPHRTS

LADD

Allowancefit

PDMS

LRATA

EES

EPfair

Medium

Medium

Low

Low

No

Gang EDF

High

High

Medium

Medium

Yes

ReTAS

SATA

1.8.3 COMPARISON TECHNIQUES

BETWEEN

SCHEDULING 1.8.3 IMPLIED METHODOLOGIES PREEMPTIVE TASK SCHEDULING FOR NON-

Algorithms

CPU Utilization

Through put

Turnaround Time

Response time

Deadline handling

Starvation free

Earliest Deadline First (EDF) Scheduling

SPFPS
High high No

E-Bfair

Low

Low

High

High

No

Yes

The Earlier Deadline First algorithm is a wide-spread scheduling algorithm for real-time systems whether Unior Multi-processors [10][11][17][18][22]. EDF scheduling is the dynamic priority driven scheduling algorithms, as explained in Preemptive Scheduling techniques. The

-----------------------------------------------------------------------------------------------------------------------------------------------------------------

tasks are chosen for execution in the higher order of their deadlines. First Come First Served (FCFS) Scheduling FCFS scheduling follows a simple principle of first in, first out (FIFO) queuing scheme [][][30]. Its average wait time is relatively longer to EDF. It is a nonpreemptive scheduling technique focusing on the nonfavored effect in I/O-bound applications. As large amount of idle times occur and processes stay idle waiting for the Central Processing Unit (CPU)-bound process to finish. Round Robin (RR) Scheduling Round-Robin scheduling [30] is a bit similar to FCFS scheduling with the extension of preemptive ability. As the name suggests, on each time quantum a new process receives access to the system resources. In this technique the process gets access to the system resources without having to wait for all processes running ahead of it to get complete first. Shortest Job First (SJF) Scheduling SJF can be implemented for both the preemptive or non-preemptive tasks [30]. It has short average waiting time and is optimal with respect to average waiting time. It works on the principle, shorter the job; earlier will be the execution. Group-EDF (gEDF) Scheduling Group-EDF can lessen the average response time for tasks. It is a bit deviation of EDF. In gEDF, tasks with same deadlines are assembled and the SJF algorithm is used for scheduling tasks within this assembled group [4][11][12][17]. 1.8.4 SUMMARY FEATURES SCHEDULING ALGORITMHS Algorithms EDF FCFS Round Robin SJF gEDF OF PREEMPTIVE

1.8.5 COMPARISON TECHNIQUES

BETWEEN

SCHEDULING

Algorithms

CPU Utilization

Throughput

Turnaround Time

Response time

Deadline handling

Starvati on free

EDF

High

High

Medium

Yes

No

FCFS

Low

Low

High

High

No

Yes

Round Robin

High

Medium

Medium

Low

No

Yes

SJF

Low

High

Yes

No

gEDF

1.9 CONCLUSION
In this survey paper, detailed work has been presented on the historical background, the generations of microprocessor and the shifting of single-core processor to the multi-core. The real time task scheduling algorithms in multiprocessors are also reported with each briefly explained. The characteristics of the fundamental architecture of the microprocessor are also explicated. The tasks involved and the parameters utilized by the assortment of scheduling algorithms for both the preemption and non-preemption based, and at the end a brief summary of the scheduling algorithms are congregated together in the form of a table for each approach. This survey of past and existing algorithms is merely an effort to reveal the research challenges existing in this field of real time task scheduling.

Features Earlier deadline; Highest priority First in, first out Time based scheduling shorter the job; earlier will be the execution Reduction of average response time

-----------------------------------------------------------------------------------------------------------------------------------------------------------------

REFERENCE
[1].
Multi-core Architecture by Nabendu Karmakar; Computer Science & Engineering; North Maharashtra University, India. [2]. Multicore Processors A Necessity by Bryan Schauer, ProQuest DiscoveryGuide, Released September 2008 [3]. Multi-Core Programming; Increasing Performance through Software, Multi-threading by Shameem Akhter & Jason Roberts, Intel Press,Intel Corporation 2006 [4]. A Survey of Hard Real-Time Scheduling for Multiprocessor Systems by ROBERT I. DAVIS and ALAN BURNS, University of York [5]. Multi-core processors An overview by Balaji Ven, Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool, UK [6]. Embedded Multi-core Processors by Philipp Zech, Philipp.Zech@student.uibk.ac.at, Seminar Embedded System Design, WS 2007/08, Institute of Computer Science, University of Innsbruck, January 11, 2008 [7]. REAL TIME OPERATING SYSTEMS, Lesson-13: Hard and Soft Real Time Design Considerations Chapter-8 L13: "Embedded Systems - Architecture, Programming and Design, Raj Kamal, Publs.: McGraw-Hill, Inc. [8]. Parallel and Distributed Computing, Lec # 12, rev1 [9]. A Survey of Multicore Processors, A review of their common attributes by Geoffrey Blake, Ronald G. Dreslinski, and Trevor Mudge, IEEE SIGNAL PROCESSING MAGAZINE, NOVEMBER 2009 [10]. Thesis on Soft Real-Time Scheduling on Multiprocessors by UmaMaheswari C. Devi Chapel Hill 2006 [11]. A Survey on Real Time Task Scheduling, G. Umarani Srikanth, A. P. Shanthi, V. Uma Maheswari, Arul Siromoney. [12]. An Experimental Comparison of Different RealTime Schedulers on Multicore Systems by Juri Lelli, Dario Faggioli, Tommaso Cucinotta, Giuseppe Lipari, May 9, 2012, Preprint submitted to Elsevier [13]. Book: Measuring Performance of Soft Real-Time Tasks on Multi-core Systems by Salman Rafiq, Master of Science Thesis, Stockholm, Sweden 2011 TRITA-ICT-EX2011:63.

[14]. Optimizing Software for Multi-core Processors, White Paper by Intel Corporation Prefetching. [15]. Real-time scheduling of transactions in multicore systems, Tou k Sarni, Audrey Queudet, Patrick Valduriez, December 18, 2008, inria-00368996, version 1 - 18 Mar 2009 [16]. Thread Scheduling for Multi-Core Platforms by Mohan Rajagopalan Brian T. Lewis Todd A. Anderson, Programming Systems Lab, Intel Corporation, Santa Clara, CA 94054 [17]. Supporting Soft Real-Time Parallel Applications on Multicore Processors by Cong Liu and James H. Anderson, Department of Computer Science, University of North Carolina at Chapel Hill [18]. Soft Real-Time on Multiprocessors: Are Analysis-Based Schedulers ReallyWorth It? By Christopher J. Kennay, Jonathan L. Hermany, Bjorn B. Brandenburgy, Alex F. Millsz, and James H. Andersony, Departments of Computer Sciencey and Statistics and Operations Researchz, The University of North Carolina at Chapel Hill [19]. Soft Real-Time Scheduling on Performance Asymmetric Multicore Platforms by John M. Calandrino, Dan Baumberger, Tong Li, Scott Hahn, and James H. Anderson; Intel Corporation, Hillsboro, OR, Department of Computer Science, The University of North Carolina at Chapel Hill. Proceedings of the 13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS'07) [20]. www.Loremate.com, Chapter 1: Introduction Real Time System [21]. Real-Time Response on Multicore Systems: It is Bigger Than You Think by Paul E. McKenney, IBM Distinguished Engineer, Linux Technology Center (Linaro), 10 July 2012, Intel Corporation 2009 [22]. Scheduling Parallel Real-Time Tasks on Multicore Processors by Karthik Lakshmanan, Shinpei Kato, Ragunathan (Raj) Rajkumar, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, USA [23]. A Categorization of Real-time Multiprocessor Scheduling Problems and Algorithms by John Carpenter, Shelby Funk, Philip Holman, Anand Srinivasan, James Anderson, and Sanjoy Baruah, Department of Computer Science, University of North Carolina at Chapel Hill

-----------------------------------------------------------------------------------------------------------------------------------------------------------------

[24]. Hua Chena, Albert Mo Kim Cheng, Ying-Wei Kuo, 2011. Assigning real time tasks to heterogeneous processors by applying ant colony optimization, Journal of Parallel and Distributed Computing, 71, pp.132-142 [25]. Jinkyu Lee, Arvind Easwaran, Insik Shin, Insup Lee, 2011. "Zero-Laxity based Real-Time Multiprocessor Scheduling", Journal of Parallel and distributed computing [26]. Franois Dorin, Patrick Meumeu Yomsi, Jol Goossens, Pascal Richard, 2010. Semi-Partitioned Hard Real-Time Scheduling with Restricted Migrations upon Identical Multiprocessor Platforms [27]. Jinkyu Lee, Arvind Easwarany, Insik Shin, Insup Leez, 2010. Multiprocessor Real-Time Scheduling Considering Concurrency and Urgency, ACM SIGBED Review, Vol -7 [28]. Fauberteau, F, Midonnet, S, George, L, 2009. Allowance-Fit: A Partitioning Algorithm for Temporal Robustness of Hard Real-Time Systems upon Multiprocessors, IEEE Conference on Emerging Technologies & Factory Automation [29]. Lakshmanan.K, de Niz D.D, Rajkumar R, 2009; Coordinated Task Scheduling, Allocation and Synchronization on Multiprocessors; Proceedings of IEEE Real-Time Systems Symposium RTTS9, pp. 469 478 [30]. Chapter no. 5; CPU SCHEDULING, Operating th Systems Concepts; 7 ed. by Silberschatz, Galvin and Gagne

-----------------------------------------------------------------------------------------------------------------------------------------------------------------