EENG 320 Electronics

Technical Memorandum #3
Lab 3: Silicon Diodes Characterization

By: Eric Apgar Pro essor: Dr. Wu !lass: Electronics 1 "ue: 9/26/2012

E#$eriment: Silicon Diodes Characterization %ntroduction: An experi ent !as per"or ed in !hich three di""erent #ariations o" circuits re#ol#ing around the use o" diodes !ere co pared in $ultisi "or to their ph%sical constructions in order to #ie! se#eral &e% characteristics. 'a el%( o)ser#ations !ith regards to ho! accurate $ultisi !as in its portra%al o" diode circuits !ere recorded in the hopes o" a&ing an accurate assess ent o" $ultisi *s diode a)ilities. +n particular( Crude( Standard( and ,heoretical diode odels !ere )uilt )oth in $ultisi and on an E-.+S )oard. .oltages and currents at #arious points on the circuit !ere easured and co pared to the co putational expressions a#aila)le "or easuring #oltage and current and these theoretical #alues !ere co pared to the E-.+S )oard easured #alues. &esults and "iscussion: ,he construction o" a /Crude0 diode circuit 12igure 13 !as the "irst circuit in the experi ent to )e )uilt and tested. Also called an /ideal diode expression(0 the crude circuit !as )uilt "ro a single diode and 1 &4 resistor in series !ith each other and su)se5uentl%( a #ar%ing nu )er o" #oltages 1ranging "ro 61 . to 7 . and increasing in .7 #olt incre ents3 !as applied across the circuit and the output #oltage !as easured 8 the easure ents o" !hich !ere precisel% recorded and docu ented in 2igure 2. As o)ser#ed "ro the graph in "igure 2( the theoretical $ultisi #alues o" the output #oltages are practicall% identical to the practical #alues easured "ro the E-.+S )oards !hich suggests that the t!o ethods o" anal%zing a diode Crude circuit are )oth accurate to a #er% precise degree. 9ecause o" the high degree o" o#erlap in the plotting o" the t!o sets o" #alues strongl% corresponds to the assu ption that the t!o ethods o" easure ent are not onl% precise )ut consistentl% accurate( seeing as the #alues "ro )oth ethods "ollo! each other closel% "or the entire data co pilation.

'i(ure ): ,he Crude diode circuit depiction in $ultisi and the corresponding readout "ro the E-.+S )oard con"iguration sho!ing the easured #oltage at an input #oltage o" 7 #oltage.

'i(ure 2: ,he chart depicting the output #oltages o" the $ultisi the output #oltages easured )% the E-.+S )oard.

si ulations as co pared to

+n addition to the Crude diode circuit( the Standard circuit !as constructed in )oth "or ats and the #alues "ro each ethod again co pared to each other in co parison "or accurac% and assess ent. ,he Standard diode circuit consisted o" design #er% si ilar to that o" the Crude circuit !ith the exception in design that the resistor and diode !ere s!itched in place( putting the resistor "irst in the circuit ahead o" the diode. ,he sa e ethodolog% !as used in this part o" the experi ent 1as co pared to part 13 !ith the output #oltages "ro the t!o ethods o" easure ent 1$ultisi and E-.+S station3 )eing used to test and assess the a)ilit% o" each ethod to calculate the output #oltages o" the circuit. 2igure : sho!s the circuit design and the corresponding output #oltage #alue at an input #oltage o" 7 #olts "or the E-.+S )oard to de onstrate a )rie" co parison )et!een the t!o circuit designs.

'i(ure 3: ,he circuit design "or the Standard circuit in $ultisi 1le"t3 and the output #oltage easured through the E-.+S station at an input o" 7 #olts 1right3. 2urther ore( 2igure ; sho!s a uch clearer co parison )et!een the t!o sets o" data that !as o)ser#ed "ro #ar%ing the input #oltages and easuring the output #oltages o" the Standard circuit. As in part 1( the inputs range "ro 61 to 7 . and !ere increased in .7 #olt incre ents. ,he chart in 2igure ; also sho!s that the t!o ethods o" data prediction atched up practicall% per"ectl% in their results. ,he data o#erlap "or )oth $ultisi data and the E-.+S )oard data is so close to 100< that it can )e sa"el% said that )oth ethods o" anal%sis !ere accurate representations in !hat the )eha#ior o" the Standard diode circuit loo&s li&e. Another aspect o" part 2 included the calculation o" the current "lo!ing through the diode due the pro#ided calculation "or ula o" +=1.in6.out3/10004. ,his calculation !as to pro#ide a #isual o)ser#ation o" the current "lo! through the diode and ho! the input #oltage a""ects this one aspect o" the Standard circuit. ,he results "ro this calculation o" the theoretical current #alues are listed in 2igure ;. As sho!n )% "igure "our( the current "lo!ing through the diode re ains at 0 A until the input #oltage reaches a)out .> #olts. ,his threshold #oltage that the diode appears to ha#e is !hat it should )e seeing as the diode used !as a .> #olt diode and thus !ould not li&el% de onstrate a lot o" )eha#ior until the threshold acti#ation #oltage o" .> . !as reached as an input. ,his is ?ust one ore indication that the E-.+S )oard !as easuring correctl% the input and output #oltages and that the Standard circuit !as

)eha#ing as it should. 'i(ure *: ,he graph a)o#e displa% the t!o sets o" data o)tained "ro the $ultisi test data and the E-.+S data. ,he identical positions o" the t!o data sets suggests that )oth ethods !ere relia)le !a%s o" collecting Standard circuit data. Also included is the graph depicting the calculation o" the current "lo! through the diode. ,he "inal part o" the experi ent !as the creation and testing o" the "inal circuit design( the ,heoretical diode design "or a circuit. ,his design 1sho!n in 2igure 73 consisted o" a t!o diode co )ination in parallel !ith each other. ,he sa e ethod o" appl%ing #aried #oltages to the input and easuring the output #oltages that !as used in all pre#ious instances !as used in this case as !ell !ith the exception that the applied #oltages ranged "ro 62 to 2 . and !as incre ented in .2 . steps.

'i(ure +: ,he $ultisi ,heoretical diode circuit and the E-.+S recorded output #oltage at an input #oltage o" 2 #olts.

easure ent o" the

,he "inal part o" the experi ent !as slightl% di""erent in execution as co pared to the pre#ious parts. +n one aspect( the resistance o" the