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Techno India EM-4/1, Sector-V, Salt Lake City, Kolkata- 700091

CSE 3rd Semester (2012-2016) Assignment list 1 Subject Name: Computer Organization Subject Code: CS 303 Submission date: 23.10.2013 1. The IBM short oating point representation uses base 16, one sign bit, a seven-bit excess 64 exponent and a normalized 24-bit fraction. a) What number is represented by the bit pattern shown below? 1 0111111 01110000 00000000 00000000 Show your answer in decimal. Note: the spaces are included in the number for readability only. b) Represent (14.3)6 in this notation. 2. For parts (a) through (e), use a floating point representation with a sign bit in the leftmost position, followed by a two-bit twos complement exponent, followed by a normalized three-bit fraction in base 2. Zero is represented by the bit pattern: 0 0 0 0 0 0. There is no hidden 1. a) What decimal number is represented by the bit pattern: 1 0 0 1 0 0? b) Keeping everything else the same but changing the base to 4 will: increase / decrease / not change the smallest representable positive number. c) What is the smallest gap between successive numbers? d) What is the largest gap between successive numbers? e) There are a total of six bits in this floating point representation, and there are 26 = 64 unique bit patterns. How many of these bit patterns are valid? 3. Represent (107.15)10 in a floating point representation with a sign bit, a seven-bit excess 64 exponent, and a normalized 24-bit fraction in base 2. There is no hidden 1. Truncate the fraction by chopping bits as necessary. 4. i)Show the IEEE 754 bit patterns for the following numbers: a) +1.1011 25 (single precision) b) +0 (single precision) c) 1.00111 21 (double precision) d) NaN (single precision)

4. ii) Represent (107.875)10 in the IEEE-754 single precision floating point representation which has a sign bit, an eight-bit excess 127 exponent, and a normalized 23-bit significand in base 2 with a hidden 1 to the left of the radix point. Truncate the fraction if necessary by chopping bits as necessary. Show your work.

5. Using the IEEE 754 single precision format, show the value (not the bit pattern) of:

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a) The largest positive representable number (note: is not a number). b) The smallest positive nonzero number that is normalized. c) The smallest positive nonzero number in denormalized format. d) The smallest normalized gap. e) The largest normalized gap. f ) The number of normalized representable numbers (including 0; note that and NaN are not numbers). 6. The 16-bit adder shown below uses a ripple carry among four-bit carry look ahead adders.

(a) What is the longest gate delay through this adder? (b) What is the shortest gate delay through this adder, from any input to any output? (c) What is the gate delay for s12? 7. Given multiplication units that each produce a 16-bit unsigned product on two unsigned 8-bit inputs, and 16-bit adders that produce a 16-bit sum and a carry-out on two 16-bit inputs and a carry-in, connect these units so that the overall unit multiplies 16-bit unsigned numbers, producing a 32-bit result. 8. Add (641)10 to (259)10 in unsigned BCD, using as few digits in the result as necessary. 9. A pocket pager contains a small processor with 27 8-bit words of memory. The ISA has four registers: R0, R1, R2, and R3. The instruction set is shown in figure as well as the bit patterns that correspond to each register, the

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Techno India EM-4/1, Sector-V, Salt Lake City, Kolkata- 700091

Instruction format, and the modes, which determine if the operand is a register (mode bit = 0) or the operand is a memory location (mode bit = 1). Either or both of the operands can be registers, but both operands cannot be memory locations. If the source or destination is a memory location, then the corresponding source or destination field in the instruction is not used since the address field is used instead. (a) Write a program using object code (not assembly code) that swaps the contents of registers R0 and R1. You are free to use the other registers as necessary, but do not use memory. Use no more than four lines of code (fewer lines are possible). Place 0s in any positions where the value does not matter. (b) Write a program using object code that swaps the contents of memory locations 12 and 13. As in part (a), you are free to use the other registers as necessary, but do not use other memory locations. Place 0s in any positions where the value does not matter. 10. (a) Write three-address, two-address, and one-address programs to compute the function A = (B-C)*(D-E). Assume 8-bit opcodes, 16-bit operands and addresses, and that data is moved to and from memory in 16-bit chunks. (Also assume that the opcode must be transferred from memory by itself.) Your code should not overwrite any of the operands. Use any temporary registers needed. (b) Compute the size of your program in bytes. (c) Compute the memory traffic your program will generate at execution time, including instruction fetches. 11. A control unit for a machine tool is shown in figure. You are to create the microcode for this machine. The behavior of the machine is as follows: If the Halt input A is ever set to 1, then the output of the machine stays halted forever and outputs a perpetual 1 on the X line, and 0 on the V and W lines. A waiting light (output V) is enabled (set to 1) when no inputs are enabled. That is, V is lit when the A, B, and C inputs are 0, and the machine is not halted. A bell is sounded (W=1) on every input event (B=1 and/or C=1) except when the machine is halted. Input D and output S can be used for state information for your microcode. Use 0s for any fields that do not matter. Hint: Fill in the lower half of the table first.

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12. Design a 16-word, four-bit RAM using 44 RAMs and a single external decoder. 13. Design an eight-word, 32-bit RAM using 8x8 RAMs. 14 Draw the circuit for a 4-to-16 tree decoder, using a maximum fan-in and fan-out of two. 15. A direct mapped cache consists of 128 slots. Main memory contains 16K blocks of 16 words each. Access time of the cache is 10 ns, and the time required to fill a cache slot is 200 ns. Load-through is not used; that is, when an accessed word is not found in the cache, the entire block is brought into the cache, and the word is then accessed through the cache. Initially, the cache is empty. Note: When referring to memory, 1K = 1024. (a) Show the format of the memory address. (b) Compute the hit ratio for a program that loops 10 times from locations 15 200. Note that although the memory is accessed twice during a miss (once for the miss, and once again to satisfy the reference), a hit does not occur for this case. To a running program, only a single memory reference is observed. (c) Compute the effective access time for this program. 16. A fully associative mapped cache has 16 blocks, with eight words per block. The size of main memory is 216 words, and the cache is initially empty. Access time of the cache is 40 ns, and the time required to transfer eight words between main memory and the cache is 1 s. (a) Compute the sizes of the tag and word fields. (b) Compute the hit ratio for a program that executes from 2045, then loops four times from 2845 before halting. Assume that when there is a miss, that the entire cache slot is filled in 1 s, and that the first word is not seen by the CPU until the entire slot is filled. That is, assume load-through is not used. Initially, the cache is empty. (c) Compute the effective access time for the program described in part (b) above. 17. A computer has 16 pages of virtual address space but only four physical page frames. Initially the physical memory is empty. A program references the virtual pages in the order: 0 2 4 5 2 4 3 11 2 10. (a) Which references cause a page fault with the LRU page replacement policy? (b) Which references cause a page fault with the FIFO page replacement policy?

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18. A virtual memory system has a page size of 1024 words, eight virtual pages, four physical page frames, and uses the LRU page replacement policy. The page table is as follows:

(a) What is the main memory address for virtual address 4096? (b) What is the main memory address for virtual address 1024? (c) A fault occurs on page 0. Which page frame will be used for virtual page 0? 19. When running a particular program with N memory accesses, a computer with a cache and paged virtual memory generates a total of M cache misses and F page faults. T1 is the time for a cache hit; T2 is the time for a main memory hit; and T3 is the time to load a page into main memory from the disk. (a) What is the cache hit ratio? (b) What is the main memory hit ratio? That is, what percentage of main memory accesses do not generate a page fault? (c) What is the overall effective access time for the system? 20. How much storage is needed for the page table for a virtual memory that has 232 bytes, with 212 bytes per page, and 8 bytes per page table entry? 21. A certain memory system has a 32 MB main memory, and a 64 KB cache. Blocks are 16 bytes in size. Show the fields in a memory address if the cache is a. associative b. direct-mapped c. 8-way set-associative 22. Design a circuitry for 5-bit comparator 23. A disk has an average seek time of 20 ms and an average rotational latency of 16.7 ms. its transfer rate is 2.0 MB/s. What size block is necessary so that delay in locating the data is only 50% of the total time to read or write a block. Discuss whether all of a virtual memory page of this size would be likely to be accessed in main memory before it is replaced.

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24. Design a 3-bit carry lookahead adder and determine the maximum number of gates between any input and each of the four outputs (3 sum bits and a carry). 25. How many gate delays are there in the longest path from some input to some output of a 64-bit adder using 4-bit carry lookahead groups and a multiple level structure? Compare with the longest path for a 64-bit ripple carry adder. 26. Convert the following decimal numbers to IEEE single-precision floating-point numbers. Report the results as hexadecimal values. You need not extend the calculation of the significand value beyond its most significant 8 bits. a. -65 b. 7.3125 c. 0.8 d. 0.000083 e. 72,000,831 f. -42.16 g. 6.02 x 1023 27. Write an ANSI C program to convert a decimal number to a 32-bit IEEE real. Report the result as a hexadecimal number, and also in scientific notation: n.nnn x 1Onn. 28. In a computer instruction format, the instruction length is 11 bits and the size of an address field is 4 bits. Is it possible to have: 5 2-address instructions 45 1-address instructions 32 0-address instructions using the format? Justify your answer. b. Assume that a computer architect has already designed 6 two-address and 24 zeroaddress instructions using the instruction format above. What is the maximum number of one-address instructions that can be added to the instruction set? 29. A set associative cache consists of 64 slots divided into 4-slot sets. Main memory contains 4K blocks of 128 words each. Show the format of the main memory address. 30. Using the page table shown below, translate virtual address 2050 into a physical address, and translate physical address 25 into a virtual address. Address length is 16 bits, page size is 2048 words. Physical memory has 4 page frames. Page Present (1-in/0-out) Page Frame 0 1 3 1 1 2 2 1 0 3 0 --

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31. An operating system uses a Least Recently Used (LRU) page replacement algorithm. Consider the following page reference ordering (pages are referenced from left to right): 1, 8, 1, 7, 8, 2, 7, 2, 1, 8, 3 What will be the number of page faults that are generated for this particular LRU case assuming that the process has been allocated four page frames, and that initially, none of the pages are in the main memory? 32. If a virtual memory system has 4 pages in real memory and the rest must be swapped to disk, determine the hit ratio for the following page address system. Assume memory starts empty. Use the First In First Out (FIFO) page replacement policy. Choose the closest answer. PAGE REQUESTS: 2 5 3 4 1 4 7 2 1 3 1 7 4 5 4 6

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