EGR 278 Digital Logic Lab File: N278L2A

Lab # 2

Characteristics of Logic Gates

A.

Objectives
The objectives of this laboratory are: to investigate various logic gate characteristics, including voltage and current levels, loading (fanout), and propagation delay. to compare the characteristics of TTL gates as measured using the 7400 quad 2-input NAND with the characteristics of CMOS gates as measured using the 74HC00 quad 2-input NAND.

B.

Materials
Breadboard Tektronix P5280 DC Power Supply Agilent 33120A Function Generator Tektronix TDS 2002 Digital Storage Oscilloscope Agilent 33401A Digital Multimeter (Two) Micronta Digital Logic Probe Six 7400 Quad 2-input NAND ICs One 74HC00 Quad 2-input NAND ICs 7400 Specification Sheet 74HC00 Specification Sheet Handout: "Downloading Data Sheets from the Internet"

C.

Introduction
The physical characteristics of logic gates often play an important role in the design of digital circuits. This lab focuses on several of these characteristics, including: voltage and current levels noise margin fanout and loading propagation delay Each of these physical characteristics are discussed below. Voltage and Current Levels Several voltage and current levels are of interest when working with logic gates, including: VOL = output voltage when the gate is LOW VOH = output voltage when the gate is HIGH VIL = input voltage when the gate is LOW VIH = input voltage when the gate is HIGH IOL = output current when the gate is LOW IOH = output current when the gate is HIGH IIL = input current when the gate is LOW IIH = input current when the gate is HIGH

Page 2 The voltages defined above have fixed values for TTL devices (as seen in the specification sheet), but CMOS devices have values that depend on the supply voltage (VDD) as shown below. VDD is typically from 2 V to 6 V. Voltage Defined Value for CMOS devices VIL 0 to (20% of VDD) VIH (70% of VDD ) to VDD VOL 0 to (1% of VDD) VOH (99% of VDD ) to VDD IIH , IIL < 1 A Noise Margins VOL(max) is lower than VIL(max) to allow for noise and signal deterioration. Similarly VOH(min) is higher than VIH(min). These differences in voltages are referred to as noise margins. Defined more exactly: VNL = LOW level noise margin = VIL(max) - VOL(max) VNH = HIGH level noise margin = VOH(min) - VIH(min) For standard TTL devices: VNL = 0.8 V - 0.4 V = 0.4 V VNH = 2.4 V - 2.0 V = 0.4 V These TTL noise margins are illustrated below:
5.0V Range of valid output HIGH voltages 2.4V HIGH Noise Margin 2.0V Output 0.8V Range of valid output LOW voltages LOW Noise Margin 0.4V 0.0V 0.0V Range of valid input LOW voltages Input 5.0V Range of valid input HIGH voltages

For HC CMOS devices the noise margin depends on VDD (see table above). If VDD = 5V, then VNL = 0.19VCC = 0.95 V VNH = 0.29VCC = 1.45 V Fanout Fanout is the number of standard loads that the output can drive. The number of standard loads is limited by the amount of input current each load requires as compared to the current that the driving gate can deliver. Fanout, therefore, is generally considered to be the smaller of the following two items:
fanout = I OL (max) I OH (max) or fanout = I IL (max) I IH (max)

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Fanout is 10 for standard TTL devices. This is illustrated below using 7400 NANDs (with their inputs tied together to act as inverters) where the output of the driving gate is LOW. Note that IOL (max) is -16 mA and IIL(max) = -1.6 mA.
1.6 mA (max) 1.6 mA (max) 16 mA (max) 1.6 mA (max)

LOW

10 loads at 1.6 mA/load = 16 mA

1.6 mA (max)

Note that IIL(max) = -1.6 mA, but a typical value would be significantly less, so a fanout of 10 is a conservative estimate. A given circuit might be able to drive more actual loads than 10 without exceeding max values for IOL or IOH . Fanout for HC 7400 series devices is calculated to be a huge 4000, but this may not be feasible. What it essentially means is that fanout is not a concern with CMOS loads. Propagation Delay Propagation delay is the time that it takes a gate to switch logic levels. Logic gates often have a different propagation delay switching from LOW to HIGH than from HIGH to LOW, so two types of delay are defined: tPLH = propagation delay when the OUTPUT switches from LOW to HIGH tPHL = propagation delay when the OUTPUT switches from HIGH to LOW An illustration of each type of propagation delay is shown below.
Input Output

Output

t PLH

50 % Input t PHL

Note that propagation delay is greatly affected by the load being driven by the gate. For HC CMOS, for example, each pF of load capacitance (beyond the 50 pF listed as the load for the specification sheet) adds about 0.66 ns to the propagation delay value. Each HC CMOS load adds 10 pF of capacitance thus increasing the propagation delay by about 6.6 ns. Propagation delay is also affected by the supply voltage for HC CMOS devices. Propagation delay is listed as 33 ns at 6V and 195 ns at 2V (with a 50 pF load).

Page 4 Static-Sensitive Devices One characteristic of CMOS devices is that they are subject due to damage to electrostatic discharge (ESD). They are often referred to as static-sensitive devices. A large voltage placed across the very high input resistance of a CMOS circuit produces internal voltages that are sufficient to destroy the gate oxide of the input field-effect transistors. A person can easily develop static electricity on their fingertips of several thousand volts by simply walking across a carpeted or waxed floor. This problem is even more severe in low humidity environments. Therefore, improper handling of a CMOS device can easily destroy it. Many CMOS devices, including the 74HC00 series devices, now contain some built-in ESD protection, but they can still be somewhat easily damaged. Note that static-sensitive devices are packaged in special anti-static containers or foam. Another important point is that CMOS devices can sometimes be only partially damaged, leading to erratic behavior. Problems due to this type of damage can be very difficult to troubleshoot. A professional workplace that deals with static-sensitive devices may take numerous precautions to insure that CMOS devices are not damaged due to ESD. Many of these are illustrated in the diagram of a static-free workstation shown below, including grounded wrist straps, ESD protective floor mats and table tops, and humidifiers or ionizers. Note that we do not have static-free workstation available. However, a few simple precautions can help minimize the chance that you will destroy your CMOS devices: Avoid directly touching the pins on any CMOS IC Use a chip extractor when removing CMOS ICs from a breadboard Keep CMOS ICs in anti-static containers when not in use Make contact with a breadboard with your hands before inserting the CMOS IC into the breadboard Once the CMOS IC has been inserted into the breadboard, treat the breadboard as an extension of the IC and use the same precautions with the breadboard as you would use with the IC. For example, make contact with the breadboard using your hands before inserting wires into the breadboard or touching a logic probe to any wire or pin inserted in the breadboard.

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D.

Preliminary Work
1. Present a documented circuit layout for Circuit 1 (part A only) below including pinouts for all ICs used, a detailed circuit diagram with pin numbers labeled (also include input switches, measurement equipment, etc.), a diagram showing the ordering of the ICs on the breadboard and the numbering (U1, U2, ) of each IC, and a wiring list. Repeat step 1 for Circuit 2, 3, and 4. Electrical Engineers until quite recently might commonly have had dozens of data books in their office so that they could check the specifications of components. This information is now commonly available over the internet and is a valuable asset. Refer to the handout provided in class: "Downloading Data Sheets from the Internet". Print out the complete data sheet for one device shown below according to the first letter of your last name as indicated below. Attach the data sheet to your report. If your last name Print out the data sheet begins with for the following device A-B 7402 C-D 7404 E-F 7408 G-H 7410 I-J 7413 K-L 7420 M-N 7425 O-Q 7427 R-S 7430 T-V 7432 W-Z 7486

2. 3.

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E.

Laboratory Work
1. Measurement of Voltages and Currents A) Construct Circuit 1 from the wiring list using a 7400 IC. Note any changes. Apply a HIGH input to the first gate (thus the output is LOW) and measure the input current (IIL) to the second gate and the output voltage (VOL) of the first gate using a digital multimeter. Repeat the measurements with a LOW input to the first gate (thus the output is HIGH) and measure the input current (IIH) to the second gate and the output voltage (VOH) of the first gate. Record the results in the table below and verify that these values are within specified limits. Measured Value Specified Value Within Specs? IIL VOL IIH VOH B) Practice using a logic probe by checking a HIGH voltage (on pin 14) and a LOW voltage (on pin 7). Then use a logic probe to check the inputs and outputs on an unused gate on the 7400 (no wires connected to the input or output, but powered up). Complete the table below. Use Logic Probe to measure Results (LOW, HIGH, or NO READING) Open inputs Open output Study the truth table for a 7400 NAND and the results just measured and complete the following statement: Since the open output of the 7400 read ______, it can be stated that OPEN INPUTS FOR 7400 SERIES GATES ACT LIKE _________ . C) Repeat step 1A and 1B using a 74HC00 IC. Be sure to exercise appropriate care since this is a static sensitive device. Assume that VDD = 5V for specifications. Measured Value Specified Value Within Specs? IIL VOL IIH VOH Use Logic Probe to measure Results (LOW, HIGH, or NO READING) Open inputs Open output OPEN INPUTS FOR 74HC00 SERIES GATES ACT LIKE _________ .

Ammeter Input switch (no connection)

Voltmeter

Circuit 1

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Measurement of Input Voltage Ranges A) Construct Circuit 2 from the wiring list using a 7400 IC. Note any changes. Using a variable DC power supply, increase the supply voltage from 0V to 5V in 0.2V increments and record the output voltage in each case in a table (see below). Do not increase the voltage above 5V or you may destroy the IC. Verify that the output voltage is correct for all input voltages that are within specified ranges for HIGH and LOW inputs (check the columns marked valid with L if valid LOW, H if valid HIGH, and N if non valid). Be sure that the current limit is set fully clockwise on the variable DC power supply. Note: Even thought a variable voltage is being applied to the input, be sure that the IC is powered at all times by a constant 5V. B) Repeat step 2A using a 74HC00 IC.

Variable DC Power Supply Voltmeter Circuit 2

Vout versus Vin for 7400 NAND:
Valid Input? Vin (V) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 Vout (V) Valid Output?

(no connection)

Vout versus Vin for 74HC00 NAND:

Valid Input? Vin (V) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 Vout (V) Valid Output?

Are the the outputs valid for all valid inputs? If not, where are they invalid and why?

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Propagation Delay Measurement A) Measure tPLH: Construct Circuit 3 from the wiring list using a 7400 IC. Note any changes. View both waveforms A and B on the oscilloscope and measure tPLH . Sketch the waveforms seen on the oscilloscope as accurately as possible using the oscilloscope screen sheets provided (on the oscilloscope screen be sure to label the input, output, vertical scale (V/div), horizontal scale (us/div). Also mark the delay and label its value and show the calculation for the delay.) B) Repeat part 3A for tPHL . Note that you can switch easily back and forth between tPLH and tPHL by changing the trigger slope on the oscilloscope from +(increasing) to (decreasing). C) Compare the measured values to values found in the specification sheet (see table below).

Use the following settings for the function generator and the oscilloscope.
Tektronix TDS 2002 Oscilloscope Control Setting Ch. 1/Ch. 2 Menu Coupling: DC BW limit: OFF V/div: Coarse Probe: 1X Invert: Off Trigger Menu Type: Edge Source: Ch. 1 Slope: Rising Mode: Auto Coupling: DC Ch.1 V/div 1V Ch. 2 V/div 1V
Agilent 33120A Function Generator 0 to 5V clock (square wave) 100 kHz

Agilent 33120A Function Generator Control Setting (square wave) Function Frequency * 100 kHz Amplitude * 5 Vpp Offset * 2.5 Vpp * Press the green Enter Number button and enter the specified value and the unit.

A Ch. 1

B Ch. 2

Tektronix TDS 2002 Oscilloscope Circuit 3

Measured Value tpHL tpLH

Specified Value

Within Specs?

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4.

TTL Fanout Measurement A) Construct Circuit 4 from the wiring list using a 7400 IC. Note any changes. Construct a table to show the output current versus the number of loads added. Begin to add loads one at a time and record the current in each case (see table below). You should anticipate adding as many as 20 loads before the maximum of 16mA is exceeded. The maximum number of loads added without exceeding 16 mA will be considered to be the fanout for this test case. Compare this value to the rated fanout for standard TTL devices (see table below). Ammeter

HIGH

(load number 1) (load number 2) (load number 3)

(load number N) Circuit 4

# Loads 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IOL (mA)

Measured Value fanout

Specified Value

Within Specs?

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F.

Report
In addition to presenting all measured data neatly and clearly in your report, include the following: 1. Form a graph of Vout versus Vin (with Vout on the y-axis) for the data measured in step 2A of the Laboratory Work. Does the output change gradually or abruptly? Somehow highlight the ranges for valid input LOWs and valid input HIGHs. Repeat step 1 for the data measured in step 2B. Discuss any values that do not fall within specified limits and suggest reasons for the discrepancies. Compare the TTL and HC CMOS families. How are they similar and how are they different? Why do you think that we did not measure fanout for the 74HC00 in step 4 of the Laboratory Work as we did for the 7400?

2. 3. 4.