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TM HIU KIT STARTER SPARTAN 3E


NI DUNG TM HIU: tng quan v vi mch FPGA v cc khi chc nng ca kit Strater Spartan 3E.

CHNG 1:FPGA- Linh kin logic kh trnh:


1.1. Tng qut:
c. Cc loi linh kin kh trnh n gin nh: EPROM, EEPROM, Flash, ROM, PLD. - thun tin cho vic th nghim, to mu, pht trin ng dng, sn xut quy m nh, ngi ta ch to ra cc linh kin logic kh trnh. y l nhng linh kin s c th lp trnh li cho nhng mc ch khc nhau. Actel C hai loi linh kin logic kh trnh chnh: CPLD ( Complex Cc hng sn xut FPGA/ CPLD: Xilinx, Atera, Atmel, QuickLogic, programmable Logic Devices) v FPGA (Field Programmable Gate Array). Trc y phn ln cc linh kin in t l c nh, khng lp trnh

1.2. Khi nim FPGA:


FPGA l vi mch cha cc logic cells. Cc Logic cells thc hin cc mch Logic v c kt ni vi nhaubowir ma trn kt ni v chuyn mch lp trnh c. - FPGA l tp hp cc phn t ri rc c kt ni theo mt cch chung.

1.3. Cc bc thc hin thit k cho FPGA:


- Thit k h thng v to file HDL - Tin hnh th nghim trong HDL v biu din m phng trn RTL. - Tng hp v bin dch. Qu trnh tng hp c nhim v chuyn cc cu lnh HDL thnh cc mc trn linh kin. Qu trnh bin dch s chuyn cc lnh HDL thnh tn hiu vt l trong chip FPGA.

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To v ti file chng trnh. Qu trnh ny s to file netlist. File ny

c ti vo linh kin FPGA tun t va n s iu khin mch logic v cc cng tc.

CHNG 2: nh tuyn v nh v cho FPGAs:


2.1. nh tuyn:
y l mt trong nhng bc c bn v quan trng nht khi thit k FPGA,v l bc cui trong giai on thit k to chui bt cho chng trnh.

2.2. Th h bng nh tuyn ngun:


- Bng nh tuyn ngun c tao ra s dung, gm hai loi: nh tuyn ton cc v nh tuyn cc b. Cc h thng FPGA hin i c s lng bng nh tuyn rt ln vi Trong nhiu trng hp ngi ta cn to cc cng c nh v v nh hng triu khi logic. tuyn cho FPGA. Vic ny m bo an ton khi thay i hay thit lp cc thng s trc khi chng ta hon thin kin trc FPGA. - Qu trnh thit lp thng s cn thit cho vic nh tuyn gm cc bc chnh sau: nh s chn cc khi logic ng vo v ng ra. t cc khi logic ng vo v ng ra trng thi cho php hiu chnh v s dng. Tng ng ha cc khi logic. nh du I/O in vo mt hng hoc ct ca FPGA. Lp quan h v chiu rng gia cc knh ngang v knh dc. Lp quan h v chiu rng gia cc vng khc nhau trong FPGA. Chuyn khi kt ni cc vng nh tuyn ln Thit lp gi tr FC ch gi tr cc vng nh tuyn trong mt knh.

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y c th l s chn ng vo v ng ra c kt ni.

nh loi v phn phi cc gi theo mt tieu chun nht inh. Chng ta cn nh chiu di mi gi, s kha trong mi gi cung nh phn loi kiu gi.
2.2.1.

nh tuyn ton cc:

- nh tuyn ton cc chia cc vng nh tuyn ang hot ng thnh cc knh hay cc khu vc nh tuyn. Trong nh tuyn ton cc, bng nh tuyn ch ra mc nh trc n gin ha qu trnh chn knh nh tuyn Sau y l mt v d v bng nh tuyn ngun:

LUT: Look- Up Table - Thc t th vn nh tuyn ton cc FPGA kh ging vi chun thit k cells (hay MPGA- Metal Programmable Gate Array). V vy nhiu k thut nh tuyn ton cc ASIC c th s dng cho nh tuyn ton cc FPGA.
2.2.2.

nh tuyn cc b:

- Chn nh tuyn cc b theo chi ph thp nht. - Loi b cc nh tuyn cc b khc trong cng khu vc.

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- Loi cc nh tuyn khng tng thch vi nh tuyn va chn cho n khi tt c cc nh tuyn ton cc c hon thin kt ni bi cc nh tuyn cc b.

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CHNG 3:Cc khi chc nng chnh ca kit Spartan 3E:


3.1. Cc cng tc, nt nhn, phm iu khin:
Cc cng tc trt: - KIT Spartan 3E c 4 cng tc trt, nh hnh sau.

- Cc cng tc ny c b tr gc phi, bn di ca board. Chng c k hiu l SW3, SW2, SW1 SW0 theo th t t tri sang phi. - Khi v tr UP hay ON, cng tc ny s kt ni vi chn 3,3V ca FPGA. y l mc logic cao. - Khi v tr DOWN hay OFF, cng tc ny s kt ni vi chn mass ca FPGA. y l mc logic thp.

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Cng

tc

nt

nhn:

- KIT ny cng c 4 cng tc nt nhn. Cng c b tr gc di bn tri ca board, c k hiu ln lt l: BTN_NORTH, BTN_SOUTH, BTN_EAST, BTN_WEST. - Khi nhn v gi, nt nhn s c ni n chn 3,3V ca FPGA. - Trong mt s ng dng, BTN_SOUTH cng l mt reset mm chn chc nng reset cho FPGA. Cng tc nt xoay: - Trn KIT. C 3 nt nhn loi ny, chng nm gia 4 cng tc nt nhn.

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- Khi xoay cc nt ny, cng tc c ni n chn 3,3V ca FPGA. LED: - C 8 LED n trn mch, c k hiu t LED7 n LED0. Theo th t t tri sang phi l LED7 n LED0.

- Mi LED c ni sn mt chn xung mass, chn cn li ni vi KIT Spartan 3E qua mt in tr hn dng 330 Ohm.

3.2.

Clock Sources:board h tr ba ngun xung clock c bn:

B dao ng onboard tn s xung clock 50MHz Xung clock c th c cung cp t ngoi board thng qua SMA-style connector.Ngoi ra FPGA c th pht ra tn hiu xung clock qua SMA-style connector. Hay la chn ci t b dao ng kiu 8 chn DIP cung cp bi mt socket in p cho tt c chn I/O trong FPGA bank0 c iu khin bi jumper JP9.Do ,nhng ngun xung clock ny cng c iu khin bi JP9.Ban u,JP9 c set mc 3.3 V.B dao ng on board l mt thit b c p 3.3 V v c th khng trnh din nh mong i khi JP9 set mc 2.5 V.

3.3.
hnh FPGA:

FPGA Configuration option:

The Spartan-3E FPGA Starter Kit board h tr nhiu s la chn cu Download FPGA design trc tip ti Spartan-3E FPGA thong qua chn JTAG,s dng giao din USB on board.
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Ghi chng trnh trn on-board 4Mbit Xilinx XCFO4S ni tip Platform Flash PROM,sau cu hnh FPGA t nh lu tr trong Platform Flash PROM s dng Mast Serial mode. Ghi chng trnh trn on-board 16Mbit ST Microelectronics SPI serialFlash PROM,ri cu hnh FPGA t nh lu tr trong SPI serial Flash PROM s dng SPI mode. Ghi chng trnh trn 128 Mbit Intel StrataFlash parallel NOR Flash PROM,ri cu hnh FPGA t nh lu tr trong Flash PROM s dng BPI Up hay BPI Down mode.

3.4.

Character LCD Screen:

FPGA iu khin LCD thong qua 4-bit data .Mc d LCD h tr giao din 8 bits data,the starter Kit Board s dng giao din 4 bits data tang kh nng kt ni v s pht trin ca cc ng dng khc trn board cng nh gim thiu s chn kt ni.

- LCD dng ngun 5V. - LCD hiu cc mc logic cao, thp qua in p. mc cao, LCD iu khin mc 5V vi TTL v 3,3V vi LVCMOS.

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- in tr 390 Ohm trn ng Data dng hn dng cho FPGA khi LCD nhn mc logic cao. - Mt s ng dng coi LCD l ngoi vi ch ghi v khng bao gi c. iu khin LCD: - LCD cho php hin th 2 x 16 k t, vi a ch theo bng sau:

3.5.
trc tip t PC

VGA Display Port:

Board gm mt port VGA thong qua DB15 connector.Kt ni port ny

3.6.

RS-232 Serial Ports:

The Spartan-3E FPGA Starter Kit board c hai cng RS-232,mt l u ci DB9 DCE connector v mt u c DTE connector.S dng DTE-style connector iu khin cc ngoai vi RS-232 khc,nh modem hay printers.

3.7.
pins mini-DIN.

PS/2 Mouse/Keyboard Port:

Board bao gm mt PS/2 Mouse/Keyboard Port v mt kt ni chun 6-

3.8. DDR SDRAM :


The Spartan-3E FPGA Starter Kit board bao gm a 512 Mbit (32M x 16) MicronTechnology DDR SDRAM (MT46V32M16) vi giao din 16bit data.Tt c chn giao din DDR SDRAM kt ni ti FPGAs I/O bank3 trn FPGA.I/O Bank 3 v DDR SDRAM c hai ly in p 2.5 V t LTC3412 regulator c kt ni t 5V supply input.

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Ngoi ra The Spartan-3E FPGA Starter Kit board cn c cc cng giao tip khc: 10/100 Ethernet Physical Layer Interface Cc connector m rng

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CHNG 4: KHI NIM,CNG C V K THUT EDK


4.1. Gii thiu:
The Xilinx Embedded Development Kit (EDK) l 1 b cc cng c v IP cho php bn thit k 1 h thng nhng hon chnh ci t cho thit b Xilinx Field Programmable Gate Array (FPGA) Embeded Development Kit: c xem nh bao ph tt c nhng th lin quan n h thng x l nhng v thit k ca chng ,the Xinlinx ISE software phi c ci t trc khi chy EDK. Xilinx Platform Studio (XPS) l mt mi trng pht trin hay giao tip ha s dng thit k b phn phn cng ca h thng x l nhng . Software Development Kit(SDK) l mt mi trng pht trin tch hp Other EDK Components : Hardware IP for Xinlinx embeded processors Driver and lilibraries for embedded software development GNU Compiler and debugger for C/C++ software development targeting the MicroBlaze and PowerPC processors Documentation Sample projects Lm Th No Cc Cng C Ny Xc Tin Qu Trnh X L

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Sau y l mt ci nhn tng qut v cch cc cng c lm vic cng nhau n gin ha qu trnh thit k Tin trnh thit k yu cu c bt u vi mt ISE project,v sau l add mt ngun vi x l nhng vo ISE project. XPS c s dng u tin cho h thng nhng.Cu hnh vi iu khin,ngoai vi, v lin kt cc thnh phn ny din ra XPS. SDK l mt mi trng pht trin phn mm cho cc ng dng n gin v phc tp. Xc nh chnh xc chc nng phn cng ca bn c th c thc hin bng cch chy thit k thng qua HDL simulator.XPS c 3 kiu m phng Behavioral Structural Timing-accurate

4.2. To mt Project:
The Base System Builder (BSB): l 1 thut s thc hin nhanh chng v hiu qu mt cng vic thit k,m sau bn c th ty chnh

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Xilinx ngh s dng BSB Wizard to ra phn c bn cho mt d n thit k h thng nhng mi.BSB c th l tt c nhng g bn cn to thit k. S dng BSB Wizard ,ban c th tao file project,chn board,cu hnh 1 vi x l hay giao tip I/O,thm vo ngoi vi bn trong,ci t software,v pht ra 1 report tm tt h thng. To ra file(*.xmp) A Xilinx Microprocessor Project (XMP) file l mt file mc nh ca h thng nhng.Tt c cc thng tin d n XPS c save trong XMP file,bao gm vi tr ca Microprocessor Hardware Specification (MHS) and Microprocessor Software Specification (MSS) files. The XMP file cng cha ng thng tin v ngun C v file header m XPS bin dch,cng nh cc file thc thi m SDK bin dch. Selecting a Board Type: BSB cho php bn chn 1 kiu board t danh sch hay tao ra mt board ring. Selecting and Configuring a Processor Bn c th chn MicroBlaze hay PowerPC processor v chn: Architecture type Device type Package Speed grade Reference clock frequency Processor-bus clock frequency Reset polarity Processor configuration for debug Cache setup Floating Point Unit (FPU) setting Selecting and Configuring Multiple I/O Interfaces BSB hiu b nh ngoi v thit b I/O c sn trn board v cho php la chn
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Which devices to use Baud rate Peripheral type Number of data bits Parity Whether or not to use interrupts Adding Internal Peripherals BSB cho php bn thm vo ngoi vi.Cc ngoi vi c h tr bi board c la chn v kin trc thit b FPGA. Setting Up Software Ng vo v ng ra chun ca thit b c th c thc hin trong BSB,v bn c th chon mt ng dng mu ngn ng C m bn mun XPS pht ra.Mi ng dng bao gm mt tp lnh lin kt.ng dng mu m bn chn bao gm kim tra b nh,kim tra ngoi vi,hay c 2. Take a Test Drive chy BSB Wizard ,bn cn phi bt u vi ISE Project Navigator,v to ra mt project vi h thng vi x l nhng ti mc nh. Start ISE Project Navigator Select File >New Project.N s truy cp ti New Project Wizard S dng thng tin bn di y la chn trong Wizard screens.

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Ch : Sau khi chy ISE Project Navigator new project wizard,n s nhn ra bn c mt h thng nhng ,v s bt u Platform Studio vi thng ip This project appears to be a blank project. Do you want to create a Base System using the BSB Wizard? (This can take a few moments.) Click Yes. By gi BSB wizard bt u,bn c th tao ra mt project s dng cu hnh c miu t bng di

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Trong phn k tip ,chng ta s bit cch quan st v iu chnh new project trong XSP
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4.3. Xilinx Platform Studio


By gi ban tao c mt project c bn vi BSB,y l lc nhn vo cc s chon c sn trong Xilinx Platform Studio(XPS).S dng XPS ,bn c th xy dng trn project bn to vi BSB.Phn ny s gip bn c ci nhn tng quan v XPS,v tho lun v cch s dng XPS iu chnh tht k ca bn. What is XPS? XPS bao gm mt giao tip ha ngi dng (GUI),cng vi mt b cc cng c hng ti d n thit k.Phn ny s miu t XPS GUI v mt vi cng c c s dng ph bin. The XPS GUI T XPS GUI ,bn c th thit k mt h thng nhng hon chnh cho vic ci t mt thit b Xilinx FPGA.Ca s chnh ca XPS c cho trn hnh 3.1 Ch rng ca s chnh ca XPS c chia thnh 3 phn: Project Information Area System Assembly Console Window

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Project Information Area The Project Information Area offers control over and information about your project. TheProject Information Area includes Project, Applications, and IP Project Tab The Project Tab,cho hnh 3-2,l cc tham kho ti cc file c lin quan n project.Thng tin c nhm trong cc mc tng qut sau : Project Files Tt c cc file thc hin project nh Microprocessor Hardware Specification (MHS) files,Microprocessor Software Specification (MSS) files,User Constrains File (UCF) files,iMPACT Command files,Implementation Option files,v Bitgen Option files. Project options Tt c cc s la chon c trng d n nh Device,Netlist,Implementation,HDL,v Sim Model options. Reference Files
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Tt c cc gi tr nhp v files output c sn xut bi XPS implementation processes.

Application Tab The Application tabs cho trn hnh 3-3,l tt c cc cu hnh la chn ng dng phn mm,header files,v source files m lin h vi mi ng dng ca d n.Vi vic chn th ny bn c th: Tao ra v thm vo mt phn mm ng dng,v ti n ti khi RAM. Thit lp s la chn bin dch Thm vo cc file header v source ti project Ch : Trong lc XPS cho php bn to ra v qun l phn mm d n,SDK yu cu cng c cho tt c software development.

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IP Catalog Tab The IP Catalog tab cho trn hnh 3-4,bao gm tt c cc EDK IP cores v custom IP cores do bn to ra. Nu mt project c m,ch c nhng IP cores m ph hp vi muc tiu ca kin trc thit b Xilinx l c th hin.Nhng thng tin ca danh mc v IP cores,bao gm phin bn pht hnh,status,lock,processor support,v bn miu t ngn. Nhng thng tin chi v IP core,bao gm lch s thay i cc phin bn,data sheet,v Microprocessor Peripheral Description (MPD) file,th sn c khi click phi menu.Ban u th IP cores c nhm li c th t phn cp theo chc nng.

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Take a Test Drive: Trong XPS GUI ,click chon th Project tab. Click the Application tab a. Collapse the Project: TestApp_Memory (using the +/- box) entry. b. Expand the four sub-headers below Project: TestApp_Peripheral Under Processor: ppc440_0, note the xparameters.h file. The xparameters.h file cha ng bn a ch h thng v l mt phn tch hp ca Board Support Package(BSP).Nu bn thc hin theo cc bc phn Test Drive,the BSP cha c tao ra,v vy file ny cha c sn. Under Compiler Options and Sources,ch rng c hai phn gm tp lnh lin kt v kim tra ng dng thi hnh c t ng pht bi BSB Wizard khi the selected test applications c to ra. Click the IP Catalog tab
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a. Tm Communication Low-Speed IP category v m rng n. b. nh v XPS_UART (16550-Style) peripheral v click phi xem PDF data sheet ca XPS_UART (16550-Style). c. Click vo icon trn trong hnh 3-5 m 2 mn hnh System Assembly View The System Assembly View cho php bn quan st v cu hnh cc khi thnh phn ca h thng. Nu the System Assembly View cha c maximized trong ca s chnh,click vo System Assembly View tab at the bottom of the pane to open it. Bus Interface, Ports, and Address Filters XPS cung cp Bus interface,Ports,v cc th a ch trong the System Assembly View(hnh 3-5), t chc thng tin v thit k ca bn v cho php bn d dng hn bin tp hardware platform ca mnh.

Connectivity Panel Vi vic chn th Bus Interfaces,bn s thy Connectivity Panel,( labeled in thefigure above). The Connectivity Panel l mt s th hin ha ca hardware platform interconnects.
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Take a Test Drive Trong System Assembly View ,click vo th Ports (located at the top of the screen). FPGA device. Expand the External Ports category to view the signals that are present outside the Ch tn tn hiu trong Net column v tm tn hiu lin quan ti RS232_Uart_1.Nhng iu ny s c tham kho trong phn k tip.ng muc ny li khi hon thnh. Ko xung nh v RS232_Uart peripheral v m rng n Right-click the RS232_Uart_1 peripheral icon and select Configure IP to launch the RS232_Uart_1:xps_uart16550_v2_00_a parameters dialog Click the directories icon (circled in Figure 3-5), and switch between the hierarchical and flat views. Platform Studio Tab Trong cng mt khng gian ca System Assembly View,c mt th Platform Studio.The Platform Studio tab display(hnh 3-6) cung cp mt lu thit k nhng. Nu ti bt k im no bn khng chc lm bc no tip theo,hay cn thm thng tin thc hin tin trnh,bn c th nhanh chng tham kho biu ny.

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CHNG 5:CC NG DNG CHO KIT SPARTAN 3E

5.1. B lc FIR 2D:


5.1.1. Gii thiu:

B lc FIR 2D c dng nhiu trong vic x l nh v x l video. ng dng c ng b nh cc port: CE, CLK, SCLR.

5.1.2. Qu trnh m phng bng chng trnh Xilinx ISE 9.1

Khi ng chng trnh Xilinx ISE 9.1

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To project

Add sourse cho project. Check syntax. Check synthesize- XST. t chn cho ng dng: Assign Package Pins. Kt ni chip: Implement Design.

To file np cho chng trnh (.bit): chn Generate Programming File.

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Kt qu trc khi np cho KIT:

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Ti liu tham kho: 1. Spartan 3E Starter Kit User guide www.xilinx.com 2. Two Dimensional Linear Filtering Application www.xilinx.com 3. http://www.xilinx.com/bvdocs/appnotes/xapp933.zip

5.2. Chng trnh iu khin LED n


5.2.1. Lnh thc hin

******************************************************* LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity inicio is
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port ( a,b : in std_logic; s : out std_logic ); end inicio architecture compuerta of inicio is begin s<= a and b end compuerta ******************************************************* 5.2.2. To file np cho KIT: Khi ng chng trnh Xilinx ISE 9.1 To project

Add sourse cho project. Check syntax. Check synthesize- XST. t chn cho ng dng: Assign Package Pins.

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Kt ni chip: Implement Design. To file np cho chng trnh (.bit):

5.2.3. Qu trnh np:

Chn Generate Target PROM/ACE File

- Right click chn Add Xilinx Device - Chn Program

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5.2.4. Kt qu

Program successed Kim tra trn LED thy ng nh gii thut Logic.

5.3. Chng trnh x l nh dng b lc FIR


5.3.1. Kt qu m phng dng Matlab 7.4

on lnh thc hin: ***************************************************** function [input_image,golden_output, input_image_a, load]=generate_golden_new() input_image=imread('gold.pgm','pgm'); figure; imshow(input_image); b = zeros(5); b(3,1)=51;
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ti :Tm hiu KIT STARTER SPARTAN 3E

THD: PGS.TS L Tin Thng

b(3,5)=51; b(3,2)=51; b(3,4)=51; b(3,3)=52; b=b/256; b=b'*b golden_output = uint8(filter2(b,input_image)); figure; imshow(golden_output); imwrite(golden_output,'golden_output.pgm','pgm'); input_image_t = 0; input_load_t = 0; pad = zeros(1,32); load_image_init = ones(590,720); for i=1:576; pad_image(i,:) = [input_image(i,:) pad]; end for i=1:590; load_image(i,:) = [load_image_init(i,:) pad]; end figure; imshow(pad_image); imwrite(pad_image,'pad_image.pgm','pgm'); figure; imshow(load_image); load_image(1,1:720+32); for i=1:576; input_image_temp = pad_image(i,:); input_image_t=[input_image_t input_image_temp]; end for i=1:590; input_load_temp = load_image(i,:); input_load_t =[input_load_t input_load_temp]; end input_image_a = input_image_t(2:576*(720+32)+1); input_image_a = [input_image_a input_image_a]; load = input_load_t(2:590*(720+32)+1); load = [load load]; end 5.3.2. Kt qu: Input:
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ti :Tm hiu KIT STARTER SPARTAN 3E

THD: PGS.TS L Tin Thng

Output:

5.3.3. Qu trnh np cho KIT:

Chn Generate Target PROM/ACE File Right click chn Add Xilinx Device
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Vit

ti :Tm hiu KIT STARTER SPARTAN 3E

THD: PGS.TS L Tin Thng

- Chn Program
5.3.4. Kt qu:

- M phng bng Matlab chy c. Cha iu khin c khi np cho KIT.

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SVTH: Trn Quc Vit- Nguyn Anh