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Hng dn s dng Xilinx ISE _ Version 1.

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THAO TC C BN LP TRNH CHO FPGA TRN XILINX ISE 8.2i


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To project mi. Chy chng trnh ISE, ta s thy giao din nh sau.

Hng dn s dng Xilinx ISE _ Version 1.0 Chn Menu File New Project.

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Trong giao din s hin ra ca s sau.

Hng dn s dng Xilinx ISE _ Version 1.0

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Nhp tn cho Project mi. Tn ny s t ng c ly lm tn ca Folder lu cc File lin quan n Project.

Hng dn s dng Xilinx ISE _ Version 1.0

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Thit lp cc thng s cho Card FPGA m ta s dng.

+ Dng sn phm (Family).

Hng dn s dng Xilinx ISE _ Version 1.0

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+ Thit b (Device).

Hng dn s dng Xilinx ISE _ Version 1.0

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+ Dng thit k, ng gi (Package). + Tc (Speed).

Hng dn s dng Xilinx ISE _ Version 1.0

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Chn Next. Ta s thy hin ra ca s Create New Source. Ta c th to 1 File Source mi t y, hoc c th to sau khi Project mi c to thnh.

+ Chn kiu Source File. Nhp tn ca Source File. Chn Next sang bc k tip.

Hng dn s dng Xilinx ISE _ Version 1.0

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+ Khai bo module ca chng trnh. Bc ny cng c th c

thc hin sau khi to Project. Chn Next.

Hng dn s dng Xilinx ISE _ Version 1.0 V Duy Nht + Giao din s hin ra ca s tm tt cc thuc tnh m ta thi t

lp cho Source File mi. Chn Finish tin hnh to Source File.

+ Chng trnh s yu cu xc nhn li vic to Source File. Ch n Next.

Hng dn s dng Xilinx ISE _ Version 1.0

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Giao din cho php Add Source File. Nu mun Add Source File, ta

chn Add Source Chn Source File cn Add Chn Add.

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Hng dn s dng Xilinx ISE _ Version 1.0

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Giao din hin ra ca s tm tt cc thuc tnh m ta thit lp cho

Project mi.

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Hng dn s dng Xilinx ISE _ Version 1.0

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Chn Finish tin hnh to Project. Sau khi hon thnh, Giao di n s

nh sau.

Double Click thy c Source File c dng .vhd ca Project.

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Hng dn s dng Xilinx ISE _ Version 1.0

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Hng dn s dng Xilinx ISE _ Version 1.0 II)

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Bin dch v thc thi project ln Kit FPGA.


Son tho chng trnh cn thc thi. Sau Click m m c

Synthesis-XST.

Double click vo Synthesis tin hnh phn tch chng trnh, ki m tra li.

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Hng dn s dng Xilinx ISE _ Version 1.0

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+ Chng trnh dang chy.

+ C li xy ra trong qu trnh kim tra, biu tng trc Synthesis s hin .


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Hng dn s dng Xilinx ISE _ Version 1.0

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+ Ta ko xung thanh Transcript Error Double Click vo thng

bo li kim tra.

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Hng dn s dng Xilinx ISE _ Version 1.0 V Duy Nht + Sau khi sa li, vic phn tch v kim tra t kt qua tt. Biu

tng hin ra mu xanh.

Click phi chut vo Implement Desingn chn Run (hoc Double Click).

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Hng dn s dng Xilinx ISE _ Version 1.0

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Tip tc vi Generate Programming File.

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Hng dn s dng Xilinx ISE _ Version 1.0

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np chng trnh ln Card FPGA, chn Configure Device.

Ca s thit lp cc ty chn cho vic kt ni thit v hin ra. Th ng ta s dng ch Default. Chn Finish.

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Hng dn s dng Xilinx ISE _ Version 1.0

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Chng trnh ang kim tra v tin hnh vic lin kt thit b, chu n b cho vic Load d liu ln Card FPGA.

Nu c li xy ta ra trong qu trnh kt ni thit b, ta ph i th c hin

kt ni li bng cch Click chut phi ln dng ch mu xanh lam Right click to Add Device or Initialize Jtag chain, chn Initialize chain.

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Hng dn s dng Xilinx ISE _ Version 1.0

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Hng dn s dng Xilinx ISE _ Version 1.0

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Hng dn s dng Xilinx ISE _ Version 1.0

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Tip theo ta phi chn Programming File cho FPGA bng cch link n File ny (nm trong Folder cha Project). Cc yu cu cn li ta ch n Bypass.
Kch vo con FPGA trn s kt ni chn Program Apply.

Chng trnh s thc hin load Data ln FPGA. Khi hon thnh, chng trnh s thng bo Program Success, hoc bo Program Failed nu nh khng hon thnh.

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