07 MOSbias

TECHNICAL REPORT
Principles and Examples of MOSFET

Technology Biasing

Dr. John Choma
Professor of Electrical & Systems Architecture Engineering
Fellow, Scintera Networks, Inc.
University of Southern California
Ming Hsieh Department of Electrical Engineering
University Park: Mail Code: 0271
Powell Hall of Engineering Room #620
Los Angeles, California 900890271
2137404692 [USC Office]
2137408677 [USC Fax]
johnc@usc.edu

ABSTRACT:
This report overviews the basic theories and design strategies that underpin the
practical realization of biasing networks suitable for high performance analog
integrated circuits realized in MOSFET technology. It uses a review of the static
models pertinent to MOS transistors to establish a technical foundation to support the
development of a family of biasing structures ranging from simple voltage reference and
current mirrors to networks featuring bias performance rendered nominally
independent of utilized supply voltages. Included among the topical issues addressed in
this document are bandgap references, regulated current mirrors, and biasing networks
delivering circuit transconductances that are independent of static currents and
voltages. Additionally, common mode feedback stabilization of circuit operating points
is discussed, as are adaptive networks that implement low power biasing by
automatically allowing for suitably large static device currents only when the
amplitudes of signals applied to a circuit are large.
April 2007
Bias Circuits University of Southern California J . Choma

EE 348 - 2 - April 2007
1.0. INTRODUCTION
Biasing is a fundamental and often challenging design task that is pervasive of all analog
circuit design initiatives. Fundamentally, biasing subcircuitry establishes the necessary condi-
tions that allow an active network comprised of interconnected, inherently nonlinear, active de-
vices to deliver nominally linear input/output (I/O) performance for stipulated input signal condi-
tions and output load terminations. Biasing networks are also designed to deliver the quiescent
currents and voltages that are deemed optimal for gain, bandwidth, degree of linearity, I/O
impedance levels, time domain settling times, standby power dissipation, and other targeted
performance metrics. In a reliable and reproducible analog signal processor, the desired
characteristics of the biasing networks must be sustained despite unavoidable excursions of
operating temperatures intrinsic to the integrated circuit chip and the non-ideal nature of the util-
ized power supply voltages. Moreover, the quiescent currents and voltages forged by the biasing
networks must be impervious to the uncertainties that are implicit to the mathematical models of
utilized active devices, the tolerances associated with passive circuit components, the degree of
matching among similar active devices afforded by foundry processes, and the parasitics associ-
ated with circuit layout and packaging.
This technical report overviews biasing cells that are commonly exploited in the design
of high performance analog integrated circuits. The overview commences with an analysis of a
simple voltage reference scheme that is commonly adopted in conjunction with the realization of
high impedance current sinks and sources, and it examines the viability of this scheme to func-
tion as a reliable and predictable current reference for arbitrary load terminations. The simple
voltage reference configuration is subsequently extended to embrace the design requirements of
minimal quiescent operating point sensitivity to temperature and variations in power line volt-
ages. Circuits that reliably bias transistors for constant and predictable forward transconductance
are addressed, as are topologies boasting improved current source and current sink properties.
The use of common mode feedback to stabilize quiescent output voltages in balanced differential
pairs is explored, as is an innovative adaptive biasing scheme that minimizes standby power
dissipation by allowing for increased levels of quiescent currents only when large input signal
amplitudes prevail.
As a foundational prelude to the bias circuit discussions disclosed in this document, the
static volt-ampere characteristics of MOSFETs are reviewed. Such a review is indispensable be-
cause mathematically tractable analyses serving to complement ultimately executed computer-
aided circuit optimization demand device modeling approximations. Some of these approxima-
tions are potentially deleterious in that they may produce undesired and unpredicted performance
perturbations from nominal design goals. The prudent circumvention or mitigation of these ef-
fects, which is tantamount to an assurance of reliable biasing networks delivering predictable
performance, mandates an insightful engineering understanding of the circuit performance
implications of pertinent models and their concomitant approximations.
2.0. STATIC MODEL OF A MOSFET
Figure (1) gives the circuit schematic symbol of both N-channel and P-channel transis-
tors. In Figure (1a), the positive reference polarity conventions for the drain current, I
d
, the gate-
source voltage, V
gs
, and the drain-source voltage, V
ds
are indicated For the P-channel device in
Figure (1b), it is more convenient to cast static volt-ampere characteristics in terms of the source-

EE 348 - 3 - April 2007
gate voltage, V
sg
, and the source-drain voltage, V
sd
. Note that positive drain current flows into
the N-channel device, while positive drain current flows out of the P-channel transistor.
+
V
gs
+
V
ds
I
d
(a).
+
V
sg
+
V
sd
I
d
(b).

Fig. (1). (a). Schematic symbol of an N-channel, or NMOS, transistor in
which the positive reference polarity convention for drain current
and both gate-source and drain-source voltages are delineted. (b).
Schematic symbol of a P-channel, or PMOS, transistor.
In Figure (1a), let V
h
designate the threshold voltage of the N-channel transistor. Assum-
ing that the device is biased for operation in its saturation regime where V
ds
V
gs
V
h
, the sim-
ple square law model relating the drain current to the applied gate-source voltage is
( )
2
no ox
d gs h
C W
I V V ,
2 L
| || |
=
| |
\ . \ .
(1)
where
no
is the mobility of electrons in the inverted channel at the oxide-semiconductor inter-
face. Specifically,
no
is the carrier mobility when lateral electric field intensities induced in the
channel by applied drain-source voltages are small. Continuing, (W/L) is the gate width to chan-
nel length gate aspect ratio, and C
ox
, the density of the capacitance associated with the gate oxide
layer, is
ox ox ox
C T . = (2)
In (2),
ox
is the dielectric constant of silicon dioxide [345 fF/cm], while T
ox
is the average thick-
ness of the insulating gate oxide. The companion volt-ampere relationship in the saturation do-
main for the P-channel transistor in Figure (1b) is
( )
2
po ox
d sg h
C
W
I V V ,
2 L
| |
| |
=
| |
\ .
\ .
(3)
which requires V
sd
V
sg
V
h
. In this relationship,
po
is the low field value of the mobility of
holes in the inverted channel, and the gate-source voltage, V
gs
, in (1) is replaced by the source-
gate voltage, V
sg
. The replacement of V
gs
by V
sg
allows threshold voltage V
h
in both (1) and (3)
to be cast as a positive voltage metric. Moreover, since the bulk-substrate terminal is returned to
the source terminal in both of the transistors highlighted in Figure (1), voltage V
h
, is unaffected
by voltage modulations at the bulk substrate terminal. The analytical disclosures in forthcoming
sections of material are expedited by rewriting (1) and (3) in the forms,
( )
( )
2
d n gs h ds
2
d p sg h sd
I V V I for NMOS
,
I V V I for NMOS
=
=
(4)
where the defining notation, I
ds
, highlights a drain current flow in the direction of drain to source
in N-channel, or NMOS, transistors, I
sd
is the source to drain current flow in P-channel, or
PMOS, devices, and

EE 348 - 4 - April 2007
no ox
n
po ox
p
C W
for NMOS
2 L
.
C
W
for PMOS
2 L
| |
=
|
\ .
| |
=
|
\ .
(5)
It should be noted that the introduced transconductance coefficient parameters,
n
and
p
, which
have dimensional units of mhos/volt, scale linearly with gate aspect ratio.
The simplified static volt-ampere relationships in (4) show that for given threshold volt-
age, gate aspect ratio, gate oxide capacitance density, and channel carrier mobility, the drain cur-
rent is determined exclusively by one voltage variable; namely, gate-source voltage V
gs
in
NMOS and source-gate voltage V
sg
in PMOS. The lack of drain current dependence on drain-
source or source-drain voltage means that the drain-source port of a MOSFET effectively be-
haves as an ideal current source. In other words, (4) suggests that the drain current can be mod-
eled as an ideal, nonlinear, voltage controlled current source, with either V
gs
or V
sg
serving as the
controlling voltage. Since the gate terminal is incident with an insulating oxide layer serving as
an interface between the gate contact metallization and the semiconductor surface, the gate con-
ducts zero static current. Accordingly, the drain-source terminal pair witnesses an ideal voltage
controlled current source, as inferred by the simple models offered in Figure (2). In short, the
simple static model of (4) stipulates that when MOSFETs operate in their saturation regions,
their drain currents are functionally dependent on only gate-source voltages. Conversely, a cur-
rent forced to flow in the MOSFET drain establishes, by virtue of (4), a unique gate-source
potential.
+
V
gs
+
V
ds
I
d
(a).
+
V
sg
+
V
sd
I
d
(b).
+
V
gs
+
V
ds
I
d
+
V
sg
+
V
sd
I
d
I
ds
I
sd
Drain
Gate
Source
Drain
Source
Gate
Gate
Gate
Source
Drain
Source
Drain

Fig. (2). (a). Simplified static model of an NMOS transistor biased for operation in
saturation. The current, I
ds
, is exclusively a function of the gate-source volt-
age, V
gs
. (b). Simplified static model of a PMOS transistor biased for
operation in saturation. The current, I
sd
, is exclusively a function of the
source-gate voltage, V
sg
. Currents I
ds
and I
sd
are defined by (4).

EE 348 - 5 - April 2007
2.1. TEMPERATURE SENSITIVITY
In contrast to bipolar technology devices, whose collector currents exhibit a positive
temperature coefficient, the static volt-ampere characteristics of MOSFETs display negative
temperature sensitivity; that is, for constant gate-source or source-gate voltages, the drain current
decreases for increasing device operating temperatures. Two principle phenomenological
sources contribute to this negative temperature coefficient. The first of these derive from the fact
that the charge carrier mobility in the inverted channel of a transistor decreases nominally as a
three-halves power law of absolute temperature. In particular,
3 2
o
o
T
(T) (T ) ,
T
| |
=
|
\ .
(6)
where (T) designates electron mobility
no
in NMOS and hole mobility
po
in PMOS at any
arbitrary absolute temperature, T, and T
o
is the reference temperature at which the reference
mobility value, (T
o
), is extracted. Since parameters
n
and
p
in (5), to which the drain currents
in (4) are proportional, are nominally linear functions of carrier mobility, the immediate effect of
increased operating temperature is clearly a diminished drain current.
In addition to a temperature-induced degradation of mobility, the threshold voltage in-
creases with temperature, thereby exacerbating the diminished drain current spawned by mobility
effects. The positive temperature coefficient of threshold voltage derives from its intimate
dependence on the Fermi potential, which effectively defines the oxide-semiconductor interface
potential corresponding to the onset of channel inversion in a MOSFET. To first order,
o
h h o F
o
T T
V (T) V (T ) 2V ,
T
| |
~ +
|
\ .
(7)
where V
h
(T) is the threshold voltage value at absolute temperature T, and the Fermi potential, V
F
,
is given by
sub
F T
i
N
V V .
N
ln
| |
=
|
\ .
(8)
In the last expression, N
sub
denotes the impurity concentration in the substrate (acceptor
concentration for NMOS and donor concentration for PMOS), N
i
is the intrinsic carrier
concentration of silicon, and V
T
is the familiar Boltzmann voltage. Unfortunately, V
F
itself
varies with temperature owing to the facts that V
T
is linearly dependent on absolute temperature
and N
i
nominally doubles for each 10 C increase in operating temperature. When due
consideration is given to mobility and threshold effects, the sensitivity of the drain current to
absolute temperature is found to be
[1]

d
0.25
I
d d F
T
o d
I I 3 4V T
S ,
T T 2 T I
(
| | c
(
~ +
|
c (
\ .

(9)
where =
n
for NMOS, =
p
for PMOS, and it is understood that V
F
, I
d
, and in the brack-
eted factor on the right hand side are each evaluated at the reference temperature, T
o
. The first
term in the bracketed quantity derives from the temperature dependence of carrier mobility,
while the second term within the bracket reflects threshold voltage sensitivity to temperature.
Accordingly, the per unit, or percentage change in drain current induced by a specified percent-
age change in operating temperature is negative and larger in magnitude than 1.50. Note, how-
ever, that for progressively larger drain currents, the temperature sensitivity of drain current
tends toward a constant of (1.50).

EE 348 - 6 - April 2007
EXAMPLE #1:
In an attempt to demonstrate the severity of the foregoing temperature issues,
consider an N-channel MOSFET having an acceptor impurity concentration in
the substrate of N
sub
= 10
15
atoms/cm
3
. At a reference temperature of T
o
= 27 C
= 300 K, the MOSFET, which is biased for a drain current of I
d
= 1 mA, deliv-
ers
n
= 50 mmhos/volt, and a threshold voltage of V
h
= 400 mV. Assume a refer-
ence temperature intrinsic carrier concentration of 10
10
atoms/cm
3
. Determine
the requisite gate-source voltage, V
gs
, such that 1 mA of drain current is sustained
at an operating temperature of 75 C.
SOLUTION #1:
(1). From (4), the gate-source voltage commensurate with 1 mA of drain current at 27 C is,
with
n
= 50 mmhos/volt and V
h
= 400 mV, V
gs
= 541.4 mV. Also, at T
o
= 27 C = 300
K, the Boltzmann voltage, V
T
, is
o
T
kT
V 25.88 mV ,
q
= = (E1-1)
where k = 1.38(10
23
) joules/K is Boltzmanns constant, and q = 1.6(10
19
) coulombs is
the magnitude of electron charge. With N
sub
= 10
15
atoms/cm
3
and N
i
= 10
10
atoms/cm
3
at
27 C, the Fermi potential in (8) is V
F
= 297.9 mV at the reference temperature.
(2). Using (7), the threshold voltage increases to V
h
= 495.3 mV at T = 75 C = 348 K, which
is an increase of almost 24%. Appealing to (6), the ratio of the carrier mobility at 348 K
to the carrier mobility at 300 K is
3 2 3 2
o
o
T (T) 300
1 1.249 .
(T ) T 348
| | | |
= = =
| |
\ . \ .
(E1-2)
Since parameter
n
is directly proportional to carrier mobility,
n
decreases by a factor of
1.249 to a 75 C value of
n
= 40.02 mmhos/volt.
(3). If a biasing circuit were to be implemented to deliver constant gate-source voltage to the
transistor of present interest,
n
= 40.02 mmhos/volt, V
h
= 495.3 mV, and V
gs
= 541.4 mV
(the gate-source voltage value computed at 27 C), the drain current in (4) becomes I
d
=
85.03 A, a whopping decrease from the original drain current value by a factor of almost
12! On the other hand, sustaining a 1 mA drain current in the face of the foregoing
temperature-induced perturbations in parameter
n
and threshold voltage V
h
requires an
updated gate-source voltage of V
gs
= 653.4 volts . In other words, the gate-source voltage
must increase by 20.7% over the 48 C increase in operating temperature.
COMMENTS: This example demonstrates that the temperature-induced effects on the drain
current conducted by a MOSFET biased in saturation can be dramatic. In the
present case, the factor of 12 decrease in quiescent drain current is certainly
large enough to engender significant concern as to the ability of the circuit in
which the considered MOSFET is embedded to sustain performance specifica-
tions over the stipulated 48 C rise in operating temperature. The design les-
son promulgated herewith is that if the desired signal performance of a circuit
is critically dependent on quiescent current level, constant gate-source voltage
is not a prudent bias design strategy. In the present case, the gate-source volt-
age setting the drain current bias on the subject transistor must increase by
20.7% over the 48 C rise in temperature. While this requirement may appear
foreboding, it is a realistic requirement of biasing compensation. To place this
contention into engineering perspective, the requisite increase in gate-source

EE 348 - 7 - April 2007
voltage, say V
gs
, is V
gs
= V
gs
(75 C) V
gs
(27 C) = 112.0 mV, which
amounts to a linearized temperature rate of voltage increase of 2.33 mV/C.
Thus, the incorporated biasing compensation must sense temperature (perhaps
by sensing current) and increase the applied gate-source bias by about 2.33 mV
for every one degree centigrade increase in temperature. As is to be demon-
strated in subsequent sections, this mandated average increase is a reasonable
design goal for well-designed biasing compensators. Indeed, the majority of
MOSFETs achieve nominally temperature invariant drain current when the ap-
plied gate-source voltage is forced to increase at a rate in the range of 1.5
mV/C to 2.5 mV/C. Interestingly enough, the 2.33 mV/C requirement does
not differ appreciably from the average temperature rate at which the base-
emitter biasing voltage applied to a bipolar junction transistor must decrease to
preserve constant quiescent collector current.
2.2. IMPROVED STATIC MODELS
The static volt-ampere characteristics delineated in (4) are, of course, only first order
approximations of the static characteristics actually observed in the laboratory. Unfortunately,
the differences between theoretic predictions and engineering observations are accentuated as de-
vices are downscaled to deep submicron dimensions. The primary shortfalls implicit to (4) are
the tacit neglect of (1) channel length modulation, (2) field-induced carrier mobility degradation,
and (3) the effects of potentially large vertical electric fields induced by gate-source biasing
[1]
.
The salient features of each of these effects are discussed in the subsections that follow and al-
though these discussions focus exclusively on NMOS devices, the results disclosed can embrace
PMOS transistors through mere notational modifications.
2.2.1. Channel Length Modulation
When an N-channel MOSFET operates in its triode regime, the drain-source voltage, V
ds
,
satisfies the inequality, V
ds
< (V
gs
V
h
) V
dsat
, where V
dsat
is termed the drain saturation voltage.
On the other hand, V
ds
(V
gs
V
h
) = V
dsat
in the saturation regime. In the triode domain for
which V
ds
< V
dsat
is a requirement, the channel comprising the charge inversion layer induced at
the oxide-semiconductor interface extends throughout the entire source to drain geometric chan-
nel length L. At the boundary between triode and saturation domains, V
ds
V
dsat
, and the chan-
nel inversion layer reduces continually from its maximal depth into the semiconductor bulk at the
source site to a depth of zero at the drain site. In effect, the channel depth is pinched to zero at
the drain-channel interface. Thus, V
ds
= V
dsat
is precisely the drain-source voltage commensurate
with the so-called pinch off condition, which effectively defines the transitional voltage
boundary between triode and saturation domains. As V
ds
increases above V
dsat
, pinch off
necessarily occurs within the source-drain channel space, which implies that the excess drain-
source voltage, (V
ds
V
dsat
), appears across a channel volume that is adjacent to the drain site
and is depleted of free charge carriers. Drain currents in saturation are therefore produced by the
superposition of two effects. The first of these effects is the diffusion transport of charge carriers
within the inversion layer extending from the source site to the drain-side boundary of the short-
ened inversion layer. Equation (4) accounts for this current component, but the subject relation-
ship exploits the presumption of an inversion layer extending throughout the source-drain length,
L. The second effect, which is not embraced by (4), is the accompanying drift transport across
the channel depletion zone of those carriers that reach the drain-side boundary of the inversion
layer.

EE 348 - 8 - April 2007
Because the excess drain voltage induces a strong lateral electric field across the deple-
tion zone of the source-drain spacing, most of the free carriers transported to the inversion layer
boundary are swept into the drain by the force associated with this field. It is therefore logical to
presuppose an actual drain current that is larger than that predicted by (4), which accounts only
for charge diffusion phenomena. A stereotypical embellishment to (4) that accounts, albeit to
first order, for the effects of the lateral electric field within the channel depletion volume is
( )
2
ds dsat ds dsat
d n gs h ds
ds
V V V V
I V V 1 I ,
V V I
| |
= + = +
|
\ .
(10)
where current I
ds
is defined by (4) and voltage V
which is termed a channel length modulation

voltage, is an additional model parameter. Although analytical expressions for V
abound in the
literature, V
is best discerned through laboratory measurement or the careful interpretation of

computer-based simulations that exploit accurate transistor models. In addition to being weakly
dependent on drain current and drain-source voltage, V
is nominally proportional to the geomet-

ric channel length, L. Accordingly, long channel devices exude negligible channel length
modulation phenomena. Unfortunately, long channel devices, which generally operate with
proportionately larger gate widths, incur bandwidth and transient response time penalties because
of the increased device capacitances they forge. But longer channel devices are suitable in
subcircuits that are not embedded in the I/O signal path and are contrived exclusively for biasing
purposes.
Clearly, the modified drain current expression reflects the current superposition concept
argued earlier. In particular, I
ds
represents the drain current component arising from the transport
of charge carriers from the source to the drain-side boundary of the channel inversion layer. The
second term on the far right hand side of (10) accounts for the aforementioned field effects in the
channel depletion zone. Note that for V
ds
= V
dsat
, I
d
reduces to I
ds
, which suggests that I
ds
is the
drain saturation current corresponding to a drain-source voltage that equals the drain saturation
voltage.
A final notable point is that (10) gives rise to the model in Figure (3), for which the
depletion component of current is seen to give rise to a resistive path in shunt with the voltage
controlled current that establishes the saturated current component, I
ds
. It follows that depletion
fields in the channel region render the voltage controlled current source at the drain-source port
of a MOSFET non-ideal.
+
V
gs
+
V
ds
I
d
+
V
gs
V
ds
I
d
I
ds
Drain
Gate
Source
Drain
Source
Gate
V
dsat
I
ds
+

Fig. (3). Incorporation of channel length modulation phenomena into the large signal static model
of an NMOS transistor. In saturated mode, V
ds
V
dsat
.

EE 348 - 9 - April 2007
2.2.2. Carrier Mobility Degradation
The NMOS and PMOS volt-ampere characteristic equations in (4) and (10) are predi-
cated on the presumption that the mobility of channel carriers within the inversion layer is a con-
stant, independent of the electric field strength in the channel. Equivalently, (4) and (10)
presume a carrier velocity that is linearly proportional to field strength, with a constant of
proportionality that can be viewed as the low field value of carrier mobility,
no
. Unfortunately,
the carrier mobility degrades with progressively increased field strengths. The immediate
ramification of mobility degradation is that the carrier velocity remains proportional to field
strength for only low field values. When channel region fields are excessive, which is a plausi-
ble situation for even modest drain-source voltages applied to transistors fabricated in deep
submicron process technologies, the velocity saturates to a value, say v
max
. In silicon, v
max
is of
the order of 0.15 m/pSEC.
From a modeling perspective, carrier mobility degradation manifests itself as a decrease
in both drain saturation voltage and drain current in the saturation regime. The pertinent equa-
tions are
[1]

( )
( ) 2 ds sat gs h
2
d n gs h sat
V M V V
I M V V 1 ,
V
(

( = +
(

(11)
and
( )
dsat sat gs h
V M V V , = (12)
where with
gs h
le
V V
,
V
(13)
the voltage scaling parameter, M
sat
, is
sat
1 2 1
M .
+
= (14)
In (13), the voltage parameter, V
le
, which for deep submicron devices typically assumes values in
the range, 0.5 volt V
le
2 volts, is
max
le
no
v
V L .
| |
=
|
\ .
(15)
Observe that for devices having relatively large channel lengths, V
le
is proportionately
large, thereby rendering parameter in (13) correspondingly small. In turn, M
sat
in (14) ap-
proaches unity, which means that the modified drain current of (11) collapses to the volt-ampere
expression in (10). On the other hand, a dramatic change to the drain current materializes for the
case of very small channel lengths. For small L, which translates to small V
le
and large ,
small L
sat
2
M .
~ (16)
If this result and (5) are substituted into (11),
( )
( )
small L
ds sat gs h
ox max gs h d
V M V V
I WC v V V 1 .
V
(

( ~ +
(

(17)

EE 348 - 10 - April 2007
Note that the very short channel diffusion current component of the net drain current is
independent of geometric channel length and is now a linear, as opposed to a square law, func-
tion of the excess gate voltage, (V
gs
V
h
). The postulated channel length independence of short
channel drain current can be rationalized by conjecturing that for very small channel lengths, the
applied drain-source voltage incurs virtually complete depletion of the channel volume. Accord-
ingly, the effective length of the inverted channel becomes minutely small, thereby minimizing
the diffusion length of mobile charge transport and thus, the diffusion component of the net drain
current. It should also be noted in (17) that if the drain-source voltage applied to the short chan-
nel MOSFET closely approximates V
dsat
, or M
sat
(V
gs
V
h
), the resultant drain current is a linear
function of the excess gate voltage. This linear function projects a constant forward
transconductance of (WC
ox
v
max
).
Figure (4) graphically displays the changes incurred in saturation regime drain current
and drain saturation voltage because of the field-induced degradation of charge carrier mobility
in the inverted channel of a MOSFET. In particular, the voltage correction factor, M
sat
, and the
current correction factor, M
sat
2
, are plotted as functions of the normalized excess gate voltage, ,
defined by (13). Observe that for very short channel lengths, which are indicative of large values
of parameter , the actual drain saturation voltage can be of the order of 50% of the drain
saturation voltage evidenced in long channel devices. Correspondingly, the drain current level
can be reduced to only 25% or so of its long channel counterpart. Typically, short channel
devices operate with parameter slightly larger than one, which render M
sat
of the order of the
inverse of root two.
0
0.2
0.4
0.6
0.8
1
0 1 2 3 4 5
Normal i zed Excess Gate Vol tage, o
C
o
r
r
e
c
t
i
o
n

F
a
c
t
o
r
Current
Correcti on, M
sat
2
Vol tage
Correcti on, M
sat

Fig. (4). Static, saturation regime voltage and current correction factors precipitated by the
mobility degradation of charge carriers in the inverted channel of a MOSFET.

EE 348 - 11 - April 2007
2.2.3. Large Vertical Electric Fields
Apart from the carrier mobility degradation incurred by strong lateral fields in the in-
verted channel of a MOSFET, carrier mobility is impacted by the vertical electric field resulting
from the applied effective interface potential, (V
gs
V
h
). In NMOS, increases in V
gs
strengthens
this vertical field so that free electrons transported from the source to the drain are encouraged to
drift ever closer to the oxide-semiconductor interface. Unfortunately, the interface is far from a
perfectly smooth boundary, if for no other reason than routine device processing invariably in-
curs ionic contamination therein. The imperfect boundary causes carrier scattering, which in
turn results in diminished carrier mobility.
To first order, the mobility attenuation resulting from increased gate overdrive can be ad-
dressed analytically by replacing the low field mobility,
no
, to which
n
in (5) is directly propor-
tional, by an effective carrier mobility,
eff
, such that
no
eff
gs h
ve
.
V V
1
V
=

+
(18)
In this expression, V
ve
is the vertical electric field modulation voltage, which is nominally di-
rectly proportional to the thickness, T
ox
, of the oxide layer. To a very rough approximation,
ve ox
V T 15 , = (19)
where T
ox
in units of angstroms returns V
ve
in units of volts. Because of (18), (11) for the satura-
tion domain current becomes
( ) ( )
2
gs h ds sat gs h
2
d n sat
gs h
ve
V V V M V V
I M 1 .
V V V
1
V
(

( = +
| |
(

+
|
\ .
(20)
Obviously, (20) is inordinately more cumbersome than is the simple, square law, volt-
ampere characteristic advanced by (4) for device operation in the saturation domain. As a result,
the design-oriented determination of a suitable gate-source voltage for a desired drain current
and corresponding drain-source voltage can be a daunting challenge. But in addition to the
computational problems precipitated merely by algebraic complexity, engineering difficulties are
additionally encountered with respect to the accurate numerical delineation of the model metrics,
n
, V
h
, V
ve
, V
, and V
le
. These latter difficulties derive from the unfortunate fact that the physical
device and charge transport properties (saturation velocity, carrier mobility, regional concentra-
tions, etc.) on which these and other model parameters depend are generally unavailable to the
circuit designer. At best, the circuit designer can reasonably expect to have presumably reliable,
detailed device model parameters suitable for computer-aided simulation of transistor perform-
ance. For example, process foundries routinely supply their customers with device models in the
form of Level 49 HSPICE or other computer-based files. Unfortunately, many, if not most, of
the hundreds of numerical entries indigenous to these files are themselves non-physical entities
that defy the formulation of satisfying mathematical relationships to physical model metrics.
These and related other design-oriented problems can prove maddening. The aforementioned is-
sues are best mitigated by coalescing manual design strategies and calculations with suitable
computer-based simulations of device properties and volt-ampere characteristics.

EE 348 - 12 - April 2007
EXAMPLE #2:
An N-channel transistor featuring a minimum channel length of 180 nM has the
Level 49 HSPICE parameters given in Table (1). The transistor is to be biased in
saturation at V
ds
= 1 volt and I
d
1 mA to achieve a small signal transconduc-
tance, g
m
, of at least 3 mmhos. Assuming that the bulk terminal is incident with
the transistor source terminal, choose a reasonable gate aspect ratio, W/L, deter-
mine the required gate-source voltage bias, V
gs
, and estimate the model parame-
ters implicit to (20).
.MODEL 180nM NMOS (LEVEL =49
+VERSION =3.1 TNOM =27 TOX =4E-9 XJ =1E-7
+NCH =2.3549E17 VTH0 =0.3627858 K1 =0.5873035 K2 =4.793052E-3
+K3 =1E-3 K3B =2.2736112 W0 =1E-7 NLX =1.675684E-7
+DVT0W =0 DVT1W =0 DVT2W =0 DVT0 =1.7838401
+DVT1 =0.5354277 DVT2 =-1.243646E-3 U0 =263.3294995 UA =-1.359749E-9
+UB =2.250116E-18 UC =5.204485E-11 VSAT =1.083427E5 A0 =2
+AGS =0.4289385 B0 =-6.378671E-9 B1 =-1E-7 KETA =-0.0127717
+A1 =5.347644E-4 A2 =0.8370202 RDSW =150 PRWG =0.5
+PRWB =-0.2 WR =1 WINT =1.798714E-9 LINT =7.631769E-9
+XL =-2E-8 XW =-1E-8 DWG =-3.268901E-9 DWB =7.685893E-9
+VOFF =-0.0882278 NFACTOR =2.5 CIT =0 CDSC =2.4E-4
+CDSCD =0 CDSCB =0 ETA0 =2.455162E-3 ETAB =1
+DSUB =0.0173531 PCLM =0.7303352 PDIBLC1 =0.2246297 PDIBLC2 =2.220529E-3
+PDIBLCB =-0.1 DROUT =0.7685422 PSCBE1=8.697563E9 PSCBE2 =5E-10
+PVAG =0 DELTA =0.01 RSH =6.7 MOBMOD =1
+PRT =0 UTE =-1.5 KT1 =-0.11 KT1L =0
+KT2 =0.022 UA1 =4.31E-9 UB1 =-7.61E-18 UC1 =-5.6E-11
+AT =3.3E4 WL =0 WLN =1 WW =0
+WWN =1 WWL =0 LL =0 LLN =1
+LW =0 LWN =1 LWL =0 CAPMOD =2
+XPART =0.5 CGDO =716E-12 CGSO =716E-12 CGBO =1E-12
+CJ =9.725711E-4 PB =0.7300537 MJ =0.365507 CJ SW =2.604808E-10
+PBSW =0.4 MJ SW =0.1 CJ SWG =3.3E-10 PBSWG =0.4
+MJ SWG =0.1 CF =0 PVTH0 =4.289276E-4 PRDSW =-4.2003751
+PK2 =-4.920718E-4 WKETA =6.938214E-4 LKETA =-0.0118628 PU0 =24.2772783
+PUA =9.138642E-11 PUB =0 PVSAT =1.680804E3 PETA0 =2.44792E-6
+PKETA =4.537962E-5)
Table (1). Representative Level 49 HSPICE parameters for an NMOS transistor in a fabrication
process featuring a minimum channel length of 180 nM.
SOLUTION #2:
(1). The applicable circuit for computer-aided investigation is offered in Figure (5), where the
transistor model parameters are those that appear in Table (1.1), and the gate aspect ratio,
W/L, is to be determined. The null voltage source in the drain circuit of the device facili-
tates the extraction of the quiescent drain current, I
d
. For biasing purposes, the area and
perimeter parameters related to device capacitance calculations are of no consequence and
can therefore be defaulted to any convenient value. Initially, set V
gs
= 1 volt and W/L =1
and, of course, V
ds
= 1 volt. The HSPICE static simulation reveals I
d
= 46.4 A, V
dsat
=
262.8 mV, V
h
= 519.7 mV, and g
m
= 136.5 mho. Since V
gs
= 1 volt is larger than V
h
=
519.7 mV and V
ds
= 1 volt > V
dsat
= 262.8 mV, the transistor is clearly turned on and oper-
ates in its saturation domain.
(2). With W/L = 1, the simulated drain current is a factor of 21.55-times smaller than the target
current of 1 mA. This observation seemingly suggests the need for increasing the gate as-

EE 348 - 13 - April 2007
pect ratio from 1 -to- 21.55, since the drain current is ostensibly proportional to W/L. In
truth, the actual drain current is not directly proportional to W/L because of numerous sec-
ond order effects, including dependencies of threshold voltage, drain saturation voltage,
and parameter M
sat
on gate width W. Experience shows that a more viable gate aspect ra-
tio adjustment is about twice that computed or in this case, about 40. With W/L = 40 and
V
gs
= V
ds
= 1 volt, HSPICE delivers I
d
= 1.08 mA, V
dsat
= 278.2 mV, V
h
= 510.2 mV, and
g
m
= 3.17 mmho. The simulated transconductance value satisfies its design target. Al-
though V
gs
can be decreased modestly to reduce the drain current to 1 mA, this exercise is
unnecessary in view of the effects of routinely encountered device processing vagaries
and model parameter uncertainties. Thus, the design requirement is satisfied for W/L =
40 and V
gs
= V
ds
= 1 volt .
+
V
gs
V
ds
I
d
0
W
/
L

=

?

Fig. (5). Circuit structure for MOSFET biasing simula-
tion. The Level 49 HSPICE parameters of the
transistor are delineated in Table (1).
(3). The model parameterization exercise begins by using (19) to compute the voltage, V
ve
.
From Table (1), the oxide thickness is T
ox
= 4(10
9
) meters, which is 40 . Accordingly,
V
ve
= 40/15 = 2.667 volts.
(4). The next step in the parameterization process entails operating the transistor undergoing
study at a drain-source voltage value that equals its saturated value of 278.2 mV. This
tack reduces the bracketed factor on the right hand side of (20) to unity, thereby simplify-
ing the computation of the effective transconductance coefficient,
n
and the voltage
parameter, V
le
, which is implicit to the correction function, M
sat
. With W/L = 40, V
gs
= 1
volt, and V
ds
= V
dsat
= 278.2 mV, HSPICE delivers I
d
= 878.33 A and V
h
= 510.0 mV.
Recalling that V
dsat
= 278.2 mV and (V
gs
V
h
) = (1 0.510) volts = 0.490 volts, (12)
delivers M
sat
= 0.5678. Using (14), parameter follows as = 2.681. Then with (V
gs

V
h
) = 490 mV, (13) yields V
le
= 182.8 mV.
(6). With V
gs
= 1 volt, V
h
= 510.0 mV, and V
ds
= V
dsat
= 278.2 mV, HSPICE gives M
sat
=
0.5678 and predicts I
d
= 878.33 A. Recalling that the voltage parameter, V
ve
, is V
ve
=
2.667 volts, parameter
n
in (20) is found to be
n
= 13.43 mmho/volt. Since this calcula-
tion pertains to a gate aspect ratio of (W/L) = 40, (5) suggests that
no
Cox/2 =
n
/40 =
335.8 mho/volt.
(7). In principle, V
ve
, V
le
, V
h
, V
dsat
, and
n
, do not vary with changes in the drain-source voltage,
V
ds
. Accordingly, the ratio of the drain current (1.08 mA) for V
ds
= 1 volt to the drain cur-
rent (878.33 A) at V
ds
= V
dsat
= 278.2 mV is solely attributed to the last parenthesized fac-
tor on the right hand side of (20); that is,

( )
ds
ds dsat
d
ds sat gs h V 1V
d
V V
ds dsat
I
V M V V
1.08 mA
1.230 1
I 878.33 A V
V V
1 .
V
=
=

= = = +
= +
(E2-1)

EE 348 - 14 - April 2007
It follows that for V
ds
= 1 volt and V
dsat
= 278.2 mV, the channel length modulation volt-
age is V

= 3.138 volts.
(8). In an attempt to demonstrate the propriety of this modeling exercise, the forward static
transfer characteristic of the subject transistor is modeled in HSPICE for both V
ds
= 1 volt
and V
ds
= 1.5 volts. The simulated results are then compared with drain current calcula-
tions deriving from (20), using the computed values of V
ve
, V
le
, and V
and
n
.
Figures (6) and (7) display the results of the foregoing comparative study. In Figure (6),
the simulated and calculated forward transistor characteristics in the saturation domain are
displayed for a drain-source voltage, V
ds
, of 1.0 volt. The calculations corroborate
reasonably well with pertinent simulations in that 12% error is observed for 0.80 volt <
V
gs
< 1.35 volts. Figure (7) confirms better corroboration between calculated and simu-
lated results for V
ds
= 1.5 volts. In particular, the computational error is within 12% for
0.85 volt < V
gs
< 1.85 volts.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Gate-Source Voltage (volts)
D
r
a
i
n

C
u
r
r
e
n
t

(
m
A
)
Simulation
Calculation

Fig. (6). Simulated and calculated values of the drain current in an N-channel transistor for a
drain-source voltage of 1 volt. The HSPICE model parameters for the considered
180 nM device are given in Table (1). The gate aspect ratio is selected to be 40.
COMMENTS: In Step #2 of the computational procedure, the gate aspect ratio, W/L, is the
pivotal metric for achieving the desired transconductance and transistor drain
current. If power dissipation is a dominant design concern, W/L can be
increased above the value of 40 discerned in this example, with the
understanding that the gate-source voltage, V
gs
, can be reduced commensu-
rately, thereby reducing the static drain current and the power dissipation of
the transistor. Of course, the primary penalty of large gate aspect ratio is a

EE 348 - 15 - April 2007
possible degradation of high frequency circuit response since the areas and
peripheral dimensions associated with various device capacitances increase
in proportion to the gate width, W.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Gate-Source Voltage (volts)
D
r
a
i
n

C
u
r
r
e
n
t

(
m
A
)
Simulation
Calculation

Fig. (7). Simulated and calculated values of the drain current in an N-channel transistor for a
drain-source voltage of 1.5 volt. The HSPICE model parameters for the considered
180 nM device are given in Table (1). The gate aspect ratio is selected to be 40.
In Step #3, the metric, V
ve
, is evaluated in terms of a purely empirical and
crude first order relationship to the oxide thickness, T
ox
. A possible way
around this empiricism is to compute V
ve
and all of the other requisite model-
ing parameters by curve fitting (20) to simulated or actually measured static
data. While this approach may be academically satisfying, it may be impru-
dent from a design time perspective. Keep in mind that biasing is not the
fundamental performance objective of an analog circuit; rather, biasing is the
necessary condition that expedites the desired analog responses.
The drain-saturation voltage, V
dsat
, is obviously a nonlinear function of the
excess gate voltage, (V
gs
V
h
), owing to the parameter, M
sat
. But in addition,
V
dsat
changes slightly with the applied drain-source voltage, V
ds
. Indeed, the
Level 49 model parameters account for a slight sensitivity of threshold volt-
age on V
ds
, which is as anticipated since the interface potential throughout the
entire channel varies somewhat as a function of the lateral (drain -to- source)
field engendered by V
ds
.
Finally, it should be noted that the computed value (3.138 volts) of the chan-
nel length modulation voltage, V
, is appreciably smaller than values often

propounded in the textbook literature. However, V
is indeed a relatively

EE 348 - 16 - April 2007
small voltage for deep submicron MOS technology transistors. This anemic
voltage is the principle cause of correspondingly small drain-source channel
resistances, which renders the realization of transconductor amplifiers, as
might be used in operational transconductor amplifier-capacitor (OTA-C) fil-
ters, a daunting challenge. The desire for accuracy surrounding the enumera-
tion of V
is exacerbated by the fact that parameter V
is not the constant that

is presumed tacitly in the foregoing demonstration. Instead, a more defini-
tive modeling study portrays V
as functionally dependent on drain-source

voltage, drain saturation voltage, and threshold voltage. If V
or the drain-
source channel resistance is critical in an analog circuit design endeavor, care
must therefore be exercised to ensure that model parameters are extracted in
terms of measured or simulated data that largely mirror the desired or ex-
pected operating state of the utilized transistor.
3.0. VOLTAGE AND CURRENT REFERENCES
Voltage references, which transform a power supply or other form of circuit voltage to a
voltage deemed more suitable for application specific linear signal processors, are fundamental
architectures in analog cells. This section analytically explores a variety of such references and
articulates their respective attributes and shortfalls. Unless stated otherwise, all transistors
embedded in the considered biasing configurations are presumed to operate in their saturation re-
gimes. Accordingly, (4) is exploited for most static volt-ampere characteristics of all transistors.
In light of the complications incurred by channel length modulation and mobility degradation
caused by both lateral and vertical electric fields, it is understood that
n
and
p
in (4) must be
interpreted as effective transconductance coefficients. In particular, these coefficients and the
associated parameters on which they depend are best discerned from either measurement or com-
puter-aided simulations, as exemplified by Example #2. Alternatively, cells intended exclusively
for biasing applications may exploit relatively long channel transistors for which
n
and
p
are
rendered nominally constant, independent of gate-source and drain-source voltages.
3.1. DIODE VOLTAGE REFERENCE
Figure (8a) depicts a simple, single transistor voltage reference using a resistor, R, and
activated by a voltage, V
x
, which may be the power supply voltage for the analog circuit of inter-
est or a smaller voltage proportional to the applied power line voltage. The transistor has its gate
and drain terminals connected together, thereby guaranteeing its saturation regime operation and
rendering the transistor functionally operational as a diode. The latter contention stems from the
fact that with the gate and drain terminals connected together, the transistor operates as a two
terminal device and conducts current only if its gate-source voltage, which is identical to its
drain-source voltage, V
ref
, exceeds the threshold potential of the transistor.
Assuming V
ref
V
h
, nodal analysis at the drain node of the transistor in Figure (8a) deliv-
ers
( )
( )
( )
2 x h ref h x ref
ref n ref h
V V V V V V
I V V ,
R R

= = (21)
which generates the reference voltage solution,
( )
n x h
ref h
n
1 4 R V V 1
V V .
2 R
+
= + (22)

EE 348 - 17 - April 2007
R
+V
x
V
ref
I
ref
(a).
V
ref
I
ref
(b).

Fig. (8). (a). Schematic diagram of a simple voltage reference circuit
using a transistor connected as a diode. (b). Alternative to (a)
in that resistance R is supplanted by a constant current source.
For V
x
equal to V
h
or for very small values of the circuit resistance, R, V
ref
converges, as expected
to V
ref
V
x
. On the other hand, if R is very large, (22) yields
x h
ref h
n
V V
V V .
R
= + (23)
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
0.50 0.70 0.90 1.10 1.30 1.50 1.70 1.90
Input Vol tage, V
x
(vol ts)
R
e
f
e
r
e
n
c
e

V
o
l
t
a
g
e
,

V
R
E
F

(
v
o
l
t
s
)
| n
R = 1 V
1
| n R = 10 V
1
| n
R = 100 V
1

Fig. (9). Static voltage response, V
ref
, to applied static input voltage, V
x
, for the bias
network in Figure (8).
Figure (9) plots the reference voltage solution, V
ref
, of (22) versus the applied static input
voltage, V
x
, for
n
R = 1 V
1
, 10 V
1
, and 100 V
1
and a presumed threshold potential, V
h
, of 500
mV. Observe that considerable sensitivity to voltage V
x
is exhibited for small values of
n
R,
while large values of
n
R exhibit a smaller sensitivity of the reference voltage to V
x
. Addition-
ally, the sensitivity of V
ref
to
n
R for most fixed values of V
x
appears to diminish with progres-

EE 348 - 18 - April 2007
sively larger
n
R. This latter observation is notable because of the inherent uncertainties in the
physical and geometric parameters on which
n
is dependent. The lesson learned herewith is that
the desirable reduced sensitivity of the reference output voltage to applied input voltage requires
suitably large values of the inverse voltage parameter,
n
R. These large parametric values can be
realized through a combination of a large circuit resistance and a large transistor gate aspect ra-
tio.
The foregoing disclosures portend a clue as to how the circuit in Figure (8a) might be
optimized. In particular, very large
n
R can be achieved by using a very large circuit resistance,
R. For very large R, the reference current, I
ref
, tends toward zero, thereby forcing voltage V
ref
to
approach the threshold potential, V
h
. Obviously, the zero reference current spawned by a large
circuit resistance is impractical. But a large circuit resistance in series with a voltage source, V
x
,
is tantamount to a current source boasting large shunt resistance. Accordingly, the circuit resis-
tance in Figure (8a) might be supplanted, as suggested in Figure (8b), by a constant reference
current, I
ref
, with the result that
ref
ref h
n
I
V V ,
= + (24)
which is the gate-source voltage solution of an N-channel MOSFET driven by a constant drain
current in the amount of I
ref
. In the limit as R is allowed to approach infinity, (24) mirrors (23) in
that V
ref
tends toward V
h
, whence I
ref
(V
x
V
h
)/R. Observe that (24) is independent of the ap-
plied bias voltage and instead, is now dependent on the reference current, I
ref
. Since the thresh-
old voltage rises with increasing device operating temperature in accordance with (7), it is
desirable that the current, I
ref
, applied to the biasing structure diminish with temperature in such a
way as to produce a nominally zero, or at least acceptably small, temperature coefficient of the
reference voltage. To this end, it can be shown, with the help of (5), (6), and (7), that the
temperature sensitivity of current I
ref
commensurate with a voltage reference posturing zero
temperature coefficient is
ref
I
ref ref
F
T
ref h
I I
3 2V
S ,
T T 2 V V
| | c
= + |
|
c
\ .
(25)
where V
F
is the Fermi potential introduced in (8). To crude first order, (25) suggests that the
temperature independence of the generated reference voltage requires a reference current whose
percentage decrease over temperature is about 50% larger than the corresponding percentage in-
crease in operating temperature.
3.2. ACTIVE VOLTAGE DIVIDER
A modification of the circuit in Figure (8a) entails replacing the circuit resistance, R, by a
second diode-connected transistor, as is illustrated in Figure (10a). The two transistors, M1 and
M2, have different gate aspect ratios, but they are otherwise identical. In particular, assume that
the two active devices are laid out in such a way as to yield
2
n1 1 1
12
n2 2 2
W L
k .
W L
= (26)
Since the two transistors are interconnected in series with one another, current I
ref
flows through
both of them, whence
( ) ( )
2 2
ref n2 x ref h n1 ref h
I V V V V V . = = (27)

EE 348 - 19 - April 2007
R
x
k R
12 x
+V
x
+V
x
V
ref
I
ref
I
ref
(a).
V
ref
(b).
M1
M2
V
h
V
h

Fig. (10). (a). Schematic diagram of a static voltage divider using two N-channel
transistors connected as individual diodes. The gate aspect ratio of
transistor M1 is k
12
2
times larger than that of M2, where constant k
12
is
defined by (22). (b). Electrical model of the circuit in (a).
Using (26), it follows that
x h 12 h
ref
12 12
V V k V
V ,
k 1 k 1
= +
+ +
(28)
which suggests that the square root ratio of the transistor gate aspect ratios stipulates the refer-
ence voltage output in terms of the applied static voltage, V
x
. Note that if k
12
= 1, V
ref
is rendered
independent of the transistor threshold voltage, V
h
, and is precisely one-half of the applied static
voltage, V
x
.
In effect, the circuit at hand behaves as an active voltage divider in that it emulates the
I/O characteristics of the classic resistive divider drawn in Figure (10b). In the latter circuit,
resistance R
x
can be chosen to ensure that the power, V
ref
I
ref
, dissipated in the electrical model is
identical to the power consumed by the active divider. In particular, since the current flowing in
the model is
( )
x h
ref
12 x
V 2V
I ,
k 1 R
=
+
(29)
( )
( )
( )
2
ref x h
ref ref ref n1 ref h
12 x
V V 2V
V I V V V ,
k 1 R
= =
+
(30)
which produces
( )
( )
x h
x
2
n1 12 ref h
V 2V
R .
k 1 V V
=
+
(31)
3.3. LOW VOLTAGE BIASING
The omnipresent shrinking of MOSFET device geometries is necessarily accompanied by
the need to operate electronic circuits at decreased supply line voltages so that potentially
catastrophic voltage overstress problems in transistors are circumvented. Diminished bias supply

EE 348 - 20 - April 2007
line voltages constrict the dynamic range of analog cells, thereby motivating the incorporation of
circuits that can operate acceptably while biased at minimal voltage levels.
To the foregoing end, the circuit offered in Figure (11) is ubiquitous in low voltage
applications
[2]
. The bulk substrate terminals, which are not delineated in the diagram, are pre-
sumed to be returned to ground or preferably and if the process allows, to the respective source
terminals of the transistors. The gate aspect ratio of transistor M2 is k
2
times larger than that of
M1 so that
M1
M2
V
bias
I
ref
V
ref

Fig. (11). Schematic diagram of a low voltage biasing
cell. The gate aspect ratio of transistor M2 is
k
2
times larger than that of transistor M1.
The substrate bulk terminals are presumed
grounded or preferably, are incident with the
respective source terminals of each transistor.
2 n2 2 2
n1 1 1
W L
k .
W L
= (32)
Since the static reference current, I
ref
, flows through both transistors,
( ) ( ) ( )
2 2 2
ref n1 gs1 h n2 gs2 h n2 ref h
I V V V V V V , = = (33)
thereby implying, with the help of (32), the voltage relationship,
( ) ( )
gs1 h gs2 h ref h
V V k V V k V V , = = (34)
where use is made of the fact that the gate-source voltage, V
gs2
, pertinent to transistor M2 is the
indicated reference output voltage, V
ref
. Moreover, the applied bias voltage, V
bias
, is adjusted to
ensure that the drain-source voltage, V
ds2
, of transistor M2 is
ds2 bias gs1 ref h
V V V V V . = (35)
If M2 is a long channel device, (35) pins M2 to the crossover region between triode and satura-
tion domains. Since the drain saturation voltage of deep submicron transistors is smaller than the
difference between gate-source and threshold voltages, (35) actually remands M2 to its saturated
domain, slightly above the triode region.
Now, the applied voltage bias, V
bias
, satisfies
bias gs1 ds2 gs1 ref h
V V V V V V , = + = + (36)
where (35) is exploited. Using (34), this relationship leads to
( )
bias h gs1 h ref h gs1 h
k 1
V V V V V V V V .
k
+
| |
= + =
|
\ .
(37)
It is interesting that the drain-source voltage, V
ds1
, established for transistor M2 is only the
threshold voltage, V
h
, since by (35),

EE 348 - 21 - April 2007
( )
ds1 ref ds2 ref ref h h
V V V V V V V . = = = (38)
If M1 is held in its saturation domain, (37) produces the requirement,
( )
h gs1 h bias h
k
V V V V V .
k 1
| |
> =
|
+
\ .
(39)
It follows that transistor M1 is saturated and transistor M2 is at the border of triode and saturation
regimes if the applied biasing voltage, V
bias
, satisfies
bias h
2k 1
V V .
k
+
| |
s
|
\ .
(40)
Finally, the reference output voltage is
gs1 h
bias h
ref gs2
V V
V kV
V V .
k k 1
+
= = =
+
(41)
Observe that for constant V
bias
, voltage V
ref
is a constant, independent of current I
ref
. Recalling
(40), it is interesting to note that the reference voltage associated with the subject biasing cell
satisfies the inequality,
bias h
ref h
V kV k 1
V V .
k 1 k
+ + | |
= s
|
+
\ .
(42)
In other words and dependent on the value chosen for parameter k, the reference output voltage
is only slightly larger than the threshold potential of the utilized transistors.
3.3.1. Output Resistance
The output resistance of the low voltage cell can be discerned through an investigation of
its small signal equivalent circuit. To this end, the pertinent low frequency small signal model is
submitted as Figure (12), where g
m1
and r
o1
respectively denote the transconductance and drain-
source channel resistance of transistor M1, g
m2
and r
o2
correspondingly represent the
transconductance and channel resistance of M2, and the current and voltage sources, I
ref
and V
bias
,
are presumed ideal. A straightforward analysis of the subject model reveals a Thvenin output
resistance, R
out
, of
M1
M2
V
bias
I
ref
I
x
V
ref
R
out
g V
m1 1
r
o1
g V
m2 x
r
o2
+ V
x
+
V
1
I
x

Fig. (12). Small signal equivalent circuit of the low voltage biasing cell. The output resistance,
R
out
, is the ratio of V
x
to I
x
.
( )
( )
o1 m1 o1 o2
x
out
x m2 m1 o1 o2
r 1 g r r
V
R .
I 1 g 1 g r r
+ +
= =
+ +
(43)

EE 348 - 22 - April 2007
For large values of the channel resistances, r
o1
and r
o2
, R
out
in (43) collapses to 1/g
m2
, which is
nominally the terminal small signal resistance of a diode-connected MOSFET. As Figure (13)
suggests, the cell shown in Figure (11) behaves approximately as a diode-connected transistor
driven by a reference current source, I
ref
, of
M1
M2
V
bias
I
ref
V
ref
M2
V
ref
(k + 1)
2
n2 bias h
(V V )
2
n1

n2 n1
= k
2

Fig. (13). Emulation of the low voltage biasing cell in Figure (11). Note that the low
voltage cell behaves as a MOS diode conducting an appropriate drain
current whose value is functionally related to the original bias voltage, V
bias
.
( ) ( )
2 2
2 2
ref n1 bias h n2 bias h
k 1
I V V V V .
k 1 k 1
| | | |
= =
| |
+ +
\ . \ .
(44)
Equation (43) posits a strategy for the accurate realization of the bias voltage, V
bias
, which
activates the gate terminal of transistor M1. To this end, consider the circuit schematic diagram
of Figure (14), where the gate aspect ratio of transistor M3 is chosen such that
M1
M2 M3
I
ref
V
ref
V

=

V
g
s
3
b
i
a
s
n1

n2 n1
= k
2
(
k

+

1
)
2
n
3

=

k
2
n
1
I
in

Fig. (14). Realization of the bias voltage, V
bias
, required of the low
voltage cell in Figure (11).
2
n3 n1
k
.
k 1
| |
=
|
+
\ .
(45)
If the drain current is I
ref
, as defined by (44), the M3 gate-source voltage, which is the voltage
established from the gate of M1 to ground, is clearly the requisite biasing voltage, V
bias
.
3.3.2. Low Voltage Cascode Current Mirror
Deep submicron MOSFETs biased at voltage and current levels that promote low circuit
power dissipation are incapable of establishing large drain-source channel resistances. This

EE 348 - 23 - April 2007
inexorable fact is disconcerting in the design of current sources and sinks and common source
transconductance amplifiers, all of which require large output port resistances. A traditional
mitigation of the channel resistance dilemma in these and related other applications entails inser-
tion of a common gate cascode stage in series with the drain output terminal of the common
source cell. Obviously, such a design tack requires power line voltages that are sufficiently large
to bias the series interconnection of two drain-source ports, as well as any other passive or active
elements that are driven by the cascode topology. But since very short channel devices are
vulnerable to voltage breakdown, the circuits that exploit them are constrained to operate with
low power line voltages that are invariably too small to accommodate the series interconnection
of several devices or elements.
The low voltage bias cell provides a viable solution to the foregoing problem. To this
end, the cascode current mirror submitted in Figure (15) has become commonplace in analog
integrated circuits utilizing deep submicron MOS technology transistors
[3]
. The gate aspect ra-
tios delineated in this diagram are normalized to the gate aspect ratio of transistor M1. For
example, the gate aspect ratio of M2 is k
2
times larger than that of M1. Ideally, the current, I
bias
,
is identical to the current, I
ref
. But owing to the simplified static models invoked for the transis-
tors embedded in the circuit, a computer-aided adjustment of current I
bias
is inevitably required to
set the voltage, V
bias
, which is applied to the gate terminals of transistors M1 and M3, to its de-
sign goal value.
M1
M2 M4
M5
M3
I
ref
I
bias
V
bias
V
ref
I
o
V
o
x 1
x k
2
k + 1
k
( )
2
x x k
2
x 1
V V
ref h
R
out

Fig. (15). A cascode current mirror that exploits the low voltage
biasing cell introduced in Figure (11).
In order to gain an appreciation of the low voltage effectiveness of the cascode mirror,
note that voltage V
ref
biases the gate-source terminals of both transistors M2 and M4. Since
transistor M2 is biased at the crossover between its triode and saturation operational regimes, the
voltage developed at the drain of transistor M2 can be as small as (V
ref
V
h
). Recalling (40) and
(41), (V
ref
V
h
) V
h
/k. But since M2 and M4 are identical, inclusive of their respective gate as-
pect ratios, the drain of transistor M4 must likewise support a voltage of (V
ref
V
h
) V
h
/k. In
turn, the gate source voltages, [V
bias
(V
ref
V
h
)] = (V
bias
V
h
/k), of M1 and M5 are rendered
identical. In view of the facts that transistors M1 and M5 are matched devices and that the drain-
source voltage of transistor M1 is, by (38), V
h
, the drain-source voltage imposed on transistor M5
is also V
h
. It follows that the voltage, V
o
, required at the output node of the current mirror is sim-
ply the sum of the drain-source voltages of transistors M5 and M4, or V
o
= V
h
+ V
h
/k = (1 +
1/k)V
h
. Thus, for example, if the mirror is designed for k = 2, the minimum acceptable voltage,
V
o
, at the output node of the cascode mirror can be as small as only 1.5times the threshold

EE 348 - 24 - April 2007
potential. In 130 nm CMOS technology, this requisite minimum voltage is generally of the order
of only 600 millivolts to 750 millivolts.
g V
m5 a
r
o5
g V
m4 b
r
o4
+ V
a
1/g
m3
+ V
b
1/g
m2
I
x
V
x
+
R
out

Fig. (16). Small signal model pertinent to an evaluation of the output
resistance, R
out
, of the current mirror in Figure (16).
The small signal output resistance, R
out
, is large by virtue of the fact that the drain-source
channel resistance of transistor M4 serves as source degeneration for transistor M5. Assuming
that the current sources, I
bias
and I
ref
, emulate ideal sources and recalling that the M1-M2 cell
approximates a simple MOSFET diode, the small signal model pertinent to calculating R
out
is the
structure in Figure (16). In this diagram, g
mi
represents the forward transconductance of the i
th

transistor, while r
oi
is the drain channel resistance of the i
th
device. A straightforward circuit
analysis of the model at hand reveals that
( )
x
out o5 m5 o5 o4
x
V
R r 1 g r r .
I
= = + + (46)
Clearly, the cascode arrangement enhances the channel resistance of M5 by effectively forging a
reasonably large resistance, (1 + g
m5
r
o5
)r
o4
, in series with r
o5
.
3.4. SUPPLY-INDEPENDENT BIASING
The biasing of an electronic network, and particularly an electronic network earmarked
for a linear signal processing application, determines its observable performance because of the
dependence of numerous transistor model parameters on quiescent currents and voltages. De-
graded network characteristics are therefore a likely consequence of quiescent operating point
fluctuations induced by temperature changes, signal overstresses that temporarily drive nomi-
nally linear circuit cells into nonlinear regimes, and other phenomena. Included among these
other phenomena are variations in power line voltages on which quiescent variables are natu-
rally dependent. Such variations are incurred by poor regulation that allows line voltages to vary
with the current supplied by the line, poor line decoupling, which exacerbates the effects of
electromagnetic interference and electrical noise induced along the bus lines, and in the case of
portable electronics, the natural diminution of battery voltage over time. While several design
strategies exist to mitigate the effects of parametric uncertainties caused by biasing uncertainties
and variations, a particularly simple and interesting approach entails the implementation of bias-
ing that is rendered independent of supply line voltage. To this end, the circuit shown in Figure
(17) establishes a foundation for supply-independent biasing.

EE 348 - 25 - April 2007
x 1
x k
p x 1
M3 M5 M4
M2 M1
x k
n
x 1
R R
l
I
Q
I
Q
k I
p Q
+V
dd

Fig. (17). Schematic diagram of a circuit for establishing a
quiescent current, I
Q
, that is nominally independent
of the supply voltage, V
dd
. The bulk terminals of
all P-channel devices are returned to the +V
dd
line.
On the other hand, the bulk terminals of the two N-
channel transistors are either grounded or, if feasi-
ble, returned to their respective source terminals.
In the subject circuit diagram, transistor M4 and diode-connected transistor M3 are identi-
cal P-channel devices whose effective transconductance coefficients are
p
. A third P-channel
device, M5, has a gate aspect ratio that is larger than the gate aspect ratio of either M3 or M4 by a
factor of k
p
. If the channel lengths of M3, M4, and M5 are long in comparison to the submicron
lengths typified by transistors earmarked for broadband signal processing and/or if the source-
drain voltages developed across these three transistors are comparably the same, the indicated
interconnection of these three devices comprise an accurate current mirror. In particular, if a
static current, I
Q
, is established in M3, the same current flows in the drain of transistor M4, while
a current of k
p
I
Q
can be supplied to the load resistance, R
l
, which terminates the drain terminal of
M5 to ground.
In Figure (17), the two N-channel devices, M1 and M2, are forced to conduct the current,
I
Q
, flowing in M3 and M4, despite the application of resistive degeneration in the source lead of
M2. These NMOS devices are identical, save for the fact that the gate aspect ratio of M2 is lar-
ger than that of M1 by a factor of k
n
. Accordingly,
( ) ( )
2 2
Q n gs1 hn n n gs2 hn
I V V k V V , = = (47)
which engenders
gs1 hn
gs2 hn
n
V V
V V .
k
= (48)
In (47) and (48), V
hn
is, of course, the threshold voltage of the N-channel units.
The insertion of resistance R in the source terminal of M2 renders current I
Q
proportional
to the difference of the gate source voltages, V
gs1
and V
gs2
, developed on M1 and M2, respec-
tively. In particular,
( ) ( )
gs1 hn gs2 hn
gs1 gs2
Q
V V V V
V V
I .
R R

= = (49)
Using (48) and (47), this result produces

EE 348 - 26 - April 2007
Q n
Q
n
I
1
I 1 .
R
k
| |
= |
|
\ .
(50)
Equation (50) gives rise to a second order relationship in current I
Q
that has two solutions. One
of these solutions is trivial; namely, I
Q
= 0 clearly satisfies (50). The other, and more interesting,
solution is
2
Q
2
n
n
1 1
I 1 ,
k
R
| |
= |
|
\ .
(51)
which is independent of the power bus voltage, V
dd
. Of course, this invariance with V
dd
is main-
tained only insofar as V
dd
is sufficiently large to ensure the saturation regime operation of transis-
tors M2, M4, and M5.
3.4.1. Constant Transconductance
In addition to projecting a quiescent current that is independent of V
dd
, (51) implies a
small signal transconductance in M1 and indeed in all transistors that is nominally independent
of V
dd
, as well as the biasing current. To demonstrate this contention, examine the M1 small sig-
nal transconductance, g
m1
, at a drain current of I
Q
. To wit, (4) yields
d1 Q
d1
m1 n Q
gs1
I I
dI
g 2 I .
dV
=
= (52)
But if (50) is substituted into this expression,
m1
n
2 1
g 1 ,
R
k
| |
= |
|
\ .
(53)
which, because of a functional dependence on only resistance R and gate aspect ratio parameter
k
n
, is accurately predictable. Aside from mere analytical predictability, a constant transconduc-
tance that is independent of both applied voltages and device currents is a pivotal requirement
underpinning the realization of maximally linear MOSFET circuit cells. The transconductance
defined by (53) is also thermally stable to the extent that resistance R can boast minimal tempera-
ture sensitivity. The particularly simple result of g
m1
= 1/R ensues if k
n
is selected as four. Since
all transistor currents are either equal to or proportional to current I
Q
, the transconductances of all
transistors in the circuit of Figure (17) are thus independent of drain currents and the power sup-
ply voltage.
3.4.2. Startup Circuit
As noted earlier, a trivial solution to the equilibrium equations indigenous to the circuit in
Figure (17) is a bias current, I
Q
, of zero. This trivial, but nonetheless stable, solution occurs with
distressing frequency. In particular, the circuit in Figure (17) may not boot up to deliver the
desired current given by (50), choosing instead to respond in the steady state to the applied
power supply voltage with zero current flowing through all transistors. Ironically, the likelihood
of null current responses increases with improved matching of transistors M3 and M4. In order
to disallow a useless null current response, the left and right hand halves of the cell comprised of
transistors M1 through M4 must be purposefully imbalanced by drawing current from either the
M1-M4 or M2-M3 drain terminal interconnection. Ideally, this current imbalance is incurred
temporarily and only immediately subsequent to the application of the power line voltage, V
dd
.

EE 348 - 27 - April 2007
Once the circuit is able to sustain the quiescent current given by (50), the imbalance induced by
an appropriate startup subcircuit that incurs the requisite imbalance is removed to preclude
unnecessary power dissipation.
Figure (18) depicts a simple startup subcircuit that has been appended to the supply-
independent circuit analyzed herewith
[4]
. The startup cell in question is comprised of capacitor C
and common source transistors M6 and M7. Note that the gate terminal of M6 is incident with
the junction of the drain terminals of M1 and M4, while the drain terminal of M7 is connected to
the junction of the drain terminals of M2 and M4. In the steady state, where capacitance C is an
open circuit, no static voltage is delivered to the gate of M7, thereby forcing M7 into cutoff. In
addition, the open circuited nature of C in the steady state precludes any drain current in M6.
Thus, the highlighted startup cell is effectively removed from the supply-independent configura-
tion when steady state biasing levels are achieved. Although the startup cell is transparent to
strict DC, it does load the M4 and M3 drain nodes with parasitic device capacitances.
Fortunately, these nodes exhibit low driving point impedances under small signal conditions ow-
ing to the diode-connected nature of M1 and M3. Nonetheless, care should be exercised in the
selection of the channel lengths and gate aspect ratios of M6 and M7 to circumvent potentially
significant frequency response degradation at high signal frequencies.
x 1
x k
p x 1
M3 M5 M4
M2
M6
M7
x k
n
R
R
l
I
Q
M1
x 1
I
Q
k I
p Q
+V
dd
C
Startup
Cell

Fig. (18). The supply-independent biasing network of Figure (17)
embellished by a startup subcircuit that precludes I
Q
= 0 in
the steady state. The currents indicated in the diagram ap-
ply only to steady state operating conditions.
Assume that the power supply voltage, V
dd
, is applied as a reasonable approximation of a
step voltage at time t = 0. If capacitance C is initially uncharged and is much larger than the net
device capacitance witnessed at the gate of transistor M7, almost all of V
dd
appears at said gate
instantly, thereby turning on M7. It is therefore clear that the drain current of M7 establishes the
aforementioned imbalance that ostensibly precludes the null current solution. The current flow-
ing in M7 necessarily derives from M3. This device turns on prior to M4, which awaits charging
of its source-gate capacitance to its threshold potential. Immediately after time t = 0, M3 begins
conducting current into the drain of M2, while M4 and M1 remain nominally in cutoff. When
current flows through M2, the sum of the gate source voltage of M2 and the voltage drop across

EE 348 - 28 - April 2007
resistance R begins to rise to the threshold potential of M1, thereby supporting the initiation of
current in the drain of M4. As the gate-source voltage of M1 continues to rise, so does the gate
source voltage of M6, which throughout this interlude, remains cutoff. But as the gate-source
voltage of M6 rises beyond threshold level, M6 conducts, which charges capacitance C toward
V
dd
and lowers the voltage at the gate of M7. When C charges to a level greater than (V
dd
V
h7
),
where V
h7
is the M7 threshold voltage, M7 switches off, which is tantamount to the circuit
achieving its steady state operating condition. Since zero current response has been precluded by
the current imbalance induced by the startup cell at the instant of voltage application, this steady
state condition supports the establishment of (51) as the only solution for current I
Q
.
3.5. BANDGAP REFERENCE
In addition to affording low voltage, low power, and supply independence, voltage refer-
ences required of high performance analog integrated circuits, and especially circuits earmarked
for high speed data acquisition and information processing, must project a high degree of
temperature insensitivity. The temperature sensitivity problem is especially severe in deep
submicron technologies for which even modest current levels correspond to the high current
densities that routinely manifest intrinsic temperature increases of as much to as much as 75 C
or larger. The most commonly invoked engineering solution to the temperature dilemma is the
bandgap reference circuit, which produces a nominally temperature invariant static output volt-
age by exploiting the inherently negative temperature coefficient of the junction potential devel-
oped across a forward biased junction diode. In particular, the bandgap reference produces an
output response that is proportional to the sum of the aforementioned junction forward bias and
the output voltage of an incorporated subcircuit, known as a PTAT generator, whose voltage out-
put is directly proportional to absolute temperature.
Conceptually, the bandgap reference is the abstraction postured in Figure (19), where the
requisite junction forward bias is extracted as the base-emitter voltage, V
be
, corresponding to a
constant current, I
c
, flowing in the collector of a bipolar junction transistor. The PTAT generator
delivers an output voltage of KV
T
, were K is a positive constant and V
T
, the Boltzmann voltage,
is
T
V kT q . = (54)
+
I
c
PTAT
Generator
KV
T
+V
p
V
ref
A
v
V
be

Fig. (19). Schematic abstraction of a bandgap reference circuit.
In (54), k is Boltzmanns constant [1.38(10
23
) joules/K], q is the magnitude of electron charge
[1.6(10
19
) coulombs], and most importantly, T is temperature in K. If the amplifier has a

EE 348 - 29 - April 2007
differential input to single ended output voltage gain of A
v
, the voltage reference, V
ref
, produced
at the output of the bandgap reference circuit is
( )
ref v be T
V A V KV . = + (55)
The constant, K, is chosen to ensure that the temperature derivative of voltage V
ref
is zero at a
specified reference temperature, say T
o
. Assuming gain A
v
and constant K are temperature
invariant, this zero temperature sensitivity criterion requires
o
o be
To T T
T dV
K ,
V dT
=
| |
| =
|
\ .
(56)
where V
To
is the reference temperature value of the Boltzmann voltage; that is V
To
= kT
o
/q.
3.5.1. PN Junction Voltage Characteristic
In the diagram of Figure (19), the base and emitter terminals make electrical contacts to
the p- and the n-sides, respectively, of an intrinsic PN junction. To a good approximation, the
indicated collector current, I
c
, relates to the temperature dependent voltage, V
be
(T), developed
from the base to the emitter terminals as
be T be T
V (T) V V (T) V
c s j s
I I A J , e e = = (57)
where I
s
denotes the temperature dependent saturation current of the transistor, J
s
is the satura-
tion current density (current per unit of the base-emitter junction cross section area), A
j
repre-
sents the base-emitter junction cross section area, and is the junction emission coefficient,
which is typically very slightly larger than one. The functional dependence of the base-emitter
voltage can be written as
[5]
,
c o
be go beo T
o o co
J T T T
V (T) V 1 V V m .
T T J T
ln ln
( | | | | | |
| |
= + + +
( | | | |
\ .
\ . \ . \ .
(58)
In this expression T
o
is an arbitrary reference temperature (usually taken as 300 K), V
go
is the
reference temperature value of the bandgap potential (1.206 volts in silicon operated at 300 K),
and V
beo
is the reference temperature value of the base-emitter junction voltage; that is, V
beo

V
be
(T
o
). Parameter m is an empirical constant whose value is approximately 2.30 in silicon, J
c
is
the density of collector current (collector current divided by the cross section area, A
j
, of the
base-emitter junction) at an absolute junction temperature of T, and finally, J
co
is the T = T
o

value of collector current density J
c
.
The temperature dependence of the current density ratio, J
c
/J
co
, is largely determined by
the circuit in which the transistor undergoing scrutiny is embedded. In most of the commonly
utilized bandgap reference cells, this ratio is rendered proportional to absolute temperature in
accordance with the simple expression,
c
co o
J T
,
J T
= (59)
assuming that any resistors utilized in the reference cell have negligibly small temperature
coefficients and assuming further that no significant temperature gradients prevail across band-
gap reference chip. Accordingly, (58) becomes
( )
be go beo T
o o o
T T T
V (T) V 1 V m 1 V ,
T T T
ln
| | | | | |
= +
| | |
\ . \ . \ .
(60)

EE 348 - 30 - April 2007
for which the temperature sensitivity, M
be
(T), as measured by the first temperature derivative of
V
be
(T), is
( )
go beo
be
be
o o
V V
k m 1 dV (T) T
M (T) 1 .
dT T q T
ln
( | |
= +
( |
\ .
(61)
Since V
go
> V
beo
and m > 1, both terms on the right hand side of this relationship are negative,
thereby confirming a negative temperature coefficient for the base-emitter potential. Figure (20)
displays a plot of M
be
(T) as a function of temperature T for the case of V
beo
=700 mV, = 1.0, m
= 2.30, and a reference temperature of T
o
= 27 C = 300.2 K. The last term is invariably
inconsequential for meaningful operating temperatures. Accordingly, and as is inferred by the
plot in Figure (20), the temperature sensitivity function, M
be
(T), is almost constant, varying in the
present case from 1.787 mV/C at T = 0 C to 1.822 mV/C at T = 100 C.
-1.85
-1.83
-1.81
-1.79
-1.77
-1.75
0 20 40 60 80 100
Juncti on Temperature (degree C)
M
be
(T) (mV/ degree C)

Fig. (20). The temperature sensitivity of the base-emitter junction voltage of a bipolar
junction transistor as a function of the junction temperature. Note that the
sensitivity function, M
be
(T), is plotted in units of mV/C and that the
temperature scale is dimensioned in centigrade degrees.
The fundamental base-emitter potential relationship of (58) is interesting from the stand-
point of its implications for two identical transistors (save for different base-emitter junction ar-
eas) operated at different collector current densities. Denote these two collector current densities
as J
c2
and J
c1
, which respectively correspond to base emitter voltages of V
be2
(T) and V
be1
(T). If
the two transistors operate at the same junction temperatures, simple algebraic manipulation con-
firms that

EE 348 - 31 - April 2007
c2
be2 be1 T
c1
J
V (T) V (T) V .
J
ln
| |
=
|
\ .
(62)
Given a constant current density ratio, J
c2
/J
c1
that is constant, independent of temperature, this
result suggests that the difference in the pertinent base-emitter junction voltages is directly
proportional to absolute temperature, where (54) is recalled. Thus, (62) can serve as the founda-
tional platform for constructing a PTAT generator. A slight shortfall of this contention is that
identical transistors carrying non-identical collector current densities are likely to be operating at
different junction temperatures. Thus, care must be exercised to preclude widely divergent cur-
rent densities or equivalently, significant temperature gradients between the two transistors.
3.5.2. Circuit Realization
The foundation of most of the currently used bipolar bandgap references is the Brokaw
circuit whose basic schematic diagram appears in Figure (21)
[6]
. The circuit at hand utilizes two
identical bipolar junction transistors, Q1 and Q2, whose junction areas are A
j1
and A
j2
, respec-
tively. The amplifier in the schematic diagram must have sufficiently large open loop gain to
drive its differential input voltage to nearly zero. With identical resistances, R, in the collector
circuits of the two transistors, currents I
1
and I
2
are resultantly equal to one another. Accord-
ingly, the reference output voltage, V
ref
, is, with transistor base currents neglected on the tacit
assumption that the transistors have large short circuit current gains,
+
Q2
R
Q1
R
R
1
R
2
I
2
I
1
Amp
I +I
1 2
+V
dd
+ +

V
be1
V
be2
V
ref

Fig. (21). Basic schematic diagram of a bandgap
reference circuit realized in bipolar junc-
tion transistor technology.
ref be2 1 1
V V 2I R , = + (63)
while
be2 be1
1
2
V V
I .
R
= (64)
By (57) and the fact that I
1
= I
2
,

EE 348 - 32 - April 2007
( )
be2 be1 T
2 j2 j1 V V V
c2
1 j1 c1 j2
I A A
J
,
I A J A
e

= = = (65)
whence
j1
c2
be2 be1 T T
c1 j2
A
J
V V V V ,
J A
ln ln
| |
| |
= = |
|
|
\ .
\ .
(66)
which is proportional to absolute temperature. But unlike the general expression of (62), observe
that the current density ratio, J
c2
/J
c1
, in the equation at hand is temperature independent in that
the identical collector currents flowing in the two transistors force this current density ratio to be
a mere ratio of device areas. Moreover, (64) and (66) combine to guarantee that current I
1
, and
hence current I
2
, is PTAT, which supports the presumption promulgated by (59) and therefore
validates the base-emitter voltage temperature sensitivity expression of (61). It follows that (66)
and (64) combine with (63) to deliver
j1
1
ref be2 1 1 be2 T
2 j2
A
2R
V V 2I R V V .
R A
ln
| |
| |
= + = + |
|
|
\ .
\ .
(67)
Using (60), the temperature sensitivity, M
ref
(T), of the output reference voltage is
( )
ref
ref
go beo j1
1
o o 2 j2
dV (T)
M (T)
dT
V V A
k m 1 T 2R k
1 .
T q T R q A
ln ln
| | ( | | | || |
= + + |
( | | |
|
\ . \ . \ .
\ .
(68)
If M
ref
(T
o
) = 0 is a design goal, the requirement imposed on the resistor ratio, R
1
/R
2
, is
( )
go beo
o 1
2 j1
j2
V V
m 1
T R
.
R A
2
A
ln
+
=
| |
|
|
\ .
(69)
Substituting this result and (60) into (67), the corresponding optimal reference voltage output (in
the sense of zero temperature coefficient at the reference temperature), V
ropt
, is
( )
ropt go T
o
T
V V m 1 V 1 .
T
ln
( | |
= +
( |
\ .
(70)
It is to be understood that by invoking (69), the temperature sensitivity of reference voltage V
ropt

in (70) is zero at the reference temperature, T
o
.
In the monolithic implementation of the subject bandgap reference cell, resistors R
1

and/or R
2
must be trimmed to the optimum reference voltage at T = T
o
. With m = 2.3 and = 1,
this desired T = T
o
value of V
ropt
is 1.240 volts. However, the numerical uncertainty surrounding
parameters and m may require that the reference temperature value of V
ropt
be determined
experimentally during design prototyping of the bandgap cell. The need for resistive trimming
derives from the uncertainties surrounding the reference temperature value, V
beo
, of the base-
emitter voltages established for the two utilized transistors, as well as the vagarious nature of
empirical parameters and m. Moreover, it must be recalled that the analysis leading to (70) is
predicated on the presumptions that the amplifier implicit to the bandgap cell has very large open
loop gain and the transistors have large short circuit current gains. The latter stipulation may

EE 348 - 33 - April 2007
prove especially troubling in CMOS processes that may not produce high quality bipolar junc-
tion transistors.
The effect of the bandgap reference generator in the sense of establishing a supply-
independent voltage reference that is minimally sensitive to junction operating temperature is
best examined numerically. To wit, the optimum reference output voltage at T = 0 C is, by
(69), 1.239515 volts, at T = 27 C (the reference temperature) V
ropt
= 1.239655 volts, and at T =
100 C, V
ropt
= 1.238732 volts. Thus, the change, say V
ropt
, in reference voltage output for a
temperature rise of 100 C from 0 C is only 783.0 V or 0.0632% of the reference temperature
value of the optimum reference output voltage. Stated even more dramatically, this voltage
change amounts to 632 ppm/K! When viewed in conjunction with the amplifier in Figure (21),
whose presumed low open loop output impedance is lowered further by the feedback incorpo-
rated in the circuit, the bandgap reference is an excellent biasing source featuring excellent
power supply rejection, temperature insensitivity, and load regulation. In actual integrated cir-
cuits, second order phenomena not embraced by the analysis undertaken herewith beget observed
temperature figures of merit that may be as much as a factor of two larger than those quoted
herewith. Nonetheless, the bandgap reference circuit remains a superb choice for the circuit de-
signer faced with achieving demanding performance specifications.
+
Q2
R
Q1
R
R
1
R
5
R
2
R
4
R
3
I I
Amp
2(I + I )
b
V /R
ref 5
+V
dd
+ +

V
be1
V
be2
V
A
V
ref
I + I
b
I + I
b
2I
b
2I + V /R
b ref 5

Fig. (22). The bandgap reference supply of Figure (21), modified to allow
for a large reference output voltage, V
A
, and compensation of
the effects of base currents flowing into transistors Q1 and Q2.
3.5.3. Increased Bandgap Reference Voltage
As noted in the preceding section, the bandgap reference circuit in Figure (21) is capable
of a reference output voltage of the order of only 1.24 volts. Larger reference outputs require the
topological structure shown in Figure (22), where resistances R
3
, R
4
, and R
5
have been appended
as shown to modify the basic structure in Figure (21). The series shunt feedback interconnection
of resistances R
4
and R
5
increases the original reference output voltage, V
ref
, to a voltage, V
A
, that

EE 348 - 34 - April 2007
is larger than V
ref
by a factor of (1 + R
4
/R
5
). On the other hand, resistance R
3
is incorporated to
cancel the effects of base currents conducted by transistors Q1 and Q2.
In order to demonstrate how the effects of transistor base currents are mitigated through
proper selection of resistance R
3
, the circuit in Figure (22) can be analyzed under the depicted
condition of equal collector currents (I) flowing in Q1 and Q2. To this end, the loop comprised
of the base-emitter junctions of Q1 and Q2 and resistances R
2
and R
3
yields
( )
be2 be1 2 2 3 b
V V R I R R I . = + + + (71)
In addition, the reference voltage, V
ref
, is given by
( )
ref be2 1 b
V V 2R I I , = + + (72)
which, when (71) is used to eliminate collector current I in the last equation, offers
( )
1 1
ref be2 be2 be1 3 b
2 2
2R 2R
V V V V R I .
R R
= + (73)
The enhanced reference voltage, V
A
, derives as
4
A 4 b ref
5
R
V 2R I 1 V .
R
| |
= + +
|
\ .
(74)
Substituting for V
ref
from (73),
( )
4 4 1 1
A be2 be2 be1 4 3 b
5 2 5 2
R R 2R R
V 1 V V V 2 R 1 R I .
R R R R
( | | | | ( | |
= + + + +
( | | | (
\ . \ . \ .
(75)
The first product of terms on the right hand side of this relationship is the enhanced reference
voltage that materializes if the transistor base currents, I
b
, are zero or equivalently, if the static
short circuit current gains of the two bipolar devices are infinitely large. It follows that the last
term in the subject equation is an error precipitated by nonzero base currents. Fortuitously, this
error term, which is proportional to I
b
, vanishes by properly constraining resistance R
3
. An
inspection of (75) reveals that the error contributed to V
A
by base currents is forced to zero if
( )
2
3 4 5
1
R
R R R .
R
| |
=
|
\ .
(76)
4.0. CONSTANT TRANSCONDUCTANCE CELLS
As noted earlier, circuits capable of providing a constant transconductance that is
independent of device bias currents, power line voltages, and operating temperature are
indispensable building blocks for the realization of linear amplifiers boasting high signal
dynamic range. One example of a viable constant transconductor has already been presented as
the circuit of Figure (17), which, when embellished by the requisite startup subcircuit exempli-
fied in the schematic diagram of Figure (18), enjoys widespread utility in high performance cir-
cuit applications. However, a shortfall of this particular cell is that the observed
transconductance, which is largely determined as the inverse of a fixed circuit resistance, cannot
be adjusted, or tuned, to compensate for design uncertainties and processing vagaries. A sec-
ond potential problem is that the driving point output resistance is limited by the channel resis-
tance of the PMOS device used to drive the load termination. In deep submicron technologies,
which invariably labor with anemic channel length modulation voltages and necessarily operate
at small drain-source biases, this channel resistance is rarely larger than a few thousand ohms. In
turn, small channel resistances that produce correspondingly small output resistances impair the

EE 348 - 35 - April 2007
linearity of broadband amplifiers, active filters, comparators, and other types of circuits indige-
nous to modern communication networks.
In this section of material, several constant transconductance cells capable of generating
constant and linearly controllable transconductances are assessed. A foundation of many of
these circuits is a simple, but nonetheless innovative, subcircuit featuring a series interconnection
of an NMOS and a PMOS transistor. This subcircuit, which has become known as the composite
field effect transistor, or COMFET, serves to launch the investigation of linear transconductors.
4.1. THE COMFET
Figure (23) schematically defines the COMFET, which is little more than the series
interconnection of an N-channel MOSFET and a P-channel MOSFET
[7]
. In the interest of the
topological generality that proves expedient for subsequent discussions, a constant voltage, V
k
, is
inserted in series between the two source terminals of the transistors. This inserted voltage can
be zero, positive, or negative. Implicit to the optimal operation of the COMFET are the
presumptions of negligible bulk-induced threshold potential modulation and/or the feasibility of
returning the two bulk terminals to their respective source terminals.
V

k
I
I
V
ge
MP
MN

Fig. (23). The circuit topology of a composite
field effect transistor of COMFET.
The constant voltage, V
k
, which may
be zero for a particular application of
the cell, is inserted in series with the
source terminals of the two transistors
in the interest of analytical generality.
Let the N-channel device, MN, have a transconductance coefficient,
n
, and let the
counterpart metric for the P-channel unit, MP, be
p
. At low signal frequencies, for which gate
currents can be ignored tacitly, the indicated current, I, flows through the drains of both transis-
tors. Thus,
( ) ( )
2 2
n gsn hn p sgp hp
I V V V V , = = (77)
where V
gsn
is the gate-source voltage of transistor MN, V
sgp
is the voltage developed from the
source to the gate of transistor MP, and V
hn
and V
hp
respectively denote the threshold voltages of
MN and MP. Equation (77) presumes that both transistors operate in their saturation regimes.
Moreover, the neglect of channel length modulation phenomena in (77) implies either that chan-
nel length modulation is negligible or/and that each transistor operates near the crossover of their
triode and saturation regimes.
Equation (77) readily provides

EE 348 - 36 - April 2007
gsn hn n
sgp hp p
V V I
.
V V I
= +
= +
(78)
From the circuit in Figure (23), the voltage, V
ge
, developed between the gates of transistors MN
and MP follows as
( )
ge gsn k sgp hn hp k
n p
1 1
V V V V V V V I .

| |
|
= + = + + +
|
\ .
(79)
If V
he
is introduced as the effective threshold potential,
he hn hp k
V V V V , + (80)
and if an effective transconductance coefficient,
e
, is defined in accordance with the implicit
relationship,
n p
e n p n p

1 1 1
,

+
+ = (81)
(79) becomes expressible as
ge he e
V V I . = + (82)
The mathematical form of the last expression is identical to either of the two relationships pos-
tured by (78). It is therefore reasonable to suggest that the COMFET behaves as an effective
MOSFET, say ME, which emulates saturation regime operation in the sense that (82) implies
( )
2
e ge he
I V V . = (83)
Observe that the effective threshold potential, V
he
, of this artificial device can be zero or even
negative, depending on the value chosen for voltage V
k
.
MN M1
M3 M2
MP
I I I
k
I
V
ss
+V
dd
+
V
ge
I
k
V
k
+

Fig. (24). The realization of the biasing source, V
k
, depicted
in the basic COMFET pair of Figure (23).
The floating bias voltage, V
k
, inserted in the source terminal legs of the COMFET in Fig-
ure (23), can be realized as the gate-source voltage of an additional N-channel transistor that is
biased to operate in the saturation regime. To wit, the circuit shown in Figure (24) proves
reasonably effective. In this circuit, the COMFET consists of N-channel transistor MN and P-
channel device MP. The drain current, I, conducted by MN flows through the diode-connected

EE 348 - 37 - April 2007
P-channel device, M2, which forms a current mirror with identical transistor M3. This mirroring
allows MN and MP to conduct identical drain currents, which means that MN and MP are effec-
tively connected in series with one another, as required by the COMFET configuration. In view
of the constant current sink, I
k
, transistor M1 conducts a drain current of (I
k
I). If M1 operates
in saturation, its gate-source voltage, which is delineated as V
k
in the subject diagram, is
( )
k h1 k n1
V V I I , = + (84)
where V
h1
and
n1
are the threshold voltage and transconductance coefficient, respectively, of
transistor M1. Note that the source to gate voltage, V
k
, of M1 is connected from the source of
MN to the source of MP, as is stipulated in the basic COMFET diagram of Figure (23). The cir-
cuit at hand therefore realizes the biased COMFET of Figure (23), provided, of course, that V
k
is
held nominally constant by selecting current I
k
to ensure that I
k
>> I.
A shortfall of the proposal diagrammed in Figure (24) is that the floating voltage, V
k
, is
dependent on the current, I, conducted by the COMFET and is therefore somewhat modulated by
differential signals applied across the gates of the N-channel and P-channel units that comprise
the COMFET. In effect, the threshold potential of the COMFET is modulated by applied input
signal, which is reminiscent of the troublesome threshold voltage sensitivity to bulk-source sig-
nal swings in individual MOSFETs. The sensitivity of V
k
to input signal can be minimized by
choosing current sink I
k
sufficiently large, but for large input signals, the requisite value of I
k

may be prohibitively large.
M1a
M1b
M2a
M2b
I
k
I
k
I
k
I
k
V
1
V
1
V
b
V
2
V
a
V
a
V
2
V
b
+V
dd
+V
dd
V
k
V
k
(a). (b).

Fig. (25). (a).The realization of a signal invariant, constant floating voltage, V
k
. (b). System level
abstraction of the circuit in (a).
A proactive response to the foregoing shortfall is the circuit offered in Figure (25a). In
this circuit, two COMFETS, M1a-M1b and M2a-M2b, are deployed in a cross-coupled differen-
tial architecture to produce a signal invariant, constant floating voltage, V
k
. As is inferred by the
system level abstraction in Figure (25b), this constant voltage is manifested as the voltage differ-
ence, (V
1
V
b
), and the counterpart voltage difference, (V
2
V
a
). The indicated voltages, V
1
and
V
2
, contain common mode biasing components and are likely to project signal components as
well. Voltages V
a
and V
b
, which are made available to drive other subcircuits that are not explic-
itly shown in the subject figure, are similarly a superposition of static and signal voltage compo-
nents. The diode connection of the P-channel transistors is not necessary for the realization of

EE 348 - 38 - April 2007
the floating voltage, but such an interconnection facilitates the biasing of the circuitry that is ulti-
mately appended to the network at hand.
Since each of the two COMFETs in Figure (25a) conduct the indicated constant current,
I
k
,
( ) ( )
2 2
k e 1 b he e 2 a he
I V V V V V V , = = (85)
where V
he
and
e
are the usual effective threshold potential and transconductance, respectively, of
a COMFET. The result at hand leads immediately to
1 b 2 a k he k e
V V V V V V I , = + (86)
which reaffirms that the only current on which voltage V
k
is dependent is a constant current, I
k
.
Equation (86) underscores that fact that despite the presence of signal components in V
1
, V
2
, V
a
,
and V
b
, the difference voltages, (V
1
V
b
) and (V
2
V
a
), are each a constant determined and
controllable by the constant current sink, I
k
. A second fact highlighted by (86) is that the
differential voltages, (V
1
V
2
) and (V
b
V
a
), are identical; that is,
1 2 b a
V V V V . (87)
4.2. COMFET TRANSCONDUCTORS
The COMFET, with or without the floating voltage source inserted between the source
terminals of the N-channel and P-channel transistors, forms the basis of several circuit cells
boasting constant and controllable transconductances. Both single ended and differential
COMFET transconductors are possible, and all such configurations, when properly biased, nomi-
nally deliver an effective I/O transconductance that is linearly dependent on a control voltage or
current.
+
M1a
M2a
M1b
M2b
R
s
V
s
V
c
+V
c
+V
dd
V
ss
L
O
A
D
I
o
I
1
I
2
+
V
ge1
+
V
ge2
R
out

Fig. (26). Single ended COMFET transconductor. The volt-
age, V
c
, is a static potential used to control the effec-
tive I/O transconductance.
4.2.1. Single Ended COMFET Transconductor
The schematic diagram in Figure (26) depicts a single ended example of a COMFET
transconductor. Two COMFETs formed of the transistor pairs, M1a-M1b and M2a-M2b, are
utilized with their drain and source terminals in series, where M1a is presumed matched to M2a
and similarly, M1b and M2b are presumed matched. Static control voltages of +V
c
and V
c
are

EE 348 - 39 - April 2007
applied respectively to the gate of N-channel transistor M1a and the gate of P-channel transistor
M2b. On the other hand, the input signal, which is represented as the series interconnection of
Thvenin signal voltage V
s
and Thvenin resistance R
s
, is applied simultaneously to the gates of
P-channel transistor M1b and N-channel transistor M2a. The circuit output port to which the
load is incident is taken as the drain interconnection of transistors M1b and M2a. This port fea-
tures a reasonably high, small signal driving point resistance, R
out
, in that it is comprised of a
parallel interconnection of resistances seen looking into the drain terminals of transistors whose
sources are effectively terminated to ground in common gate stages. If g
mn
and r
on
respectively
symbolize the small signal forward transconductance and channel resistance of the N-channel
transistors and if g
mp
and r
op
are respectively the transconductance and channel resistance of the
P-channel units, it is easily demonstrated that this output resistance is
mp op
mn on
out on op op on
mp op mn on
1 g r
1 g r
R r r r r .
1 g r 1 g r
( | | + ( | | +
= + + ( |
( |
|
+ +
( ( \ . \ .
(88)
which is larger than the resistance value of the parallel combination of r
on
and r
op
.
Recalling (83) and (79), currents I
1
and I
2
in the diagram of Figure (26) are
( )
( )
2
1 e ge1 he
2
2 e ge2 he
I V V
,
I V V
=
=
(89)
where
ge1 c s
V V V = (90)
is the gate to gate voltage developed on the upper COMFET in the subject diagram, and
ge2 c s
V V V = + (91)
is the gate to gate voltage developed on the lower COMFET. The effective threshold voltage,
V
he
, is merely the sum of the threshold potentials of the N- and P-channel devices. Since the load
current, I
o
, established in response to the applied signal voltage is simply the current difference,
(I
2
I
1
), (89) yields
( )( )
o 2 1 e ge1 ge2 he ge2 ge1
I I I V V 2V V V . = = + (92)
Using (90) and (91), this result reduces to
( )
o 2 1 e c he s me s
I I I 4 V V V G V , = = (93)
which suggests an effective I/O transconductance, G
me
, of
( )
me e c he
G 4 V V . = (94)
To be sure, the actually observed output current response to input voltage excitation is not per-
fectly linear, as is suggested by (93), because of the numerous device modeling liberties implicit
to the foregoing analysis. But it is nonetheless notable that the linear dependence of output cur-
rent on input voltage postured by (93) is gleaned without recourse to small signal modeling of
the square law current expressions in (89). Moreover, the value of the effective I/O transconduc-
tance materializes as a function that is linearly dependent on the control voltage, V
c
. Since the
device threshold voltages, and thus voltage V
he
, increase with operating temperature, and the
transconductance parameter decreases with temperature owing to its functional dependence on
free carrier mobility, a control voltage implemented with a suitable temperature rate of rise can
conceivably stabilize the effective transconductance over temperature.

EE 348 - 40 - April 2007
4.2.2. Differential COMFET Transconductor
The most common form of a differential COMFET transconductor exploits the biased
COMFET cell of Figure (24) to arrive at the balanced topology depicted in Figure (27). An
inspection of the subject figure confirms that two biased COMFET cells, which are delineated
respectively as an a and a b appended to the device labeling, are exploited to forge a
differential topology. One proviso to this statement is that an additional transistor, M4a on the
left half of the differential circuit and M4b on the right half, is incorporated to realize load cur-
rents that mirror current I
a
in the left COMFET (MNa-MPa) and current I
b
conducted by the right
COMFET (MNb-MPb). Although the load in Figure (27) consists of two single ended resis-
tances, R, across which a differential output voltage, V
o
, is extracted, these load resistances can
be supplanted by constant current sinks across which any type of load impedance can be con-
nected differentially. Voltage V
c
is a static excitation that can be used to control the differential
transconductance, which is (I
a
I
b
)/(V
1
V
2
). Because only a single power supply is used in the
transconductor at hand, the applied input voltages, V
1
and V
2
, must contain a common mode bias-
ing component, V
cm
, that superimposes with the differential input signal, V
di
, in accordance with
MNa M1a
M
3
a
M2a
MPa
I
a
I I
k a
I
a
+V
dd
I
k
V
k
+
M4a
MNb M1b
M
3
b
M2b
MPb
I
b
I I
k b
I
b
I
k
V
k
+
M4b
I
a
I
b
R
+ V
o
V
1
V
2
R
V
c

Fig. (27). Balanced differential COMFET transconductor. Voltage V
c
serves to control the effective
transconductance that links the differential output current, (I
a
I
b
), to the differential input
voltage (V
1
V
2
).
di
1 cm
di
2 cm
V
V V
2
.
V
V V
2
= +
=
(95)
The determination of the effective forward transconductance, say G
me
, for the differential
cell in Figure (27) commences with the observation that the current, I
a
, which flows through the
single ended load resistance, R, in the left half of the circuit is conducted by the COMFET com-
prised of transistors MNa and MPa. Similarly, current I
b
, which flows through resistance R in
the right half of the network is mirrored as the current flowing through the MNb-MPb COMFET.
Noting that the gate to gate voltage developed across the MNa-MPa pair is (V
1
V
c
) and that the
counterpart gate to gate voltage for the MNb-MPb pair is (V
2
V
c
), (83) readily yields
( )
( )
2
a e 1 c he
2
b e 2 c he
I V V V
,
I V V V
=
=
(96)

EE 348 - 41 - April 2007
where V
he
, the effective COMFET threshold voltage given by (80), accounts for the floating volt-
age, V
k
, synthesized as the gate-source voltages of the presumably matched transistors, M1a and
M1b. The differential output current, (I
a
I
b
), to which the indicated differential output voltage,
V
o
, is directly proportional, follows as
( ) ( )
2 2
a b e 1 c he 2 c he
I I V V V V V V .
(
=
(

(96)
A modest amount of algebra and (95) reduce the last result to
( )
a b e cm c he di
I I 2 V V V V . = (97)
Equation (97) underscores the apparent linear dependence of the differential output current on
the differential input voltage. It also projects an effective I/O transconductance of
( )
me e cm c he
G 2 V V V , = (98)
which decreases linearly with increasing values of the control voltage, V
c
. Observe that for a
given common mode input voltage, V
cm
, a fixed control voltage, V
c
, and a known effective
threshold potential, V
he
, G
me
is independent of all active device currents and the power bus volt-
age, V
dd
, assuming, of course, that saturation regime operation of all transistors is sustained.
Naturally, the linearity caveat appended to the discussion of the single ended
transconductor of Figure (26) applies to the strictly linear expression in (97). But in addition,
there is a likelihood of limited dynamic range in the network of Figure (27), particularly when
small power bus voltages, which are mandated of analog chips realized in deep submicron
technologies, are used. The fundamental problem is the dependence of V
he
on floating voltage
V
k
. An inspection of the diagram in Figure (27) reveals that V
k
is constant if and only if the cur-
rent, I
k
, supplied by the constant current sinks is significantly larger than current I
a
and current I
b
.
M1a
M1b
M2a
M2b
I
k
I
k
V
1
V
a
V
2
+V
dd
M3a
M3b
M4a
M4b
V
b
R R
V
do
+
I
a
I
b
I
a
I
k
I
k
I
b

Fig. (28). Alternative to the balanced differential COMFET transconductor of Figure (27). The
effective transconductance from the differential input voltage, (V
1
V
2
), to the differen-
tial output current, (I
a
I
b
), is set and controlled by the constant current sinks, I
k
.
Figure (28) offers an alternative differential transconductor that mitigates the dynamic
range shortfall of the network in Figure (27) by circumventing the problems associated with a

EE 348 - 42 - April 2007
COMFET threshold voltage dependence on signal swing. The circuit appends two COMFETs,
respectively forged by transistors M3a-M3b and transistors M4a-M4b, to the constant floating
voltage cell depicted in Figure (25a). The applied input voltages, V
1
and V
2
, which subscribe to
(95), produce a differential output voltage response, V
do
, which, by virtue of the single ended
resistive loads, R, is directly proportional to the differential output current, (I
a
I
b
). Because the
circuit of Figure (25a) is embedded within the architecture at hand, equations (85) through (87)
remain applicable. If all four COMFETs are matched,
( )
( )
2
a e 1 a he
2
b e 2 b he
I V V V
,
I V V V
=
=
(99)
whence with the help of (86), (87), and Figure (25b), the differential output current is found to be
( )( )
a b e k he 1 2
I I 4 V V V V , = (100)
where V
k
is the voltage difference given by (86). Using (86) once again, as well as (95),
a b e k di me di
I I 4 I V G V , = (101)
which defines an effective differential I/O transconductance of
me e k
G 4 I . = (102)
Equation (102) confirms a transconductance that is independent of signal voltages and currents.
The subject transconductance is linearly proportional to the square root of the currents, I
k
, con-
ducted by the current sinks in Figure (28). Obviously, G
me
can be couched as proportional to a
control voltage, say V
c
, applied to the gate-source terminals of saturated MOSFETs configured to
realize the drain currents of I
k
.
4.3. NMOS TRANSCONDUCTOR
The realization of generic transconductance amplifiers is hardly a laudable accomplish-
ment in view of the fact that NMOS and PMOS transistors configured as common source
configurations naturally emulate voltage controlled current sources. But the realization of an
exclusively NMOS transconductor featuring constant and conveniently controllable I/O
transconductance is a challenge. A notable and reasonably popular example of such a realization
is the balanced architecture offered in Figure (29)
[8],[9]
. In this diagram, transistors M1, M2, M5,
and M6 are matched devices, as are transistors M3, M4, M7, and M8. The latter four transistors
need not be identical to the previously noted four transistors, and all transistors are biased to
operate in their saturation domains.
In the circuit at hand, input voltages V
1
and V
2
are applied to the gates of transistors M1
and M2, respectively, which comprise a balanced common source differential pair boasting high
common mode rejection ratio owing to the presumably large impedance of the current sink, I
k
.
The transconductance control voltage, V
c
, serves as a gate-source bias for transistors M7 and M8.
This control voltage establishes a constant drain current, I
cQ
, in M7 and M8, as well as in the
drains of transistors M3 and M4. If care is exercised to ensure that the drain-source voltages of
transistors M3 and M4 are at least approximately the same as the voltages developed from the
drain to the source of transistors M7 and M8, the gate-source voltages of M3 and M4 equal the
applied control voltage, V
c
. Accordingly, the voltage developed at the gate of transistor M5 is
voltage V
1
reduced by control voltage V
c
, and since V
c
is a constant, the signal component of
voltage V
1
is identical to that which drives the gate of transistor M5. Since voltage V
1
also ex-
cites the gate of M1, and in view of the balanced differential nature of the M1-M2 pair, transistor
M5 is effectively connected in shunt anti-phase shunt with M1. Similarly, the signal component

EE 348 - 43 - April 2007
of voltage V
2
appears at the gate of transistor M6, thereby effecting a shunt anti-phase shunt
interconnection with transistor M2. As the forthcoming analyses confirm, these interconnections
promote the realization of a constant and predictable I/O transconductance whose value is
directly proportional to the applied control voltage, V
c
.
M3
M8
M7
M5
M1
M4
M6
M2
I
k
V
k
R R
+ V
do
I
a
I
d1
I
d5
I
d6
I
cQ
I
cQ
I
cQ
I
cQ
I
b
I
d2
V
1
V
2
V
c
+V
dd

Fig. (29). Balanced differential transconductor using only N-channel transistors. All eight
transistors must be matched.
The first order analysis of the transconductor in Figure (29) begins with the observation
that because of the indicated drain interconnections of M1, M2, M5, and M6, the currents, I
a
and
I
b
, conducted by the single ended load resistances, R, are
a d1 d6
b d 2 d5
I I I
.
I I I
= +
= +
(103)
Using the simple square law model advanced by (4),
( )
( )
2
d1 n 1 k h
2
d6 n 2 c k h
I V V V
,
I V V V V
=
=
(104)
while
( )
( )
2
d 2 n 2 k h
2
d5 n 1 c k h
I V V V
,
I V V V V
=
=
(105)
where V
k
is the voltage appearing across the current sink, I
k
. The preceding two sets of equations
can be substituted into (103) to arrive at an expression for the differential current, (I
a
I
b
), to
which the indicated differential output voltage, V
do
, is directly proportional. After indulging

EE 348 - 44 - April 2007
annoying, but nonetheless straightforward, algebra, the result is the remarkably simple relation-
ship
( )
a b n c 1 2 me di
I I 2 V V V G V , = (106)
where V
di
represents the differential input signal, and
me n c
G 2 V = (107)
is the effective differential transconductance of the circuit. Observe that this transconductance is
directly proportional to the applied control voltage, V
c
.
At least two notable design observations can be proffered with respect to the circuit in
Figure (29) and its concomitant analysis. The first of these observations is that the applied con-
trol voltage, V
c
, manifests constant and equal, signal invariant drain currents, I
cQ
, in transistors
M3, M4, M7, and M8, despite the application of single ended signal voltages V
1
and V
2
to the
gates of M3 and M4. The proper operation of the circuit requires that equal gate-source voltages
between M3-M7 and M4-M8 be sustained for all operational environments. Such an egalitarian
condition presupposes that the drain-source voltages of M3 and M4 respectively equate to the
drain-source voltages developed on transistors M7 and M8. Under standby conditions, this
requirement sets the power bus voltage, V
dd
, to a level of 2(V
cm
V
c
), where V
cm
denotes the
common mode quiescent component of signals V
1
and V
2
. Unfortunately, V
c
changes at user
discretion or in accordance with the system application of the circuit. Moreover, omnipresent
channel length modulation and carrier mobility degradation compromise drain-source voltage,
and thus gate-source voltage, equality between M3-M7 and between M4-M8 under signal condi-
tions. These deleterious phenomena are skirted by relatively long channel lengths, which, to be
sure, degrade device response speeds. However, response speeds and bandwidths in M3, M4,
M7, and M8 are not a concern in that these devices conduct no signal currents. Accordingly,
deep submicron channel lengths in the aforementioned four transistors should be avoided to en-
sure that the gate-source voltages of transistors M3 and M4 nominally mirror the applied control
voltage, V
c
.
A second observation is that apart from establishing the desired linearity between I/O
transconductance and control voltage, the shunt anti-phase shunt interconnections of transistors
M1-M5 and M2-M6 serve to support wideband circuit performance. In particular, these connec-
tions neutralize most of the net gate-drain capacitances of transistors M1 and M2. This capaci-
tance cancellation is laudable when the loads, which are delineated herewith as simple passive
resistances, R, are supplanted by P-channel current sources, whose high impedances exacerbate
the problems associated with Miller multiplication of gate-drain capacitance
[10]
. To wit, note that
the gate of transistor M5 is driven by the same signal component that excites the gate of transis-
tor M1, since the gate-source voltage of M3 is a signal invariant constant that is, in fact, the con-
trol voltage, V
c
. Note further that the gate-drain capacitance of M5 is resultantly connected
effectively from the gate of M1 to a phase inverted drain of M1. Thus, the gate-drain capacitance
of transistor M1 is placed in shunt with the negative of the gate-drain capacitance of M5. But
these two capacitances, which derive largely from gate overlap with the drain implant, are nomi-
nally equal, especially since the quiescent drain-source voltages of M1 and M5 are identical un-
der balanced operational conditions. The immediate effect is a neutralized, or null effective
value, of the gate-drain capacitance of transistor M1. Similar arguments prevail with respect to
transistors M2 and M6.

EE 348 - 45 - April 2007
5.0. BIAS COMPENSATION MEASURES
The continuing down scaling of device feature sizes is necessarily accompanied by in-
creased uncertainties in device processing, particularly with respect to geometrical dimensions,
the profiles of device dopant concentrations, and many of the physical parameters (mobility,
permeability, diffusion lengths, Debye lengths, etc.) that influence attainable circuit perform-
ance. These uncertainties are exacerbated by the low breakdown voltages indigenous to deep
submicron technology devices, which translates to a need to bias circuits that exploit this
technology at low power bus voltages. In turn, low voltage biasing forces circuit designers to
implement monolithic circuits whose performance sensitivity to the key circuit level parameters
that are influenced by processing uncertainties is higher than levels deemed acceptable in earlier
generation designs. An additional design-oriented ambiguity derives from the device model
parameters traditionally supplied by processing foundries. The nature of the vast majority of the
parameters implicit to a device model file provided to the circuit designer are disappointingly
non-physical, largely because of empiricisms invoked to represent multidimensional, incom-
pletely understood, or otherwise complicated semiconductor device phenomena.
Device and even layout-related parametric uncertainties notwithstanding, the low voltage
circuits required of new generation communication and data processing circuits and systems
must nonetheless deliver reliable and predictable I/O performance. Appropriate circuit
compensation techniques, some of which can be implemented as tunable, standard cell, drop-in
structures for monolithic analog and mixed signal chips, are therefore implicitly to low voltage
design methodologies.
It is possible that some of the bias compensation requirements manifested by the forego-
ing technological shortfalls amount to little more than the implementation of appropriate nega-
tive feedback used to control such metrics as gain, I/O impedance levels, bandwidth, settling
times, and the like. Although prudently applied feedback enjoys laudable parametric desensitiza-
tion advantages, its utility in high performance low voltage circuits is somewhat guarded. A
notable limitation of feedback is its propensity toward poor closed loop transient responses or
even outright closed loop instability unless care is exercised to ensure an open loop characterized
by a dominant pole frequency response
[11]
. Unfortunately, open loop pole dominance often lim-
its the attainable closed loop bandwidth, and its realization may require circuit measures that
manifest increases in standby power dissipation. The potential instability issues surrounding
imprudent feedback are rendered especially daunting at high signal frequencies where extreme
parametric uncertainties and/or excessive input signal strengths force the active network
undergoing compensation to operate nonlinearly
[12]
.
In the subsections that follow, abridged discussions of a few innovative bias compensa-
tion schemes are presented. The topics to which attention is focused do not comprise an exhaus-
tive treatment of the type of compensation, or tuning, measures foreseen as essential to the
proper operation of low voltage circuits. Instead, they are offered to serve as a plausible founda-
tion for the development of more advanced tuning circuits, and they offer a glimpse as to the
kinds of compensation that can be realized currently.
5.1. COMMON MODE BIAS COMPENSATION
Any presumably balanced differential amplifier, such as the simple structure appearing in
Figure (30), is vulnerable to mismatched electrical characteristics between transistor and passive
component pairs. The immediate effect of the operational imbalance deriving from such mis-

EE 348 - 46 - April 2007
matches is deteriorated common mode rejection ratio, which in turn spawns potentially signifi-
cant bandwidth compression, reduced dynamic range, and several other performance drawbacks.
Because device mismatches are inevitable in deep submicron technologies, common mode
compensation aimed toward reproducibly attaining design goals in differential analog signal
processors is an inherent necessity in high performance integrated circuits
[13]-[16]
.
M1 M2
M3 M4
V
Q

V
B

V
do
V
di
2
2
V
Q
+
V
do
2
V
B
+
V
di
2
V
bias
V
dd
R
I

Fig. (30). Balanced differential amplifier using P-channel current
sources in the drain load circuits of the N-channel transis-
tors to achieve high voltage gain.
Voltage biasing problems are especially acute in differential amplifiers that exploit active
current source loads to achieve high open loop gain. The differential pair in Figure (30) drama-
tizes the biasing issue at hand. In this circuit, the small signal differential voltage gain, V
do
/V
di
, is
large because the effective load resistance imposed on each N-channel device is the parallel
combination of the relatively large drain-source channel resistances of the N-channel and P-
channel units. But since each drain node is the junction of a P-channel current source placed in
series with an N-channel transistor that behaves as a current sink under quiescent operating
conditions, the accurate and reproducible delineation of the quiescent value, V
Q
, of the common
mode voltages at the two output ports is virtually impossible. Indeed, if all transistors have infi-
nitely large channel resistances, voltage V
Q
is analytically indeterminate. Even if the P-channel
transistors are supplanted by passive resistances, V
Q
remains problematic because of active de-
vice and resistance mismatches.
5.1.1. Common Mode Feedback
Figure (30) provides a clue as to the engineering strategy for sustaining a design goal of a
static voltage, V
Q
, at the two single ended output ports of the balanced amplifier. For example,
suppose that the actually observed value, say V
Qx
, of this voltage is slightly larger than V
Q
. Then
an appropriate increase in the applied bias voltage, V
bias
, serves to return the observed quiescent
output voltage toward V
Q
since a positive perturbation of V
bias
manifests reduced drain to ground
voltage in all four transistors. Conversely, if the observed quiescent output voltages are smaller
than V
Q
, an appropriate decrease in V
bias
returns the aforementioned drain to ground voltages to
the desired value, V
Q
. Unfortunately, a manual adjustment of V
bias
is suitable only for the correc-
tion of the common mode output voltage at circuit startup, wherein V
bias
effectively serves to
calibrate the circuit in the face of processing uncertainties, device mismatches, and the like.

EE 348 - 47 - April 2007
An automated adjustment of voltage V
bias
is obviously called for if proper compensation
for the effects of processing uncertainties and device mismatches is to be coalesced with requi-
site in situ adjustments for the deleterious consequences of temperature variations, power bus
voltage changes, and the like. An incorporation of suitable automation invariably embodies a
feedback subcircuit that executes three operational tasks. The first of these tasks is to sense the
variable that is to be controlled and corrected. In the present case, this variable is the voltage
V
Qx
, developed at the drains of transistors M1 and M2. The second task compares this monitored
variable to its design goal value. In the case under present consideration, the design goal for the
aforementioned drain voltage is voltage V
Q
, whence a comparison embraces an evaluation of the
voltage difference, (V
Qx
V
Q
). The third and final task entails the realization of a circuit that
produces an output response that is nominally proportional to the difference between the moni-
tored and design goal values of the variable to be controlled. This output response must be
suitable for application to the network port to which manually applied excitation results in proper
control of the variable of interest. For the circuit in Figure (30), the subject response is to be
capable of supplanting the constant voltage, V
bias
, applied to the gates of transistors M3 and M4.
Accordingly, the subcircuit designed to drive the gates of M3 and M4 must generate a suitably
increasing voltage if V
Qx
> V
Q
and a decreasing voltage for V
Qx
< V
Q
.
To the foregoing end, consider the compensation scheme proposed in Figure (31)
[17]
. The
architecture at hand appends the matched transistor pairs, M5-M6 and M7-M8, to the differential
amplifier shown in Figure (30). In addition, two matched resistances of value R, which are con-
nected between the drain nodes of the original N-channel transistors, M1 and M2, comprise the
vehicle for sensing the static output voltage earmarked for control and compensation. The sens-
ing voltage, V
cm
= V
Qx
, is extracted at the common node to which the two resistances are inci-
dent. It is important to interject that resistance R must be significantly larger than the parallel
combination of the channel resistances indigenous to M1-M3 and M2-M4 if a degradation of the
differential gain exacted from the original version of the amplifier is to be avoided.
M5 M2 M6
M3
M4
M7 M8
V
Qx
V
B
V
bias
V
cm
+V
dd
R
I
V
Qx
M1
V
B
V
Q
R R
I
k

Fig. (31). An example of common mode biasing compensation, as applied to the balanced
differential amplifier in Figure (30). Because the compensation scheme addresses
static operating circumstances, only quiescent voltages are delineated in the diagram.
Voltage V
cm
is applied to the M6 gate of the appended differential pair comprised of
transistors M5 and M6. On the other hand, V
Q
, the desired quiescent value of the single ended
output voltages, activates the gate of M5. It follows that the M5-M6 amplifier is driven by the

EE 348 - 48 - April 2007
voltage difference, (V
cm
V
Q
) = (V
Qx
V
Q
), thereby accomplishing the requisite comparison be-
tween monitored and desired variable values. Transistors M7 and M8 accomplish differential to
single ended conversion, which is tantamount to perturbing the voltage at the drain of M5 by an
amount that is nominally proportional to the applied difference voltage, (V
Qx
V
Q
). This single
ended output voltage, which is returned to the gates of the P-channel transistors, M3-M4, in-
creases from its quiescent value when (V
Qx
V
Q
) is positive and decreases with respect to its
quiescent level when (V
Qx
V
Q
) is negative. In other words, the direction in which the M5 drain
voltage changes in response to the positive or negative voltage difference, (V
Qx
V
Q
), mirrors
that by which voltage V
bias
in the circuit of Figure (30) must change to offset increases or de-
creases in the static common mode output voltages of the M1-M2 differential pair.
5.1.2. Alternative Common Mode Feedback Compensation
The archival literature is rife with schema aimed toward controlling the static common
mode output voltages of balanced differential networks. A ubiquitously exploited example of
common mode feedback compensation is the Whatly circuit depicted in Figure (32)
[14]
. In this
network, the presumably balanced output ports whose static common mode voltages are to be
controlled are connected directly to the gates of transistors M1 and M2. In the subject figure, the
observed static common mode voltage is V
Qx
, while the differential signal developed across the
balanced output ports of the network to be compensated is V
do
. The desired common mode volt-
age, V
Q
, is applied as a reference voltage to the gates of transistors M3 and M4. Transistors M1
through M4 operate in saturation. The diode-connected transistor, M5, provides a current path to
ground for transistors M2 and M3, while transistor M6 returns the drain currents of M1 and M2 to
ground. The voltage, V
bias
, established across M5 feeds back to the differential amplifier in a
fashion that encourages the observed voltage difference, (V
Qx
V
Q
), to converge as closely as
possible to zero. For example, if the considered differential amplifier is the balanced M1-M2-R
I

architecture depicted in Figure (30), V
bias
can serve as the indicated control voltage applied to the
gates of transistors M3 and M4. Since the differential signal dynamics of the balanced amplifier
must be impervious to common mode feedback compensation, at least at lower signal frequen-
cies, it is important that V
bias
be exclusively a static voltage, independent of the output signal
voltage, V
do
, of the differential amplifier. Note that this stipulation presumes linearity in the
differential amplifier identified for compensation since quiescent operating point levels in
nonlinear networks are affected by the even ordered harmonics generated by the amplifier.
Transistors M1 through M4 are matched devices; M5 and M6 need not be matched to one another
or to any of transistors M1 through M4. Finally, the proper operation of the compensation net-
work relies on very high common mode rejection in both the M1-M3 and M2-M4 pairs, which
translates into requiring that the current sources, I
k
, be characterized by very high impedance.
In order to grasp an understanding of the operation of the compensator in Figure (32), as-
sume first that V
Qx
= V
Q
and a quiescent state wherein the differential signal voltage, V
do
, is zero.
Then since transistors M1 through M4 are matched devices, their drains conduct identical cur-
rents equal to I
k
/2; that is, I
d1
= I
d2
= I
d3
= I
d4
= I
k
/2. The drain current, I
d6
, which is conducted
by transistor M6, is the sum of drain currents I
d1
and I
d2
and thus, I
d6
= I
k
. Likewise, currents I
d3

and I
d4
sum to establish a drain current, I
d5
, in transistor M5 of I
d5
= I
k
, whence the particular
value of voltage V
bias
, say V
bias
= V
bo
, developed from drain to source of M5 is
bias bo h5 k n5
V V V I . = + (108)
In this expression, V
h5
denotes the threshold voltage of transistor M5, while
n5
represents the
effective transconductance parameter of M5. It is to be understood that voltage V
bo
is precisely

EE 348 - 49 - April 2007
the voltage that the common mode compensator must return to the controlled differential ampli-
fier if this amplifier is to establish a static common mode output voltage equal to the design goal
of V
Q
.
M1 M4 M3
M5
M2
I
k
I
k
V
Q
V +
Qx
V
do
2
V
Qx

V
do
2
V
bias
I
d1
I
d3
I
d4
I
d5
I
d2
+V
dd
M6
I
d6
V
bias2

Fig. (32). The Whatly common mode feedback compensation network. The desired static
common mode voltage is V
Q
, while its observed counterpart at the output port of the
controlled differential pair is V
Qx
. Transistors M1 through M4 are matched devices
operated in their saturated regimes.
Assume now that V
Qx
> V
Q
and that V
do
is a small, but nonzero, signal voltage. Since V
Qx

simultaneously drives the gates of P-channel transistors M1 and M2, V
Qx
> V
Q
reduces the quies-
cent value, I
k
/2, of the M1 drain current by an amount that can be denoted as I
k
/2. In light of
the constant current source, I
k
, the static M3 drain current must increase by the same amount.
Similarly, the quiescent drain current conducted by M2 reduces by I
k
/2, while the quiescent cur-
rent of M4 increases by I
k
/2. Analogous statements apply to the signal responses, say I
s
, of
these four drain currents when the differential signal voltage, V
do
, increases. Specifically, V
do
>
0 imposes an instantaneous positive signal voltage at the gate of M1, which serves to reduce the
instantaneous drain current of M1 by I
s
and increase the instantaneous M3 drain current by I
s
.
On the other hand, positive V
do
decreases the signal voltage applied to the gate of transistor M2,
which increases the signal component of the M2 drain current, while decreasing its counterpart
signal current in the drain of M3. The foregoing observations lead to
k k
d1 s
k k
d3 s
I I
I I
2
,
I I
I I
2
=
+
= +
(109)
and

EE 348 - 50 - April 2007
k k
d 2 s
k k
d4 s
I I
I I
2
.
I I
I I
2
= +
+
=
(110)
It follows that
d5 d3 d4 k k
I I I I I , = + = + (111)
which asserts that transistor M5 conducts no signal current. The voltage, V
bias
, developed across
M5 is likewise divorced of any signal components, which in turn implies that the feedback path
returning V
bias
to the original balanced differential pair exerts no impact on the differential output
signal voltage of the pair. Using the traditional square law volt-ampere characteristic of a
MOSFET operating in saturation, this voltage is seen to be
( )
bias h5 k k n5
V V I I , = + + (112)
and from (108),
k k
bias bo
n5 k
I I
V V 1 1 .
I
| |
= + +
|
|
\ .
(113)
The last result defines the voltage change with respect to its quiescent value, V
bo
, that the com-
mon mode compensator develops in response to the common mode voltage perturbation, (V
Qx

V
Q
), sensed at the controlled output port of a differential amplifier.
It should also be noted that the drain current of transistor M6 is, like that of M5, also
independent of signal-induced fluctuations in the drain currents of M1 through M4. In particular,
d6 d1 d 2 k k
I I I I I , = + = (114)
which produces a voltage, V
bias2
, across M6, assuming M6 and M5 are matched, of
k k
bias2 bo
n5 k
I I
V V 1 1 .
I
| |
= +
|
|
\ .
(115)
Thus, while V
bias
increases with progressive increases in the static common mode voltage, V
Qx
,
V
bias2
decreases with increasing V
Qx
.
5.2. ADAPTIVE BIASING
MOS technology amplifiers and transconductors using transistors in the I/O signal path
that are biased at low currents and low voltages suffer an inherent operating limitation. In
particular, while these configurations boast low power consumption under quiescent operating
conditions, they are incapable of operating linearly when called upon to deliver the large output
currents mandated by robust input signals. A plausible circumvention of this dilemma in
differential amplifiers is the implementation of so called adaptive biasing, wherein the biasing
currents flowing through the transistors embedded in the differential input stage are automati-
cally adjusted in response to applied differential signal swing
[18]-[20]
. In particular, adaptive bias-
ing boosts the input stage current when large differential input signals are applied, while remand-
ing these input stage currents to their quiescent design levels when small input signals prevail.
Of course, simple current mirroring can translate any boost of input stage currents to the output
stage of the considered network, thereby allowing for the possibility of sustaining an output re-
sponse that is a nominally linear function of the input signal level.

EE 348 - 51 - April 2007
5.2.1. Linearity Restrictions Of Differential Amplifiers
The practical need for adaptive biasing is easily established by examining the differential
transconductance of the simple balanced cell abstracted in Figure (33). In this diagram, I
k
is a
constant current sink serving as the tail current for the differential pair comprised of matched
transistors M1 and M2. The applied voltages, V
1
and V
2
, are given by (95), where it is noted that
the voltage difference, (V
1
V
2
), is the differential input signal, V
di
. In response to V
1
and V
2
,
currents I
1
and I
2
flow to forge a differential output current, I
do
, which is merely the current
difference, (I
1
I
2
). The differential transconductance, say g
md
, of the amplifier follows as
do 1 2
md
di 1 2
I I I
g .
V V V
(116)
M1 M2
I
k
I
1
I
2
V
1
V
2

Fig. (33). Simple balanced differential pair used to illus-
trate basic nonlinearity concepts with respect to
the differential current response, (I
1
I
2
), to
differential input voltage, (V
1
V
2
).
Assuming that the transistors at hand are biased in saturation and assuming that the sim-
ple square law volt-ampere characteristic applies to M1 and M2, (4) yields
gs1 h 1 n
gs2 h 2 n
V V I
,
V V I
= +
= +
(117)
where
n
and V
h
respectively denote the transconductance parameter and threshold voltage of
both transistors, V
gs1
is the gate-source voltage of transistor M1, and V
gs2
is the gate-source volt-
age of M2. The differential input voltage, V
di
, is obviously (V
gs1
V
gs2
) and thus,
1 2
di
n n
I I
V .

= (118)
Using the fact that currents I
1
and I
2
must sum to the tail current, I
k
, the last relationship gives
rise to
2 k 1 2
di
n
I 2 I I
V .
= (119)
Now, note that
( ) ( )
2 2 2 2
1 2 1 2 1 2
k do
I I I I I I 4I I . + = (120)
Upon combining the preceding two relationships, the differential output current, I
do
, is seen to
derive from the expression,

EE 348 - 52 - April 2007
2 2 4 2
n k n
do di di
I 2 I V V . = + (121)
Recalling (116), it follows that
2
n
do di
md n k
di k
V
I
g 2 I 1 .
V 2I
| |
|
=
|
\ .
(122)
Under quiescent conditions, each transistor of the differential pair conducts a current of I
k
/2.
Accordingly, the transconductance, g
mQ
, of each device at the quiescent operating point is,
returning to (4),
d k
d k
mQ n n k
gs n
I I 2
d I I
g 2 2 I .
dV 2
=
= = = (123)
Thus, (122) can be couched as the form,
2 2
n n
di di
md n k mQ
k k
V V
g 2 I 1 g 1 .
2I 2I
| |
|
= =
|
\ .
(124)
To the extent that the simple square law relationship is a suitable representation of the
volt-ampere characteristics of a MOSFET, (124) indicates that the differential transconductance,
g
md
, of a balanced amplifier is a constant equal to the transconductance of a transistor at its
operating point if and only if
2
k n
di
2I V . >> (125)
Since constant I/O transconductance is indicative of amplifier I/O linearity, (125) can be taken as
the necessary condition underlying nominally linear amplifier performance. Observe the relative
ease of satisfying (125) for small differential input signals. But for large input signals, the tail
current, I
k
, must be commensurately large, which naturally impinges negatively on the power
budget of the system in which the subject differential amplifier is embedded. The constraint
voiced by (125) is particularly troublesome when the differential inputs cycle between large and
small values. In such an event, the tail current must be chosen in accordance with the largest
anticipated differential input voltage, even though these large inputs may be observed for only a
small fraction of the input signal duty cycle. Adaptive biasing proves expeditious for this situa-
tion in that it allows I
k
to be increased as a function of increasing V
di
, thereby allowing a quies-
cent value of I
k
to be chosen in accordance with the anticipated smaller values of differential in-
put signals.
5.2.2. Adaptive Network
An examination of the functionality of adaptive biasing begins with a consideration of the
simple transconductor in Figure (34). The amplifier is shown driving a capacitive load, C
l
. In
view of the fact that this load capacitor faces relatively high output impedance, the circuit at
hand is suitable for use as an integrator, which is a fundamental building block of transconduc-
tor-based biquadratic filters
[21]
. The two input voltages, V
1
and V
2
, applied to the balanced pair
comprised of transistors M1 and M2 abide by (95), where V
di
represents the differential input sig-
nal applied from the gate terminal of transistor M1 to the gate terminal of M2. On the other
hand, V
cm
designates the common mode input voltage, which includes requisite gate biasing for
both of the input stage transistors. Thus, V
1
= V
2
= V
cm
under quiescent, or zero signal, condi-
tions. The M1-M2 pair drives P-channel diode-connected loads consisting of the matched

EE 348 - 53 - April 2007
transistors, M3 and M4. Observe that transistor M6 mirrors the current flowing through M4. If
the gate aspect ratio of transistor M6 is K-times that of transistor M4, the static current conducted
by both transistors M6 and M8 is KI
k
/2, where I
k
is the tail current conducted by the current sink-
ing transistor, M9. The static voltage, V
k
, is the M9 gate-source biasing that supports current I
k
.
Transistors M5 and M7 are respectively matched to M6 and M8 and are inserted to maintain bal-
anced quiescent operation. Note that like the relationship between transistors M6 and M4, the
gate aspect ratio of M5 is K-times larger than the gate aspect ratio of transistor M3.
M1 M2
M7 M8
M3 M6 M4 M5
V
1
V
2
V
o
I
1
M9 V
k
I
k
I
2
KI
2
KI
1
C
l
+V
dd
(K) (K) (1) (1)

Fig. (34). Simple transconductance amplifier terminated at its output port in a
load capacitance, C
l
. The gate aspect ratio of transistor M6 is K-times
that of M4, and the gate aspect ratio of M5 is K-times that of transistor
M3. In the quiescent state for which V
1
= V
2
= V
cm
, I
1
= I
2
= I
k
/2.
As suggested earlier, the objective of adaptive biasing applied to balanced differential
amplifiers is to increase the tail current, I
k
in Figure (33), in proportion to the applied differential
input voltage, V
di
. The foundation of such an adaptive subcircuit is the current differencing
scheme originally developed for bipolar technology abstracted in Figure (35)
[22]
. If the current
flowing into terminal 1 is I
1
, which might be a mirrored version of the drain current flowing into
transistor M1 in the differential amplifier of Figure (34), transistor Ma conducts a current of I
1
.
Since the Ma-Mb pair is a current mirror with identical gate aspect ratios, the drain current con-
ducted by transistor Mb is also I
1
. Now, if current I
2
, which is possibly a mirrored version of the
M2 drain current in Figure (34), flows into terminal 2, the drain of transistor Mc necessarily con-
ducts a current, (I
2
I
1
). It follows that the current flowing into terminal 3 is P(I
2
I
1
), since the
Mc-Md pair is a current mirror whose ratio of gate aspect ratios is P. Note that if I
1
= I
2
, the
gate-source voltage of Mc, and hence of Md, falls to its threshold level, thereby yielding no
current flowing into terminal 3. Moreover, if I
1
> I
2
, transistor Mc, which always operates in
saturation, is forced into cutoff since a saturated N-channel transistor cannot support a negative
drain current. Because of the current mirror topology formed by transistors Mc and Md, zero
current is resultantly conducted by transistor Md when I
1
> I
2
. Letting I
3
designate the current
flowing into terminal 3, the foregoing observations can be summarized as
( )
3 2 1 2 1
3 2 1
I P I I , I I
.
I 0, I I
=
=
>
s
(126)

EE 348 - 54 - April 2007
Mb Md Ma Mc
I
1
I
3
I
1
I
2
I
1
I I
2 1
P(I I )
2 1
1 2 3
(P)

Fig. (35). Current differencing network. The gate aspect ratios of
transistors M
a
, M
b
, and M
c
are identical, while the gate
aspect ratio of transistor M
d
is P-times larger than that
of M
a
, M
b
, or M
c
.
M6 M5
M9 V
k
I
k
M1 M2 V
1
V
2
I
1
I
2
I
2
I
1
M3 M4
M
1
0
M
1
1
M7 M15 M13
I
2
M17
P(I I )
2 1
M8 M14 M12 M16

P(I I )
1 2
I
1
I
2
I
1
(P) (P)
M19
(K)
KI
1
M21
V
o
C
l
+V
dd
M18
M20
(K)
KI
2
I
t
I
1
I
2
KI
1
K(I I )
2 1
A
d
a
p
t
i
v
e

C
e
l
l
A
c
t
i
v
a
t
e
s

F
o
r

I

>

I
1
2
A
d
a
p
t
i
v
e
C
e
l
l
A
c
t
i
v
a
t
e
s
F
o
r
I
>
I
2
1
Core Of Original
Differential Pair

Fig. (36). The transconductance amplifier of Figure (33) with adaptive biasing incorporated to allow
for signal dependent increases in the tail current, I
k
, of the differential input stage.
Figure (36) depicts the amplifier in Figure (34) with adaptive biasing incorporated. Two
adaptive kernels are used to allow tail current boosting for both positive and negative differential
input voltages, V
di
. These individual cells correspond respectively to I
1
> I
2
and I
1
< I
2
, where I
1

and I
2
are the signal dependent drain currents of transistors M1 and M2. Thus, when I
1
> I
2
,
transistor M14 conducts a current of P(I
1
I
2
), while transistors M15 and M17 are cutoff. On the
other hand, I
2
> I
1
forces M15 to conduct P(I
2
I
1
), while constraining transistors M14 and M16
to cutoff. Note that the current, I
1
, which activates the adaptive cell comprised of transistors M7,

EE 348 - 55 - April 2007
M13, M15, and M17 and is the current conducted by M1 in the differential input stage, derives
from the current mirror formed of transistors M3 and M11. The same current, I
1
, applied to the
M8-M12-M14-M16 adaptive cell is forged by the M3-M5 mirror. The current, I
2
, which is the
current conducted by M2 in the differential pair, is applied to the M8-M12-M14-M16 cell as the
current response to the M4-M10 mirror. The same current activating the other adaptive cell de-
rives from the M4-M6 mirror. Transistor M18, whose gate aspect ratio is K-times larger than that
of M4, M6, and M10, is inserted to source a current of KI
2
to the output port. Transistor M19 is
identical to M18. It preserves circuit balance while conducting a current of KI
1
. Observe that the
drain of transistor M19 drives a diode-connected transistor, M21. In turn, the gate of M21 is inci-
dent with the gate of transistor M20, which is identical to M21. Accordingly, the drain of M20
conducts KI
1
. In conjunction with the drain current, KI
2
, of transistor M18, this current renders a
current of K(I
2
I
1
) available to the load, which is this case is a simple capacitance, C
l
.
Clearly, the differential amplifier tail current, which is nominally I
k
and is set by applied
biasing, V
k
, is boosted by an amount of P(I
1
I
2
) when V
di
is sufficiently positive or by an
amount of P(I
2
I
1
) if V
di
is suitably negative. In other words, the effective tail current, I
t
, is
( )
( )
k 1 2 di
t
k 2 1 di
I P I I , for V 0
I .
I P I I , for V 0
+ >
=
+ <
(127)
The adaptive biasing network proposed herein remains a work in progress. One of the
shortfalls of the approach is that the amount by which the tail current of the subject differential
pair is enhanced is dependent on input signal. Accordingly, I
t
is no longer sustained as a con-
stant current but instead, it is a superposition of a constant current, I
k
, and a component depend-
ent on a time varying differential input voltage. This state of affairs contributes to the presence
of a small, but non-negligible second order harmonic in the overall differential current response.
A possible mitigation of this dilemma, which is currently undergoing exploration, is to enhance
the tail current by an amount proportional to the peak value of the applied differential input sig-
nal, as opposed to proportionality on instantaneous differential current. Another potential prob-
lem is the delay implicit to the current correction. This delay can increase distortion and even
generate stability problems. Both of these, as well as other less serious, problems, are rectifiable
and thus, the adaptive circuit can be postulated as a design scheme for improving amplifier effi-
ciency in the sense of reducing standby power dissipation. Of course, the adaptive network can
also result in improved network linearity, if the effective tail current can be maintained time
invariant.
6.0. REFERENCES
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[3]. D. A. J ohns and K. Martin, Analog Integrated Circuit Design. New York: J ohn Wiley & Sons,
Inc., 1997, pp. 256-259.
[4]. Q. A. Khan, S. J . Wadhwa, and K. Misri, Low Power Startup Circuits for Voltage and Current
Reference With Zero Steady State Current, Proc. 2003 ISLPED Conf., pp. 184-188, Aug. 25-
27, 2003.

EE 348 - 56 - April 2007
[5]. Y. Tsividis, Accurate Analysis of Temperature Effects in I
c
-V
be
Characteristics with Applica-
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[6]. P. Brokaw, A Simple Three-Terminal IC Bandgap Reference, IEEE J. of Solid-State Circuits,
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[7]. E. Seevinck and R. F. Wassenaar, A Versatile CMOS Linear Transconductor/Square-Law
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[8]. Z. Wang and W. Guggenbhl, A Voltage-Controllable Linear MOS Transconductor Using
Bias Offset Technique, IEEE J. of Solid-State Circuits, vol. 25, pp. 315-317, Feb. 1990.
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m
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th
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TECHNICAL REPORT

Principles and Examples of MOSFET

which is termed a channel length modulation

is best discerned through laboratory measurement or the careful interpretation of

is nominally proportional to the geomet-

, is appreciably smaller than values often

is exacerbated by the fact that parameter V

is not the constant that

as functionally dependent on drain-source

M8 M14 M12 M16

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