BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, PILANI INSTRUCTION DIVISION II SEMESTER, 2012-2013 Course Handout (Part -11) Date

: 07-01-2013 In addition to Part-I (General Handout for all courses appended to the time table) this portion gives further specific details regarding the course. Course No. Course Title Instructors 1. : MEL G642 : VLSI Architectures : S Gurunarayanan(P), Amalin Prince(G), V Srihari(H), Pawan Sharma(P)

Scope and Objective of the Course : The basic objective of the course is to familiarize the students with high performance computer architectures suitable for VLSI implementations. The course includes the details of the design of controller and datapath of single chip microprocessor with a typical processor as an example along with its addressing modes, instruction set etc. The course will also cover single cycle and multicycle and pipeline implementation RISC architectures and Application Specific Instruction Set processor.

2.

Text Books (1) Computer Organization and Design- The Hardware Software Interface : 4th Edition Author: John L. Hennessy & David A. Patterson Publisher: Elsevier- 2009 (2) Microprocessor Logic Design: Flowchart Method Author: Nick Tredenick Publisher: Digital Press, 1987.

3.

Reference Books (1) Digital Design and Synthesis with Verilog HDL. Author: Eli Sternheim, Rajvir Singh, Rajeev Madhavan and Yatin Trivedi Publisher: Automata Publishing Co., San Jose, CA. (2) Computer Organization and Architecture Designing for Performance, Fourth Edition Author: William Stallings Publisher: Prentice-Hall, 1997. (3) VLSI Digital Signal Processors Author: Vijay K. Madisetti Publisher: Butterworth-Beinemann/IEEE Press, 1995. (4) DSP Integrated Circuits J L.Wanhammar Publisher: Academic Press, 1999.

4.

Course Plan: S.No. Topic 1. 2. 3. VLSI System and Architectures: An Overview Instruction set overview & Addressing modes and instruction format of a CISC Processor Implementation strategies for CISC instruction set: Block level architecture for non-pipelined implementation RT-Ievel design, its capture via hardware flow charts. Block level architecture for a fetch-decode-execute pipelined implementation. No. of Lectures 1 1

1 1

Techniques for optimisation of the Control unit using hardware flow-charting. Techniques for optimisation of the data path using hardware flowcharting. Implementation of Instruction Decoder, Data Path Control Sequencer, Bus Controller and Exception Handling.

2 3 3 3

RISC Architecture (MIPS/ARM Example)

6.

8. 8. 9.

Micro architecture Introduction to Data path and Control Single-Cycle Processor Multi-Cycle Processor Pipelined Processor Introduction to advanced Micro architectures Instruction level parallelism and Super-scalar processors. Memory hierarchy. Architectures for Programmable DSPs Basic DSP Architecture and Performance Requirements Introduction to ASIP Design Flow A simple DSP processor Design Instruction Set and Operations DSP ASIP Instruction Set Design Designing RISC Based Instructions Designing CISC Based Instructions Design of Datapath Controller and memory Subsystem

8 3 3
4

10

Total No. of Lectures

40

5. Assignments: Assignments will be given to students during the course from time to time. These will include some design assignments to be implemented in the VLSI laboratory, report submission on some latest topics on design issues of different architectures. 6. Evaluation Schedule: Components Duration Weightage Test I CB Test II CB Assignments/ Lab test 50 min 50 min 15 15 Date 22/02/2012 05/04/2013 Time Venue Remarks CB CB 11-11.50AM Teleprecence room 11-11.50AM Teleprecence room

30 40

Comprehensive 3 hrs.

To be announced (TBA) 12/05/2013

AN

TBA

OB/CB

7. Chamber Consultation Hour: Will be announced in the class. 8. Notices: Notices will be put up in EEE Department Notice Boards of respective campuses ONLY. Instructor-in-charge