SIDDAGANGA INSTITUTE OF TECHNOLOGY, TUMKUR

(AN AUTONOMOUS INSTITUTION UNDER VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELGAUM)

Project Seminar on

Analysis of Ultra Low Power Fully Programmable Frequency Divider

Under the guidance Mr. B. Sudarshan, Associate professor Department of E&C SIT, Tumkur
M.E.,

By: Ajay Kumar Ananda T Anaji Apoorva prakash Navaneeth B H 1SI09EC005 1SI09EC011 1SI09EC118 1SI09EC024

DEPARTMENT OF ELECTRONICS AND COMMUNICATION 2012-13

OUTLINE
Introduction Pulse swallow frequency divider Different Prescaler architectures Delay and power consumption Fully programmable divider Conclusion References

OBJECTIVE
Focuses on reducing the power consumption and increasing the operating frequency

To choose suitable Prescaler architecture for specific application

MOTIVATION
The Prescaler is one of the most critical blocks in synthesizer since, it operates at highest frequency and consumes large amount of power. The power reduction in the first stage of the Prescaler is important in realizing a low power frequency synthesizer.

DIFFERENT PRESCALERS
TSPC E-TSPC Conventional TSPC 2/3 prescaler Design-I 2/3 prescaler Design-II 2/3 prescaler TSPC 32/33 and 47/48 prescaler Fully programmable Divider: 32/33 prescaler Fully Programmable Divider: 47/48 prescaler
5

PULSE SWALLOW FREQUENCY DIVIDER

Figure : courtesy : [1]

6

PULSE SWALLOW FREQUENCY DIVIDER (CONTD..)

Prescaler is an electronic counting machine used to reduce a high frequency electrical signal to lower frequency by integer division Operates at highest frequencies and consumes more power

THEORY OF OPERATION
Prescaler divides the input frequency by N+1 or N based on the modulus control Program counter and Swallow counter divides the output by a fixed value of P and S respectively Start from the reset, prescaler divides by N+1 until swallow counter is full After (N+1)S pulses at the input, the modulus control changes to N and continues to count until P counter is full. Total pulses = (N+1)S + N(P-S) = NP+S
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HOW TO REDUCE THE POWER

CONSUMPTION

By decreasing the size of the transistors By reducing the number of switching gates By blocking the power supply to one of the D flip flop during divide-by-2 operation

CURRENT-MODE LOGIC DIVIDERS

Very sensitive to input amplitude Requires buffers or level shifters at the output

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DYNAMIC LOGIC DIVIDERS

The CMOS latches eliminates the static current consumption and use fewer transistors than the CML latches. The switching speed of the static circuits depends on two factors namely; Current conduction level through a MOS transistor Parasitic capacitances
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SYNCHRONOUS 2/3 PRESCALER

Figure : courtesy : [1
12

TSPC

Hold Mode: Clk=0, M2=ON M4=ON M7=OFF & M8=OFF S1 charges S2 Charges to VDD Floating O/P

Evaluation Mode: Clk=1, M2=OFF M5 =ON & M6=ON S2 discharges through M5 & M6
13

Figure : courtesy : [1

RESULTS >>

EXTENDED TSPC (E-TSPC)

14

Figure : courtesy : [1]

RESULTS >>

SHORT CIRCUIT POWER IN E-TSPC

15

POWER CONSUMPTION OF TSPC AND E-TSPC

Power consumption of TSPC and E-TSPC flip-flop (mW)
1.4

1.175
1.2 1

0.8

0.6

0.4

0.2

0.0647
16
TSPC E-TSPC

PROPAGATION SPEED COMPARISON

The output load capacitance of E-TSPC is lower than that of TSPC. The charging time constant of E-TSPC is smaller than TSPC. The propagation delay of TSPC stage is higher than that of the E-TSPC stage. This implies that TSPC flip-flop has a lower operating frequency compared to that of the E-TSPC flip-flop.
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POWER CONSUMPTION ANALYSIS

Total power consumption of a digital circuit is given by

(3)

Switching power depends on fclk and CL Short circuit power is due to conduction of current directly from the supply to ground. Leakage power due to leakage current which is technology dependent.
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POWER CONSUMPTION ANALYSIS(CONTD..)

TSPC circuits cause more switching power than E-TSPC circuits. Switching power can be reduced by optimization techniques such as reducing the number of switching stages and the width of the transistors. In TSPC circuits, one of the transistors in each stage is always off, there exists NO short-circuit power. Large short-circuit power and considerable amount of switching power makes the E-TSPC logic less suitable of low power applications compared to TSPC.
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CONVENTIONAL TSPC 2/3 PRESCALER

Figure : courtesy : [1]

Due to the large load on DFF2 and difficulty to embed the OR, AND gates into the DFF which introduces additional delay and the speed of conventional 2/3 prescaler. Also causes more power dissipation.
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CONVENTIONAL TSPC 2/3 PRESCALER(CONTD..)

The maximum operating frequency of the conventional 2/3 prescaler is limited due to the logic OR and logic AND gates. The conventional TSPC 2/3 prescaler has 12 stages and each stage has a switching output node. The switching power is given by

(4)

21

RESULTS >>

TSPC 2/3 PRESCALER: DESIGN-I

Figure : courtesy : [1]

22

DIVIDE-BY-2 OPERATION
When MC= 1, transistor M10 turns-on and node S3 switches to logic 0 irrespective of the data at node S2.

23

DIVIDE-BY-3 OPERATION
When MC= 0 , transistor M10 turns-off and the inverted data at node S2 is passed to the node S3.

24

Figure : courtesy : [1]

PROPAGATION DELAY OF THE 2/3 PRESCALER

The total propagation delay in divide-by-2 mode of operation is equal to the propagation delay of DFF2.

In divide-by-3 mode of operation, since both DFF1 and DFF2 are active, the propagation delay is equal to the sum of propagation delay of embedded NOR gate DFF1 and DFF2 respectively
25

SWITCHING POWER OF DESIGN-I

The switching power saved by Design-I prescaler is almost 42% and its speed is improved by 1.3 times

26

SHORT-CIRCUIT POWER OF THE DESIGN-I 2/3 PRESCALER

During the divide-by-2 mode when control logic signal MC = 1, the transistor M10 turns-on, allowing a direct path from supply to ground when transistor M7 turns-on.

The power consumption of the prescaler is given by the sum of switching power in DFF1 and DFF2, short circuit power in 3rd stage of DFF1 and short circuit power in DFF2.
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RESULTS >>

TSPC 2/3 PRESCALER: DESIGN-II

Figure : courtesy : [1]

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DESIGN II(CONTD..)
An extra PMOS transistor M1a is connected between the power supply and DFF1 whose input is the controlled by the logic signal MC. DFF1 contributes to the power consumption due to the continuous switching at the nodes S1 and S2 respectively.

29

DESIGN II-DIVIDE-BY-2 OPERATION

Figure : courtesy : [1]

30

DESIGN-II TSPC 2/3 PRESCALER: DIVIDE-BY2 OPERATION

31

POWER SAVING ANALYSIS IN DIVIDE-BY-2

OPERATION

32

POWER ANALYSIS(CONTD..)

33

POWER ANALYSIS(CONTD..)

RESULTS >>

POWER CONSUMPTION COMPARISON

Power consumption (mW)

2.655

1.421 1.213 1.141

0.7331 0.631

Conv. E-TSPC

Conv. TSPC

Design-I

Design-II

Divide by 32

Divide by 47

35

POWER CONSUMPTION COMPARISON

Power consumption (mW)

2.541

1.138 0.8951 0.893

1.046

1.141

Conv. E-TSPC

Conv. TSPC

Design-I

Design-II

Divide by 33

Divide by 48

36

DESIGN AND ANALYSIS OF TSPC 32/33 (N/N+1) PRESCALER

To verify the advantages of the proposed ultralow power prescaler of Design-II, a divide 32/33 dual modulus unit is implemented with the 2/3 prescaler of Design-II

37

TSPC 32/33 PRESCALER USING DESIGN-II 2/3 PRESCALER

In this 32/33 prescaler, the proposed 2/3 prescaler unit is followed by four stages of the toggled TSPC divide-by-2 units

38

Figure : courtesy : [1]

RESULTS >>

TSPC 47/48 PRESCALER USING DESIGN-II

Figure : courtesy : [1]

39

RESULTS >>

FULLY PROGRAMMABLE FREQUENCY DIVIDER-I

Fig.1 Programmable frequency divider

Figure : courtesy : [4]

40

7-BIT PROGRAMMABLE P-COUNTER

41

Figure : courtesy : [4]

END OF COUNT (EOC)

Fig.3 EOC of p-count

Figure : courtesy : [4]

The EOC logic circuit is used to detect when the P-counter reaches the state Q1Q2Q3Q4Q5Q6Q7=0000000 The output of EOC logic circuit goes low P-counter is loaded with the 42 preset value.

RELOADABLE TSPC DFF FOR P-COUNTER

Fig.2 Reloadable DFF

The signals LD and LDB are used to reload the programmable state of the FF. When (PI) of the each FF is loaded with a value and LD signal goes low, the P-counter begins to count down. FF remains in the divide-by-2 mode until the counter reaches the 43 state 0000010.

RELOADABLE TSPC DFF FOR S-COUNTER

When SP goes high, the S-counter remains idle for a period of N*(P-S) clock cycles.
44

5-BIT PROGRAMMABLE S-COUNTER

45

Figure : courtesy : [4]

END OF COUNT (EOC)

46

FULLY PROGRAMMABLE FREQUENCY DIVIDER-II

Figure : courtesy : [4]

47

6-BIT PROGRAMMABLE S-COUNTER

48

Figure : courtesy : [4]

6-BIT PROGRAMMABLE P-COUNTER

49

Figure : courtesy : [4]

CONCLUSION
Design II 2/3 prescaler is capable of operating upto 4.5GHz and the amount of power saved is 60% and 45% in divide-by-2 and divide-by-3 respectively, compared to conventional 2/3 prescaler. Fully programmable divider consumes a power of 0.934mW at 1.8v and the duty cycle of the output is 1MHz signal is close to 47%.

50

REFERENCES
[1] M.Vamshi Krishna et.al, Design and Analysis of Ultra-Low Power True-Single-Phase Clock CMOS 2/3 Prescaler, IEEE Trans. On Circuits and Systems-I: Reg. Papers, Vol.57, no.1, pp. 7282, Jan. 2010. [2] John P. Uyemura, CMOS Logic Circuit Design, Springer edition 2001. [3] X. P. Yu, M. A. Do, W. M. Lim, K. S. Yeo, and J. G. Ma, Design and optimization of the extended true single-phase clock-based prescaler, IEEE Trans. Microw. Theory Tech., vol. 54, no. 11, Nov. 2006. S. Pellerano, M.Vamshi Krishna, C. Samori, and A. L. Lacaita, A Low Power Fully Programmable 1MHz Resolution 2.4GHz CMOS51 PLL Frequency Synthesizer IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 378383, Feb. 2004.

THANK YOU

TSPC SCHEMATIC

53

WAVEFORM OF TSPC

54

DELAY AND POWER CONSUMPTION OF TSPC FLIP-FLOP

Parameters Operating voltage (V) Max. operating freq.(MHz) Output frequency (MHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (uW) With parasitics 1.8 2.5 1.25 37 88 62.5 64.71 Without parasitics 1.8 2.5 1.25 27 73 50 45.93

55

LAYOUT OF TSPC

56

CIRCUIT INVENTORY OF TSPC FLIP-FLOP

LIBRARY analogLib analogLib gpdk180 gpdk180 CELL Pcapacitor Presistor nmos pmos VIEW Symbol symbol ivpcell ivpcell TOTAL 142 47 5 4

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WAVEFORM OF E-TSPC FLIP-FLOP

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DELAY AND POWER CONSUMPTION OF ETSPC FLIP-FLOP

Parameters Operating voltage (V) Max. operating freq.(MHz) Output frequency (MHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (mW) With parasitics 1.8 2.5 1.25 50 20 35 1.175 Without parasitics 1.8 2.5 1.25 40 15 27.5 1.173
59

LAYOUT OF E-TSPC

60

CIRCUIT INVENTORY OF E-TSPC

LIBRARY analogLib analogLib gpdk180 gpdk180

CELL Pcapacitor Presistor nmos pmos

VIEW symbol symbol ivpcell ivpcell

TOTAL 121 37 3 3

61

CONVENTIONAL TSPC 2/3

PRESCALER SCHEMATIC

62

WAVEFORMS OF CONVENTIONAL TSPC 2/3 PRESCALER IN DIVIDE BY-2 MODE

63

LAYOUT OF CONVENTIONAL TSPC 2/3 PRESCALER IN DIVIDE BY-2 MODE

64

WAVEFORMS OF CONVENTIONAL TSPC 2/3 PRESCALER IN DIVIDE BY-3 MODE

65

LAYOUT OF CONVENTIONAL TSPC 2/3 PRESCALER IN DIVIDE BY-3 MODE

66

DELAY AND POWER CONSUMPTION OF CONVENTIONAL TSPC

Parameters Divide By 2 mode With parasitics 1.8 2.5 Divide by 2 mode Without parasitics 1.8 2.5 Divide by 3 mode With parasitics 1.8 2.5 Divide by 3 mode Without parasitics 1.8 2.5

Operating voltage (V) Max. operating freq.(GHz) Output frequency (GHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (mW)

1.25

1.25

0.833

0.833

41 58 49.5 1.421

30 34 32 0.978

45 66 55.5 1.433

30 35 32.5 1.138
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CIRCUIT INVENTORY OF CONVENTIONAL TSPC

Divide by 2 mode TOTAL 626 216 18 16 Divide by 3 mode TOTAL 615 218 18 16

LIBRARY analogLib analogLib gpdk180 gpdk180

CELL Pcapacitor Presistor nmos pmos

VIEW symbol symbol ivpcell ivpcell

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DESIGN-I 2/3 PRESCALER SCHEMATIC

69

WAVEFORM OF DESIGN-I PRESCALER IN DIVIDE-BY-2 MODE

70

LAYOUT OF BY-2 MODE

DESIGN-I PRESCALER IN DIVIDE-

71

WAVEFORMS OF DESIGN-I PRESCALER IN DIVIDE-BY-3 MODE

72

LAYOUT OF DIVIDE-BY-3 OPERATION OF DESIGN-I 2/3 PRESCALER

73

DELAY AND POWER CONSUMPTION OF DESIGN-I PRESCALER

Parameters Divide By 2 mode With parasitics 1.8 4.5 Divide by 2 mode Without parasitics 1.8 4.5 Divide by 3 mode With parasitics 1.8 4.5 Divide by 3 mode Without parasitics 1.8 4.5

Operating voltage (V) Max. operating freq.(GHz) Output frequency (GHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (mW)

2.25

2.25

1.5

1.5

49 69 59 1.412

48 69 58.5 1.213

34 45 39.5 1.341

28 32 30 0.8951
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DESIGN-II 2/3 PRESCALER SCHEMATIC

75

WAVEFORMS OF DESIGN-II 2/3 PRESCALER IN DIVIDE-BY-2 MODE

76

LAYOUT OF DESIGN-II 2/3 PRESCALER IN DIVIDE-BY-2 MODE

77

WAVEFORMS OF DESIGN-II 2/3 PRESCALER IN DIVIDE-BY-3 MODE

78

LAYOUT OF DESIGN-II 2/3 PRESCALER IN DIVIDE-BY-3 MODE

79

C
Parameters Divide By 2 mode With parasitics 1.8 4.5 Divide by 2 mode Without parasitics 1.8 4.5 Divide by 3 mode With parasitics 1.8 4.5 Divide by 3 mode Without parasitics 1.8 4.5

Operating voltage (V) Max. operating freq.(GHz) Output frequency (GHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (mW)

2.25

2.25

1.5

1.5

49 69 59 1.412

48 69 58.5 1.213

34 45 39.5 1.341

28 32 30 0.8951
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DIVIDE-BY-32 SCHEMATIC

81

WAVEFORMS OF TSPC 32/33 PRESCALER IN DIVIDE-BY-32 MODE

82

LAYOUT OF TSPC 32/33 PRESCALER IN DIVIDE-BY-32 MODE

83

DIVIDE-BY-33 SCHEMATIC

84

WAVEFORMS OF TSPC 32/33 PRESCALER IN DIVIDE-BY-33 MODE

85

LAYOUT OF TSPC 32/33 PRESCALER IN DIVIDEBY-33 MODE

86

WAVEFORMS OF TSPC 47/48 PRESCALER IN DIVIDE-BY-47 MODE

87

LAYOUT OF TSPC 47/48 PRESCALER IN DIVIDEBY-47 MODE

88

WAVEFORMS OF TSPC 47/48 PRESCALER IN DIVIDE-BY-48 MODE

89

LAYOUT OF TSPC 47/48 PRESCALER IN DIVIDE-BY-48 MODE

90

DELAY AND POWER CONSUMPTION

Parameters Operating voltage (V) Max. operating freq.(GHz) Output frequency (GHz) tpHL(ps) tpLH (ps) tp (ps) Power consumption (mW) Divide By 32 mode 1.8 2.5 Divide by 33 Divide by 47 Divide by 48 mode mode mode 1.8 2.5 1.8 2.5 1.8 2.5

0.078

0.075

0.053

0.052

160 110 135 733.1

150 130 140 1.046

240 140 190 1.141

230 130 180 1.141

91

POWER CONSUMPTION COMPARISON

Power consumption (mW)

2.655

1.421 1.213 1.141

0.7331 0.631

Conv. E-TSPC

Conv. TSPC

Design-I

Design-II

Divide by 32

Divide by 47

92

POWER CONSUMPTION COMPARISON

Power consumption (mW)

2.541

1.138 0.8951 0.893

1.046

1.141

Conv. E-TSPC

Conv. TSPC

Design-I

Design-II

Divide by 33

Divide by 48

93