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Hng dn thc hnh vi Microblaze

Thc hnh vi Microblaze iu khin LCD dng EDK 10.1: Trong ti liu ny chng ti gii thiu cch iu khin LCD trn dng board c chp h tr Microblaze. Interface giao tip vi LCD l ngoi vi GPIO. Cc iu kin v thi gian khi iu khin LCD s c x l bi ngoi vi Timer (c hai ngoi vi GPIO v Timer u l cc IP c tch hp sn trong EDK). Chng trnh c chc nng chnh l xa mn hnh LCD, Hin th k t ln LCD v di chuyn con tr mn hnh. Cc bc tin hnh xy dng chng trnh: 1. To mt project t EDK:

2. Chn loi board, hng v revision board m bn ang s dng, bn c th chn custom board nu board ca bn khng c trong mc Board name.

3. Chn processor l Microblaze. 4. Chn tn s, dung lng BRAM v ty chn Debug ph hp vi board bn ang dng:

5. Mc chn IO Interface ch chn RS232_DCE.

6. Chn RS232_DCE cho c STDIN v STDOUT, b chn Memory test.

7. Sau khi to xong project, add IP GPIO cho LCD.

8. Kt ni instance GPIO ti PLB bus:

9. Double click vo instance xps_gpio_0 v chn Data Channel With l 7.

8. Chn tab Ports v g vo LCD_IO cho mc net name ca GPIO_IO.

9. Sau chn li External Ports cho GPIO_IO.

10. Chuyn sang tab Addresses chn 32K cho xps_gpio_0 v click vo Generate Addresses

11. Thm IP XPS Timer vo project, cng kt ni instance xps_timer_0 ti PLB bus trong tab Bus Interfaces, chn dung lng b nh l 32K v to a ch b nh cho instance ny trong tab Addresses.

12. Gn chn LCD cho bus xps_gpio_0 trong file system.ucf :

Thm ni dung constraints sau vo file system.ucf :


#### Module LCD_IO constraints #### Module LCD_IO constraints # LCD_FPGA_DB4 Net LCD_IO_pin<6> Net LCD_IO_pin<6> # LCD_FPGA_DB5 Net LCD_IO_pin<5> Net LCD_IO_pin<5> # LCD_FPGA_DB6 Net LCD_IO_pin<4> Net LCD_IO_pin<4> # LCD_FPGA_DB7 Net LCD_IO_pin<3> Net LCD_IO_pin<3> # LCD_FPGA_RW Net LCD_IO_pin<2> Net LCD_IO_pin<2> # LCD_FPGA_RS Net LCD_IO_pin<1> Net LCD_IO_pin<1> # LCD_FPGA_E Net LCD_IO_pin<0> Net LCD_IO_pin<0> LOC = R15; IOSTANDARD=LVCMOS33; LOC = R16; IOSTANDARD=LVCMOS33; LOC = P17; IOSTANDARD=LVCMOS33; LOC = M15; IOSTANDARD=LVCMOS33; LOC = L17; IOSTANDARD=LVCMOS33; LOC = L18; IOSTANDARD=LVCMOS33; LOC = M18; IOSTANDARD=LVCMOS33;

13. Chn mc Application chnh sa li ni dung file TestApp_Peripheral.c nh sau: click here 14. To file Linker Script:

15. Vo Hardware chn Generate Bitstream EDK bin dch project. Sau chn Download Bitstream load chng trnh xung con FPGA. Ch : Cc bn c th tham kho cc hm th vin trong EDK cng nh cc v d mu trong th mc ci t: EDK\sw\XilinxProcessorIPLib\driver. Ti liu tham kho 1. www.fpgadeveloper.com 2. www.xilinx.com