VHDL (VHSIC hardware description language)

VHDL is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate

arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language. VHDL was originally developed at the behest of the U.S Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment. The idea of being able to simulate this documentation was so obviously attractive that logic simulators were developed that could read the VHDL files. The next step was the development of logic synthesis tools that read the VHDL, and output a definition of the physical implementation of the circuit. The initial version of VHDL, designed to IEEE standard 1076-1987, included a wide range of data types, including numerical (integer and real), logical

(bit and boolean), character and time,plusarrays of bit called bit_vector and of character called string. A problem not solved by this edition, however, was "multi-valued logic", where a signal's drive strength (none, weak or strong) and unknown values are also considered. This required IEEE standard 1164, which defined the 9-value logic types:

scalar std_logic and its vector version std_logic_vector. In addition to IEEE standard 1164, several child standards were introduced to extend functionality of the language. IEEE standard 1076.2 added better handling of real and complex data types. IEEE standard 1076.3 introduced signed and unsigned types to facilitate arithmetical operations on vectors. IEEE standard 1076.1 (known as VHDLAMS) provided analog and mixed-signal circuit design extensions.

VHDL is commonly used to write text models that describe a logic circuit. Such a model is processed by a synthesis program, only if it is part of the logic design. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called a testbench. Advantages The key advantage of VHDL, when used for systems design, is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires). Another benefit is that VHDL allows the description of a concurrent system. VHDL is a dataflow language, unlike procedural computing languages such as BASIC, C, and assembly code, which all run sequentially, one instruction at a time. A VHDL project is multipurpose. Being created once, a calculation block can be used in many other projects. However, many formational and functional block parameters can be tuned (capacity parameters, memory size, element base, block composition and interconnection structure). A VHDL project is portable. Being created for one element base, a computing device project can be ported on another element base, for example VLSI with various technologies.

Disadvantages The abstractions used for modeling digital circuits in VHDL have different semantics than actual hardware, so it does not work well below the RTL abstraction. Specifically it has no built-in type that supports bidirectional components like "pass gates" sometimes used in MOS, and there is no (easy) way to describe such behavior in user code. The signal abstraction also fails to

separate strength, value and certainty which makes it inefficient when not using standard library types. The analog support (aka VHDL-A) is not integrated as well as Verilog-AMS, so a lot of work is left in the users' hands. The failure to implement inheritance means you have to type a lot of extra code. e.g. component and entity declarations often contain the same information, so inheriting one from the other would be useful. Likewise the strong typing destroys polymorphism and means you end up with multiple copies of the same structural code just to get wire types to match.