Bo co lab 3 MIPS Single-Cycle CPU

A. Mc ch: Thit k CPU MIPS Single- Cycle 32 bit n gin c th thc hin cc lnh LW, SW, J, JR, BNE, XORI, ADD, SUB, SLT. B. Thit k : I. Datapath : 1. Phn loi cc lnh : C nhiu cch phn loi lnh, nhng y khi thit k cc lnh LW, SW, J, JR, BNE, XORI, ADD, SUB, SLT chng ta s phn loi nh sau : - lnh memory-reference : LW, SW - lnh arithmetic-reference : SUB, ADD, XORI,SLT - lnh r nhnh : BNE, J, JR 2. Cc thnh phn ca MIPS CPU : Instruction Memory : l ni lu gi cc lnh ca chng trnh, mi lnh c mt a ch ring.

PC Counter (PC) : cha gi tr a ch ca lnh hin thi.

Adder : dng tng gi tr ca thanh ghi PC, ch n lnh tip theo c a ch l PC+4.

Register File (RF ) :- bao gm 32 thanh ghi. - ng vo Read register1, Read register 2 dng xc nh a ch ca thanh ghi m chng ta mun c d liu, ng ra Read data1, Read data2 cha ni dung ca thanh ghi m Read register1, Readregister2 ch n. - khi tn hiu RegWrite =1 qu trnh ghi d liu vo Register File s c thc hin, ng vo Write register dng xc nh a ch m chng ta mun ghi d liu vo, Write data cha gi tr mi ghi vo Register File. D liu mi s c ghi vo khi c tn hiu clock.

 ALU : dng thc hin cc php ton.

ALU CONTROL LINES 00 01 10 11

FUNCTION Add XOR Sub SLT

i vi cc lnh thuc nhm lnh arthmetic- logic s dng khi ALU thc hin cc php tnh. Lnh memory reference s dng khi tnh ton a ch. Lnh BNE s dng khi ny so snh. Lnh J,JR khng s dng khi ny. Data Memory : - l ni lu tr d liu. - khi tn hiu MemWrite=1 th d liu mi s c ghi vo. - khi tn hiu MemWrite=0 th khi ny c d liu, trong qu trnh c d liu khi ny phn ng theo combination logic.

Sign extension: - dng m rng du. - d liu vo 16 bit s c m rng thnh 32 bit, du m rng ph thuc vo bit th 16 ca d liu a vo.

Shift left 2 : dng nhn d liu vi 4.

 MUX : dng la chn mt ng vo trong nhiu ng vo.

Datapath ca MIPS CPU: Tng qut vic thc thi lnh l - ly lnh - gii m lnh - thc hin lnh Cc lnh khc nhau c chung cc bc ly lnh v gii m lnh. Chng ta s dng thanh ghi PC (cha a ch ca cu lnh hin thi ) ly lnh t Instruction memory v sau tng PC thnh PC+4 ch n lnh tip theo. Tip theo cu lnh s c a n khi Control Unit v Register File gii m cu lnh, xc nh thanh ghi no cn s dng, mc ch ca cu lnh l thc hin nhim v g.

3.

Cc bc tip theo ca qu trnh thc thi lnh ph thuc vo cc cu trc ca tng lnh. Chng ta s xem xt cc khun dng lnh thit k cc datapath cho tng lnh sao cho ph hp. a. Datapath ca cc lnh arthmetic- reference : ADD, SUB,SLT : Cc lnh ny thuc khun dng lnh R-type :

Cc ton hng ca cc php ton l cc gi tr cha trong cc thanh ghi c a ch nm trong trng rs,rt. Trng op v func cho bit chnh xc chng ta phi thc hin php ton no. Kt qu tnh ton c s c lu vo thanh ghi trong Register File c a ch nm trong trng rd.

 XORI : Lnh ny thuc dng I- type :

Lnh ny thc hin php ton XOR gia mt gi tr c cha trong thanh ghi( thanh ghi ny c a ch cha trong trng rs ) vi mt gi tr hng. Gi tr hng ny cha trong cu lnh l 16bit nhng n s c m rng thnh gi tr 32 bit. Kt qu ca php ton s c lu vo thanh ghi trong Register File, thanh ghi ny c a ch nm trong trng rt.

b. Datapath ca cc lnh memory reference : Cc lnh LW v SW thuc khun dng lnh I-type. Trong khun dng lnh I-type trng address 16bit tng ng vi offset v trng rs tng ng vi base register trong cu ln LW, SW. i vi lnh LW th trng rt l a ch n v i vi lnh SW th trng ny l ngun. LW : Cc offset 16 bit s c m rng du thnh 32 bit. Khi ALU c s dng tnh tng gia offset c m rng vi gi tr ch trong thanh ghi m base register ch n. Kt qu ca php tnh ny c xem l a ch ca v tr nh trong Data memory. Gi tr ca nh ny s c ghi li vo trong Register File, vo thanh ghi c a ch nm trong trng rt.

 SW : Cc offset 16 bit s c m rng du thnh 32 bit. Khi ALU c s dng tnh tng gia offset c m rng vi gi tr ch trong thanh ghi m base register ch n. Kt qu ca php tnh ny c xem l a ch ca v tr nh trong Data memory. Gi tr trong thanh ghi c a chi nm trong trng rs s c ghi vo v tr nh ny.

c. Datapath ca lnh nhy : BNE: Lnh ny thuc khun dng lnh I-type. Gi tr ca thanh ghi c a ch nm trong trng rs,rt s c so snh vi nhau. Nu hai gi tr ny khng bng nhau thi nhy n a ch c gi tr address (32 bit) + PC+4. Trng address 16 bit s c m rng thnh 32 bit. PC= PC+4 + Sign_ext (Imm16)<<2;

 J: Lnh ny thuc khun dng lnh J-type : op (6 bit ) 2 target (26 bit) target (26 bit)

PC={PC[31:28], target, 00}

JR: Lnh ny c khun dng nh sau : op (6 bit ) rs (5 bit ) 0 (15 bit ) 8

PC= Reg{rs}

Sau khi thit k datapath cho tng lnh ring, chng ta ghp chng li c c datapath ca MIPS CPU nh sau :

II. Control Unit : Cc tn hiu iu khin v ngha ca chng :

Signal name RegDst RegWrite ALUSrc PCSrc MemWrite MemtoReg Jump JumpReg

Effect when deasserted The register destination number for the Write register comes from the rt field ( bits 20: 16 ) None The second ALU operand comes from the second register file output ( Read data 2 ) The PC is replaced by the output of the adder that computes the value of the PC+4 None The value fed to the register Write data input comes from the ALU The PC is replaced by the output of the mux that has the PCSrc signal controlling The PC is replaced by the output of the mux that has the Jump signal controlling

Effect when asserted The register destination number for the Write register comes from the rd field ( bits 15:11 ) The register on the Write register input is the written with the value on the Write data input The signe second on the Write operand is the signextended, lower 16 bits of the instruction The PC is replaced by the output of the adder that computes the branch target Data memory contents designated by the address input are replaced by the value on the Write data input The value fed to the register Write data input comes from the data memory The PC is replaced by the jump target The PC is replaced by the adder that jumpreg target

Cc tn hiu iu khin i vi cc lnh:

RegDest 1 0 X X 0 X X

ALUSrc MemtoReg RegWrite MemWrite Branch

0 1 1 0 1 X X 0 1 X X 0 X X 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 X X

Jump
0 0 0 0 0 1 X

JumpReg ALUOp
0 0 0 0 0 0 1 10 00 00 01 11 XX XX

R- type LW SW BNE XORI J JR

Ghp tn hiu iu khin vo s datapath trn ta c hnh v nh sau:

C. Code Verilog : module mips(input clk, reset, output [31:0] pc, instr, readdata1, readdata2, ALUresult, readdata, writedata1, output zero, carryout, overfow, negative); mips_cpu mc(clk, reset, instr, memwrite, zero, carryout, overfow, negative, ALUresult, writedata1, readdata1, readdata2, readdata, pc); InstructionMem im(instr, pc); endmodule module mips_cpu ( input clk, reset, input [31:0] instr, output memwrite, zero, carryout, overflow, negative, output [31:0] ALUresult, writedata1, readdata1, readdata2, readdata, pc);

wire regdst, ALUsrc, memtoreg, regwrite, pcsrc, jump,jumpreg; wire [1:0] alucontrol; mips_control mc(instr[31:26], instr[5:0], zero, regdst, ALUsrc, memtoreg, regwrite, memwrite, pcsrc, jump, jumpreg,alucontrol); mips_datapath md(clk, reset, regdst, ALUsrc, memtoreg, regwrite, pcsrc, jump, memwrite,jumpreg, alucontrol, instr, readdata, ALUresult, writedata1, readdata1, readdata2, pc, zero, carryout, overflow, negative); endmodule module mips_control( input [5:0] op, funct,

input zero, output regdst, ALUsrc, memtoreg, regwrite, memwrite, pcsrc, jump, jumpreg, output reg [1:0] alucontrol); wire [1:0] aluop; wire zero1, branch; reg [8:0] control; assign {regdst, ALUsrc, memtoreg, regwrite, memwrite, branch, jump,jumpreg, aluop} = control; always @(*) case(op) 6'b000000: begin if (funct<= 6'b001000) control<=10'bxxx00xx1xx ; // JR else control <= 10'b1001000010; //Rtype end 6'b100011: control <= 10'b0111000000; //LW 6'b101011: control <= 10'bx1x0100000; //SW 6'b000101: control <= 10'bx0x0010001; //BNE 6'b001110: control <= 10'b0101000011; //XORI 6'b000010: control <= 10'bxxx00x10xx; //J default: control <= 10'bxxxxxxxxxx; //??? endcase always @(*) case(aluop) 2'b00: alucontrol <= 2'b00; // LW, SW (ADD) 2'b01: alucontrol <= 2'b10; // BNE (SUB) 2'b11: alucontrol <= 2'b01; //XORI (XOR) default: case(funct) // RTYPE 6'b100000: alucontrol <= 2'b00; // ADD 6'b100010: alucontrol <= 2'b10; // SUB 6'b100110: alucontrol <= 2'b01; // XOR 6'b101010: alucontrol <= 2'b11; // SLT default: alucontrol <= 2'bxx; // ??? endcase endcase assign zero1 = ~zero; assign pcsrc = branch & zero1; endmodule module mips_datapath (input clk, reset, regdst, ALUsrc, memtoreg, regwrite, pcsrc, jump, memwrite,jumpreg, input [1:0] alucontrol, input [31:0] instr, inout [31:0] readdata, output [31:0] ALUresult, writedata1, readdata1, readdata2, pc, output zero, carryout, overflow, negative); wire [4:0] writereg;

wire [31:0] pcnext, pcnextbr, pcplus4, pcbranch,pcnext1; wire [31:0] srcdata, signextend1, shiftleft21; adder signextend shiftleft2 adder mux32 mux32 mux32 mips_pc regfile clk); mux5 mux32 dataMem alu alucontrol); mux32 endmodule module mux3(instr[20:16], instr[15:11], regdst, writereg); mux4(readdata2, signextend1, ALUsrc, srcdata); dm(readdata, ALUresult, readdata2, memwrite, clk); alu(ALUresult, carryout, zero, overflow, negative, readdata1, srcdata, mux5(ALUresult, readdata, memtoreg, writedata1); ad1(pc, 32'b100, pcplus4); se(instr[15:0], signextend1); sl2(signextend1,shiftleft21); ad2(pcplus4, shiftleft21, pcbranch); mux1(pcplus4, pcbranch, pcsrc, pcnextbr); mux2(pcnextbr, {pcplus4[31:28], instr[25:0], 2'b00}, jump, pcnext1); mux6(pcnext1,readdata1,jumpreg,pcnext); pcreg(clk, reset, pcnext, pc); rf(readdata1, readdata2, writedata1, instr[25:21], instr[20:16], writereg, regwrite,

adder(input [31:0] a, b, output [31:0] y);

assign y = a + b; endmodule module shiftleft2(input output [31:0] a, [31:0] y);

assign y = {a[29:0], 2'b00}; endmodule module signextend(input [15:0] a, output [31:0] y);