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HNG DN S DNG PHN MM EDK 10.

1i
Gii thiu : Trong chng trnh o to, chc hn th no cc bn cng c hc mn Vi X L v th nghim vi x l, v cc bn lm quen vi vic lp trnh 89C51 bng ngn ng Assembly dnh cho h 8051.Tuy nhin, bn cnh cc bn cng c th lp trnh cho h 8051 bng ngn ng C (c th l Keil C), ti liu c th c cun THIT K H THNG VI H 8051 ca thy Tng Vn On. V ngn ng C l ngn ng cp cao nn vic lp trnh cho 8051 d dng hn so vi s dng ngn ng Assembly. Vic vit chng trnh ri vo 89C51c gi l nhng v h thng to ra c gi l h thng nhng. Tuy nhin, 8051 c hn ch l b nh nh(c trong ln ngoi), nn y, mnh xin gii thiu mt h thng nhng hon ton (khng c sn Vi u khin), vi iu khin v chng trnh iu khin y cng s c nhng vo trong mt FPGA( Field Programable Gate Array). V mt trong nhng chng trnh thng dng c s dng hin nay l chng trnh EDK (Embedded Design /Development Kit) c vit bi hng Xilinx v s dng FPGA ca hng Xilinx. Ti liu ny s hng dn cc bn s dng phn mm EDK 7.1i ,l version 2005 ca hng Xilinx. Chng trnh EDK 10.1i l mt chng trnh thn thin vi ngi s dng, gip chng ta c th d dng thit k mt h thng phc tp m ch thao tc n gin, v thc cht, EDK s dng cc chng trnh VHDL vit sn (gi l cc IP) nn ta khng cn vit cc IP , m ch s dng n, phn quan trng l chng ta phi vit phn mm iu khin chip nhng c vit sn , v iu ny cng thc s khng phi l kh khn v chng ta khng cn s dng tp lnh Asembly ca chip nhng (c t tn l MicroBlaze) m chng ta s s dng ngn ng Standard C hay C++ vit chng trnh iu khin icroBlaze (tng ng vi mt vi x l 32 bit, i vi version 4.0 cn c thm FPU/n v x l du chm ng) v cc th vin h tr sn vi cc hniu khin ngoi vi rt nhiu) Sau y xin i vo chi tit hng dn s dng, xin lu , file ny s i km theo file hng dn hnh nh Lu :chng trnh EDK 10.1i ch c th chy c khi cc bn ci phn mm Xilinx ISE 10.1 CC BC TO MT PROJECT : Bc 1: to h thng phn cng c bn trong XPS (Xilinx Platform Studio): khi cc bn cho chy chng trnh EDK th mt ca s xut hin gi l ca s XPS, chng ta s bt u to Project y, mn hnh khi ng chng trnh nh sau :

Trong hp thoiu tin xut hin, cho php chng ta thao tc c bn : - Base System Builder Wizard :hp thoi ny s cho php chng ta tao mt Project mi - Open A Recent Project : m mt Project c sn y s bt uvibcto mt Project mi: nhn Ok khi hp chn Base System , hp thoi tip theo s hin ra:

hp thoi ny, phn mm s yu cu t tn cho th mc cha Project v cc th mc lin quan, nhn Browse v to mt th mc vi mt ng dn c th, y,

chng ta s t tn cho th mc l vidu, lu nhn Open 2 ln, chng trnh s t ng to ra file system.xmp trong th mc chng ta va to :

Nhn OK i n bc tip theo, bc ny chng ta s to mt h thng vi s h tr sn ca phn mm.

Nhn Next i n bc tip theo:

bc ny s cho php chng ta to xy dng mt h thng da trn cc Kit h tr sn ca Xilinx hoc chng ta s to ra mt h thng ring da trn cc h tr c sn ca phm mm : - I would like to creat a system for the following development Board: to h thng da trn cc Kit Development ca Xilinx, v d nh AFX Virtex II Pro fg456 Proto Board , Spartan 3_Starter Board -I would like to creat a system for a custom Board: to mt board ring vi cc phn cng v ngoi vic h tr trong phn mm, Lu y ch l chng trnh chy trn Kit Development ch khng phi chng trnh np trc tip to sn phn chuyn dng.

y chng ta s to ra h thng m c h tr sn, m c th l s dng Kit Spartan 3-Starter, ta chon nh sau :

Hnh trn l mt trn v di vi cc ngoi vi ca KIT Spartan_3 Starter. Phn ny cc bn tham kho qua File: ug130.pdf trong trang web xilinx.com.

Chng ta cng c th s dng Kit Development khc nu c( v d Kit Virtex II Pro). Nhn Next qua bc tip theo.

Kit Spartan 3 Starter vi cc thng s c sn phn trn, cn phn di trong chn MicroBlaze hoc Power PC th ch c th chn MicroBlaze v n l mt vi x l mm, tc l n cng c nhng vo FPGA trn Kit, cn Power PC l chip cng , tc l chip ny c sn trn Kit (Vd Virtex II Pro hay Virtex IV), do vy, chng ta s khng tn ti nguyn trn FPGA khi s dng Power PC (nu dng cc Kit trn m s dng MicroBlaze th s tn thm ti nguyn trn FPGA), ngha l i vi cc Kit c h tr Power PC ta ch cn nhng phn mm iu khin m khng cn nhng vi x l. Do vy i vi cc thit k ln hoc cn vit thm cc ngoi vi th chng ta mi s dng Power PC, cn bnh thng chng ta s dng MicroBlaze v tnh linhng ca n. Nhn Next qua bc tip theo.

hp thoi ny cho php chng ta chn tn s (vi iu lin l Kit phi h tr nhiu tn s, nu khng chng ta c mc nh), v chn kch thc BRAM (Block RAM: lRAM trong chip, tc cao v do chip qun l trc tip), kch thc ny ty thuc vo s lng cng ca FPGA c s dng, i vi Spartan 3 c s dng trong Kit Spartan 3 Starter th kch thc ti a ca BRAM l 16KB. Phn debug th c mc nh v phn lin qua n tp lnh Debug m y khng cp, nu bn no c nhu cu tm hiu v phn Debug ny th xin hy tm ti liu. Nhn Next bc tip theo.

u tin l cng truyn bt ng b UART, giao thc truyn ca n c h tr sn v gi l OPB UARTLITE, thng th chng ta dng n giao thip vi my tnh hay bt k thit b no s dng cng truyn bt ng b, tc truyn chng ta c th l chn c, vn lu l khng nn chn qu ln ,v mt lnh x l ca C tng ng vi nhiu chu k my, m xung cung cp l 50MHz (c th cao hn i vi cc Board khc hay chng ta c mch to daong gn thm) hn na thng th chng ta truyn lng data rt ln nn nu cc bn chn tc cao th d gy hiu nhm mc dn n truyn sai d liu, y xin chn tc l 38600b bps, chng ta cng c th chn s bit cho data truyn i, ti a l 32 bit , v chn truyn bit Parity (kim tra li) hoc khng, cc bn nh tc truyn v cc phn chn sau ny giao tip vi my tnh hoc cc cc thit b m chng ta mun giao tip vi h thng chng ta va to ra. Phn tip l LED_8 bit, LED 7 on c gi tn l XPS GPIO, cng c h tr s dng 8 LED n v LED 7 on trn Kit, DataSheet i km, cc bn c th tham kho tm hiu cc thng s. Trong thit k v d ny, ta chn c cng RS232 v LED_8 bit trong hp thoi u tin ny, khng chn LED 7 on. Nhn Next chn cc ngoi vi khc :

hp thoi ny cho php chn ngoi vi l 4 nt nhn trn kit, thc cht 4 nt nhn ny chng ta ch c s dng 3 nt nhn, v chng trnh s dng nt User Reset hay Button 3 lm nt khi ng ngi dng, nt ny khc vi nt Reset h thng (RESET), khi nhn nt ny, chng trnh s c thc thi li t u mt ln na, cn nt reset h thng s RESET ton b h thng li, trong chng trnh ny s khng s dng 2 ngoi vi ny (nh du khng chn vo cc tng ng). Tip theo chng ta l ty chn cc DIP switch v SRAM (8 nt trt trn Board): trong thit k ny s khng s dng DIP Switch , nhng s dng SRAM v y l thit b lu tr ngoi c kch thc ln (1 MB), dng lu tr d liu rt tt, mt k Read/Write ca n tng ng t 5->7 chu k lnh. Nhn Next 2 ln hon thnh vic thit k ban u. Bc tip theo s cho chng ta chn thit b IN/OUT hay khng, v c to ra chng trnh chy th test_Memory_Application hay khng, chng ta mc nh bc ny, ngha l thit b IN/OUT ca chng ta l RS232 v cho php to ra File Test chng trnh, file test ny chng ta s chnh sa li ty ,y l chng trnh s iu khin Chip nhng MicroBlaze.

Nhn Next n bc tip theo, bc ny s cho php chng ta t chng trnh, d liu v vng stack trong BRAM hoc SRAM.

Nhn Next v phn ny chng ta s chnh sa sau. Chng trnh s hin hp thoi hon tt thit k, hp thoi ny cc bn s thy hin ln mt s cc thng s ca cc ngoi vi va chn, bn c th quay ngc li chnh sa hoc nhn Generate hon tt thit k:

Mt hp thoi thng bo cc bc thit k thnh cng, nhn Finish hon thnh.

Sau khi hon chnh cc tt c cc bc trn,mn hnh XPS hin ra nh sau :

trn cng l cc thanh cng c vi cc cng c h tr nh dch ra chi bit, np vo Kit, m phng bn tri mn hnh l ca s qun l project v qun l ng dng, IP catalog. ca s bn phi, trong Tab System Assembly View bn c th chnh sa li thit k, nu mun chnh sa, b sung hay b bt ngoi vi, cc bn nhn chut phi vo CPU-microblaze_0, s c cc th Tab hin ra tng ng. Mc Add/ Edit Core cho php chng ta thm bt, chnh sa phn cng: ngoi vi a ch, Port, thng s: Nu mun thm phn no, ta chn Tab IP catalog bn ca s tri, chn IP, nhn Add IP. Mun bt ta chn phn cn bt bn ca s phi trong Tab System Assembly View v nhn chut phi, chn Delete Instance. Tuy nhin nu khng c ngoi vi tng ng th chng ta s khng la chn chnh sa. Hn na, a ch v cc Port l do h thng quy nh, c trong bng datasheet tng ng vi mi Kit, nn nu khng cn thit th ta khng chnh sa phn ny. Tng ng vi Platform Setting cng vy,trong hp thoi ny ch c phn nn quan tm l cc th vin b sung, nu mun s dng cc bn nn tm hiu cc tp lnh ca cc th vin ny : V d th vin xilmfs dng qun l th mc v tp tin Tuy nhin cc th vin ny cng khng cn thit, v cc th vin lin quan n h thng chng ta to ra th phn mm t ng to ra cho chng ta, ngoi ra cn h

tr thm th vin chun ca C nn nu khng c nhu cu th khng nn thm vo cc th vin ny. Tab Application, ng dng m chng ta to ra dc t ng nh du chn khi dch chng trnh, th chng trnh ny s l chng trnh iu khin ca chng ta. phn ny c hai phn rt quan trng m chng ta cn ch la file Linker_Script thuc tab Complier Option, v file TestApp_Memery.c thuc tab Source: File Linker_Script: File Linker Script s cho php chng ta t chng trnh ,d liu v vng Stack vo cc b nh c th c ca h thng, mc nh chng trnh s chn BRAM a vo, tuy nhin, nu chng ta mun x l d liu chng hn th kch thc ca BRAM l qu nh cha d liu, khi ta cn mt b nh khc a d liu vo, v File Linker_Script ny s cho php chng ta lm iu , lu v Kit Spartan 3 Starter ch c SRAM nn chng ta ch c th d liu trong vng BRAM hoc SRAM, nu cc bn mun t vng no vo SRAM, th cui phn , cc bn s chn ilmb_cntlr hoc SRAM_256Kx32_C_MEM0_BASEADDR
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400; /* Define all the memory regions in the system */ MEMORY {SRAM_256Kx32_C_MEM0_BASEADDR : ORIGIN = 0x20100000, LENGTH = 0x000FFFFF ilmb_cntlr : ORIGIN = 0x00000000, LENGTH = 0x1fff } /* Specify the default entry point to the program */ ENTRY(_start) /* Define the sections, and where they are mapped in memory */ SECTIONS { .text : { _ftext = .; *(.text) *(.text.*) *(.gnu.linkonce.t*) _etext = .; } > ilmb_cntlr .rodata : _frodata = *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) _erodata = .; } > ilmb_cntlr

{ .;

/* Alignments by 8 to ensure that _SDA2_BASE_ on a word boundary */ .sdata2 : { .=ALIGN(8); _sdata2_start = .; *(.sdata2) .=ALIGN(8); _sdata2_end = .; } > ilmb_cntlr _sdata2_size = _sdata2_end - _sdata2_start; PROVIDE (_SDA2_BASE_ = _sdata2_start + (_sdata2_size / 2 )); .data : { . = ALIGN(4); _fdata = .; a = 0x1000; *(.data) *(.data.*) *(.gnu.linkonce.d*) _edata = .; } > SRAM_256Kx32_C_MEM0_BASEADDR .eh_frame : { *(.eh_frame) } > ilmb_cntlr /* Alignments by 8 to ensure that _SDA_BASE_ on a word boundary */ /* Note that .sdata and .sbss must be contiguous */ .sdata : { . = ALIGN(8); _ssro = .; *(.sdata) } > ilmb_cntlr .sbss : { . = ALIGN(4); PROVIDE (__sbss_start = .); *(.sbss) EME-ST09 www2.hcmut.edu.vn/~vkchau/ . = ALIGN(8); _essro = .; } > ilmb_cntlr PROVIDE (__sbss_end = _essro); _ssro_size = _essro - _ssro; PROVIDE (_SDA_BASE_ = _ssro + (_ssro_size / 2 )); .bss : { . = ALIGN(4); PROVIDE (__bss_start = .); *(.bss) *(COMMON) . = ALIGN(4); PROVIDE (__bss_end = .); } > ilmb_cntlr

.bss_stack : { . = ALIGN(8); _heap = .; _heap_start = _heap; . += _STACK_SIZE; . = ALIGN(8); _stack = .; __stack = _stack; } > SRAM_256Kx32_C_MEM0_BASEADDR }

chng trnh ny, mnh s to mt ng dng nhp d liu t bn phm (chng hn 100 k t), lu trong SRAM v cho hin th gi tr nh phn theo bng m ASCII ln LED 8 bit, do vy ta chn vng data t trong SRAM, tuy nhin vng bss_stack cui cng cng nnt trong SRAM, khai bo nh trn th chng ta c th t d liu vo trong SRAM. V file TestApp_Memery cha chnh sa (do phn mm t to) :
#include "xutil.h" #include "xgpio_l.h" /* * Routine to write a pattern out to a GPIO * which is configured as an output * PARAMETER C_ALL_INPUTS = 0 */ void WriteToGPOutput(Xuint32 BaseAddress, int gpio_width) { int i=0, j=0; volatile int delay=0; int numTimes = 5; XGpio_mSetDataDirection(BaseAddress, 1, 0x00000000); /* Set as outputs */ while (numTimes > 0) { j = 1; for(i=0; i<(gpio_width-1); i++) { XGpio_mSetDataReg(BaseAddress, 1, j); j = j << 1; for (delay=0; delay<1000000; delay++) { ; //wait } }j = 1; j = ~j; for(i=0; i<(gpio_width-1); i++) { XGpio_mSetDataReg(BaseAddress, 1, j); j = j << 1; for (delay=0; delay<1000000; delay++) { ; //wait }

}numTimes--; } }//==================================================== int main (void) { print("-- Entering main() --\r\n"); /* * MemoryTest routine will not be run for the memory at * 0x00000000 (dlmb_cntlr) * because it is being used to hold a part of this application program */ WriteToGPOutput(XPAR_LEDS_8BIT_BASEADDR, 8); /* Testing EMC Memory (SRAM_256Kx32)*/ { XStatus status; print("Starting MemoryTest for SRAM_256Kx32:\r\n"); print(" Running 32-bit test..."); status = XUtil_MemoryTest32((Xuint32*)XPAR_SRAM_256KX32_MEM0_BASEADDR, 1024, 0xAAAA5555, XUT_ALLMEMTESTS); if (status == XST_SUCCESS) { print("PASSED!\r\n"); }else { print("FAILED!\r\n"); } print(" Running 16-bit test..."); status = XUtil_MemoryTest16((Xuint16*)XPAR_SRAM_256KX32_MEM0_BASEADDR, 2048, 0xAA55, XUT_ALLMEMTESTS); if (status == XST_SUCCESS) { print("PASSED!\r\n"); }else { print("FAILED!\r\n"); } print(" Running 8-bit test..."); status = XUtil_MemoryTest8((Xuint8*)XPAR_SRAM_256KX32_MEM0_BASEADDR, 4096, 0xA5, XUT_ALLMEMTESTS); if (status == XST_SUCCESS) { print("PASSED!\r\n"); }else { print("FAILED!\r\n"); } }print("-- Exiting main() --\r\n"); return 0; } Chng trnh trn ch test b nh ,sau y l chng trnh ca v d : #include "xparameters.h" #include "xutil.h" #include "xgpio_l.h"

main() {int i; extern char a[100] /*bin a phic khai bo trong Linker_Script, c a ch Offset l phn sau phn sau du bng a = 0x1000; tha ch ca a[0] s l0x20101000,va ch btu ca SRAM l 0x20100000 */ xil_printf(chuong trinh bat dau\n\r); for(i=0;i<100;i++) {a[i]=XuartLite_RecvByte(STDIN_BASEADDRESS); xil_printf(\n\rky tu ban vua nhap la :%c,a[i]); xil_printf(\n\rgia tri thap phan vua nhap la:%d,a[i]); xil_printf(\n\rgia tri thap luc phan ban moi vua nhap la:%x,a[i]); Xgpio_mSetDataReg(0x40000000,1,a[i]); }xil_printf(chuong trinh ket thuc) }

Chng trnh ny s hin th dng u tin l dng chuong trinh bat dau, sau xung dng, mn hnh giao tip vi my tnh s ch bn nhp tng gi tr ca dy a[i], hin th gi tr thp phn v thp lc phn ny ln mn hnh giao tip vi my tnh,v hin th gi tr nh phn ln 8 LED n ca my Board Spartan-3 Starter, v c tip tc nh vy khi cc bn nhp xong 100 gi tr (bt k bng ng no, min l truyn qua cng RS-232), th mn hnh xut ra dng chuong trinh ket thuc Cc hm XuartLite_RecvByte, v hm Xgpio_mSetDataReg l hm c vit sn , cc bn nn tm hiu cc hm ny, n nm trong cc ngoi vi tng ng, v d hm XuartLite_RecvByte nm trong ngoi vi UART(RS232) cn hm Xgpio_mSetDataReg nm trong ngoi vi GPIO(Led 8 bit), mun xem cc hm ny cc bn vo Tab System, chn ngoi vi tng ng : trong phn Driver, cc bn nhn chut phi, chn View API Doc xem th vin cc hm vit sn, mt iu lu l khng phi tt c cc ngoi vi u c hm vit sn. Nh vy chng ta xong phn h thng v chng trnh iu khin, tip theo, cc bn cho dch chng trnh, nhn vo nt trn thanh cng c dch, lu thi gian dch l rt lu, c th gn 10 pht, v trong khi dch, my s tn dng ton b kh nng ca CPU, v lm cho CPU rt nng, c th my s khi ng li do nhit qu cao, nn cc bn cn gii nhit tt cho CPU trnh tnh trng khi ng li ca my, nu khng chng ta s phi lm li t u. Sau khi dch xong, giao tip vi my tnh, chng ta dng chng trnh Hyper Terminal , l chng trnh Window h tr sn s dng cng truyn btng b UART trn my tnh, bt chng trnh Hyper Terminal ln :

t tn cho chng trnh (ch l th tc), nhn OK chn cng COM1, nhn OK i tip theo chn tc truyn, bit kim tra chn l,lu l phi ng b vi tc ca cng UART ca MicroBlaze m chng ta chn t u: Nh vy l Kit ca chng ta c th giao tip vi my tnh qua cng truyn bt ng b. Ni dy truyn d liu (s dng cng 25 chn trn my tnh) v cng ni tip tryn chng trnh t phn mm xung Kit v giao tip gia Kit v my tnh, lu phi ng chn, nu khng mun Kit c th h. Sau , np (nhng) ton b h thng vo Kit bng nt th chng ta c mt h thng hot ng c lp c th giao tip vi thit b khc ( y l my tnh), trong trng hp ny, Kit ca chng ta s l my ch ,cn my tnh l ngoi vi giao tip. Chng trnh m phng s c gi kem theo File .wrf Kt qu ca chng trnh Hyper Termainal sau khi chy chng trnh:

Gi tr nh phn s c hin th trn 8 LED n ca Kit t Led 1->Led 8,kt qu cc bn xem trong File.wrf . Cc bn cng c th to ra mt ngoi vi ring gioa tip vi MicroBlaze, chng hn giao tip vi bn phm qua cng PS2 c sn trn Kit, tuy nhin, mun vit c giao tip ny th cc bn phi nm vng ngn ng VHDL hoc Verilog HDL, s dng phn mm ISE thi k, v vn l cc bn phi vit ton b cc giao thc , cc th vin cho ngoi vi mi to ra, EDK 7.1i khng h tr vit bng C, bn no quan tm th xin tm hiu mc: Creat and Import Peripheral Wizard trong File est_rm.pdf. y l chng trnh mi, ti liu t nn trong khi vit c t nhiu sai st, mong cc bn b qua.