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A Controller Area Network Bus Transceiver Behavioral Model for Network Design and Simulation
William Prodanov, Student Member, IEEE, Maurizio Valle, Member, IEEE, and Roman Buzas
AbstractThe main purpose of this paper is to develop reliable and affordable tools and methodologies for the design, simulation, and fault analysis of Controller Area Network (CAN) bus networks. In this paper, a behavioral model of a CAN bus transceiver is proposed and experimentally veried. Moreover, we developed a methodology to efciently manage the trade-off concerning accuracy, simulation speed, and convergence issues which are usually involved in the simulation of large CAN bus networks. To this aim, three different architectures of the transceiver behavioral model have been implemented: They can be selected by the user to address specic requirements of intended analyses. The architectures are based on a set of behavioral models of the basic mixed-signal circuit building blocks of the transceiver. The models were implemented using the VHDL-AMS language. Signal integrity, fault analysis, power consumption analysis, corner analysis, etc., can be effectively and reliably implemented. Simulation and experimental results, which demonstrate our approach efciency, are reported. Index TermsBehavioral modeling and simulation, CAN bus transceivers and networks, Controller Area Network (CAN), fault simulation and analysis, mixed-signal integrated circuits, signal integrity analysis, VHDL-AMS.

I. I NTRODUCTION HE Controller Area Network (CAN) network application domain has been increasing signicantly [1][6] over the last several years. Moreover, the growing diffusion of CAN in safety- or mission-critical applications (e.g., automotive and biomedical systems) asks for suitable techniques to assess the dependability of CAN networks. The continuous increase in the integration level of electronic systems is, indeed, making more difcult than ever to guarantee an acceptable degree of reliability [7]. Therefore, test and fault diagnosis of network integration are strongly required to ensure that all CAN bus devices are able to correctly and reliably interact as specied. The design and validation process of CAN networks is time consuming and expensive, as some iteration steps between
Manuscript received May 7, 2008; revised June 3, 2009. First published June 23, 2009; current version published August 12, 2009. This work was supported by ON Semiconductor Inc. W. Prodanov is with the Integrated Circuits Laboratory, Federal University of Santa Catarina, Florianopolis 88040-900, Brazil (e-mail: william.prodanov@ gmail.com). M. Valle is with the Department of Biophysical and Electronic Engineering, University of Genoa, 16145 Genoa, Italy (e-mail: maurizio.valle@unige.it). R. Buzas is with ON Semiconductor Inc., 619 00 Brno, Czech Republic (e-mail: roman_buzas@onsemi.com). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TIE.2009.2025298

design and validation are needed. Validation by measurements on prototype vehicles is not exhaustive; in fact, corner or faulty conditions can be hardly congured. Moreover, worst case congurations are usually not available during the early stages of development process, and tolerance values are distributed randomly among networked devices. Modifying a prototype topology would signicantly increase the development costs and time [8]. Therefore, a reliable and efcient methodology must be implemented to effectively manage development risks and validation issues. To address the aforementioned issues and for assessing verication and for fast prototyping of CAN bus networks, we propose a solution based on mixed-mode behavioral modeling and simulation. Behavioral modeling of all network components, including relevant corner conditions, allows handy verications by simulation in early development stages and brings significant improvements in terms of cost and time to market for network designers. Behavioral modeling and simulation can tremendously simplify the integration of CAN networks into applications. In order to propose an effective solution, specic aspects concerning CAN network characteristics must be taken into account. In particular, the following properties and issues must be carefully dealt with by the proposed solution. 1) Signal integrity: A reliable representation of bus-line electrical signals permits the optimization of the entire system considering many variables, for instance, different operating temperatures for each transceiver, different input impedances in the case of hybrid networks, the device parameter variation within the specied range, etc. 2) One of the main aspects of accurately representing electrical bus signals is the related amount of electromagnetic emission (EME). Mainly in automotive systems, which are well known as noisy electromagnetic environments, EME investigation must be addressed. 3) Test and fault diagnosis of network integration are strongly required to ensure that all CAN bus devices are able to correctly and reliably interact together as specied. 4) The verication of CAN networks must ensure that the worst case combination of parameters (i.e., corner analysis) and tolerances assures sufcient signal integrity. 5) A network diagnosis considering whether any electronic control unit (ECU) is working properly has an important and direct impact on the network reliability assessment.

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6) Thermal aspects are an important issue mainly for systems working in harsh environments. Modeling thermal behavior is closely related to a correct instantaneous power consumption estimation. 7) CAN networks, including a large number of ECUs working in different operating conditions, require a special attention regarding the convergence in transient analyses. Moreover, usually, network complexity constrains the simulation computational effort required to simulate its behavior. 8) One of the most compelling reasons to model and simulate CAN networks is that the standard guidelines for the physical implementation of a CAN network are too constricting for the optimizations that vehicle designers wish to make: automobile designers want to stretch boundaries of run and stub lengths to achieve cost and weight goals; aircraft manufacturers have run lengths that cannot possibly be achieved inside the guidelines. They need to verify that these nonstandard designs are both safe and reliable. According to the aforementioned context, a mixed-mode model of a CAN bus transceiver was developed [9][11]. The proposed model is able to emulate all the real device operating modes, to accurately model power consumption in each operating mode, to accurately represent electrical characteristics as voltages levels, I/O signal characteristics, and I/O pin impedances, to consider the device timing characteristics, to continuously monitor the device operation, to assert that devices are operating within its maximum absolute ratings, etc. The proposed model allows the signal integrity and electrical behavior simulation of full CAN bus systems. Normal and faulty operating conditions in the network are properly modeled. All transceiver I/O signals are modeled in the analog domain, allowing an easy integration with transistor level circuit simulators. Concerning behavioral modeling specic aspects, the adopted methodology to face accuracy, simulation speed, and convergence trade-offs consists in the development of three different architectures. Each architecture makes use of different modeling approaches and abstraction levels [12], [13]. However, any of them includes a minimum set of features to allow a meaningful system diagnostic and verication. The modularity allows easy model customization as well. The model was implemented using the VHDL-AMS language [14][17]: It was chosen mainly because it is widely supported by available mixed-mode circuit simulators. Moreover, VHDL-AMS provides features for modeling the digital and analog domains and the communication interface. It is an IEEE open standard [18]. In this paper, relevant CAN protocol characteristics, proposed model features, and performance will be illustrated as follows. 1) The model structure and its main characteristics and features are illustrated. In particular, the three model architectures are introduced. 2) Simulation examples are shown to illustrate basic properties and operation of the model.

Fig. 1. CAN bus transceiver mixed-mode behavioral model block diagram.

3) A summary of meaningful test results is reported to demonstrate that the model is reliable in many different operating conditions, including normal and faulty situations. The tests prove that the model behavior matches all the device datasheet operating description and functionalities. 4) Finally, transient analysis simulations are compared with experimental measurements. The simulation results highlight that one can validate (in real operating conditions) the network behavior in a reliable way. II. CAN B US T RANSCEIVER B EHAVIORAL M ODEL The CAN bus transceiver device chosen as a reference for the behavioral model development is the NCV7341 [19]. It is an example of available off-the-shelf transceiver fully compatible with CAN standard [20], [21]. It acts as interface between the CAN protocol controller and the CAN bus. It is primarily intended for high-speed applications, and it can achieve the maximum speed specied in [20] (i.e., up to 1.0 Mb/s). To the best of the authors knowledge, no mixed-mode behavioral models for CAN transceivers have been reported in literature. Even where a reference to available models is given [8], the transceiver model itself is not presented in a formal and systematic way in order to proof its completeness and major performance (e.g., computational effort and accuracy). Moreover, many of published works that present tools for CAN networks analysis and validation (see [3] and [22][27]) do not include any aspects related to CAN physical layer. The block diagram of the CAN bus transceiver mixed-mode behavioral model is shown in Fig. 1. All the transceiver I/O signals at the model boundary are represented in the analog domain. This feature allows the model to be mixed with transistor level models within electrical simulation tools (i.e., SPICE-like simulators). For this reason, signals to/from the digital module must be converted into the analog domain. The model is, on purpose, structured into submodules to allow easy customization. This characteristic is useful also for verications of system basis chips (SBCs)1 with integrated transceivers and for the creation of more complex SBC models.
1 System-based chips (SBCs) are integrated systems that combined several popular functions (i.e., bus drivers, voltage regulators, wake-up switches, SPI, etc.). They are typically used in automotive MCU-based systems.

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TABLE I CAN B US T RANSCEIVER M ODEL A RCHITECTURE C HARACTERISTICS

The analog module is also able to model the instantaneous power consumption based on the actual device operating mode. This feature permits the temperature behavior modeling and accurate total power consumption estimation. The internal operating temperature is computed by the thermal module indicated. The model is able to give info and warning messages describing the device operating condition and error messages whenever any absolute maximum rating of the transceiver is exceeded. This feature has an important and direct impact on the network reliability assessment. The conguration package allows the user to easily set up the transceiver model parameters. It also allows one to run corner analyses. The transceiver model implements all the device functionalities [19]. Analog-domain-related features are covered and discussed in this paper due to the impact they have on the electrical characteristics of input and output signals (see Sections III and IV). The analog module comprises many internal blocks: 1) one-bit digital-to-analog and analog-to-digital interfaces; 2) power-supply voltage monitors; 3) high-speed and low-power receivers; 4) CAN bus transmitter drivers; 5) internal voltage references; 6) pull-ups and pull-downs. Aside from the analog functionalities, it is worth to note that the NCV7341 device is not only CAN bus transmitter and receiver (i.e., a transceiver). It has ve operational modes, and a digital logic block (digital module in the model) manages mode transitions. The operational modes are the following: normal mode, receive-only mode, standby mode, go-to-sleep mode, and sleep mode. Moreover, the digital module manages the interface between digital I/O signals and the bus controller device. NCV7341 also implements undervoltage monitor and related actions as mode transitions, disable of RX part, etc. This functionality is, once more, managed by the digital module which also includes debouncers from sleep mode via WAKE pin or CAN bus. Finally, the digital module implements overtemperature monitoring control. The model implements the main NCV7341 characteristics and some additional behavioral modeling features, in order to enhance the CAN network assessment capabilities, as follows: 1) output voltage slope control to minimize EME; 2) maximum output current limiter; 3) voltage references reecting power-supply state; 4) thermal shutdown based on the instantaneous power consumption estimation; 5) device timing specications; 6) maximum absolute rating monitoring;

7) accurate nonlinear output impedance modeling; 8) bus short-circuit condition modeling; 9) instantaneous power consumption estimation based on the operational mode; 10) temperature behavioral model. A. Behavioral Model Development Methodology The complex scenario where the transceiver model has to work claims for a special attention to the most important aspects of mixed-mode behavioral modeling. An accurate model is very important for signal integrity investigation [11]. Simulation speedup compared to traditional simulation approaches is a mandatory feature for behavioral models. At last but not least, the system complexity gives rise to many simulation convergence problems during transient analysis: It does not matter how fast and accurate the model is if it is not able to converge in all operating conditions [9]. These problems must be managed, and unfortunately, their requirements go to different directions. The methodology used in this paper to face the mixed-mode behavioral modeling requirements consists of mixing different modeling abstraction levels and mathematical approximations for each block of the transceiver structure. Piecewise linear, exponential functions, and Taylor series approximations were used, giving different performance in terms of accuracy, speed, and convergence. Moreover, some transceiver functions were described using high-level programming language constructors, while others make use of hierarchical descriptions and lowlevel abstraction modeling approach. In order to implement the model in such a modular structure, a basic building block library was created. A detailed discussion about the development of the building blocks and the overall development methodology can be found in [9]. The modular methodology approach was exploited according to Table I. Table I shows the three different architectures that were implemented. Different approximations and features were arranged in each architecture: The user can arbitrarily choose one of them according to the accuracy level and simulation speed required for a given analysis. Nonetheless, a minimum set of features is present in all architectures, allowing a meaningful signal integrity and/or device behavior analyses for any combination of model architectures inserted in a CAN bus system simulation. Please note that any previously mentioned feature (see Section II) not included in Table I is present in all congurations. III. B EHAVIORAL S IMULATION R ESULTS In mixed-signal electronic systems, the functionality is distributed over both analog and digital parts (e.g., an analog

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Fig. 2.

Simulated CANH output dc characteristic. (a) Simulation setup. (b) CANH output characteristic.

Fig. 3.

Simulated CANL output dc characteristic. (a) Simulation setup. (b) CANL output characteristic.

feedback loop to the digital part), and verifying the digital or analog parts separately is not effective. In fact, the interaction between analog and digital parts is error prone. Therefore, the model must be simulated in several different operating modes and conditions to fully verify its behavior [28]. In this context, the purposes of results shown in this section are given in the following: 1) to verify the behavior of analog I/O interfaces according to device specications [19]; 2) to prove that the analog and the digital parts of the model are interacting correctly; 3) to assess differences among the implemented architectures according to Table I. The transceiver model was implemented using the Cadence mixed-signal framework CAD environment (IUS v5.7). Nonetheless, the model fully matches the VHDL-AMS standard, and it is completely portable to any other simulator that supports the language. The PC workstation used to perform the tests is an Intel P4, 2.66-GHz, 512-MB RAM, and Linux O.S.

A. Output Driver DC Simulation The rst simulation results shown in this section are related to the dc characteristics of CANH and CANL output pins of transmitter drivers. The simulation was performed for all three model architectures as described in Table I. Fig. 2 shows the setup used to simulate the output dc characteristic of CANH pin and the simulation result. The analysis is performed, setting the transceiver model to dominant state and applying a 0 to the TxD pin, and then, a dc sweep analysis is performed. Fig. 3 shows the same result for CANL pin. ACCURATE and MODERATE architectures have a much more smoothed characteristic than a FAST architecture, as expected according to the approximation used to model the output driver (see Table I). Finally, the ACCURATE model architecture is supposed to better match the real device behavior than MODERATE one, as it will be shown in Section IV. B. CAN Bus Signal Integrity Analysis In order to verify the CAN bus transceiver behavioral model transient response, a simple network composed of two

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Fig. 4. Network setup structure used for transient analyses.

Fig. 6. CANH and CANL signal integrity analysis using the FAST model architecture.

Fig. 5. CANH and CANL signal integrity analysis using the ACCURATE model architecture.

transceivers, TrA and TrB, was congured as shown in Fig. 4. The resistors and the capacitor were included as indicated by the CAN standard [20]. This conguration allows the verication of each single device behavior, taking into account the operational mode (e.g., wake-up, stand-by, normal mode, etc.), the timing of I/O signals, and the transceiver output impedance values. The CAN bus electrical signal characteristic is probably the most important aspect that the model has to properly represent. It allows signal integrity analyses, and it is the basis of the CAN network performance validation. Fig. 5 shows the CANH and CANL signals in a simplied example of signal integrity verication where recessive-todominant and dominant-to-recessive bit transmission transitions are depicted, using the ACCURATE model architecture. A rst signal feature is the transmission delay from a TxD event to the effective CANH(L) signal change and the delay from a bus-line event detection to the RxD change. In general, the signal timing characteristics are strongly inuenced by transceiver internal delays. Setting the related transceiver model parameters to the worst case conditions is useful in order to validate CAN systems operating at high bit rates. Moreover, the signal timing analysis is essential for the bitwise arbitration of the CAN protocol handshake. The maximum voltage variation slope of CANH(L) signals is limited in order to minimize EME effects: Simulations demonstrated that the model can properly represent the real device operation as will be shown in Section IV. At the bottom of the gure, the differential and the common-mode voltages, VDIFF and VCM, respectively, are shown. The VCM peaks come from different transmission delay values of TxD-to-CANH and TxD-to-CANL. The possibility of representing such a situation allows EME performance evaluation.

Fig. 7.

Internal state hopping and remote wake-up analysis.

In order to illustrate the differences between two model architectures, Fig. 6 shows the same simulation depicted earlier using the FAST architecture. Please note the differences on CANH(L) signal transitions by considering both cases. The VCM voltage peaks increase as well. Considering the accuracy loss, it is clear that this model architecture is not indicated to accurate signal integrity verication. Its utilization is advised to speed up the validation of CAN networks with high number of devices after a previous detailed signal integrity study using the ACCURATE architecture. C. State Hopping Analysis A simulation that illustrates the interactions between the digital and the analog modules of the mixed-mode model is shown in Fig. 7. The analysis shows a state hopping analysis (power-on, normal, stand-by, and sleep states). The signal PWR_TrA shown in Fig. 7 represents the device instantaneous power consumption. It is used to model the thermal behavior of the transceiver, allowing the implementation of the power-shutdown feature, and it can be used to monitor the power consumption of the entire CAN network system. After a rst power-on period, TrA is sent to a normal state, and it accesses the CAN bus. Then, the STB and EN signals are set to 0.0 V to send TrA to the stand-by state. When entering this state, TrA greatly reduces the bias currents, as it can be seen on signal PWR_TrA that models the instantaneous total power consumption. While TrA is set to the stand-by mode,

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TABLE II T EST-C ASE D ESCRIPTION AND S IMULATION T IME

TABLE III CPU U SAGE T IME

TrB accesses the bus. TrA, which is monitoring the bus lines by means of its low-power receiver block, recognizes that a remote wake-up was requested (WAKEUP digital ag). RxD is set to 0.0 V in this case. In such a state, if STB is set to 3.3 V, TrA wakes up, as shown in Fig. 7. Finally, TrA is set to the sleep mode, when EN = 0.0 V and ST B = 3.3 V. It is worth to note that the signals TxD, RxD, EN, and STB are analog signals. Even if they represent digital data that the CAN controller sends/receives to/from a given transceiver, they are set within the range of 0.03.3 V as analog signals instead of 0 and 1. D. CAN Bus Transceiver Model General Performance Aside from the detailed simulation examples previously introduced, many other verication tests were done. The three available model architectures presented in Table I were used. Table II gives a brief description of the main performed tests. Tests 3 and 4 are the ones presented in Sections III-B and III-C, respectively. Note that for Test 3 (Section III-B), only a small part of the transient analysis is shown in Figs. 5 and 6 for convenience. The other test cases are of primary importance for the complete model verication. They are useful to verify the analog interface behavior and the information transfer between analog and digital modules as well. The test cases, which have been taken into account, cover the following. 1) The critical parameters needed for reliable communication and error validation. These are Tests 1, 3, and 5. Test 1 shows correct timing of the protection of the bus being stuck by a node, sending dominant or incorrect messages as a result of collapsed software bubbling idiot or hardware failure as some short on PCB (e.g., TxD to ground). Test 3 validates important timing (TxD-busRxD loop delay) for correct sampling of the state of the bus. Test 5 veries all most common bus shorts which can occur in real network. 2) All functional states of the transceiver (Test 4, Test 6, Test 7). 3) Potential PCB failure or overload of VIO regulator (Test 2). The third column of Table II reports the simulation period of transient analyses. Table III shows the CPU usage time in seconds for each test. The results show that the proposed approach can manage the speed and accuracy trade-off. The results shown in Table III indicate from 42% to +73% CPU usage time variation, taking the MODERATE architecture as a reference. This factor strongly depends on the given test-

case characteristics. Test cases where a high number of bit transmissions occur (Tests 2 and 5) show the most signicant differences. It is worth to note that for real operating conditions, where many devices are supposed to be active at the same time, a huge number of state changeswhich means bit transmissionsare expected. Therefore, following the previous results, an overall factor of 30%40% variation on CPU usage time is presumed, which can imply many CPU usage hours for a complete system validation. In terms of CPU simulation speed, device level SPICE-like simulations, despite using behavioral description of computationally expensive parts (e.g., internal oscillator), were approximately 600 times slower than the VHDL-AMS ACCURATE architecture model results. Moreover, behavioral model simulations also create signicantly smaller output database, which allows easier system debugging and result visualization. The simulation time of a whole network (e.g., ten nodes) is very limited, i.e., in the range of some tens of seconds, and it strongly depends on the network size, the model architecture, the input conguration, and the simulation period size. As a nal remark, the robustness related to dc and transient analysis is demonstrated by the amount of test cases taken into account. IV. B EHAVIORAL S IMULATION AND M EASUREMENT R ESULT C OMPARISON The CAN transceiver model verication was mainly performed by comparing simulation results with experimental measurements. The setup used for both simulations and measurements is shown in Fig. 8. The setup is similar to the one used to perform the transient analysis shown in Section III. Nonetheless, in order to better represent the real operating conditions, nonideal effects of transmission lines and powersupply lines must be taken into account. In the practical setup, two transceivers were connected to the bus line with 0.5-m-long cables. Termination of the bus was modeled, including small inductance (50.0 nH) and scope probe capacitances (10.0 pF) used during measurements. For all bus short-circuit test cases, the inductance of the shorts was modeled. Results presented in this section are organized as follows. In the rst set, we assess signal integrity of behavioral model simulation results by comparing them with measurements. Second, the behavioral simulation results are compared with the measurements of CAN bus network in real faulty conditions (i.e., in the presence of some disturbances as short circuits and unpowered nodes connected to the bus line).

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Fig. 8. Experimental test-bench setup for simulation result and experimental data comparison.

MODERATE model results still match on voltage levels with measurements during recessive and dominant states. However, differential CANH and CANL signal matching determines the involved amount of EME. Symmetrical signals cause constant common-mode voltage and zero common-mode current, resulting in no EME. Therefore, considering that FAST and MODERATE model inaccurately signal transitions, they are not suitable for signal integrity and EME investigations. B. CAN Network Fault Analyses In order to demonstrate model accuracy performance, the transient responses in some faulty situations are shown in the next sections. Some fault conditions were applied, for example, bus lines to power-supply shorts, bus lines to ground shorts, shorts between both bus lines, and removal of power supply from one of the network transceivers. The model capability of accurately modeling faults is very useful during CAN systems early development stages. An important consequence is that the time effort and the network prototyping costs can be meaningfully reduced. Here, only the ACCURATE model results are compared with the measured data because the accuracy of signal representation is of great value. The results obtained for the other two models follow, in general, the dynamic response characteristics shown in Figs. 9 and 10. In other words, sharp voltage transitions, in the presence of the line and short-circuit inductances, result in overestimated overshootings. Nonetheless, FAST and MODERATE models may still be efciently used when less complex situations must be analyzed (e.g., low bit rate data transmission, data communication from CAN bus line to CAN controller device under no-faulty conditions, etc.). 1) CAN Bus Short-Circuit Fault Analyses: Short of CANL bus wire to VBAT (i.e., 12-V battery) is expected to create zero differential voltage and, thus, no communication on the bus. Although the value of the resistance modeling the short was virtually equal to 0 , due to the inductance of the wire short, pulses in the range of tens of nanoseconds and 2.0 V

Fig. 9. Recessive-to-dominant state transition.

Fig. 10. Dominant-to-recessive state transition.

A. Signal Integrity Assessment Figs. 9 and 10 show a comparison of the measured results with the simulated ones using all three model architectures. They show the dominant and recessive state representation in the bus lines and the state transitions recessive-to-dominant and dominant-to-recessive, respectively. In both cases, transceiver power supplies have typical values, and no bus error has been injected. The measured and ACCURATE model data match, mainly regarding the bus signal voltage slope. The FAST and

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Fig. 13. CANH line to CANL line short circuit at 1 Mb/s.

Fig. 11. CANL line to VBAT short circuit.

Fig. 14. CANH line to CANL line short circuit at 20 kb/s.

Fig. 12. CANH line to VDD power-supply short circuit.

of magnitude are still visible both in simulated and measured data (see Fig. 11). Please note that the behavioral model is accurate enough to represent the small glitches seen in the RxD signal (due to the different CANH and CANL signal pulse amplitudes, the bus differential voltage reaches the threshold level that denes a dominant state). Fig. 12 shows the transient response when a short circuit between the CANH line and VDD is present. This is a case of nondestructive communication fault. As it can be seen, the common-mode voltage (CANH + CANL)/2 in recessive state is VDD. When the transceiver tries to force a dominant state, the CANL voltage drops down to about 1.5 V as expected. As a consequence, for each dominant-to-recessive transition, the common-mode voltage will have a step of around 1.75 V, which will cause EME being signicantly increased mainly

in the frequency range of communication. Therefore, even if the communication is still possible, the EME performance is compromised. Fig. 13 shows a low-ohmic short-circuit2 condition between both CAN bus lines. The resulting common-mode voltage in the dominant state is strongly dependent on the mismatch between the maximum current values of CANH and CANL drivers. Once more, the VHDL-AMS model is able to efciently represent the signal behavior during this fault condition. Consequently, the resulting EME due to common-mode voltage variations can be correctly estimated. In this example, a dominant bit was supposed to be transmitted at 1.0 Mb/s. Fig. 14 shows the same situation depicted in Fig. 13, but at a lower bit rate, i.e., 20 kb/s. 2) CAN Bus-Line Disturbance Caused by a Node With Power-Supply Failure: A possible faulty situation is the one where one or more transceivers are not power supplied (or unpowered). In the following test, the transceiver exhibits powersupply undervoltage detection: It means that, if one of the
2 Much

lower resistance value than the bus line termination ones.

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Fig. 15. Unpowered node inuence on communication at 1 Mb/s.

tion levels, have been mixed together in order to congure three different transceiver model architectures. As a consequence, the end user may arbitrarily choose among them according to the application requirements which may differ by speed, accuracy, and convergence constraints. Simulations results were presented and, when applicable, compared with measured data. The results demonstrate that the presented modeling methodology allows one to check functional behavior and signal integrity of the CAN bus networks in a cost-efcient way. The model proved to be able to accurately model main electrical aspects of CAN bus transceivers (i.e., timing, I/O port impedances, power consumption, etc.). Special attention was given to fault condition analysis. The model was implemented using the VHDL-AMS language. The model structure allows the use of corner parameter analysis methodology. The great level of modularity used to develop the models allows an easy customization of internal blocks. The possibility to validate the network with a complete set of other network elements (e.g., terminations, commonmode chokes, cables, etc.) and reliability-related aspects (e.g., operating range check, absolute maximum rating violation, and thermal behavior) gives to CAN network designers a tool for more efcient design development. A wide range of mixed-mode integrated circuits and systems can be modeled using the proposed methodology, for instance, Flexray transceivers that work with bit rates up to 10 Mb/s. R EFERENCES
[1] P. Marino, F. Poza, M. Dominguez, and S. Otero, Electronics in automotive engineering: A topdown approach for implementing industrial eldbus technologies in city buses and coaches, IEEE Trans. Ind. Electron., vol. 56, no. 2, pp. 589600, Feb. 2009. [2] F. Gil-Castineira, F. Gonzalez-Castano, and L. Franck, Extending vehicular can eldbuses with delay-tolerant networks, IEEE Trans. Ind. Electron., vol. 55, no. 9, pp. 33073314, Sep. 2008. [3] J. Suwatthikul, R. McMurran, and R. P. Jones, Automotive network diagnostic systems, in Proc. Int. Symp. IES, Oct. 2006, pp. 14. [4] H. F. Othman, Y. R. Aji, F. T. Fakhreddin, and A. R. Al-Ali, Controller area networks: Evolution and applications, in Proc. 2nd IEEE Int. Conf. ICTTA, Apr. 2006, pp. 30883093. [5] N. Navet, Y. Song, F. Simonot-Lion, and C. Wilwert, Trends in automotive communication systems, Proc. IEEE, vol. 93, no. 6, pp. 12041223, Jun. 2005. [6] D. Lim and A. Anbuky, A distributed industrial battery management network, IEEE Trans. Ind. Electron., vol. 51, no. 6, pp. 11811193, Dec. 2004. [7] M. S. Reorda and M. Violante, On-line analysis and perturbation of CAN networks, in Proc. 19th IEEE DFT , Oct. 2004, pp. 424432. [8] T. Gerke and C. Schanze, Development and verication of in-vehicle networks in a virtual environment, in SAE Technical Paper Series, Paper 2006-01-0168. Warrendale, PA: SAE Int., May 2005. [9] W. Prodanov, M. Valle, R. Buzas, and H. Piersciski, Behavioral models of basic mixed-mode circuits: Practical issues and application, in Proc. ECCTD, Seville, Spain, Aug. 2007, vol. 1, pp. 854857. [10] W. Prodanov, M. Valle, R. Buzas, and H. Piersciski, A mixed-mode behavioral model for a controller-area-network bus transceiver: A case study, in Proc. IEEE BMAS, San Jose, CA, Sep. 2007, pp. 6771. [11] R. Buzas, W. Prodanov, and M. Valle, CAN network design and verication using behavioral modeling languages, in Proc. 12th iCC, Barcelona, Spain, Mar. 2008, pp. 7-17-8. [12] A. J. Gines, E. Peralias, A. Rueda, N. M. Madrid, and R. Seepold, A mixed-signal design reuse methodology based on parametric behavioural models with non-ideal effects, in Proc. DATE, Mar. 2002, pp. 310314.

Fig. 16. Unpowered node inuence on communication at 20 kb/s.

voltages at supply pins drops below a given value, the transceiver is forced into a low-power mode. Consequently, it acts as an undesirable load on the bus, and it pulls the bus to ground. Instead, in normal mode, the transceiver keeps the bus wire voltage biased around midway the supply voltage range. The fault again results into nonoptimal EME performance, while communication in terms of differential voltage value is not affected. This case, as shown in Fig. 15, represents a worst case condition as the network is composed by two nodes, and one node is unpowered (i.e., 50% of nodes). In larger size networks, inuence of few unpowered transceivers is minimized by the higher number of power supplied ones. Fig. 16 shows a situation when lower bit rate (20 kb/s, usually used in industrial applications) is used and an unpowered node is present. The result is that the unpowered node strongly pulls the network to ground during recessive state. V. C ONCLUSION A CAN bus transceiver mixed-mode behavioral model has been presented. Basic block models, with high and low abstrac-

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[13] S. Huss, Model Engineering in Mixed-Signal Circuit Design., 1st ed. Norwell, MA: Kluwer, 2001. [14] E. Christen, K. Bakalar, A. Dewey, and E. Moser, Analog and mixedsignal modeling using the VHDL-AMS language, presented at the 36th Des. Autom. Conf., Jun. 1999. [15] P. V. Nikitin and C.-J. R. Shi, VHDL-AMS based modeling and simulation of mixed-technology microsystems: A tutorial, Integration VLSI J., vol. 40, no. 3, pp. 261273, Apr. 2007. [16] A. Doboli and R. Vemuri, Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 11, pp. 1504 1520, Nov. 2003. [17] P. Ashenden, G. Peterson, and D. Teegarden, The System Designers Guide to VHDL-AMS: Analog, Mixed-Signal and Mixed-Technology Modeling. San Mateo, CA: Morgan Kaufmann, Sep. 2002. [18] VHDL Analog and Mixed-Signal Extensions, IEEE Std., Rev. IEEE Std. 1076.1-2007, Nov. 2007. [19] High-Speed Low Power CAN Transceiver, ON Semiconductor, Phoenix, AZ, 2008. [Online]. Available: http://www.onsemi.com/PowerSolutions/ product.do?id=NCV7341 [20] ISO 11898, Road VehiclesController Area Network (CAN), International Organization for Standardization, 2003. [Online]. Available: http:// www.iso.org [21] BOSCHCAN Specication Version 2.0, Robert Bosch GmbH, Stuttgart, Germany, 1991. [Online]. Available: http://www.bosch.com [22] J. Hu, G. Li, X. Yu, and J. Zhou, Can modeling and network simulation for city-bus information integrated control system, in Proc. ICMA, Aug. 2007, pp. 17181723. [23] M. Bago, S. Marijan, and N. Peric, Modeling controller area network communication, in Proc. 5th IEEE Int. Conf. Ind. Informat., Jun. 2007, vol. 1, pp. 485490. [24] I. A. Gravagne, J. M. Davis, J. J. Dacunha, and R. J. Marks, Bandwidth reduction for controller area networks using adaptive sampling, in Proc. IEEE ICRA, Apr. 2004, vol. 5, pp. 52505255. [25] G. Cena and A. Valenzano, FastCAN: A high-performance enhanced can-like network, IEEE Trans. Ind. Electron., vol. 47, no. 4, pp. 951 963, Aug. 2000. [26] P. Castelpietra, Y.-Q. Song, F. Simonot-Lion, and M. Attia, Analysis and simulation methods for performance evaluation of a multiple networked embedded architecture, IEEE Trans. Ind. Electron., vol. 49, no. 6, pp. 12511264, Dec. 2002. [27] H. A. Hansson, T. Nolte, C. Norstrom, and S. Punnekkat, Integrating reliability and timing analysis of can-based systems, IEEE Trans. Ind. Electron., vol. 49, no. 6, pp. 12401250, Dec. 2002. [28] R. Lissel and J. Gerlach, Introducing new verication methods into a companys design ow: An industrial users point of view, in Proc. DATE, Apr. 2007, pp. 16.

William Prodanov (S00) was born in Franca, Brazil, in 1976. He received the B.S. and M.S. degrees in electrical engineering from the Federal University of Santa Catarina (UFSC), Florianopolis, Brazil, in 1999 and 2002, respectively, and the Ph.D. degree in electronics engineering from the University of Genoa (UNIGE), Genoa, Italy, in 2008. From 2002 to 2003, he was with the Integrated Circuits Laboratory, UFSC, as a Microlectronics Researcher, prior to joining the Microelectronics Laboratory, UNIGE, for his Ph.D. studies. He is currently with the Integrated Circuits Laboratory, UFSC, where he is involved in postdoctoral research activities. His research interests include mixed-signal behavioral modeling and mixed-signal integrated circuits design.

Maurizio Valle (M01) received the M.S. and Ph.D. degrees in electronic engineering and computer science from the University of Genoa (UNIGE), Genoa, Italy, in 1985 and 1990, respectively. In 1992, he joined the Department of Biophysical and Electronic Engineering (DIBE), UNIGE, as an Assistant Professor, where he has been an Associate Professor of electronic engineering since January 2007. He has been in charge of several R&D contracts and projects. He is the author of more than 130 scientic papers published in national and international conference proceedings and journals. His research interests include electronic and microelectronic systems and applications, sensor circuit interfaces, sensor networks, and tactile systems for robots.

Roman Buzas was born in the Slovak Republic in 1969. He received the M.S. degree in electrical engineering from Slovak Technical University, Bratislava, Slovakia, in 1993. From 1993 to 1995, he was involved in research on GaAs-based circuits. Since 1995, he has been involved in mixed-signal integrated circuit design. His integrated circuit design career started at CEDO, Brno, Czech Republic. In 1996, he joined the Alcatel Microelectronics Design Center, Brno, where he has remained through the acquisition of Alcatel Microelectronics by AMIS in 2003 and the acquisition of AMIS in 2008 by ON Semiconductor Inc. Since 2006, he has been mostly working on integratedcircuit design of vehicle circuits such as CAN, LIN, and Flexray transceivers and system-based chips.